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armv8: layerscape: move ns_dev[] define from h to c file.
Move ns_dev[] from header file to C file to avoid compiling warning when header file is included by others. Signed-off-by: Ran Wang <ran.wang_1@nxp.com> [YS: rewrite commit message] Reviewed-by: York Sun <york.sun@nxp.com>
This commit is contained in:
Ran Wang
York Sun
parent
1711add3dc
commit
cd35855492
3 changed files with 167 additions and 164 deletions
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@ -87,84 +87,4 @@ enum csu_cslx_ind {
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CSU_CSLX_DSCR = 121,
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};
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static struct csu_ns_dev ns_dev[] = {
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{CSU_CSLX_PCIE2_IO, CSU_ALL_RW},
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{CSU_CSLX_PCIE1_IO, CSU_ALL_RW},
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{CSU_CSLX_MG2TPR_IP, CSU_ALL_RW},
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{CSU_CSLX_IFC_MEM, CSU_ALL_RW},
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{CSU_CSLX_OCRAM, CSU_ALL_RW},
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{CSU_CSLX_GIC, CSU_ALL_RW},
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{CSU_CSLX_PCIE1, CSU_ALL_RW},
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{CSU_CSLX_OCRAM2, CSU_ALL_RW},
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{CSU_CSLX_QSPI_MEM, CSU_ALL_RW},
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{CSU_CSLX_PCIE2, CSU_ALL_RW},
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{CSU_CSLX_SATA, CSU_ALL_RW},
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{CSU_CSLX_USB1, CSU_ALL_RW},
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{CSU_CSLX_QM_BM_SWPORTAL, CSU_ALL_RW},
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{CSU_CSLX_PCIE3, CSU_ALL_RW},
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{CSU_CSLX_PCIE3_IO, CSU_ALL_RW},
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{CSU_CSLX_USB3, CSU_ALL_RW},
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{CSU_CSLX_USB2, CSU_ALL_RW},
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{CSU_CSLX_PFE, CSU_ALL_RW},
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{CSU_CSLX_SERDES, CSU_ALL_RW},
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{CSU_CSLX_QDMA, CSU_ALL_RW},
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{CSU_CSLX_LPUART2, CSU_ALL_RW},
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{CSU_CSLX_LPUART1, CSU_ALL_RW},
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{CSU_CSLX_LPUART4, CSU_ALL_RW},
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{CSU_CSLX_LPUART3, CSU_ALL_RW},
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{CSU_CSLX_LPUART6, CSU_ALL_RW},
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{CSU_CSLX_LPUART5, CSU_ALL_RW},
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{CSU_CSLX_DSPI1, CSU_ALL_RW},
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{CSU_CSLX_QSPI, CSU_ALL_RW},
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{CSU_CSLX_ESDHC, CSU_ALL_RW},
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{CSU_CSLX_IFC, CSU_ALL_RW},
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{CSU_CSLX_I2C1, CSU_ALL_RW},
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{CSU_CSLX_I2C3, CSU_ALL_RW},
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{CSU_CSLX_I2C2, CSU_ALL_RW},
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{CSU_CSLX_DUART2, CSU_ALL_RW},
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{CSU_CSLX_DUART1, CSU_ALL_RW},
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{CSU_CSLX_WDT2, CSU_ALL_RW},
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{CSU_CSLX_WDT1, CSU_ALL_RW},
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{CSU_CSLX_EDMA, CSU_ALL_RW},
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{CSU_CSLX_SYS_CNT, CSU_ALL_RW},
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{CSU_CSLX_DMA_MUX2, CSU_ALL_RW},
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{CSU_CSLX_DMA_MUX1, CSU_ALL_RW},
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{CSU_CSLX_DDR, CSU_ALL_RW},
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{CSU_CSLX_QUICC, CSU_ALL_RW},
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{CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW},
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{CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW},
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{CSU_CSLX_SFP, CSU_ALL_RW},
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{CSU_CSLX_TMU, CSU_ALL_RW},
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{CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW},
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{CSU_CSLX_SCFG, CSU_ALL_RW},
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{CSU_CSLX_FM, CSU_ALL_RW},
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{CSU_CSLX_SEC5_5, CSU_ALL_RW},
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{CSU_CSLX_BM, CSU_ALL_RW},
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{CSU_CSLX_QM, CSU_ALL_RW},
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{CSU_CSLX_GPIO2, CSU_ALL_RW},
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{CSU_CSLX_GPIO1, CSU_ALL_RW},
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{CSU_CSLX_GPIO4, CSU_ALL_RW},
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{CSU_CSLX_GPIO3, CSU_ALL_RW},
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{CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW},
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{CSU_CSLX_CSU, CSU_ALL_RW},
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{CSU_CSLX_IIC4, CSU_ALL_RW},
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{CSU_CSLX_WDT4, CSU_ALL_RW},
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{CSU_CSLX_WDT3, CSU_ALL_RW},
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{CSU_CSLX_ESDHC2, CSU_ALL_RW},
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{CSU_CSLX_WDT5, CSU_ALL_RW},
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{CSU_CSLX_SAI2, CSU_ALL_RW},
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{CSU_CSLX_SAI1, CSU_ALL_RW},
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{CSU_CSLX_SAI4, CSU_ALL_RW},
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{CSU_CSLX_SAI3, CSU_ALL_RW},
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{CSU_CSLX_FTM2, CSU_ALL_RW},
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{CSU_CSLX_FTM1, CSU_ALL_RW},
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{CSU_CSLX_FTM4, CSU_ALL_RW},
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{CSU_CSLX_FTM3, CSU_ALL_RW},
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{CSU_CSLX_FTM6, CSU_ALL_RW},
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{CSU_CSLX_FTM5, CSU_ALL_RW},
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{CSU_CSLX_FTM8, CSU_ALL_RW},
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{CSU_CSLX_FTM7, CSU_ALL_RW},
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{CSU_CSLX_DSCR, CSU_ALL_RW},
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};
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#endif
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@ -91,88 +91,4 @@ enum csu_cslx_ind {
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CSU_CSLX_MAX,
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};
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static struct csu_ns_dev ns_dev[] = {
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{ CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
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{ CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
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{ CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
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{ CSU_CSLX_IFC_MEM, CSU_ALL_RW },
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{ CSU_CSLX_OCRAM, CSU_ALL_RW },
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{ CSU_CSLX_GIC, CSU_ALL_RW },
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{ CSU_CSLX_PCIE1, CSU_ALL_RW },
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{ CSU_CSLX_OCRAM2, CSU_ALL_RW },
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{ CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
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{ CSU_CSLX_PCIE2, CSU_ALL_RW },
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{ CSU_CSLX_SATA, CSU_ALL_RW },
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{ CSU_CSLX_USB3, CSU_ALL_RW },
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{ CSU_CSLX_SERDES, CSU_ALL_RW },
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{ CSU_CSLX_QDMA, CSU_ALL_RW },
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{ CSU_CSLX_LPUART2, CSU_ALL_RW },
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{ CSU_CSLX_LPUART1, CSU_ALL_RW },
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{ CSU_CSLX_LPUART4, CSU_ALL_RW },
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{ CSU_CSLX_LPUART3, CSU_ALL_RW },
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{ CSU_CSLX_LPUART6, CSU_ALL_RW },
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{ CSU_CSLX_LPUART5, CSU_ALL_RW },
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{ CSU_CSLX_DSPI2, CSU_ALL_RW },
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{ CSU_CSLX_DSPI1, CSU_ALL_RW },
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{ CSU_CSLX_QSPI, CSU_ALL_RW },
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{ CSU_CSLX_ESDHC, CSU_ALL_RW },
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{ CSU_CSLX_2D_ACE, CSU_ALL_RW },
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{ CSU_CSLX_IFC, CSU_ALL_RW },
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{ CSU_CSLX_I2C1, CSU_ALL_RW },
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{ CSU_CSLX_USB2, CSU_ALL_RW },
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{ CSU_CSLX_I2C3, CSU_ALL_RW },
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{ CSU_CSLX_I2C2, CSU_ALL_RW },
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{ CSU_CSLX_DUART2, CSU_ALL_RW },
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{ CSU_CSLX_DUART1, CSU_ALL_RW },
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{ CSU_CSLX_WDT2, CSU_ALL_RW },
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{ CSU_CSLX_WDT1, CSU_ALL_RW },
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{ CSU_CSLX_EDMA, CSU_ALL_RW },
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{ CSU_CSLX_SYS_CNT, CSU_ALL_RW },
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{ CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
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{ CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
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{ CSU_CSLX_DDR, CSU_ALL_RW },
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{ CSU_CSLX_QUICC, CSU_ALL_RW },
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{ CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
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{ CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
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{ CSU_CSLX_SFP, CSU_ALL_RW },
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{ CSU_CSLX_TMU, CSU_ALL_RW },
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{ CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
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{ CSU_CSLX_RESERVED0, CSU_ALL_RW },
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{ CSU_CSLX_ETSEC1, CSU_ALL_RW },
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{ CSU_CSLX_SEC5_5, CSU_ALL_RW },
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{ CSU_CSLX_ETSEC3, CSU_ALL_RW },
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{ CSU_CSLX_ETSEC2, CSU_ALL_RW },
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{ CSU_CSLX_GPIO2, CSU_ALL_RW },
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{ CSU_CSLX_GPIO1, CSU_ALL_RW },
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{ CSU_CSLX_GPIO4, CSU_ALL_RW },
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{ CSU_CSLX_GPIO3, CSU_ALL_RW },
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{ CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
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{ CSU_CSLX_CSU, CSU_ALL_RW },
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{ CSU_CSLX_ASRC, CSU_ALL_RW },
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{ CSU_CSLX_SPDIF, CSU_ALL_RW },
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{ CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
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{ CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
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{ CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
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{ CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
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{ CSU_CSLX_SAI2, CSU_ALL_RW },
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{ CSU_CSLX_SAI1, CSU_ALL_RW },
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{ CSU_CSLX_SAI4, CSU_ALL_RW },
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{ CSU_CSLX_SAI3, CSU_ALL_RW },
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{ CSU_CSLX_FTM2, CSU_ALL_RW },
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{ CSU_CSLX_FTM1, CSU_ALL_RW },
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{ CSU_CSLX_FTM4, CSU_ALL_RW },
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{ CSU_CSLX_FTM3, CSU_ALL_RW },
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{ CSU_CSLX_FTM6, CSU_ALL_RW },
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{ CSU_CSLX_FTM5, CSU_ALL_RW },
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{ CSU_CSLX_FTM8, CSU_ALL_RW },
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{ CSU_CSLX_FTM7, CSU_ALL_RW },
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{ CSU_CSLX_COP_DCSR, CSU_ALL_RW },
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{ CSU_CSLX_EPU, CSU_ALL_RW },
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{ CSU_CSLX_GDI, CSU_ALL_RW },
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{ CSU_CSLX_DDI, CSU_ALL_RW },
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{ CSU_CSLX_RESERVED1, CSU_ALL_RW },
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{ CSU_CSLX_USB3_PHY, CSU_ALL_RW },
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{ CSU_CSLX_RESERVED2, CSU_ALL_RW },
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};
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#endif
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@ -9,6 +9,173 @@
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#include <asm/arch/ns_access.h>
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#include <asm/arch/fsl_serdes.h>
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#ifdef CONFIG_ARCH_LS1021A
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static struct csu_ns_dev ns_dev[] = {
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{ CSU_CSLX_PCIE2_IO, CSU_ALL_RW },
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{ CSU_CSLX_PCIE1_IO, CSU_ALL_RW },
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{ CSU_CSLX_MG2TPR_IP, CSU_ALL_RW },
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{ CSU_CSLX_IFC_MEM, CSU_ALL_RW },
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{ CSU_CSLX_OCRAM, CSU_ALL_RW },
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{ CSU_CSLX_GIC, CSU_ALL_RW },
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{ CSU_CSLX_PCIE1, CSU_ALL_RW },
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{ CSU_CSLX_OCRAM2, CSU_ALL_RW },
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{ CSU_CSLX_QSPI_MEM, CSU_ALL_RW },
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{ CSU_CSLX_PCIE2, CSU_ALL_RW },
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{ CSU_CSLX_SATA, CSU_ALL_RW },
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{ CSU_CSLX_USB3, CSU_ALL_RW },
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{ CSU_CSLX_SERDES, CSU_ALL_RW },
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{ CSU_CSLX_QDMA, CSU_ALL_RW },
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{ CSU_CSLX_LPUART2, CSU_ALL_RW },
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{ CSU_CSLX_LPUART1, CSU_ALL_RW },
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{ CSU_CSLX_LPUART4, CSU_ALL_RW },
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{ CSU_CSLX_LPUART3, CSU_ALL_RW },
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{ CSU_CSLX_LPUART6, CSU_ALL_RW },
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{ CSU_CSLX_LPUART5, CSU_ALL_RW },
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{ CSU_CSLX_DSPI2, CSU_ALL_RW },
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{ CSU_CSLX_DSPI1, CSU_ALL_RW },
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{ CSU_CSLX_QSPI, CSU_ALL_RW },
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{ CSU_CSLX_ESDHC, CSU_ALL_RW },
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{ CSU_CSLX_2D_ACE, CSU_ALL_RW },
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{ CSU_CSLX_IFC, CSU_ALL_RW },
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{ CSU_CSLX_I2C1, CSU_ALL_RW },
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{ CSU_CSLX_USB2, CSU_ALL_RW },
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{ CSU_CSLX_I2C3, CSU_ALL_RW },
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{ CSU_CSLX_I2C2, CSU_ALL_RW },
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{ CSU_CSLX_DUART2, CSU_ALL_RW },
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{ CSU_CSLX_DUART1, CSU_ALL_RW },
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{ CSU_CSLX_WDT2, CSU_ALL_RW },
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{ CSU_CSLX_WDT1, CSU_ALL_RW },
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{ CSU_CSLX_EDMA, CSU_ALL_RW },
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{ CSU_CSLX_SYS_CNT, CSU_ALL_RW },
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{ CSU_CSLX_DMA_MUX2, CSU_ALL_RW },
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{ CSU_CSLX_DMA_MUX1, CSU_ALL_RW },
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{ CSU_CSLX_DDR, CSU_ALL_RW },
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{ CSU_CSLX_QUICC, CSU_ALL_RW },
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{ CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW },
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{ CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW },
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{ CSU_CSLX_SFP, CSU_ALL_RW },
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{ CSU_CSLX_TMU, CSU_ALL_RW },
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{ CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW },
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{ CSU_CSLX_RESERVED0, CSU_ALL_RW },
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{ CSU_CSLX_ETSEC1, CSU_ALL_RW },
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{ CSU_CSLX_SEC5_5, CSU_ALL_RW },
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{ CSU_CSLX_ETSEC3, CSU_ALL_RW },
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{ CSU_CSLX_ETSEC2, CSU_ALL_RW },
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{ CSU_CSLX_GPIO2, CSU_ALL_RW },
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{ CSU_CSLX_GPIO1, CSU_ALL_RW },
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{ CSU_CSLX_GPIO4, CSU_ALL_RW },
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{ CSU_CSLX_GPIO3, CSU_ALL_RW },
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{ CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW },
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{ CSU_CSLX_CSU, CSU_ALL_RW },
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{ CSU_CSLX_ASRC, CSU_ALL_RW },
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{ CSU_CSLX_SPDIF, CSU_ALL_RW },
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{ CSU_CSLX_FLEXCAN2, CSU_ALL_RW },
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{ CSU_CSLX_FLEXCAN1, CSU_ALL_RW },
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{ CSU_CSLX_FLEXCAN4, CSU_ALL_RW },
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{ CSU_CSLX_FLEXCAN3, CSU_ALL_RW },
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{ CSU_CSLX_SAI2, CSU_ALL_RW },
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{ CSU_CSLX_SAI1, CSU_ALL_RW },
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{ CSU_CSLX_SAI4, CSU_ALL_RW },
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{ CSU_CSLX_SAI3, CSU_ALL_RW },
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{ CSU_CSLX_FTM2, CSU_ALL_RW },
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{ CSU_CSLX_FTM1, CSU_ALL_RW },
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{ CSU_CSLX_FTM4, CSU_ALL_RW },
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{ CSU_CSLX_FTM3, CSU_ALL_RW },
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{ CSU_CSLX_FTM6, CSU_ALL_RW },
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{ CSU_CSLX_FTM5, CSU_ALL_RW },
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{ CSU_CSLX_FTM8, CSU_ALL_RW },
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{ CSU_CSLX_FTM7, CSU_ALL_RW },
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{ CSU_CSLX_COP_DCSR, CSU_ALL_RW },
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{ CSU_CSLX_EPU, CSU_ALL_RW },
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{ CSU_CSLX_GDI, CSU_ALL_RW },
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{ CSU_CSLX_DDI, CSU_ALL_RW },
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{ CSU_CSLX_RESERVED1, CSU_ALL_RW },
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{ CSU_CSLX_USB3_PHY, CSU_ALL_RW },
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{ CSU_CSLX_RESERVED2, CSU_ALL_RW },
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};
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#else
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static struct csu_ns_dev ns_dev[] = {
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{CSU_CSLX_PCIE2_IO, CSU_ALL_RW},
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{CSU_CSLX_PCIE1_IO, CSU_ALL_RW},
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{CSU_CSLX_MG2TPR_IP, CSU_ALL_RW},
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{CSU_CSLX_IFC_MEM, CSU_ALL_RW},
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{CSU_CSLX_OCRAM, CSU_ALL_RW},
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{CSU_CSLX_GIC, CSU_ALL_RW},
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{CSU_CSLX_PCIE1, CSU_ALL_RW},
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{CSU_CSLX_OCRAM2, CSU_ALL_RW},
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{CSU_CSLX_QSPI_MEM, CSU_ALL_RW},
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{CSU_CSLX_PCIE2, CSU_ALL_RW},
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{CSU_CSLX_SATA, CSU_ALL_RW},
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{CSU_CSLX_USB1, CSU_ALL_RW},
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{CSU_CSLX_QM_BM_SWPORTAL, CSU_ALL_RW},
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{CSU_CSLX_PCIE3, CSU_ALL_RW},
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{CSU_CSLX_PCIE3_IO, CSU_ALL_RW},
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{CSU_CSLX_USB3, CSU_ALL_RW},
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{CSU_CSLX_USB2, CSU_ALL_RW},
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{CSU_CSLX_PFE, CSU_ALL_RW},
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{CSU_CSLX_SERDES, CSU_ALL_RW},
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{CSU_CSLX_QDMA, CSU_ALL_RW},
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{CSU_CSLX_LPUART2, CSU_ALL_RW},
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{CSU_CSLX_LPUART1, CSU_ALL_RW},
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{CSU_CSLX_LPUART4, CSU_ALL_RW},
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{CSU_CSLX_LPUART3, CSU_ALL_RW},
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{CSU_CSLX_LPUART6, CSU_ALL_RW},
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{CSU_CSLX_LPUART5, CSU_ALL_RW},
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{CSU_CSLX_DSPI1, CSU_ALL_RW},
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{CSU_CSLX_QSPI, CSU_ALL_RW},
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{CSU_CSLX_ESDHC, CSU_ALL_RW},
|
||||
{CSU_CSLX_IFC, CSU_ALL_RW},
|
||||
{CSU_CSLX_I2C1, CSU_ALL_RW},
|
||||
{CSU_CSLX_I2C3, CSU_ALL_RW},
|
||||
{CSU_CSLX_I2C2, CSU_ALL_RW},
|
||||
{CSU_CSLX_DUART2, CSU_ALL_RW},
|
||||
{CSU_CSLX_DUART1, CSU_ALL_RW},
|
||||
{CSU_CSLX_WDT2, CSU_ALL_RW},
|
||||
{CSU_CSLX_WDT1, CSU_ALL_RW},
|
||||
{CSU_CSLX_EDMA, CSU_ALL_RW},
|
||||
{CSU_CSLX_SYS_CNT, CSU_ALL_RW},
|
||||
{CSU_CSLX_DMA_MUX2, CSU_ALL_RW},
|
||||
{CSU_CSLX_DMA_MUX1, CSU_ALL_RW},
|
||||
{CSU_CSLX_DDR, CSU_ALL_RW},
|
||||
{CSU_CSLX_QUICC, CSU_ALL_RW},
|
||||
{CSU_CSLX_DCFG_CCU_RCPM, CSU_ALL_RW},
|
||||
{CSU_CSLX_SECURE_BOOTROM, CSU_ALL_RW},
|
||||
{CSU_CSLX_SFP, CSU_ALL_RW},
|
||||
{CSU_CSLX_TMU, CSU_ALL_RW},
|
||||
{CSU_CSLX_SECURE_MONITOR, CSU_ALL_RW},
|
||||
{CSU_CSLX_SCFG, CSU_ALL_RW},
|
||||
{CSU_CSLX_FM, CSU_ALL_RW},
|
||||
{CSU_CSLX_SEC5_5, CSU_ALL_RW},
|
||||
{CSU_CSLX_BM, CSU_ALL_RW},
|
||||
{CSU_CSLX_QM, CSU_ALL_RW},
|
||||
{CSU_CSLX_GPIO2, CSU_ALL_RW},
|
||||
{CSU_CSLX_GPIO1, CSU_ALL_RW},
|
||||
{CSU_CSLX_GPIO4, CSU_ALL_RW},
|
||||
{CSU_CSLX_GPIO3, CSU_ALL_RW},
|
||||
{CSU_CSLX_PLATFORM_CONT, CSU_ALL_RW},
|
||||
{CSU_CSLX_CSU, CSU_ALL_RW},
|
||||
{CSU_CSLX_IIC4, CSU_ALL_RW},
|
||||
{CSU_CSLX_WDT4, CSU_ALL_RW},
|
||||
{CSU_CSLX_WDT3, CSU_ALL_RW},
|
||||
{CSU_CSLX_ESDHC2, CSU_ALL_RW},
|
||||
{CSU_CSLX_WDT5, CSU_ALL_RW},
|
||||
{CSU_CSLX_SAI2, CSU_ALL_RW},
|
||||
{CSU_CSLX_SAI1, CSU_ALL_RW},
|
||||
{CSU_CSLX_SAI4, CSU_ALL_RW},
|
||||
{CSU_CSLX_SAI3, CSU_ALL_RW},
|
||||
{CSU_CSLX_FTM2, CSU_ALL_RW},
|
||||
{CSU_CSLX_FTM1, CSU_ALL_RW},
|
||||
{CSU_CSLX_FTM4, CSU_ALL_RW},
|
||||
{CSU_CSLX_FTM3, CSU_ALL_RW},
|
||||
{CSU_CSLX_FTM6, CSU_ALL_RW},
|
||||
{CSU_CSLX_FTM5, CSU_ALL_RW},
|
||||
{CSU_CSLX_FTM8, CSU_ALL_RW},
|
||||
{CSU_CSLX_FTM7, CSU_ALL_RW},
|
||||
{CSU_CSLX_DSCR, CSU_ALL_RW},
|
||||
};
|
||||
#endif
|
||||
|
||||
void set_devices_ns_access(unsigned long index, u16 val)
|
||||
{
|
||||
u32 *base = (u32 *)CONFIG_SYS_FSL_CSU_ADDR;
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue