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clk: Add MPC83xx clock driver
Add a clock driver for the MPC83xx architecture. Signed-off-by: Mario Six <mario.six@gdsys.cc>
This commit is contained in:
Mario Six
Simon Glass
parent
76fdad1f21
commit
07d538d281
11 changed files with 938 additions and 1 deletions
23
Documentation/devicetree/bindings/clk/fsl,mpc83xx-clk.txt
Normal file
23
Documentation/devicetree/bindings/clk/fsl,mpc83xx-clk.txt
Normal file
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@ -0,0 +1,23 @@
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MPC83xx system clock devices
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MPC83xx SoCs supply a variety of clocks to drive various components of a
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system.
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Required properties:
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- compatible: must be one of "fsl,mpc8308-clk",
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"fsl,mpc8309-clk",
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"fsl,mpc8313-clk",
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"fsl,mpc8315-clk",
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"fsl,mpc832x-clk",
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"fsl,mpc8349-clk",
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"fsl,mpc8360-clk",
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"fsl,mpc8379-clk"
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depending on which SoC is employed
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- #clock-cells: Must be 1
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Example:
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socclocks: clocks {
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compatible = "fsl,mpc832x-clk";
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#clock-cells = <1>;
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};
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@ -523,6 +523,9 @@ F: drivers/ram/mpc83xx_sdram.c
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F: include/dt-bindings/memory/mpc83xx-sdram.h
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F: drivers/sysreset/sysreset_mpc83xx.c
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F: drivers/sysreset/sysreset_mpc83xx.h
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F: drivers/clk/mpc83xx_clk.c
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F: drivers/clk/mpc83xx_clk.h
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F: include/dt-bindings/clk/mpc83xx-clk.h
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F: arch/powerpc/cpu/mpc83xx/
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F: arch/powerpc/include/asm/arch-mpc83xx/
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@ -6,6 +6,8 @@
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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*/
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#ifndef CONFIG_CLK_MPC83XX
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#include <common.h>
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#include <mpc83xx.h>
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#include <command.h>
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@ -590,3 +592,5 @@ U_BOOT_CMD(clocks, 1, 0, do_clocks,
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"print clock configuration",
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" clocks"
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);
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#endif
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74
arch/powerpc/include/asm/arch-mpc83xx/soc.h
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74
arch/powerpc/include/asm/arch-mpc83xx/soc.h
Normal file
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@ -0,0 +1,74 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2018
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* Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
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*/
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#ifndef _MPC83XX_SOC_H_
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#define _MPC83XX_SOC_H_
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enum soc_type {
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SOC_MPC8308,
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SOC_MPC8309,
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SOC_MPC8313,
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SOC_MPC8315,
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SOC_MPC832X,
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SOC_MPC8349,
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SOC_MPC8360,
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SOC_MPC8379,
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};
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bool mpc83xx_has_sdhc(int type)
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{
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return (type == SOC_MPC8308) ||
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(type == SOC_MPC8309) ||
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(type == SOC_MPC8379);
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}
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bool mpc83xx_has_tsec(int type)
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{
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return (type == SOC_MPC8308) ||
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(type == SOC_MPC8313) ||
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(type == SOC_MPC8315) ||
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(type == SOC_MPC8349) ||
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(type == SOC_MPC8379);
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}
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bool mpc83xx_has_pcie1(int type)
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{
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return (type == SOC_MPC8308) ||
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(type == SOC_MPC8315) ||
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(type == SOC_MPC8379);
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}
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bool mpc83xx_has_pcie2(int type)
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{
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return (type == SOC_MPC8315) ||
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(type == SOC_MPC8379);
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}
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bool mpc83xx_has_sata(int type)
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{
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return (type == SOC_MPC8315) ||
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(type == SOC_MPC8379);
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}
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bool mpc83xx_has_pci(int type)
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{
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return type != SOC_MPC8308;
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}
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bool mpc83xx_has_second_i2c(int type)
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{
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return (type != SOC_MPC8315) &&
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(type != SOC_MPC832X);
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}
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bool mpc83xx_has_quicc_engine(int type)
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{
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return (type == SOC_MPC8309) ||
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(type == SOC_MPC832X) ||
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(type == SOC_MPC8360);
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}
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#endif /* _MPC83XX_SOC_H_ */
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@ -75,7 +75,7 @@
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/* All PPC boards must swap IDE bytes */
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#define CONFIG_IDE_SWAP_IO
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#if defined(CONFIG_DM_SERIAL)
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#if defined(CONFIG_DM_SERIAL) && !defined(CONFIG_CLK_MPC83XX)
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/*
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* TODO: Convert this to a clock driver exists that can give us the UART
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* clock here.
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@ -30,6 +30,9 @@ struct arch_global_data {
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#endif
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/* TODO: sjg@chromium.org: Should these be unslgned long? */
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#if defined(CONFIG_MPC83xx)
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#ifdef CONFIG_CLK_MPC83XX
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u32 core_clk;
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#else
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/* There are other clocks in the MPC83XX */
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u32 csb_clk;
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# if defined(CONFIG_MPC8308) || defined(CONFIG_MPC831x) || \
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@ -62,6 +65,7 @@ struct arch_global_data {
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u32 mem_sec_clk;
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# endif /* CONFIG_MPC8360 */
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#endif
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#endif
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#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
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u32 lbc_clk;
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void *cpu;
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@ -107,4 +107,10 @@ config ICS8N3QV01
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Crystal Oscillator). The output frequency can be programmed via an
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I2C interface.
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config CLK_MPC83XX
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bool "Enable MPC83xx clock driver"
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depends on CLK
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help
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Support for the clock driver of the MPC83xx series of SoCs.
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endmenu
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@ -18,6 +18,7 @@ obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o
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obj-$(CONFIG_CLK_BOSTON) += clk_boston.o
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obj-$(CONFIG_CLK_EXYNOS) += exynos/
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obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
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obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o
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obj-$(CONFIG_CLK_OWL) += owl/
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obj-$(CONFIG_CLK_RENESAS) += renesas/
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obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o
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410
drivers/clk/mpc83xx_clk.c
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410
drivers/clk/mpc83xx_clk.c
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@ -0,0 +1,410 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2017
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* Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <dm/lists.h>
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#include <dt-bindings/clk/mpc83xx-clk.h>
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#include <asm/arch/soc.h>
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#include "mpc83xx_clk.h"
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DECLARE_GLOBAL_DATA_PTR;
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/**
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* struct mpc83xx_clk_priv - Private data structure for the MPC83xx clock
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* driver
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* @speed: Array containing the speed values of all system clocks (initialized
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* once, then only read back)
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*/
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struct mpc83xx_clk_priv {
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u32 speed[MPC83XX_CLK_COUNT];
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};
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/**
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* is_clk_valid() - Check if clock ID is valid for given clock device
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* @clk: The clock device for which to check a clock ID
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* @id: The clock ID to check
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*
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* Return: true if clock ID is valid for clock device, false if not
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*/
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static inline bool is_clk_valid(struct udevice *clk, int id)
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{
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ulong type = dev_get_driver_data(clk);
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switch (id) {
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case MPC83XX_CLK_MEM:
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return true;
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case MPC83XX_CLK_MEM_SEC:
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return type == SOC_MPC8360;
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case MPC83XX_CLK_ENC:
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return (type == SOC_MPC8308) || (type == SOC_MPC8309);
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case MPC83XX_CLK_I2C1:
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return true;
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case MPC83XX_CLK_TDM:
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return type == SOC_MPC8315;
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case MPC83XX_CLK_SDHC:
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return mpc83xx_has_sdhc(type);
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case MPC83XX_CLK_TSEC1:
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case MPC83XX_CLK_TSEC2:
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return mpc83xx_has_tsec(type);
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case MPC83XX_CLK_USBDR:
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return type == SOC_MPC8360;
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case MPC83XX_CLK_USBMPH:
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return type == SOC_MPC8349;
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case MPC83XX_CLK_PCIEXP1:
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return mpc83xx_has_pcie1(type);
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case MPC83XX_CLK_PCIEXP2:
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return mpc83xx_has_pcie2(type);
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case MPC83XX_CLK_SATA:
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return mpc83xx_has_sata(type);
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case MPC83XX_CLK_DMAC:
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return (type == SOC_MPC8308) || (type == SOC_MPC8309);
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case MPC83XX_CLK_PCI:
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return mpc83xx_has_pci(type);
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case MPC83XX_CLK_CSB:
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return true;
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case MPC83XX_CLK_I2C2:
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return mpc83xx_has_second_i2c(type);
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case MPC83XX_CLK_QE:
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case MPC83XX_CLK_BRG:
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return mpc83xx_has_quicc_engine(type) && (type != SOC_MPC8309);
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case MPC83XX_CLK_LCLK:
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case MPC83XX_CLK_LBIU:
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case MPC83XX_CLK_CORE:
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return true;
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}
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return false;
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}
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/**
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* init_single_clk() - Initialize a clock with a given ID
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* @dev: The clock device for which to initialize the clock
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* @clk: The clock ID
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*
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* The clock speed is read from the hardware's registers, and stored in the
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* private data structure of the driver. From there it is only retrieved, and
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* not set.
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*
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* Return: 0 if OK, -ve on error
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*/
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static int init_single_clk(struct udevice *dev, int clk)
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{
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struct mpc83xx_clk_priv *priv = dev_get_priv(dev);
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immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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ulong type = dev_get_driver_data(dev);
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struct clk_mode mode;
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ulong mask;
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u32 csb_clk = get_csb_clk(im);
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int ret;
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ret = retrieve_mode(clk, type, &mode);
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if (ret) {
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debug("%s: Could not retrieve mode for clk %d (ret = %d)\n",
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dev->name, clk, ret);
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return ret;
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}
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if (mode.type == TYPE_INVALID) {
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debug("%s: clock %d invalid\n", dev->name, clk);
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return -EINVAL;
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}
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if (mode.type == TYPE_SCCR_STANDARD) {
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mask = GENMASK(31 - mode.low, 31 - mode.high);
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switch (sccr_field(im, mask)) {
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case 0:
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priv->speed[clk] = 0;
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break;
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case 1:
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priv->speed[clk] = csb_clk;
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break;
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case 2:
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priv->speed[clk] = csb_clk / 2;
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break;
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case 3:
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priv->speed[clk] = csb_clk / 3;
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break;
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default:
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priv->speed[clk] = 0;
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}
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return 0;
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}
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if (mode.type == TYPE_SPMR_DIRECT_MULTIPLY) {
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mask = GENMASK(31 - mode.low, 31 - mode.high);
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priv->speed[clk] = csb_clk * (1 + sccr_field(im, mask));
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return 0;
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}
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if (clk == MPC83XX_CLK_CSB || clk == MPC83XX_CLK_I2C2) {
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priv->speed[clk] = csb_clk; /* i2c-2 clk is equal to csb clk */
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return 0;
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}
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if (clk == MPC83XX_CLK_QE || clk == MPC83XX_CLK_BRG) {
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u32 pci_sync_in = get_pci_sync_in(im);
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u32 qepmf = spmr_field(im, SPMR_CEPMF);
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u32 qepdf = spmr_field(im, SPMR_CEPDF);
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u32 qe_clk = (pci_sync_in * qepmf) / (1 + qepdf);
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if (clk == MPC83XX_CLK_QE)
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priv->speed[clk] = qe_clk;
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else
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priv->speed[clk] = qe_clk / 2;
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return 0;
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}
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if (clk == MPC83XX_CLK_LCLK || clk == MPC83XX_CLK_LBIU) {
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u32 lbiu_clk = csb_clk *
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(1 + spmr_field(im, SPMR_LBIUCM));
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u32 clkdiv = lcrr_field(im, LCRR_CLKDIV);
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if (clk == MPC83XX_CLK_LBIU)
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priv->speed[clk] = lbiu_clk;
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switch (clkdiv) {
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case 2:
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case 4:
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case 8:
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priv->speed[clk] = lbiu_clk / clkdiv;
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break;
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default:
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/* unknown lcrr */
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priv->speed[clk] = 0;
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}
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return 0;
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}
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if (clk == MPC83XX_CLK_CORE) {
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u8 corepll = spmr_field(im, SPMR_COREPLL);
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u32 corecnf_tab_index = ((corepll & 0x1F) << 2) |
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((corepll & 0x60) >> 5);
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if (corecnf_tab_index > (ARRAY_SIZE(corecnf_tab))) {
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debug("%s: Core configuration index %02x too high; possible wrong value",
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dev->name, corecnf_tab_index);
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return -EINVAL;
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}
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switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) {
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case RAT_BYP:
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case RAT_1_TO_1:
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priv->speed[clk] = csb_clk;
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break;
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case RAT_1_5_TO_1:
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priv->speed[clk] = (3 * csb_clk) / 2;
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break;
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case RAT_2_TO_1:
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priv->speed[clk] = 2 * csb_clk;
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break;
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case RAT_2_5_TO_1:
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priv->speed[clk] = (5 * csb_clk) / 2;
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break;
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case RAT_3_TO_1:
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priv->speed[clk] = 3 * csb_clk;
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break;
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default:
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/* unknown core to csb ratio */
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priv->speed[clk] = 0;
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}
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return 0;
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}
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/* Unknown clk value -> error */
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debug("%s: clock %d invalid\n", dev->name, clk);
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return -EINVAL;
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}
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/**
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* init_all_clks() - Initialize all clocks of a clock device
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* @dev: The clock device whose clocks should be initialized
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*
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* Return: 0 if OK, -ve on error
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*/
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static inline int init_all_clks(struct udevice *dev)
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{
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int i;
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for (i = 0; i < MPC83XX_CLK_COUNT; i++) {
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int ret;
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if (!is_clk_valid(dev, i))
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continue;
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ret = init_single_clk(dev, i);
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if (ret) {
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debug("%s: Failed to initialize %s clock\n",
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dev->name, names[i]);
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return ret;
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}
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}
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return 0;
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}
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static int mpc83xx_clk_request(struct clk *clock)
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{
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/* Reject requests of clocks that are not available */
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if (is_clk_valid(clock->dev, clock->id))
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return 0;
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else
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return -ENODEV;
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}
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static ulong mpc83xx_clk_get_rate(struct clk *clk)
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{
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struct mpc83xx_clk_priv *priv = dev_get_priv(clk->dev);
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if (clk->id >= MPC83XX_CLK_COUNT) {
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debug("%s: clock index %lu invalid\n", __func__, clk->id);
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return 0;
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}
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return priv->speed[clk->id];
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}
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int get_clocks(void)
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{
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/* Empty implementation to keep the prototype in common.h happy */
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return 0;
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}
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int get_serial_clock(void)
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{
|
||||
struct mpc83xx_clk_priv *priv;
|
||||
struct udevice *clk;
|
||||
int ret;
|
||||
|
||||
ret = uclass_first_device_err(UCLASS_CLK, &clk);
|
||||
if (ret) {
|
||||
debug("%s: Could not get clock device\n", __func__);
|
||||
return ret;
|
||||
}
|
||||
|
||||
priv = dev_get_priv(clk);
|
||||
|
||||
return priv->speed[MPC83XX_CLK_CSB];
|
||||
}
|
||||
|
||||
const struct clk_ops mpc83xx_clk_ops = {
|
||||
.request = mpc83xx_clk_request,
|
||||
.get_rate = mpc83xx_clk_get_rate,
|
||||
};
|
||||
|
||||
static const struct udevice_id mpc83xx_clk_match[] = {
|
||||
{ .compatible = "fsl,mpc8308-clk", .data = SOC_MPC8308 },
|
||||
{ .compatible = "fsl,mpc8309-clk", .data = SOC_MPC8309 },
|
||||
{ .compatible = "fsl,mpc8313-clk", .data = SOC_MPC8313 },
|
||||
{ .compatible = "fsl,mpc8315-clk", .data = SOC_MPC8315 },
|
||||
{ .compatible = "fsl,mpc832x-clk", .data = SOC_MPC832X },
|
||||
{ .compatible = "fsl,mpc8349-clk", .data = SOC_MPC8349 },
|
||||
{ .compatible = "fsl,mpc8360-clk", .data = SOC_MPC8360 },
|
||||
{ .compatible = "fsl,mpc8379-clk", .data = SOC_MPC8379 },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static int mpc83xx_clk_probe(struct udevice *dev)
|
||||
{
|
||||
struct mpc83xx_clk_priv *priv = dev_get_priv(dev);
|
||||
ulong type;
|
||||
int ret;
|
||||
|
||||
ret = init_all_clks(dev);
|
||||
if (ret) {
|
||||
debug("%s: Could not initialize all clocks (ret = %d)\n",
|
||||
dev->name, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
type = dev_get_driver_data(dev);
|
||||
|
||||
if (mpc83xx_has_sdhc(type))
|
||||
gd->arch.sdhc_clk = priv->speed[MPC83XX_CLK_SDHC];
|
||||
|
||||
gd->arch.core_clk = priv->speed[MPC83XX_CLK_CORE];
|
||||
gd->arch.i2c1_clk = priv->speed[MPC83XX_CLK_I2C1];
|
||||
if (mpc83xx_has_second_i2c(type))
|
||||
gd->arch.i2c2_clk = priv->speed[MPC83XX_CLK_I2C2];
|
||||
|
||||
gd->mem_clk = priv->speed[MPC83XX_CLK_MEM];
|
||||
|
||||
if (mpc83xx_has_pci(type))
|
||||
gd->pci_clk = priv->speed[MPC83XX_CLK_PCI];
|
||||
|
||||
gd->cpu_clk = priv->speed[MPC83XX_CLK_CORE];
|
||||
gd->bus_clk = priv->speed[MPC83XX_CLK_CSB];
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mpc83xx_clk_bind(struct udevice *dev)
|
||||
{
|
||||
int ret;
|
||||
struct udevice *sys_child;
|
||||
|
||||
/*
|
||||
* Since there is no corresponding device tree entry, and since the
|
||||
* clock driver has to be present in either case, bind the sysreset
|
||||
* driver here.
|
||||
*/
|
||||
ret = device_bind_driver(dev, "mpc83xx_sysreset", "sysreset",
|
||||
&sys_child);
|
||||
if (ret)
|
||||
debug("%s: No sysreset driver: ret=%d\n",
|
||||
dev->name, ret);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_DRIVER(mpc83xx_clk) = {
|
||||
.name = "mpc83xx_clk",
|
||||
.id = UCLASS_CLK,
|
||||
.of_match = mpc83xx_clk_match,
|
||||
.ops = &mpc83xx_clk_ops,
|
||||
.probe = mpc83xx_clk_probe,
|
||||
.priv_auto_alloc_size = sizeof(struct mpc83xx_clk_priv),
|
||||
.bind = mpc83xx_clk_bind,
|
||||
};
|
||||
|
||||
static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
int i;
|
||||
char buf[32];
|
||||
struct udevice *clk;
|
||||
int ret;
|
||||
struct mpc83xx_clk_priv *priv;
|
||||
|
||||
ret = uclass_first_device_err(UCLASS_CLK, &clk);
|
||||
if (ret) {
|
||||
debug("%s: Could not get clock device\n", __func__);
|
||||
return ret;
|
||||
}
|
||||
|
||||
for (i = 0; i < MPC83XX_CLK_COUNT; i++) {
|
||||
if (!is_clk_valid(clk, i))
|
||||
continue;
|
||||
|
||||
priv = dev_get_priv(clk);
|
||||
|
||||
printf("%s = %s MHz\n", names[i], strmhz(buf, priv->speed[i]));
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(clocks, 1, 1, do_clocks,
|
||||
"display values of SoC's clocks",
|
||||
""
|
||||
);
|
||||
379
drivers/clk/mpc83xx_clk.h
Normal file
379
drivers/clk/mpc83xx_clk.h
Normal file
|
|
@ -0,0 +1,379 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2018
|
||||
* Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
|
||||
*/
|
||||
|
||||
/**
|
||||
* enum ratio - Description of a core clock ratio
|
||||
* @RAT_UNK: Unknown ratio
|
||||
* @RAT_BYP: Bypass
|
||||
* @RAT_1_TO_8: Ratio 1:8
|
||||
* @RAT_1_TO_4: Ratio 1:4
|
||||
* @RAT_1_TO_2: Ratio 1:2
|
||||
* @RAT_1_TO_1: Ratio 1:1
|
||||
* @RAT_1_5_TO_1: Ratio 1.5:1
|
||||
* @RAT_2_TO_1: Ratio 2:1
|
||||
* @RAT_2_5_TO_1: Ratio 2.5:1
|
||||
* @RAT_3_TO_1: Ratio 3:1
|
||||
*/
|
||||
enum ratio {
|
||||
RAT_UNK,
|
||||
RAT_BYP,
|
||||
RAT_1_TO_8,
|
||||
RAT_1_TO_4,
|
||||
RAT_1_TO_2,
|
||||
RAT_1_TO_1,
|
||||
RAT_1_5_TO_1,
|
||||
RAT_2_TO_1,
|
||||
RAT_2_5_TO_1,
|
||||
RAT_3_TO_1
|
||||
};
|
||||
|
||||
/**
|
||||
* struct corecnf - Description for a core clock configuration
|
||||
* @core_csb_ratio: Core clock frequency to CSB clock frequency ratio
|
||||
* @vco_divider: VCO divider (Core VCO frequency = Core frequency * VCO divider)
|
||||
*/
|
||||
struct corecnf {
|
||||
int core_csb_ratio;
|
||||
int vco_divider;
|
||||
};
|
||||
|
||||
/*
|
||||
* Table with all valid Core CSB frequency ratio / VCO divider combinations as
|
||||
* indexed by the COREPLL field of the SPMR
|
||||
*/
|
||||
static const struct corecnf corecnf_tab[] = {
|
||||
{RAT_BYP, RAT_BYP}, /* 0x00 */
|
||||
{RAT_BYP, RAT_BYP}, /* 0x01 */
|
||||
{RAT_BYP, RAT_BYP}, /* 0x02 */
|
||||
{RAT_BYP, RAT_BYP}, /* 0x03 */
|
||||
{RAT_BYP, RAT_BYP}, /* 0x04 */
|
||||
{RAT_BYP, RAT_BYP}, /* 0x05 */
|
||||
{RAT_BYP, RAT_BYP}, /* 0x06 */
|
||||
{RAT_BYP, RAT_BYP}, /* 0x07 */
|
||||
{RAT_1_TO_1, RAT_1_TO_2}, /* 0x08 */
|
||||
{RAT_1_TO_1, RAT_1_TO_4}, /* 0x09 */
|
||||
{RAT_1_TO_1, RAT_1_TO_8}, /* 0x0A */
|
||||
{RAT_1_TO_1, RAT_1_TO_8}, /* 0x0B */
|
||||
{RAT_1_5_TO_1, RAT_1_TO_2}, /* 0x0C */
|
||||
{RAT_1_5_TO_1, RAT_1_TO_4}, /* 0x0D */
|
||||
{RAT_1_5_TO_1, RAT_1_TO_8}, /* 0x0E */
|
||||
{RAT_1_5_TO_1, RAT_1_TO_8}, /* 0x0F */
|
||||
{RAT_2_TO_1, RAT_1_TO_2}, /* 0x10 */
|
||||
{RAT_2_TO_1, RAT_1_TO_4}, /* 0x11 */
|
||||
{RAT_2_TO_1, RAT_1_TO_8}, /* 0x12 */
|
||||
{RAT_2_TO_1, RAT_1_TO_8}, /* 0x13 */
|
||||
{RAT_2_5_TO_1, RAT_1_TO_2}, /* 0x14 */
|
||||
{RAT_2_5_TO_1, RAT_1_TO_4}, /* 0x15 */
|
||||
{RAT_2_5_TO_1, RAT_1_TO_8}, /* 0x16 */
|
||||
{RAT_2_5_TO_1, RAT_1_TO_8}, /* 0x17 */
|
||||
{RAT_3_TO_1, RAT_1_TO_2}, /* 0x18 */
|
||||
{RAT_3_TO_1, RAT_1_TO_4}, /* 0x19 */
|
||||
{RAT_3_TO_1, RAT_1_TO_8}, /* 0x1A */
|
||||
{RAT_3_TO_1, RAT_1_TO_8}, /* 0x1B */
|
||||
};
|
||||
|
||||
/**
|
||||
* enum reg_type - Register to read a field from
|
||||
* @REG_SCCR: Use the SCCR register
|
||||
* @REG_SPMR: Use the SPMR register
|
||||
*/
|
||||
enum reg_type {
|
||||
REG_SCCR,
|
||||
REG_SPMR,
|
||||
};
|
||||
|
||||
/**
|
||||
* enum mode_type - Description of how to read a specific frequency value
|
||||
* @TYPE_INVALID: Unknown type, will provoke error
|
||||
* @TYPE_SCCR_STANDARD: Read a field from the SCCR register, and use it
|
||||
* as a divider for the CSB clock to compute the
|
||||
* frequency
|
||||
* @TYPE_SCCR_ONOFF: The field describes a bit flag that can turn the
|
||||
* clock on or off
|
||||
* @TYPE_SPMR_DIRECT_MULTIPLY: Read a field from the SPMR register, and use it
|
||||
* as a multiplier for the CSB clock to compute the
|
||||
* frequency
|
||||
* @TYPE_SPECIAL: The frequency is calculated in a non-standard way
|
||||
*/
|
||||
enum mode_type {
|
||||
TYPE_INVALID = 0,
|
||||
TYPE_SCCR_STANDARD,
|
||||
TYPE_SCCR_ONOFF,
|
||||
TYPE_SPMR_DIRECT_MULTIPLY,
|
||||
TYPE_SPECIAL,
|
||||
};
|
||||
|
||||
/* Map of each clock index to its human-readable name */
|
||||
static const char * const names[] = {
|
||||
[MPC83XX_CLK_CORE] = "Core",
|
||||
[MPC83XX_CLK_CSB] = "Coherent System Bus",
|
||||
[MPC83XX_CLK_QE] = "QE",
|
||||
[MPC83XX_CLK_BRG] = "BRG",
|
||||
[MPC83XX_CLK_LBIU] = "Local Bus Controller",
|
||||
[MPC83XX_CLK_LCLK] = "Local Bus",
|
||||
[MPC83XX_CLK_MEM] = "DDR",
|
||||
[MPC83XX_CLK_MEM_SEC] = "DDR Secondary",
|
||||
[MPC83XX_CLK_ENC] = "SEC",
|
||||
[MPC83XX_CLK_I2C1] = "I2C1",
|
||||
[MPC83XX_CLK_I2C2] = "I2C2",
|
||||
[MPC83XX_CLK_TDM] = "TDM",
|
||||
[MPC83XX_CLK_SDHC] = "SDHC",
|
||||
[MPC83XX_CLK_TSEC1] = "TSEC1",
|
||||
[MPC83XX_CLK_TSEC2] = "TSEC2",
|
||||
[MPC83XX_CLK_USBDR] = "USB DR",
|
||||
[MPC83XX_CLK_USBMPH] = "USB MPH",
|
||||
[MPC83XX_CLK_PCIEXP1] = "PCIEXP1",
|
||||
[MPC83XX_CLK_PCIEXP2] = "PCIEXP2",
|
||||
[MPC83XX_CLK_SATA] = "SATA",
|
||||
[MPC83XX_CLK_DMAC] = "DMAC",
|
||||
[MPC83XX_CLK_PCI] = "PCI",
|
||||
};
|
||||
|
||||
/**
|
||||
* struct clk_mode - Structure for clock mode descriiptions
|
||||
* @low: The low bit of the data field to read for this mode (may not apply to
|
||||
* some modes)
|
||||
* @high: The high bit of the data field to read for this mode (may not apply to
|
||||
* some modes)
|
||||
* @type: The type of the mode description (one of enum mode_type)
|
||||
*/
|
||||
struct clk_mode {
|
||||
u8 low;
|
||||
u8 high;
|
||||
int type;
|
||||
};
|
||||
|
||||
/**
|
||||
* set_mode() - Build a clock mode description from data
|
||||
* @mode: The clock mode description to be filled out
|
||||
* @low: The low bit of the data field to read for this mode (may not apply to
|
||||
* some modes)
|
||||
* @high: The high bit of the data field to read for this mode (may not apply to
|
||||
* some modes)
|
||||
* @type: The type of the mode description (one of enum mode_type)
|
||||
*
|
||||
* Clock mode descriptions are a succinct description of how to read a specific
|
||||
* clock's rate from the hardware; usually by reading a specific field of a
|
||||
* register, such a s the SCCR register, but some types use different methods
|
||||
* for obtaining the clock rate.
|
||||
*/
|
||||
static void set_mode(struct clk_mode *mode, u8 low, u8 high, int type)
|
||||
{
|
||||
mode->low = low;
|
||||
mode->high = high;
|
||||
mode->type = type;
|
||||
}
|
||||
|
||||
/**
|
||||
* retrieve_mode() - Get the clock mode description for a specific clock
|
||||
* @clk: The identifier of the clock for which the clock description should
|
||||
* be retrieved
|
||||
* @soc_type: The type of MPC83xx SoC for which the clock description should be
|
||||
* retrieved
|
||||
* @mode: Pointer to a clk_mode structure to be filled with data for the
|
||||
* clock
|
||||
*
|
||||
* Since some clock rate are stored in different places on different MPC83xx
|
||||
* SoCs, the SoC type has to be supplied along with the clock's identifier.
|
||||
*
|
||||
* Return: 0 if OK, -ve on error
|
||||
*/
|
||||
static int retrieve_mode(int clk, int soc_type, struct clk_mode *mode)
|
||||
{
|
||||
switch (clk) {
|
||||
case MPC83XX_CLK_CORE:
|
||||
case MPC83XX_CLK_CSB:
|
||||
case MPC83XX_CLK_QE:
|
||||
case MPC83XX_CLK_BRG:
|
||||
case MPC83XX_CLK_LCLK:
|
||||
case MPC83XX_CLK_I2C2:
|
||||
set_mode(mode, 0, 0, TYPE_SPECIAL);
|
||||
break;
|
||||
case MPC83XX_CLK_MEM:
|
||||
set_mode(mode, 1, 1, TYPE_SPMR_DIRECT_MULTIPLY);
|
||||
break;
|
||||
case MPC83XX_CLK_LBIU:
|
||||
case MPC83XX_CLK_MEM_SEC:
|
||||
set_mode(mode, 0, 0, TYPE_SPMR_DIRECT_MULTIPLY);
|
||||
break;
|
||||
case MPC83XX_CLK_TSEC1:
|
||||
set_mode(mode, 0, 1, TYPE_SCCR_STANDARD);
|
||||
break;
|
||||
case MPC83XX_CLK_TSEC2:
|
||||
if (soc_type == SOC_MPC8313) /* I2C and TSEC2 are the same register */
|
||||
set_mode(mode, 2, 3, TYPE_SCCR_STANDARD);
|
||||
else /* FIXME(mario.six@gdsys.cc): This has separate enable/disable bit! */
|
||||
set_mode(mode, 0, 1, TYPE_SCCR_STANDARD);
|
||||
break;
|
||||
case MPC83XX_CLK_SDHC:
|
||||
set_mode(mode, 4, 5, TYPE_SCCR_STANDARD);
|
||||
break;
|
||||
case MPC83XX_CLK_ENC:
|
||||
set_mode(mode, 6, 7, TYPE_SCCR_STANDARD);
|
||||
break;
|
||||
case MPC83XX_CLK_I2C1:
|
||||
if (soc_type == SOC_MPC8349)
|
||||
set_mode(mode, 2, 3, TYPE_SCCR_STANDARD);
|
||||
else /* I2C and ENC are the same register */
|
||||
set_mode(mode, 6, 7, TYPE_SCCR_STANDARD);
|
||||
break;
|
||||
case MPC83XX_CLK_PCIEXP1:
|
||||
set_mode(mode, 10, 11, TYPE_SCCR_STANDARD);
|
||||
break;
|
||||
case MPC83XX_CLK_PCIEXP2:
|
||||
set_mode(mode, 12, 13, TYPE_SCCR_STANDARD);
|
||||
break;
|
||||
case MPC83XX_CLK_USBDR:
|
||||
if (soc_type == SOC_MPC8313 || soc_type == SOC_MPC8349)
|
||||
set_mode(mode, 10, 11, TYPE_SCCR_STANDARD);
|
||||
else
|
||||
set_mode(mode, 8, 9, TYPE_SCCR_STANDARD);
|
||||
break;
|
||||
case MPC83XX_CLK_USBMPH:
|
||||
set_mode(mode, 8, 9, TYPE_SCCR_STANDARD);
|
||||
break;
|
||||
case MPC83XX_CLK_PCI:
|
||||
set_mode(mode, 15, 15, TYPE_SCCR_ONOFF);
|
||||
break;
|
||||
case MPC83XX_CLK_DMAC:
|
||||
set_mode(mode, 26, 27, TYPE_SCCR_STANDARD);
|
||||
break;
|
||||
case MPC83XX_CLK_SATA:
|
||||
/* FIXME(mario.six@gdsys.cc): All SATA controllers must have the same clock ratio */
|
||||
if (soc_type == SOC_MPC8379) {
|
||||
set_mode(mode, 24, 25, TYPE_SCCR_STANDARD);
|
||||
set_mode(mode, 26, 27, TYPE_SCCR_STANDARD);
|
||||
set_mode(mode, 28, 29, TYPE_SCCR_STANDARD);
|
||||
set_mode(mode, 30, 31, TYPE_SCCR_STANDARD);
|
||||
} else {
|
||||
set_mode(mode, 18, 19, TYPE_SCCR_STANDARD);
|
||||
set_mode(mode, 20, 21, TYPE_SCCR_STANDARD);
|
||||
}
|
||||
break;
|
||||
case MPC83XX_CLK_TDM:
|
||||
set_mode(mode, 26, 27, TYPE_SCCR_STANDARD);
|
||||
break;
|
||||
default:
|
||||
debug("%s: Unknown clock type %d on soc type %d\n",
|
||||
__func__, clk, soc_type);
|
||||
set_mode(mode, 0, 0, TYPE_INVALID);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* get_spmr() - Read the SPMR (System PLL Mode Register)
|
||||
* @im: Pointer to the MPC83xx main register map in question
|
||||
*
|
||||
* Return: The SPMR value as a 32-bit number.
|
||||
*/
|
||||
static inline u32 get_spmr(immap_t *im)
|
||||
{
|
||||
u32 res = in_be32(&im->clk.spmr);
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
/**
|
||||
* get_sccr() - Read the SCCR (System Clock Control Register)
|
||||
* @im: Pointer to the MPC83xx main register map in question
|
||||
*
|
||||
* Return: The SCCR value as a 32-bit number.
|
||||
*/
|
||||
static inline u32 get_sccr(immap_t *im)
|
||||
{
|
||||
u32 res = in_be32(&im->clk.sccr);
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
/**
|
||||
* get_lcrr() - Read the LCRR (Clock Ratio Register)
|
||||
* @im: Pointer to the MPC83xx main register map in question
|
||||
*
|
||||
* Return: The LCRR value as a 32-bit number.
|
||||
*/
|
||||
static inline u32 get_lcrr(immap_t *im)
|
||||
{
|
||||
u32 res = in_be32(&im->im_lbc.lcrr);
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
/**
|
||||
* get_pci_sync_in() - Read the PCI synchronization clock speed
|
||||
* @im: Pointer to the MPC83xx main register map in question
|
||||
*
|
||||
* Return: The PCI synchronization clock speed value as a 32-bit number.
|
||||
*/
|
||||
static inline u32 get_pci_sync_in(immap_t *im)
|
||||
{
|
||||
u8 clkin_div;
|
||||
|
||||
clkin_div = (get_spmr(im) & SPMR_CKID) >> SPMR_CKID_SHIFT;
|
||||
return CONFIG_SYS_CLK_FREQ / (1 + clkin_div);
|
||||
}
|
||||
|
||||
/**
|
||||
* get_csb_clk() - Read the CSB (Coheren System Bus) clock speed
|
||||
* @im: Pointer to the MPC83xx main register map in question
|
||||
*
|
||||
* Return: The CSB clock speed value as a 32-bit number.
|
||||
*/
|
||||
static inline u32 get_csb_clk(immap_t *im)
|
||||
{
|
||||
u8 spmf;
|
||||
|
||||
spmf = (get_spmr(im) & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
|
||||
return CONFIG_SYS_CLK_FREQ * spmf;
|
||||
}
|
||||
|
||||
/**
|
||||
* spmr_field() - Read a specific SPMR field
|
||||
* @im: Pointer to the MPC83xx main register map in question
|
||||
* @mask: A bitmask that describes the bitfield to be read
|
||||
*
|
||||
* Return: The value of the bit field as a 32-bit number.
|
||||
*/
|
||||
static inline uint spmr_field(immap_t *im, u32 mask)
|
||||
{
|
||||
/* Extract shift from bitmask */
|
||||
uint shift = mask ? ffs(mask) - 1 : 0;
|
||||
|
||||
return (get_spmr(im) & mask) >> shift;
|
||||
}
|
||||
|
||||
/**
|
||||
* sccr_field() - Read a specific SCCR field
|
||||
* @im: Pointer to the MPC83xx main register map in question
|
||||
* @mask: A bitmask that describes the bitfield to be read
|
||||
*
|
||||
* Return: The value of the bit field as a 32-bit number.
|
||||
*/
|
||||
static inline uint sccr_field(immap_t *im, u32 mask)
|
||||
{
|
||||
/* Extract shift from bitmask */
|
||||
uint shift = mask ? ffs(mask) - 1 : 0;
|
||||
|
||||
return (get_sccr(im) & mask) >> shift;
|
||||
}
|
||||
|
||||
/**
|
||||
* lcrr_field() - Read a specific LCRR field
|
||||
* @im: Pointer to the MPC83xx main register map in question
|
||||
* @mask: A bitmask that describes the bitfield to be read
|
||||
*
|
||||
* Return: The value of the bit field as a 32-bit number.
|
||||
*/
|
||||
static inline uint lcrr_field(immap_t *im, u32 mask)
|
||||
{
|
||||
/* Extract shift from bitmask */
|
||||
uint shift = mask ? ffs(mask) - 1 : 0;
|
||||
|
||||
return (get_lcrr(im) & mask) >> shift;
|
||||
}
|
||||
33
include/dt-bindings/clk/mpc83xx-clk.h
Normal file
33
include/dt-bindings/clk/mpc83xx-clk.h
Normal file
|
|
@ -0,0 +1,33 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* (C) Copyright 2018
|
||||
* Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
|
||||
*/
|
||||
|
||||
#ifndef DT_BINDINGS_MPC83XX_CLK_H
|
||||
#define DT_BINDINGS_MPC83XX_CLK_H
|
||||
#define MPC83XX_CLK_CORE 0
|
||||
#define MPC83XX_CLK_CSB 1
|
||||
#define MPC83XX_CLK_QE 2
|
||||
#define MPC83XX_CLK_BRG 3
|
||||
#define MPC83XX_CLK_LBIU 4
|
||||
#define MPC83XX_CLK_LCLK 5
|
||||
#define MPC83XX_CLK_MEM 6
|
||||
#define MPC83XX_CLK_MEM_SEC 7
|
||||
#define MPC83XX_CLK_ENC 8
|
||||
#define MPC83XX_CLK_I2C1 9
|
||||
#define MPC83XX_CLK_I2C2 10
|
||||
#define MPC83XX_CLK_TDM 11
|
||||
#define MPC83XX_CLK_SDHC 12
|
||||
#define MPC83XX_CLK_TSEC1 13
|
||||
#define MPC83XX_CLK_TSEC2 14
|
||||
#define MPC83XX_CLK_USBDR 15
|
||||
#define MPC83XX_CLK_USBMPH 16
|
||||
#define MPC83XX_CLK_PCIEXP1 17
|
||||
#define MPC83XX_CLK_PCIEXP2 18
|
||||
#define MPC83XX_CLK_SATA 19
|
||||
#define MPC83XX_CLK_DMAC 20
|
||||
#define MPC83XX_CLK_PCI 21
|
||||
/* Count */
|
||||
#define MPC83XX_CLK_COUNT 22
|
||||
#endif /* DT_BINDINGS_MPC83XX_CLK_H */
|
||||
Loading…
Reference in a new issue