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sunxi: add support for Allwinner H6 SoC
Allwinner H6 is a new SoC from Allwinner features USB3 and PCIe interfaces. This patch adds support for it. The corresponding DTSI file, from Linux next-20180720, is also introduced. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
This commit is contained in:
Icenowy Zheng
Jagan Teki
parent
da2616543a
commit
6f796a9bb4
8 changed files with 546 additions and 2 deletions
288
arch/arm/dts/sun50i-h6.dtsi
Normal file
288
arch/arm/dts/sun50i-h6.dtsi
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@ -0,0 +1,288 @@
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// SPDX-License-Identifier: (GPL-2.0+ or MIT)
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/*
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* Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/sun50i-h6-ccu.h>
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#include <dt-bindings/clock/sun50i-h6-r-ccu.h>
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#include <dt-bindings/reset/sun50i-h6-ccu.h>
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#include <dt-bindings/reset/sun50i-h6-r-ccu.h>
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <0>;
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enable-method = "psci";
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};
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cpu1: cpu@1 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <1>;
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enable-method = "psci";
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};
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cpu2: cpu@2 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <2>;
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enable-method = "psci";
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};
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cpu3: cpu@3 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <3>;
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enable-method = "psci";
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};
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};
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iosc: internal-osc-clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <16000000>;
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clock-accuracy = <300000000>;
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clock-output-names = "iosc";
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};
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osc24M: osc24M_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "osc24M";
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};
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osc32k: osc32k_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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clock-output-names = "osc32k";
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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ccu: clock@3001000 {
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compatible = "allwinner,sun50i-h6-ccu";
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reg = <0x03001000 0x1000>;
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clocks = <&osc24M>, <&osc32k>, <&iosc>;
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clock-names = "hosc", "losc", "iosc";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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gic: interrupt-controller@3021000 {
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compatible = "arm,gic-400";
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reg = <0x03021000 0x1000>,
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<0x03022000 0x2000>,
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<0x03024000 0x2000>,
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<0x03026000 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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pio: pinctrl@300b000 {
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compatible = "allwinner,sun50i-h6-pinctrl";
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reg = <0x0300b000 0x400>;
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interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_APB1>, <&osc24M>, <&osc32k>;
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clock-names = "apb", "hosc", "losc";
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gpio-controller;
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#gpio-cells = <3>;
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interrupt-controller;
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#interrupt-cells = <3>;
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mmc0_pins: mmc0-pins {
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pins = "PF0", "PF1", "PF2", "PF3",
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"PF4", "PF5";
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function = "mmc0";
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drive-strength = <30>;
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bias-pull-up;
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};
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mmc2_pins: mmc2-pins {
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pins = "PC1", "PC4", "PC5", "PC6",
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"PC7", "PC8", "PC9", "PC10",
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"PC11", "PC12", "PC13", "PC14";
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function = "mmc2";
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drive-strength = <30>;
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bias-pull-up;
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};
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uart0_ph_pins: uart0-ph {
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pins = "PH0", "PH1";
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function = "uart0";
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};
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};
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mmc0: mmc@4020000 {
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compatible = "allwinner,sun50i-h6-mmc",
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"allwinner,sun50i-a64-mmc";
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reg = <0x04020000 0x1000>;
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clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
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clock-names = "ahb", "mmc";
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resets = <&ccu RST_BUS_MMC0>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mmc1: mmc@4021000 {
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compatible = "allwinner,sun50i-h6-mmc",
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"allwinner,sun50i-a64-mmc";
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reg = <0x04021000 0x1000>;
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clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
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clock-names = "ahb", "mmc";
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resets = <&ccu RST_BUS_MMC1>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mmc2: mmc@4022000 {
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compatible = "allwinner,sun50i-h6-emmc",
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"allwinner,sun50i-a64-emmc";
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reg = <0x04022000 0x1000>;
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clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
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clock-names = "ahb", "mmc";
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resets = <&ccu RST_BUS_MMC2>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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uart0: serial@5000000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x05000000 0x400>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&ccu CLK_BUS_UART0>;
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resets = <&ccu RST_BUS_UART0>;
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status = "disabled";
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};
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uart1: serial@5000400 {
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compatible = "snps,dw-apb-uart";
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reg = <0x05000400 0x400>;
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interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&ccu CLK_BUS_UART1>;
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resets = <&ccu RST_BUS_UART1>;
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status = "disabled";
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};
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uart2: serial@5000800 {
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compatible = "snps,dw-apb-uart";
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reg = <0x05000800 0x400>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&ccu CLK_BUS_UART2>;
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resets = <&ccu RST_BUS_UART2>;
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status = "disabled";
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};
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uart3: serial@5000c00 {
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compatible = "snps,dw-apb-uart";
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reg = <0x05000c00 0x400>;
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&ccu CLK_BUS_UART3>;
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resets = <&ccu RST_BUS_UART3>;
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status = "disabled";
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};
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r_ccu: clock@7010000 {
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compatible = "allwinner,sun50i-h6-r-ccu";
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reg = <0x07010000 0x400>;
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clocks = <&osc24M>, <&osc32k>, <&iosc>,
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<&ccu CLK_PLL_PERIPH0>;
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clock-names = "hosc", "losc", "iosc", "pll-periph";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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r_intc: interrupt-controller@7021000 {
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compatible = "allwinner,sun50i-h6-r-intc",
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"allwinner,sun6i-a31-r-intc";
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interrupt-controller;
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#interrupt-cells = <2>;
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reg = <0x07021000 0x400>;
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interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
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};
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r_pio: pinctrl@7022000 {
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compatible = "allwinner,sun50i-h6-r-pinctrl";
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reg = <0x07022000 0x400>;
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interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&osc32k>;
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clock-names = "apb", "hosc", "losc";
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gpio-controller;
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#gpio-cells = <3>;
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interrupt-controller;
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#interrupt-cells = <3>;
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r_i2c_pins: r-i2c {
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pins = "PL0", "PL1";
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function = "s_i2c";
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};
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};
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r_i2c: i2c@7081400 {
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compatible = "allwinner,sun6i-a31-i2c";
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reg = <0x07081400 0x400>;
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interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&r_ccu CLK_R_APB2_I2C>;
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resets = <&r_ccu RST_R_APB2_I2C>;
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pinctrl-names = "default";
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pinctrl-0 = <&r_i2c_pins>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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};
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@ -82,6 +82,7 @@ config SUN8I_RSB
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config SUNXI_SRAM_ADDRESS
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hex
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default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5
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default 0x20000 if MACH_SUN50I_H6
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default 0x0
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---help---
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Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
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@ -287,6 +288,14 @@ config MACH_SUN50I_H5
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select FIT
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select SPL_LOAD_FIT
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config MACH_SUN50I_H6
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bool "sun50i (Allwinner H6)"
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select ARM64
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select SUPPORT_SPL
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select FIT
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select SPL_LOAD_FIT
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select DRAM_SUN50I_H6
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endchoice
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# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
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@ -380,6 +389,7 @@ config DRAM_CLK
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default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
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MACH_SUN8I_V3S
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default 672 if MACH_SUN50I
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default 744 if MACH_SUN50I_H6
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---help---
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Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
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must be a multiple of 24. For the sun9i (A80), the tested values
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@ -399,7 +409,7 @@ config DRAM_ZQ
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default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
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default 127 if MACH_SUN7I
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default 14779 if MACH_SUN8I_V3S
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default 3881979 if MACH_SUN8I_R40
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default 3881979 if MACH_SUN8I_R40 || MACH_SUN50I_H6
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default 4145117 if MACH_SUN9I
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default 3881915 if MACH_SUN50I
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---help---
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@ -411,6 +421,7 @@ config DRAM_ODT_EN
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default y if MACH_SUN8I_A23
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default y if MACH_SUN8I_R40
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default y if MACH_SUN50I
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default y if MACH_SUN50I_H6
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---help---
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Select this to enable dram odt (on die termination).
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@ -501,6 +512,7 @@ config SYS_CLK_FREQ
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default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
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default 1008000000 if MACH_SUN8I
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default 1008000000 if MACH_SUN9I
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default 888000000 if MACH_SUN50I_H6
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config SYS_CONFIG_NAME
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default "sun4i" if MACH_SUN4I
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@ -510,6 +522,7 @@ config SYS_CONFIG_NAME
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default "sun8i" if MACH_SUN8I
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default "sun9i" if MACH_SUN9I
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default "sun50i" if MACH_SUN50I
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default "sun50i" if MACH_SUN50I_H6
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config SYS_BOARD
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default "sunxi"
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@ -715,6 +728,7 @@ config VIDEO_SUNXI
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depends on !MACH_SUN8I_V3S
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depends on !MACH_SUN9I
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depends on !MACH_SUN50I
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depends on !MACH_SUN50I_H6
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select VIDEO
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imply VIDEO_DT_SIMPLEFB
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default y
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@ -947,6 +961,7 @@ config SPL_STACK_R_ADDR
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default 0x4fe00000 if MACH_SUN8I
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default 0x2fe00000 if MACH_SUN9I
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default 0x4fe00000 if MACH_SUN50I
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default 0x4fe00000 if MACH_SUN50I_H6
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config SPL_SPI_SUNXI
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bool "Support for SPI Flash on Allwinner SoCs in SPL"
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@ -96,6 +96,8 @@ int print_cpuinfo(void)
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puts("CPU: Allwinner A64 (SUN50I)\n");
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#elif defined CONFIG_MACH_SUN50I_H5
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puts("CPU: Allwinner H5 (SUN50I)\n");
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#elif defined CONFIG_MACH_SUN50I_H6
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puts("CPU: Allwinner H6 (SUN50I)\n");
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#else
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#warning Please update cpu_info.c with correct CPU information
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puts("CPU: SUNXI Family\n");
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@ -256,7 +256,7 @@ config SPL_SHA256_SUPPORT
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config SPL_FIT_IMAGE_TINY
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bool "Remove functionality from SPL FIT loading to reduce size"
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depends on SPL_FIT
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default y if MACH_SUN50I || MACH_SUN50I_H5
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default y if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN50I_H6
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help
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Enable this to reduce the size of the FIT image loading code
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in SPL, if space for the SPL binary is very tight.
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125
include/dt-bindings/clock/sun50i-h6-ccu.h
Normal file
125
include/dt-bindings/clock/sun50i-h6-ccu.h
Normal file
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@ -0,0 +1,125 @@
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// SPDX-License-Identifier: (GPL-2.0+ or MIT)
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/*
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* Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
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*/
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#ifndef _DT_BINDINGS_CLK_SUN50I_H6_H_
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#define _DT_BINDINGS_CLK_SUN50I_H6_H_
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#define CLK_PLL_PERIPH0 3
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#define CLK_CPUX 21
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#define CLK_APB1 26
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#define CLK_DE 29
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#define CLK_BUS_DE 30
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#define CLK_DEINTERLACE 31
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#define CLK_BUS_DEINTERLACE 32
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#define CLK_GPU 33
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#define CLK_BUS_GPU 34
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#define CLK_CE 35
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#define CLK_BUS_CE 36
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#define CLK_VE 37
|
||||
#define CLK_BUS_VE 38
|
||||
#define CLK_EMCE 39
|
||||
#define CLK_BUS_EMCE 40
|
||||
#define CLK_VP9 41
|
||||
#define CLK_BUS_VP9 42
|
||||
#define CLK_BUS_DMA 43
|
||||
#define CLK_BUS_MSGBOX 44
|
||||
#define CLK_BUS_SPINLOCK 45
|
||||
#define CLK_BUS_HSTIMER 46
|
||||
#define CLK_AVS 47
|
||||
#define CLK_BUS_DBG 48
|
||||
#define CLK_BUS_PSI 49
|
||||
#define CLK_BUS_PWM 50
|
||||
#define CLK_BUS_IOMMU 51
|
||||
|
||||
#define CLK_MBUS_DMA 53
|
||||
#define CLK_MBUS_VE 54
|
||||
#define CLK_MBUS_CE 55
|
||||
#define CLK_MBUS_TS 56
|
||||
#define CLK_MBUS_NAND 57
|
||||
#define CLK_MBUS_CSI 58
|
||||
#define CLK_MBUS_DEINTERLACE 59
|
||||
|
||||
#define CLK_NAND0 61
|
||||
#define CLK_NAND1 62
|
||||
#define CLK_BUS_NAND 63
|
||||
#define CLK_MMC0 64
|
||||
#define CLK_MMC1 65
|
||||
#define CLK_MMC2 66
|
||||
#define CLK_BUS_MMC0 67
|
||||
#define CLK_BUS_MMC1 68
|
||||
#define CLK_BUS_MMC2 69
|
||||
#define CLK_BUS_UART0 70
|
||||
#define CLK_BUS_UART1 71
|
||||
#define CLK_BUS_UART2 72
|
||||
#define CLK_BUS_UART3 73
|
||||
#define CLK_BUS_I2C0 74
|
||||
#define CLK_BUS_I2C1 75
|
||||
#define CLK_BUS_I2C2 76
|
||||
#define CLK_BUS_I2C3 77
|
||||
#define CLK_BUS_SCR0 78
|
||||
#define CLK_BUS_SCR1 79
|
||||
#define CLK_SPI0 80
|
||||
#define CLK_SPI1 81
|
||||
#define CLK_BUS_SPI0 82
|
||||
#define CLK_BUS_SPI1 83
|
||||
#define CLK_BUS_EMAC 84
|
||||
#define CLK_TS 85
|
||||
#define CLK_BUS_TS 86
|
||||
#define CLK_IR_TX 87
|
||||
#define CLK_BUS_IR_TX 88
|
||||
#define CLK_BUS_THS 89
|
||||
#define CLK_I2S3 90
|
||||
#define CLK_I2S0 91
|
||||
#define CLK_I2S1 92
|
||||
#define CLK_I2S2 93
|
||||
#define CLK_BUS_I2S0 94
|
||||
#define CLK_BUS_I2S1 95
|
||||
#define CLK_BUS_I2S2 96
|
||||
#define CLK_BUS_I2S3 97
|
||||
#define CLK_SPDIF 98
|
||||
#define CLK_BUS_SPDIF 99
|
||||
#define CLK_DMIC 100
|
||||
#define CLK_BUS_DMIC 101
|
||||
#define CLK_AUDIO_HUB 102
|
||||
#define CLK_BUS_AUDIO_HUB 103
|
||||
#define CLK_USB_OHCI0 104
|
||||
#define CLK_USB_PHY0 105
|
||||
#define CLK_USB_PHY1 106
|
||||
#define CLK_USB_OHCI3 107
|
||||
#define CLK_USB_PHY3 108
|
||||
#define CLK_USB_HSIC_12M 109
|
||||
#define CLK_USB_HSIC 110
|
||||
#define CLK_BUS_OHCI0 111
|
||||
#define CLK_BUS_OHCI3 112
|
||||
#define CLK_BUS_EHCI0 113
|
||||
#define CLK_BUS_XHCI 114
|
||||
#define CLK_BUS_EHCI3 115
|
||||
#define CLK_BUS_OTG 116
|
||||
#define CLK_PCIE_REF_100M 117
|
||||
#define CLK_PCIE_REF 118
|
||||
#define CLK_PCIE_REF_OUT 119
|
||||
#define CLK_PCIE_MAXI 120
|
||||
#define CLK_PCIE_AUX 121
|
||||
#define CLK_BUS_PCIE 122
|
||||
#define CLK_HDMI 123
|
||||
#define CLK_HDMI_SLOW 124
|
||||
#define CLK_HDMI_CEC 125
|
||||
#define CLK_BUS_HDMI 126
|
||||
#define CLK_BUS_TCON_TOP 127
|
||||
#define CLK_TCON_LCD0 128
|
||||
#define CLK_BUS_TCON_LCD0 129
|
||||
#define CLK_TCON_TV0 130
|
||||
#define CLK_BUS_TCON_TV0 131
|
||||
#define CLK_CSI_CCI 132
|
||||
#define CLK_CSI_TOP 133
|
||||
#define CLK_CSI_MCLK 134
|
||||
#define CLK_BUS_CSI 135
|
||||
#define CLK_HDCP 136
|
||||
#define CLK_BUS_HDCP 137
|
||||
|
||||
#endif /* _DT_BINDINGS_CLK_SUN50I_H6_H_ */
|
||||
24
include/dt-bindings/clock/sun50i-h6-r-ccu.h
Normal file
24
include/dt-bindings/clock/sun50i-h6-r-ccu.h
Normal file
|
|
@ -0,0 +1,24 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.xyz>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_
|
||||
#define _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_
|
||||
|
||||
#define CLK_AR100 0
|
||||
|
||||
#define CLK_R_APB1 2
|
||||
|
||||
#define CLK_R_APB1_TIMER 4
|
||||
#define CLK_R_APB1_TWD 5
|
||||
#define CLK_R_APB1_PWM 6
|
||||
#define CLK_R_APB2_UART 7
|
||||
#define CLK_R_APB2_I2C 8
|
||||
#define CLK_R_APB1_IR 9
|
||||
#define CLK_R_APB1_W1 10
|
||||
|
||||
#define CLK_IR 11
|
||||
#define CLK_W1 12
|
||||
|
||||
#endif /* _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ */
|
||||
73
include/dt-bindings/reset/sun50i-h6-ccu.h
Normal file
73
include/dt-bindings/reset/sun50i-h6-ccu.h
Normal file
|
|
@ -0,0 +1,73 @@
|
|||
// SPDX-License-Identifier: (GPL-2.0+ or MIT)
|
||||
/*
|
||||
* Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_RESET_SUN50I_H6_H_
|
||||
#define _DT_BINDINGS_RESET_SUN50I_H6_H_
|
||||
|
||||
#define RST_MBUS 0
|
||||
#define RST_BUS_DE 1
|
||||
#define RST_BUS_DEINTERLACE 2
|
||||
#define RST_BUS_GPU 3
|
||||
#define RST_BUS_CE 4
|
||||
#define RST_BUS_VE 5
|
||||
#define RST_BUS_EMCE 6
|
||||
#define RST_BUS_VP9 7
|
||||
#define RST_BUS_DMA 8
|
||||
#define RST_BUS_MSGBOX 9
|
||||
#define RST_BUS_SPINLOCK 10
|
||||
#define RST_BUS_HSTIMER 11
|
||||
#define RST_BUS_DBG 12
|
||||
#define RST_BUS_PSI 13
|
||||
#define RST_BUS_PWM 14
|
||||
#define RST_BUS_IOMMU 15
|
||||
#define RST_BUS_DRAM 16
|
||||
#define RST_BUS_NAND 17
|
||||
#define RST_BUS_MMC0 18
|
||||
#define RST_BUS_MMC1 19
|
||||
#define RST_BUS_MMC2 20
|
||||
#define RST_BUS_UART0 21
|
||||
#define RST_BUS_UART1 22
|
||||
#define RST_BUS_UART2 23
|
||||
#define RST_BUS_UART3 24
|
||||
#define RST_BUS_I2C0 25
|
||||
#define RST_BUS_I2C1 26
|
||||
#define RST_BUS_I2C2 27
|
||||
#define RST_BUS_I2C3 28
|
||||
#define RST_BUS_SCR0 29
|
||||
#define RST_BUS_SCR1 30
|
||||
#define RST_BUS_SPI0 31
|
||||
#define RST_BUS_SPI1 32
|
||||
#define RST_BUS_EMAC 33
|
||||
#define RST_BUS_TS 34
|
||||
#define RST_BUS_IR_TX 35
|
||||
#define RST_BUS_THS 36
|
||||
#define RST_BUS_I2S0 37
|
||||
#define RST_BUS_I2S1 38
|
||||
#define RST_BUS_I2S2 39
|
||||
#define RST_BUS_I2S3 40
|
||||
#define RST_BUS_SPDIF 41
|
||||
#define RST_BUS_DMIC 42
|
||||
#define RST_BUS_AUDIO_HUB 43
|
||||
#define RST_USB_PHY0 44
|
||||
#define RST_USB_PHY1 45
|
||||
#define RST_USB_PHY3 46
|
||||
#define RST_USB_HSIC 47
|
||||
#define RST_BUS_OHCI0 48
|
||||
#define RST_BUS_OHCI3 49
|
||||
#define RST_BUS_EHCI0 50
|
||||
#define RST_BUS_XHCI 51
|
||||
#define RST_BUS_EHCI3 52
|
||||
#define RST_BUS_OTG 53
|
||||
#define RST_BUS_PCIE 54
|
||||
#define RST_PCIE_POWERUP 55
|
||||
#define RST_BUS_HDMI 56
|
||||
#define RST_BUS_HDMI_SUB 57
|
||||
#define RST_BUS_TCON_TOP 58
|
||||
#define RST_BUS_TCON_LCD0 59
|
||||
#define RST_BUS_TCON_TV0 60
|
||||
#define RST_BUS_CSI 61
|
||||
#define RST_BUS_HDCP 62
|
||||
|
||||
#endif /* _DT_BINDINGS_RESET_SUN50I_H6_H_ */
|
||||
17
include/dt-bindings/reset/sun50i-h6-r-ccu.h
Normal file
17
include/dt-bindings/reset/sun50i-h6-r-ccu.h
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
|
||||
/*
|
||||
* Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_
|
||||
#define _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_
|
||||
|
||||
#define RST_R_APB1_TIMER 0
|
||||
#define RST_R_APB1_TWD 1
|
||||
#define RST_R_APB1_PWM 2
|
||||
#define RST_R_APB2_UART 3
|
||||
#define RST_R_APB2_I2C 4
|
||||
#define RST_R_APB1_IR 5
|
||||
#define RST_R_APB1_W1 6
|
||||
|
||||
#endif /* _DT_BINDINGS_RST_SUN50I_H6_R_CCU_H_ */
|
||||
Loading…
Reference in a new issue