mirror of
https://github.com/AsahiLinux/u-boot
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armv7r: dts: am654: Add initial support
Add R5 specific dts for am654-evm. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Schuyler Patton <spatton@ti.com> Signed-off-by: James Doublesin <doublesin@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Lokesh Vutla
Tom Rini
parent
2d0eba3a45
commit
00b34e9937
4 changed files with 492 additions and 1 deletions
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@ -559,7 +559,7 @@ dtb-$(CONFIG_TARGET_STM32MP1) += \
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stm32mp157c-ed1.dtb \
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stm32mp157c-ev1.dtb
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dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb
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dtb-$(CONFIG_SOC_K3_AM6) += k3-am654-base-board.dtb k3-am654-r5-base-board.dtb
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targets += $(dtb-y)
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156
arch/arm/dts/k3-am654-base-board-ddr4-1600MHz.dtsi
Normal file
156
arch/arm/dts/k3-am654-base-board-ddr4-1600MHz.dtsi
Normal file
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@ -0,0 +1,156 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
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* This file was generated by the AM65x_DRA80xM EMIF Tool:
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* http://www.ti.com/lit/pdf/spracj0
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* Configuration Parameters
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* Memory Type: DDR4
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* Data Rate: 1600
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* ECC Enabled: No
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* Data Width: 32
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*/
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#define DDR_PLL_FREQUENCY 400000000
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#define DDRCTL_MSTR 0x41040010
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#define DDRCTL_RFSHCTL0 0x00210070
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#define DDRCTL_ECCCFG0 0x00000000
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#define DDRCTL_RFSHTMG 0x0061008C
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#define DDRCTL_CRCPARCTL0 0x00008000
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#define DDRCTL_CRCPARCTL1 0x1A000000
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#define DDRCTL_CRCPARCTL2 0x0048051E
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#define DDRCTL_INIT0 0x400100C4
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#define DDRCTL_INIT1 0x004F0000
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#define DDRCTL_INIT3 0x02140501
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#define DDRCTL_INIT4 0x00000020
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#define DDRCTL_INIT5 0x00100000
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#define DDRCTL_INIT6 0x00000480
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#define DDRCTL_INIT7 0x000004E8
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#define DDRCTL_DRAMTMG0 0x0C0A1B0D
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#define DDRCTL_DRAMTMG1 0x00030313
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#define DDRCTL_DRAMTMG2 0x0506050A
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#define DDRCTL_DRAMTMG3 0x0000400C
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#define DDRCTL_DRAMTMG4 0x06020206
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#define DDRCTL_DRAMTMG5 0x04040302
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#define DDRCTL_DRAMTMG6 0x00000004
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#define DDRCTL_DRAMTMG7 0x00000404
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#define DDRCTL_DRAMTMG8 0x03030C05
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#define DDRCTL_DRAMTMG9 0x00020208
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#define DDRCTL_DRAMTMG10 0x001C180A
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#define DDRCTL_DRAMTMG11 0x1106010E
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#define DDRCTL_DRAMTMG12 0x00020008
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#define DDRCTL_DRAMTMG13 0x0B100002
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#define DDRCTL_DRAMTMG14 0x00000000
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#define DDRCTL_DRAMTMG15 0x0000003F
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#define DDRCTL_DRAMTMG17 0x00500028
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#define DDRCTL_ZQCTL0 0x21000040
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#define DDRCTL_ZQCTL1 0x0202FAF0
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#define DDRCTL_DFITMG0 0x04888206
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#define DDRCTL_DFITMG1 0x000A0606
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#define DDRCTL_DFITMG2 0x00000604
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#define DDRCTL_DFIMISC 0x00000001
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#define DDRCTL_ADDRMAP0 0x001F1F1F
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#define DDRCTL_ADDRMAP1 0x003F0808
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#define DDRCTL_ADDRMAP2 0x00000000
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#define DDRCTL_ADDRMAP3 0x00000000
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#define DDRCTL_ADDRMAP4 0x00001F1F
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#define DDRCTL_ADDRMAP5 0x08080808
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#define DDRCTL_ADDRMAP6 0x08080808
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#define DDRCTL_ADDRMAP7 0x00000F0F
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#define DDRCTL_ADDRMAP8 0x00000A0A
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#define DDRCTL_ADDRMAP9 0x00000000
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#define DDRCTL_ADDRMAP10 0x00000000
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#define DDRCTL_ADDRMAP11 0x001F1F00
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#define DDRCTL_DQMAP0 0x00000000
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#define DDRCTL_DQMAP1 0x00000000
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#define DDRCTL_DQMAP4 0x00000000
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#define DDRCTL_DQMAP5 0x00000000
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#define DDRCTL_PWRCTL 0x00000000
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#define DDRCTL_RANKCTL 0x00000000
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#define DDRCTL_ODTCFG 0x0600060C
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#define DDRCTL_ODTMAP 0x00000001
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#define DDRPHY_PGCR0 0x07001E00
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#define DDRPHY_PGCR1 0x020046C0
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#define DDRPHY_PGCR2 0x00F0BFE0
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#define DDRPHY_PGCR3 0x55AA0080
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#define DDRPHY_PGCR6 0x00013001
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#define DDRPHY_PTR2 0x00083DEF
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#define DDRPHY_PTR3 0x00061A80
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#define DDRPHY_PTR4 0x00000120
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#define DDRPHY_PTR5 0x00027100
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#define DDRPHY_PTR6 0x04000320
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#define DDRPHY_PLLCR0 0x021c4000
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#define DDRPHY_DXCCR 0x00000038
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#define DDRPHY_DSGCR 0x02A0C129
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#define DDRPHY_DCR 0x0000040C
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#define DDRPHY_DTPR0 0x041A0B06
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#define DDRPHY_DTPR1 0x28140000
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#define DDRPHY_DTPR2 0x0034E300
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#define DDRPHY_DTPR3 0x02800800
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#define DDRPHY_DTPR4 0x31180805
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#define DDRPHY_DTPR5 0x00250B06
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#define DDRPHY_DTPR6 0x00000505
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#define DDRPHY_ZQCR 0x008A2A58
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#define DDRPHY_ZQ0PR0 0x000077DD
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#define DDRPHY_ZQ1PR0 0x000077DD
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#define DDRPHY_MR0 0x00000214
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#define DDRPHY_MR1 0x00000501
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#define DDRPHY_MR2 0x00000000
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#define DDRPHY_MR3 0x00000020
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#define DDRPHY_MR4 0x00000000
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#define DDRPHY_MR5 0x00000480
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#define DDRPHY_MR6 0x000004E8
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#define DDRPHY_MR11 0x00000000
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#define DDRPHY_MR12 0x00000000
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#define DDRPHY_MR13 0x00000000
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#define DDRPHY_MR14 0x00000000
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#define DDRPHY_MR22 0x00000000
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#define DDRPHY_VTCR0 0xF3C32028
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#define DDRPHY_DX8SL0PLLCR0 0x021c4000
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#define DDRPHY_DX8SL1PLLCR0 0x021c4000
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#define DDRPHY_DX8SL2PLLCR0 0x021c4000
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#define DDRPHY_DTCR0 0x8000B1C7
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#define DDRPHY_DTCR1 0x00010236
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#define DDRPHY_ACIOCR5 0x04800000
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#define DDRPHY_IOVCR0 0x0F0C0C0C
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#define DDRPHY_DX0GCR0 0x00000000
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#define DDRPHY_DX0GCR1 0x00000000
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#define DDRPHY_DX0GCR2 0x00000000
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#define DDRPHY_DX0GCR3 0x00000000
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#define DDRPHY_DX1GCR0 0x00000000
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#define DDRPHY_DX1GCR1 0x00000000
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#define DDRPHY_DX1GCR2 0x00000000
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#define DDRPHY_DX1GCR3 0x00000000
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#define DDRPHY_DX2GCR0 0x40700204
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#define DDRPHY_DX2GCR1 0x00007FFF
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#define DDRPHY_DX2GCR2 0x00000000
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#define DDRPHY_DX2GCR3 0xFFC0010B
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#define DDRPHY_DX3GCR0 0x40700204
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#define DDRPHY_DX3GCR1 0x00007FFF
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#define DDRPHY_DX3GCR2 0x00000000
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#define DDRPHY_DX3GCR3 0xFFC0010B
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#define DDRPHY_DX4GCR0 0x40703220
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#define DDRPHY_DX4GCR1 0x55556000
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#define DDRPHY_DX4GCR2 0xAAAA0000
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#define DDRPHY_DX4GCR3 0xFFE18587
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#define DDRPHY_DX0GCR4 0x0E00B03C
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#define DDRPHY_DX1GCR4 0x0E00B03C
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#define DDRPHY_DX2GCR4 0x0E00B03C
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#define DDRPHY_DX3GCR4 0x0E00B03C
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#define DDRPHY_DX4GCR4 0x0E00B03C
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#define DDRPHY_PGCR5 0x01010004
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#define DDRPHY_DX0GCR5 0x00000049
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#define DDRPHY_DX1GCR5 0x00000049
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#define DDRPHY_DX2GCR5 0x00000049
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#define DDRPHY_DX3GCR5 0x00000049
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#define DDRPHY_DX4GCR5 0x00000049
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#define DDRPHY_DX0GTR0 0x00020002
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#define DDRPHY_DX1GTR0 0x00020002
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#define DDRPHY_DX2GTR0 0x00020002
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#define DDRPHY_DX3GTR0 0x00020002
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#define DDRPHY_DX4GTR0 0x00020002
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#define DDRPHY_ODTCR 0x00010000
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#define DDRPHY_DX8SL0IOCR 0x04800000
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#define DDRPHY_DX8SL1IOCR 0x04800000
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#define DDRPHY_DX8SL2IOCR 0x04800000
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#define DDRPHY_DX8SL0DXCTL2 0x00141830
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#define DDRPHY_DX8SL1DXCTL2 0x00141830
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#define DDRPHY_DX8SL2DXCTL2 0x00141830
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196
arch/arm/dts/k3-am654-ddr.dtsi
Normal file
196
arch/arm/dts/k3-am654-ddr.dtsi
Normal file
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@ -0,0 +1,196 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
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*/
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/ {
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memorycontroller: memorycontroller@0298e000 {
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compatible = "ti,am654-ddrss";
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reg = <0x0 0x0298e000 0x0 0x200>,
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<0x0 0x02980000 0x0 0x4000>,
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<0x0 0x02988000 0x0 0x2000>;
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reg-names = "ss", "ctl", "phy";
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clocks = <&k3_clks 20 0>;
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power-domains = <&k3_pds 20>,
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<&k3_pds 244>;
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assigned-clocks = <&k3_clks 20 1>;
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assigned-clock-rates = <DDR_PLL_FREQUENCY>;
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u-boot,dm-spl;
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ti,ctl-reg = <
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DDRCTL_DFIMISC
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DDRCTL_DFITMG0
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DDRCTL_DFITMG1
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DDRCTL_DFITMG2
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DDRCTL_INIT0
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DDRCTL_INIT1
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DDRCTL_INIT3
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DDRCTL_INIT4
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DDRCTL_INIT5
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DDRCTL_INIT6
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DDRCTL_INIT7
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DDRCTL_MSTR
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DDRCTL_ODTCFG
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DDRCTL_ODTMAP
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DDRCTL_RANKCTL
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DDRCTL_RFSHCTL0
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DDRCTL_RFSHTMG
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DDRCTL_ZQCTL0
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DDRCTL_ZQCTL1
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>;
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ti,ctl-crc = <
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DDRCTL_CRCPARCTL0
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DDRCTL_CRCPARCTL1
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DDRCTL_CRCPARCTL2
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>;
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ti,ctl-ecc = <
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DDRCTL_ECCCFG0
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>;
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ti,ctl-map = <
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DDRCTL_ADDRMAP0
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DDRCTL_ADDRMAP1
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DDRCTL_ADDRMAP2
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DDRCTL_ADDRMAP3
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DDRCTL_ADDRMAP4
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DDRCTL_ADDRMAP5
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DDRCTL_ADDRMAP6
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DDRCTL_ADDRMAP7
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DDRCTL_ADDRMAP8
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DDRCTL_ADDRMAP9
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DDRCTL_ADDRMAP10
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DDRCTL_ADDRMAP11
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DDRCTL_DQMAP0
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DDRCTL_DQMAP1
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DDRCTL_DQMAP4
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DDRCTL_DQMAP5
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>;
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ti,ctl-pwr = <
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DDRCTL_PWRCTL
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>;
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ti,ctl-timing = <
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DDRCTL_DRAMTMG0
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DDRCTL_DRAMTMG1
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DDRCTL_DRAMTMG2
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DDRCTL_DRAMTMG3
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DDRCTL_DRAMTMG4
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DDRCTL_DRAMTMG5
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DDRCTL_DRAMTMG6
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DDRCTL_DRAMTMG7
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DDRCTL_DRAMTMG8
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DDRCTL_DRAMTMG9
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DDRCTL_DRAMTMG11
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DDRCTL_DRAMTMG12
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DDRCTL_DRAMTMG13
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DDRCTL_DRAMTMG14
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DDRCTL_DRAMTMG15
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DDRCTL_DRAMTMG17
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>;
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ti,phy-cfg = <
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DDRPHY_DCR
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DDRPHY_DSGCR
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DDRPHY_DX0GCR0
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DDRPHY_DX0GCR1
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DDRPHY_DX0GCR2
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DDRPHY_DX0GCR3
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DDRPHY_DX0GCR4
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DDRPHY_DX0GCR5
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DDRPHY_DX0GTR0
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DDRPHY_DX1GCR0
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DDRPHY_DX1GCR1
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DDRPHY_DX1GCR2
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DDRPHY_DX1GCR3
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DDRPHY_DX1GCR4
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DDRPHY_DX1GCR5
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DDRPHY_DX1GTR0
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DDRPHY_DX2GCR0
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DDRPHY_DX2GCR1
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DDRPHY_DX2GCR2
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DDRPHY_DX2GCR3
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DDRPHY_DX2GCR4
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DDRPHY_DX2GCR5
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DDRPHY_DX2GTR0
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DDRPHY_DX3GCR0
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DDRPHY_DX3GCR1
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DDRPHY_DX3GCR2
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DDRPHY_DX3GCR3
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DDRPHY_DX3GCR4
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DDRPHY_DX3GCR5
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DDRPHY_DX3GTR0
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DDRPHY_DX4GCR0
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DDRPHY_DX4GCR1
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DDRPHY_DX4GCR2
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DDRPHY_DX4GCR3
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DDRPHY_DX4GCR4
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DDRPHY_DX4GCR5
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DDRPHY_DX4GTR0
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DDRPHY_DX8SL0DXCTL2
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DDRPHY_DX8SL0IOCR
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DDRPHY_DX8SL0PLLCR0
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DDRPHY_DX8SL1DXCTL2
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DDRPHY_DX8SL1IOCR
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DDRPHY_DX8SL1PLLCR0
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DDRPHY_DX8SL2DXCTL2
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DDRPHY_DX8SL2IOCR
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DDRPHY_DX8SL2PLLCR0
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DDRPHY_DXCCR
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DDRPHY_ODTCR
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DDRPHY_PGCR0
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DDRPHY_PGCR1
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DDRPHY_PGCR2
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DDRPHY_PGCR3
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DDRPHY_PGCR5
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DDRPHY_PGCR6
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>;
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ti,phy-ctl = <
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DDRPHY_DTCR0
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DDRPHY_DTCR1
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DDRPHY_MR0
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DDRPHY_MR1
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DDRPHY_MR2
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DDRPHY_MR3
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DDRPHY_MR4
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DDRPHY_MR5
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DDRPHY_MR6
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DDRPHY_MR11
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DDRPHY_MR12
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DDRPHY_MR13
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DDRPHY_MR14
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DDRPHY_MR22
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DDRPHY_PLLCR0
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DDRPHY_VTCR0
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>;
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ti,phy-ioctl = <
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DDRPHY_ACIOCR5
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DDRPHY_IOVCR0
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>;
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ti,phy-timing = <
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DDRPHY_DTPR0
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DDRPHY_DTPR1
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DDRPHY_DTPR2
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DDRPHY_DTPR3
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DDRPHY_DTPR4
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DDRPHY_DTPR5
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DDRPHY_DTPR6
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DDRPHY_PTR2
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DDRPHY_PTR3
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DDRPHY_PTR4
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DDRPHY_PTR5
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DDRPHY_PTR6
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>;
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ti,phy-zq = <
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DDRPHY_ZQ0PR0
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DDRPHY_ZQ1PR0
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DDRPHY_ZQCR
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>;
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};
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};
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139
arch/arm/dts/k3-am654-r5-base-board.dts
Normal file
139
arch/arm/dts/k3-am654-r5-base-board.dts
Normal file
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@ -0,0 +1,139 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
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*/
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/dts-v1/;
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#include "k3-am654.dtsi"
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#include "k3-am654-base-board-u-boot.dtsi"
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#include "k3-am654-base-board-ddr4-1600MHz.dtsi"
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#include "k3-am654-ddr.dtsi"
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/ {
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compatible = "ti,am654-evm", "ti,am654";
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model = "Texas Instruments AM654 R5 Base Board";
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aliases {
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serial0 = &wkup_uart0;
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serial2 = &main_uart0;
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};
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chosen {
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stdout-path = "serial2:115200n8";
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tick-timer = &timer1;
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};
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aliases {
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remoteproc0 = &sysctrler;
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remoteproc1 = &a53_0;
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};
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a53_0: a53@0 {
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compatible = "ti,am654-rproc";
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reg = <0x0 0x00a90000 0x0 0x10>;
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power-domains = <&k3_pds 61>,
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<&k3_pds 202>;
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resets = <&k3_reset 202 0>;
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assigned-clocks = <&k3_clks 202 0>;
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assigned-clock-rates = <800000000>;
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ti,sci = <&dmsc>;
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ti,sci-proc-id = <32>;
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ti,sci-host-id = <10>;
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u-boot,dm-spl;
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};
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vtt_supply: vtt_supply {
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compatible = "regulator-gpio";
|
||||
regulator-name = "vtt";
|
||||
regulator-min-microvolt = <0>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpios = <&wkup_gpio0 28 GPIO_ACTIVE_HIGH>;
|
||||
states = <0 0x0 3300000 0x1>;
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
};
|
||||
|
||||
&cbass_main {
|
||||
timer1: timer@40400000 {
|
||||
compatible = "ti,omap5430-timer";
|
||||
reg = <0x0 0x40400000 0x0 0x80>;
|
||||
ti,timer-alwon;
|
||||
clock-frequency = <25000000>;
|
||||
u-boot,dm-pre-reloc;
|
||||
};
|
||||
};
|
||||
|
||||
&cbass_mcu {
|
||||
mcu_secproxy: secproxy@28380000 {
|
||||
compatible = "ti,am654-secure-proxy";
|
||||
reg = <0x0 0x2a380000 0x0 0x80000>,
|
||||
<0x0 0x2a400000 0x0 0x80000>,
|
||||
<0x0 0x2a480000 0x0 0x80000>;
|
||||
reg-names = "rt", "scfg", "target_data";
|
||||
#mbox-cells = <1>;
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
};
|
||||
|
||||
&cbass_wakeup {
|
||||
sysctrler: sysctrler {
|
||||
compatible = "ti,am654-system-controller";
|
||||
mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>;
|
||||
mbox-names = "tx", "rx";
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
wkup_gpio0: wkup_gpio0@42110000 {
|
||||
compatible = "ti,k2g-gpio", "ti,keystone-gpio";
|
||||
reg = <0x42110000 0x100>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
ti,ngpio = <56>;
|
||||
ti,davinci-gpio-unbanked = <0>;
|
||||
clocks = <&k3_clks 59 0>;
|
||||
clock-names = "gpio";
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&dmsc {
|
||||
mboxes= <&mcu_secproxy 7>, <&mcu_secproxy 6>, <&mcu_secproxy 5>;
|
||||
mbox-names = "tx", "rx", "notify";
|
||||
ti,host-id = <4>;
|
||||
ti,secure-host;
|
||||
};
|
||||
|
||||
&wkup_uart0 {
|
||||
u-boot,dm-spl;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wkup_uart0_pins_default>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wkup_pmx0 {
|
||||
u-boot,dm-spl;
|
||||
wkup_uart0_pins_default: wkup_uart0_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_WKUP_IOPAD(0x00a0, PIN_INPUT | MUX_MODE0) /* (AB1) WKUP_UART0_RXD */
|
||||
AM65X_WKUP_IOPAD(0x00a4, PIN_OUTPUT | MUX_MODE0) /* (AB5) WKUP_UART0_TXD */
|
||||
AM65X_WKUP_IOPAD(0x00c8, PIN_INPUT | MUX_MODE1) /* (AC2) WKUP_GPIO0_6.WKUP_UART0_CTSn */
|
||||
AM65X_WKUP_IOPAD(0x00cc, PIN_OUTPUT | MUX_MODE1) /* (AC1) WKUP_GPIO0_7.WKUP_UART0_RTSn */
|
||||
>;
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
wkup_vtt_pins_default: wkup_vtt_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
AM65X_WKUP_IOPAD(0x0040, PIN_OUTPUT_PULLUP | MUX_MODE7) /* WKUP_GPIO0_28 */
|
||||
>;
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
};
|
||||
|
||||
&memorycontroller {
|
||||
vtt-supply = <&vtt_supply>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wkup_vtt_pins_default>;
|
||||
};
|
||||
Loading…
Add table
Reference in a new issue