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bcm6838: add initial support
This adds the initial support of the Broadcom BCM6838 SoC familly, only cpu, dram, uart and leds are supported. Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
This commit is contained in:
Philippe Reynes
Daniel Schwierzeck
parent
3e4a68d32b
commit
341032d3f1
4 changed files with 145 additions and 0 deletions
75
arch/mips/dts/brcm,bcm6838.dtsi
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75
arch/mips/dts/brcm,bcm6838.dtsi
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@ -0,0 +1,75 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com>
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*/
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#include "skeleton.dtsi"
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/ {
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compatible = "brcm,bcm6838";
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cpus {
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reg = <0x14e00000 0x4>;
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#address-cells = <1>;
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#size-cells = <0>;
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u-boot,dm-pre-reloc;
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cpu@0 {
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compatible = "brcm,bcm6838-cpu", "mips,mips4Kc";
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device_type = "cpu";
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reg = <0>;
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u-boot,dm-pre-reloc;
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};
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cpu@1 {
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compatible = "brcm,bcm6838-cpu", "mips,mips4Kc";
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device_type = "cpu";
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reg = <1>;
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u-boot,dm-pre-reloc;
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};
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};
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clocks {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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u-boot,dm-pre-reloc;
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periph_osc: periph-osc {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <50000000>;
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u-boot,dm-pre-reloc;
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};
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};
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ubus {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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u-boot,dm-pre-reloc;
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memory: memory-controller@12000000 {
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compatible = "brcm,bcm6328-mc";
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reg = <0x12000000 0x1000>;
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u-boot,dm-pre-reloc;
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};
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uart0: serial@14e00500 {
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compatible = "brcm,bcm6345-uart";
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reg = <0x14e00500 0x18>;
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clocks = <&periph_osc>;
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status = "disabled";
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};
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leds: led-controller@14e00f00 {
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compatible = "brcm,bcm6328-leds";
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reg = <0x14e00f00 0x28>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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};
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};
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@ -14,6 +14,7 @@ config SYS_SOC
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default "bcm6368" if SOC_BMIPS_BCM6368
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default "bcm6362" if SOC_BMIPS_BCM6362
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default "bcm63268" if SOC_BMIPS_BCM63268
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default "bcm6838" if SOC_BMIPS_BCM6838
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choice
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prompt "Broadcom MIPS SoC select"
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@ -118,6 +119,18 @@ config SOC_BMIPS_BCM63268
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This supports BMIPS BCM63268 family including BCM63168, BCM63169,
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BCM63268 and BCM63269.
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config SOC_BMIPS_BCM6838
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bool "BMIPS BCM6838 family"
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select MIPS_L1_CACHE_SHIFT_4
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select MIPS_TUNE_4KC
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select SUPPORTS_BIG_ENDIAN
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select SUPPORTS_CPU_MIPS32_R1
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select SWAP_IO_SPACE
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select SYSRESET_SYSCON
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help
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This supports BMIPS BCM6838 family including BCM68380, BCM68381,
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and BCM68385.
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endchoice
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choice
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@ -66,6 +66,10 @@
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#define STRAPBUS_63268_FCVO_SHIFT 21
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#define STRAPBUS_63268_FCVO_MASK (0xf << STRAPBUS_63268_FCVO_SHIFT)
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#define REG_BCM6838_OTP_BRCMBITS0 0x440
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#define VIPER_6838_FREQ_SHIFT 18
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#define VIPER_6838_FREQ_MASK (0x7 << VIPER_6838_FREQ_SHIFT)
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struct bmips_cpu_priv;
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struct bmips_cpu_hw {
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@ -272,6 +276,26 @@ static ulong bcm63268_get_cpu_freq(struct bmips_cpu_priv *priv)
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}
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}
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static ulong bcm6838_get_cpu_freq(struct bmips_cpu_priv *priv)
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{
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unsigned int mips_viper_freq;
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mips_viper_freq = readl_be(priv->regs + REG_BCM6838_OTP_BRCMBITS0);
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mips_viper_freq = (mips_viper_freq & VIPER_6838_FREQ_MASK)
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>> VIPER_6838_FREQ_SHIFT;
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switch (mips_viper_freq) {
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case 0x0:
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return 600000000;
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case 0x1:
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return 400000000;
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case 0x2:
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return 240000000;
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default:
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return 0;
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}
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}
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static int bcm6328_get_cpu_count(struct bmips_cpu_priv *priv)
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{
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u32 val = readl_be(priv->regs + REG_BCM6328_OTP);
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@ -346,6 +370,12 @@ static const struct bmips_cpu_hw bmips_cpu_bcm63268 = {
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.get_cpu_count = bcm6358_get_cpu_count,
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};
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static const struct bmips_cpu_hw bmips_cpu_bcm6838 = {
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.get_cpu_desc = bmips_short_cpu_desc,
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.get_cpu_freq = bcm6838_get_cpu_freq,
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.get_cpu_count = bcm6358_get_cpu_count,
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};
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/* Generic CPU Ops */
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static int bmips_cpu_get_desc(struct udevice *dev, char *buf, int size)
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{
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@ -444,6 +474,9 @@ static const struct udevice_id bmips_cpu_ids[] = {
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}, {
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.compatible = "brcm,bcm63268-cpu",
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.data = (ulong)&bmips_cpu_bcm63268,
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}, {
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.compatible = "brcm,bcm6838-cpu",
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.data = (ulong)&bmips_cpu_bcm6838,
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},
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{ /* sentinel */ }
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};
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24
include/configs/bmips_bcm6838.h
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24
include/configs/bmips_bcm6838.h
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@ -0,0 +1,24 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2018 Philippe Reynes <philippe.reynes@softathome.com>
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*/
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#ifndef __CONFIG_BMIPS_BCM6838_H
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#define __CONFIG_BMIPS_BCM6838_H
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/* CPU */
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#define CONFIG_SYS_MIPS_TIMER_FREQ 160000000
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/* RAM */
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_SDRAM_BASE 0x80000000
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/* U-Boot */
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#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000
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#if defined(CONFIG_BMIPS_BOOT_RAM)
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_SYS_INIT_SP_OFFSET 0x2000
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#endif
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#endif /* __CONFIG_BMIPS_BCM6838_H */
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