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https://github.com/AsahiLinux/u-boot
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imx8: add mmu and dram related functions
Add mmu memmap, some memory regions are reserved by M4, Arm Trusted Firmware, so need to get memreg using SCFW API and setup the memmap. Add dram_init, dram_init_banksize, get_effective_memsize functions, according to the memreg. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Peng Fan
Stefano Babic
parent
c1aae21d89
commit
930b595291
1 changed files with 284 additions and 0 deletions
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@ -14,6 +14,7 @@
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#include <asm/arch/sys_proto.h>
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#include <asm/arch-imx/cpu.h>
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#include <asm/armv8/cpu.h>
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#include <asm/armv8/mmu.h>
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#include <asm/mach-imx/boot_mode.h>
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DECLARE_GLOBAL_DATA_PTR;
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@ -208,3 +209,286 @@ int mmc_get_env_dev(void)
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return board_mmc_get_env_dev(devno);
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}
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#endif
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#define MEMSTART_ALIGNMENT SZ_2M /* Align the memory start with 2MB */
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static int get_owned_memreg(sc_rm_mr_t mr, sc_faddr_t *addr_start,
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sc_faddr_t *addr_end)
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{
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sc_faddr_t start, end;
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int ret;
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bool owned;
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owned = sc_rm_is_memreg_owned(-1, mr);
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if (owned) {
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ret = sc_rm_get_memreg_info(-1, mr, &start, &end);
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if (ret) {
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printf("Memreg get info failed, %d\n", ret);
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return -EINVAL;
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}
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debug("0x%llx -- 0x%llx\n", start, end);
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*addr_start = start;
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*addr_end = end;
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return 0;
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}
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return -EINVAL;
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}
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phys_size_t get_effective_memsize(void)
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{
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sc_rm_mr_t mr;
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sc_faddr_t start, end, end1;
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int err;
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end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
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for (mr = 0; mr < 64; mr++) {
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err = get_owned_memreg(mr, &start, &end);
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if (!err) {
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start = roundup(start, MEMSTART_ALIGNMENT);
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/* Too small memory region, not use it */
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if (start > end)
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continue;
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/* Find the memory region runs the u-boot */
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if (start >= PHYS_SDRAM_1 && start <= end1 &&
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(start <= CONFIG_SYS_TEXT_BASE &&
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end >= CONFIG_SYS_TEXT_BASE)) {
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if ((end + 1) <= ((sc_faddr_t)PHYS_SDRAM_1 +
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PHYS_SDRAM_1_SIZE))
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return (end - PHYS_SDRAM_1 + 1);
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else
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return PHYS_SDRAM_1_SIZE;
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}
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}
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}
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return PHYS_SDRAM_1_SIZE;
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}
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int dram_init(void)
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{
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sc_rm_mr_t mr;
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sc_faddr_t start, end, end1, end2;
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int err;
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end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
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end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
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for (mr = 0; mr < 64; mr++) {
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err = get_owned_memreg(mr, &start, &end);
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if (!err) {
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start = roundup(start, MEMSTART_ALIGNMENT);
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/* Too small memory region, not use it */
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if (start > end)
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continue;
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if (start >= PHYS_SDRAM_1 && start <= end1) {
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if ((end + 1) <= end1)
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gd->ram_size += end - start + 1;
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else
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gd->ram_size += end1 - start;
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} else if (start >= PHYS_SDRAM_2 && start <= end2) {
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if ((end + 1) <= end2)
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gd->ram_size += end - start + 1;
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else
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gd->ram_size += end2 - start;
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}
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}
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}
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/* If error, set to the default value */
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if (!gd->ram_size) {
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gd->ram_size = PHYS_SDRAM_1_SIZE;
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gd->ram_size += PHYS_SDRAM_2_SIZE;
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}
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return 0;
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}
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static void dram_bank_sort(int current_bank)
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{
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phys_addr_t start;
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phys_size_t size;
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while (current_bank > 0) {
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if (gd->bd->bi_dram[current_bank - 1].start >
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gd->bd->bi_dram[current_bank].start) {
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start = gd->bd->bi_dram[current_bank - 1].start;
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size = gd->bd->bi_dram[current_bank - 1].size;
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gd->bd->bi_dram[current_bank - 1].start =
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gd->bd->bi_dram[current_bank].start;
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gd->bd->bi_dram[current_bank - 1].size =
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gd->bd->bi_dram[current_bank].size;
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gd->bd->bi_dram[current_bank].start = start;
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gd->bd->bi_dram[current_bank].size = size;
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}
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current_bank--;
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}
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}
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int dram_init_banksize(void)
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{
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sc_rm_mr_t mr;
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sc_faddr_t start, end, end1, end2;
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int i = 0;
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int err;
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end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
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end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
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for (mr = 0; mr < 64 && i < CONFIG_NR_DRAM_BANKS; mr++) {
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err = get_owned_memreg(mr, &start, &end);
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if (!err) {
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start = roundup(start, MEMSTART_ALIGNMENT);
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if (start > end) /* Small memory region, no use it */
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continue;
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if (start >= PHYS_SDRAM_1 && start <= end1) {
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gd->bd->bi_dram[i].start = start;
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if ((end + 1) <= end1)
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gd->bd->bi_dram[i].size =
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end - start + 1;
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else
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gd->bd->bi_dram[i].size = end1 - start;
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dram_bank_sort(i);
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i++;
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} else if (start >= PHYS_SDRAM_2 && start <= end2) {
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gd->bd->bi_dram[i].start = start;
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if ((end + 1) <= end2)
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gd->bd->bi_dram[i].size =
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end - start + 1;
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else
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gd->bd->bi_dram[i].size = end2 - start;
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dram_bank_sort(i);
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i++;
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}
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}
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}
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/* If error, set to the default value */
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if (!i) {
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
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gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
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}
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return 0;
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}
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static u64 get_block_attrs(sc_faddr_t addr_start)
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{
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u64 attr = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN;
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if ((addr_start >= PHYS_SDRAM_1 &&
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addr_start <= ((sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) ||
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(addr_start >= PHYS_SDRAM_2 &&
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addr_start <= ((sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE)))
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return (PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE);
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return attr;
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}
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static u64 get_block_size(sc_faddr_t addr_start, sc_faddr_t addr_end)
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{
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sc_faddr_t end1, end2;
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end1 = (sc_faddr_t)PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE;
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end2 = (sc_faddr_t)PHYS_SDRAM_2 + PHYS_SDRAM_2_SIZE;
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if (addr_start >= PHYS_SDRAM_1 && addr_start <= end1) {
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if ((addr_end + 1) > end1)
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return end1 - addr_start;
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} else if (addr_start >= PHYS_SDRAM_2 && addr_start <= end2) {
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if ((addr_end + 1) > end2)
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return end2 - addr_start;
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}
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return (addr_end - addr_start + 1);
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}
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#define MAX_PTE_ENTRIES 512
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#define MAX_MEM_MAP_REGIONS 16
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static struct mm_region imx8_mem_map[MAX_MEM_MAP_REGIONS];
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struct mm_region *mem_map = imx8_mem_map;
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void enable_caches(void)
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{
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sc_rm_mr_t mr;
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sc_faddr_t start, end;
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int err, i;
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/* Create map for registers access from 0x1c000000 to 0x80000000*/
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imx8_mem_map[0].virt = 0x1c000000UL;
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imx8_mem_map[0].phys = 0x1c000000UL;
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imx8_mem_map[0].size = 0x64000000UL;
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imx8_mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN;
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i = 1;
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for (mr = 0; mr < 64 && i < MAX_MEM_MAP_REGIONS; mr++) {
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err = get_owned_memreg(mr, &start, &end);
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if (!err) {
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imx8_mem_map[i].virt = start;
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imx8_mem_map[i].phys = start;
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imx8_mem_map[i].size = get_block_size(start, end);
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imx8_mem_map[i].attrs = get_block_attrs(start);
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i++;
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}
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}
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if (i < MAX_MEM_MAP_REGIONS) {
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imx8_mem_map[i].size = 0;
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imx8_mem_map[i].attrs = 0;
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} else {
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puts("Error, need more MEM MAP REGIONS reserved\n");
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icache_enable();
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return;
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}
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for (i = 0; i < MAX_MEM_MAP_REGIONS; i++) {
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debug("[%d] vir = 0x%llx phys = 0x%llx size = 0x%llx attrs = 0x%llx\n",
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i, imx8_mem_map[i].virt, imx8_mem_map[i].phys,
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imx8_mem_map[i].size, imx8_mem_map[i].attrs);
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}
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icache_enable();
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dcache_enable();
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}
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#ifndef CONFIG_SYS_DCACHE_OFF
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u64 get_page_table_size(void)
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{
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u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64);
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u64 size = 0;
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/*
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* For each memory region, the max table size:
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* 2 level 3 tables + 2 level 2 tables + 1 level 1 table
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*/
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size = (2 + 2 + 1) * one_pt * MAX_MEM_MAP_REGIONS + one_pt;
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/*
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* We need to duplicate our page table once to have an emergency pt to
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* resort to when splitting page tables later on
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*/
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size *= 2;
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/*
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* We may need to split page tables later on if dcache settings change,
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* so reserve up to 4 (random pick) page tables for that.
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*/
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size += one_pt * 4;
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return size;
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}
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#endif
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