Commit graph

22763 commits

Author SHA1 Message Date
Aswath Govindraju
626a2fdb98 arm: dts: k3-j721s2: Add r5 specific dt support
Add initial support for device tree that runs on R5.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08 09:41:27 -05:00
Aswath Govindraju
a9d8cf24a4 arm: dts: Add support for A72 specific J721S2 Common Processor Board
The EVM architecture for J721S2 is similar to that of J721E and J7200. It
is as follows,

+------------------------------------------------------+
|   +-------------------------------------------+      |
|   |                                           |      |
|   |        Add-on Card 1 Options              |      |
|   |                                           |      |
|   +-------------------------------------------+      |
|                                                      |
|                                                      |
|                     +-------------------+            |
|                     |                   |            |
|                     |   SOM             |            |
|  +--------------+   |                   |            |
|  |              |   |                   |            |
|  |  Add-on      |   +-------------------+            |
|  |  Card 2      |                                    |    Power Supply
|  |  Options     |                                    |    |
|  |              |                                    |    |
|  +--------------+                                    | <---
+------------------------------------------------------+
                                 Common Processor Board

Common Processor board is the baseboard that contains most of the actual
connectors, power supply etc. The System on Module (SoM) is plugged on to
the common processor baord. Therefore, add support for peripherals brought
out in the common processor board.

Link to Common Processor Board: https://www.ti.com/lit/zip/sprr439

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08 09:41:27 -05:00
Aswath Govindraju
05d441a713 arm: dts: Add initial support for J721S2 System on Module
A System on Module (SoM) contains the SoC, PMIC, DDR and basic high speed
components necessary for functionality. Therefore, add support for the
components present on the SoM.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2022-02-08 09:41:27 -05:00
Aswath Govindraju
2bab70ed04 arm: dts: Add initial support for J721S2 SoC
The J721S2 SoC belongs to the K3 Multicore SoC architecture platform,
providing advanced system integration in automotive ADAS applications and
industrial applications requiring AI at the network edge. This SoC extends
the Jacinto 7 family of SoCs with focus on lowering system costs and power
while providing interfaces, memory architecture and compute performance for
single and multi-sensor applications.

Some highlights of this SoC are:

* Dual Cortex-A72s in a single cluster, three clusters of lockstep capable
dual Cortex-R5F MCUs, Deep-learning Matrix Multiply Accelerator(MMA), C7x
floating point Vector DSP.
* 3D GPU: Automotive grade IMG BXS-4-64
* Vision Processing Accelerator (VPAC) with image signal processor and
Depth and Motion Processing Accelerator (DMPAC)
* Two CSI2.0 4L RX plus one eDP/DP, two DSI Tx, and one DPI interface.
* Two Ethernet ports with RGMII support.
* Single 4 lane PCIe-GEN3 controllers, USB3.0 Dual-role device subsystems,
* Up to 20 MCANs, 5 McASP, eMMC and SD, OSPI/HyperBus memory controller,
QSPI, I3C and I2C, eCAP/eQEP, eHRPWM, MLB among other peripherals.
* Hardware accelerator blocks containing AES/DES/SHA/MD5 called SA2UL
management.

See J721S2 Technical Reference Manual (SPRUJ28 – NOVEMBER 2021)
for further details: http://www.ti.com/lit/pdf/spruj28

Introduce basic support for the J721S2 SoC.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
2022-02-08 09:41:27 -05:00
David Huang
681023aba4 arm: K3: Add basic support for J721S2 SoC definition
Add basic support for J721S2 SoC definition

Signed-off-by: David Huang <d-huang@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Hari Nagalla <hnagalla@ti.com>
2022-02-08 09:41:26 -05:00
Marcel Ziswiler
2bc2f817ce board: toradex: add verdin imx8m plus support
This adds initial support for the Toradex Verdin iMX8M Plus Quad 4GB WB
IT V1.0B module. They are strapped to boot from eFuses which are factory
fused to properly boot from their on-module eMMC. U-Boot supports
booting from the on-module eMMC only, SDP support is disabled for now
due to missing i.MX 8M Plus USB support.

Functionality wise the following is known to be working:
- eMMC, 8-bit and 4-bit MMC/SD card slots
- Ethernet both on-module eQoS and FEC (requires PHY on carrier board)
- GPIOs
- I2C

Boot sequence is:
SPL ---> ATF (TF-A) ---> U-boot proper

ATF, U-boot proper and u-boot.dtb images are packed into a FIT image,
loaded by SPL.

Boot:
U-Boot SPL 2022.04-rc1-00164-g21a0312611-dirty (Feb 07 2022 - 11:34:04 +0100)
Quad die, dual rank failed, attempting dual die, single rank configuration.
Normal Boot
WDT:   Started watchdog@30280000 with servicing (60s timeout)
Trying to boot from BOOTROM
Find img info 0x&48025a00, size 872
Need continue download 1024
Download 779264, Total size 780424
NOTICE:  BL31: v2.2(release):rel_imx_5.4.70_2.3.2_rc1-5-g835a8f67b
NOTICE:  BL31: Built : 16:52:37, Aug 26 2021

U-Boot 2022.04-rc1-00164-g21a0312611-dirty (Feb 07 2022 - 11:34:04 +0100)

CPU:   Freescale i.MX8MP[8] rev1.1 at 1200 MHz
Reset cause: POR
DRAM:  8 GiB
Core:  78 devices, 18 uclasses, devicetree: separate
WDT:   Started watchdog@30280000 with servicing (60s timeout)
MMC:   FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... OK
In:    serial
Out:   serial
Err:   serial
Model: Toradex Verdin iMX8M Plus Quad 4GB Wi-Fi / BT IT V1.0B, Serial# 06817281
Carrier: Toradex Verdin Development Board V1.1A, Serial# 10807609
Setting variant to wifi
Net:   Hard-coding pdata->enetaddr
eth1: ethernet@30be0000, eth0: ethernet@30bf0000 [PRIME]
Hit any key to stop autoboot:  0
Verdin iMX8MP #

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-07 16:33:22 +01:00
Michal Simek
af98bf62fa arm64: zynqmp: Remove SOM *u-boot.dtsi
Disable mmc from u-boot.dtsi file because it was there only for kv260
board. With kr260 this is not needed because we will switch to full DT per
board with SD/EMMC there too.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/3440d9f94361b4800658f313a5785f43ee84ecf3.1642590109.git.michal.simek@xilinx.com
2022-02-07 10:37:21 +01:00
Heiko Thiery
16c7369ede board: kontron: pitx-imx8m: Add Kontron pitx-imx8m board support
The Kontron pitx-imx8m is an NXP i.MX8MQ based board in the pITX form factor.

Signed-off-by: Heiko Thiery <heiko.thiery@gmail.com>
2022-02-05 15:49:02 +01:00
Angus Ainslie
be63dc7956 mach-imx: iomux-v3: add a define for the SION bit
SION (Software Input On Field) - force the select mode input path

Signed-off-by: Angus Ainslie <angus@akkea.ca>
2022-02-05 15:49:02 +01:00
Angus Ainslie
881c8a6154 arm: dts: imx8mq kernel dts updates
Update to the 5.16 imx8mq dts files and dt bindings

Changes since v1:

Dropped rfkill.h that is not in linux mainline yet.

Signed-off-by: Angus Ainslie <angus@akkea.ca>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-05 15:49:02 +01:00
Dario Binacchi
0c9c5d2ca5 mx6: crm_regs: drop BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ
Commit 97c16dc8bf ("imx: mx6ull: update the REFTOP_VBGADJ setting")
made this macro unused. Then remove it.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-05 15:49:02 +01:00
Dario Binacchi
c1af358cf5 imx: mx6ull: fix REFTOP_VBGADJ setting
The previous code wrote the contents of the fuse as is in the
REFTOP_VBGADJ[2:0], but this was wrong if you consider the contents of
the table in the code comment. This table is also different from the
table in the commit description. But then, which of the two is correct?
If it is assumed that an unprogrammed fuse has a value of 0 then for
backward compatibility of the code REFTOP_VBGADJ[2:0] must be set to
6 (b'110). Therefore, the table in the code comment can be considered
correct as well as this patch.

Fixes: 97c16dc8bf ("imx: mx6ull: update the REFTOP_VBGADJ setting")
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2022-02-05 15:49:02 +01:00
Richard Zhu
0e0ae730bb arm64: dts: imx8mm: Add the pcie support
Add the PCIe support on i.MX8MM platforms.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Tim Harvey <tharvey@gateworks.com>
Tested-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Marek Vasut <marex@denx.de> # Pick from Linux 854a4766ac12 ("arm64: dts: imx8mm: Add the pcie support")
2022-02-05 15:49:01 +01:00
Richard Zhu
f1cc436247 arm64: dts: imx8mm: Add the pcie phy support
Add the PCIe PHY support on iMX8MM platforms.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Tim Harvey <tharvey@gateworks.com>
Tested-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Marek Vasut <marex@denx.de> # Pick from Linux b9ec888f636f ("arm64: dts: imx8mm: Add the pcie phy support")
2022-02-05 15:49:01 +01:00
Ying-Chun Liu (PaulLiu)
6c3373b386 arm: dts: add imx8mp-rsb3720-a1 dts file
Add board dts for Advantech's imx8mp-rsb3720-a1

Signed-off-by: Darren Huang <darren.huang@advantech.com.tw>
Signed-off-by: Kevin12.Chen <Kevin12.Chen@advantech.com.tw>
Signed-off-by: Phill.Liu <Phill.Liu@advantech.com.tw>
Signed-off-by: Tim Liang <tim.liang@advantech.com.tw>
Signed-off-by: wei.zeng <wei.zeng@advantech.com.cn>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: uboot-imx <uboot-imx@nxp.com>
2022-02-05 15:49:01 +01:00
Marek Vasut
dd4b3ca52c arm64: dts: imx8mm: Add missing MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B
The i.MX8M Mini Application Processor Reference Manual, Rev. 3, 11/2020
documents AF MX8MM_IOMUXC_NAND_READY_B_SD3_RESET_B , add it into the
pinmux tables.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-05 15:49:01 +01:00
Oliver Stäbler
9aac5c3c7e arm64: dts: imx8mm/q: Fix pad control of SD1_DATA0
Fix address of the pad control register
(IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0) for SD1_DATA0_GPIO2_IO2.  This seems
to be a typo but it leads to an exception when pinctrl is applied due to
wrong memory address access.

Signed-off-by: Oliver Stäbler <oliver.staebler@bytesatwork.ch>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Fixes: c1c9d41319c3 ("dt-bindings: imx: Add pinctrl binding doc for imx8mm")
Fixes: 748f908cc882 ("arm64: add basic DTS for i.MX8MQ")
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Marek Vasut <marex@denx.de> # Picked from Linux 5cfad4f45806f ("arm64: dts: imx8mm/q: Fix pad control of SD1_DATA0")
2022-02-05 15:49:01 +01:00
Marek Vasut
2c9d2acefa ARM: imx: imx8m: Add PLL 1.4 GHz, 1.5 GHz, 1.6 GHz, 1.8 GHz options
Add PLL 1.4 GHz, 1.5 GHz, 1.6 GHz, 1.8 GHz options for iMX8M SoCs
in case they should be operated faster, e.g. to improve boot time.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2022-02-05 15:49:01 +01:00
Marek Vasut
66e90be99f ARM: imx: imx8m: Align PLL 1.2 GHz option with Linux
Linux uses slightly different divider settings for the 1.2 GHz PLL
configuration, adjust the coefficients to match Linux.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2022-02-05 15:49:01 +01:00
Andrey Zhizhikin
1289ff7bd7 imx8m: lock id_swap_bypass bit in tzc380 enable
According to TRM for i.MX8M Nano and Plus, GPR10 register contains lock
bit for TZASC_ID_SWAP_BYPASS bit. This bit is required to be set in
order to avoid AXI bus errors when GPU is enabled on the platform.
TZASC_ID_SWAP_BYPASS bit is alread set for all imx8m applicable
derivatives, but is missing a lock settings to be applied.

Set the TZASC_ID_SWAP_BYPASS_LOCK bit for those derivatives which have
it implemented.

Since we're here, provide also names to bits from TRM instead of using
BIT() macro in the code.

Fixes: deca6cfbf5 ("imx8mn: set BYPASS ID SWAP to avoid AXI bus errors")
Fixes: a07c718129 ("imx8mp: set BYPASS ID SWAP to avoid AXI bus errors")
Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Cc: Peng Fan <peng.fan@nxp.com>
2022-02-05 15:49:01 +01:00
Adam Ford
2f95456a9a imx: imx8mm_beacon: Enable USB
With the updated device tree's having USB support, enable in
U-Boot.  This also requires the addition of the imx8m power
domain, since the USB is gated by the power domain controller.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-05 15:49:01 +01:00
Adam Ford
d81c6a9f63 arm: dts: imx8mm-beacon: Resync dtsi with Kernel 5.17-rc1
Resync the SOM and baseboar files with the device trees that will
be included in 5.17-RC1 when it's cut.  This will improve pinmuxing
for USDHC1 and add USB functionality.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-05 15:49:01 +01:00
Andrey Zhizhikin
94588ff395 imx8mn-ddr4-evk: generate single bootable image
As suggested in commit 028abfd9b1 ("imx8mm-evk: Generate a single
bootable flash.bin again") for imx8mm_evk, it is possible to produce
single bootable image via binman. This restores the original behavior in
distros, where only one boot container is used to create target image.

Perform similar adaptions in order to provide single bootable image for
imx8mn-ddr4-evk derivate.

Update documentation to drop additional step of copying u-boot.itb

Fixes: 353dfe4b43 ("imx8mn-ddr4-evk: switch to use binman")
Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-05 15:49:01 +01:00
Patrick Wildt
ea4e9387e3 arm64: dts: imx8mq-u-boot.dtsi: improve odd blob-ext naming
Rather than using odd implicit blob-ext naming, explicitly specify the
type to be of blob-ext and therefore also simplify the node naming.

Signed-off-by: Patrick Wildt <patrick@blueri.se>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-02-05 15:49:01 +01:00
Patrick Wildt
49f55653fd arm64: dts: imx8mm-u-boot.dtsi: use dash for node names
Some of the nodes were named using a underscore, so rectify this and
consistenly use dashes.

Signed-off-by: Patrick Wildt <patrick@blueri.se>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2022-02-05 15:49:01 +01:00
Patrick Wildt
553216f6f9 arm64: dts: imx8mq-u-boot.dtsi: explicitly add spl filename
Explicitly add SPL aka u-boot-spl.bin filename.

Signed-off-by: Patrick Wildt <patrick@blueri.se>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-02-05 15:49:01 +01:00
Patrick Wildt
440c7d1188 arm64: dts: imx8mq-u-boot.dtsi: alphabetically re-order properties
Alphabetically re-order properties.

Signed-off-by: Patrick Wildt <patrick@blueri.se>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-02-05 15:49:01 +01:00
Heiko Thiery
1bcda4efed imx: imx8mm: imx8mm-kontron-n801x-s: add common board u-boot.dtsi
When using a board variant that selects the lvds specific dtb the
*.u-boot.dtsi file will not be included. To have a lvds dtb specific
u-boot.dtsi file move this part to a common board u-boot.dtsi file and
include this in the board base u-boot.dtsi and create an additional one
for the lvds variant.

Signed-off-by: Heiko Thiery <heiko.thiery@gmail.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2022-02-05 15:49:01 +01:00
Michael Trimarchi
02737ac86d cmd_nandbcb: Support secondary boot address of imx8mn
Add support of secondary boot address for imx8mn. The secondary
boot address is hardcoded in the fuse. The value is calculated
from there according to the following description:

The fuse IMG_CNTN_SET1_OFFSET (0x490[22:19]) is defined as follows:
- Secondary boot is disabled if fuse value is bigger than 10, n = fuse
  value bigger than 10.
- n == 0: Offset = 4MB
- n == 2: Offset = 1MB
- Others & n <= 10 : Offset = 1MB*2^n
- For FlexSPI boot, the valid values are: 0, 1, 2, 3, 4, 5, 6, and 7.

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
2022-02-05 13:38:39 +01:00
Sven Schwermer
0be742d06d imx: Enable ACTLR.SMP in SPL for i.MX6/7
Similar to what has been done before with c5437e5b for u-boot proper, we
enable the SMP bit for SPL as well. This is necessary when SDP booting
straight into Linux, i.e. falcon boot. When SDP boot mode is active, the
ROM code does not set this bit which makes the caches not work once
activated in Linux.

On an i.MX6ULL (528MHz), this reduces a minimal kernel's boot time into
an initramfs shell from ~6.1s down to ~1.2s.

Signed-off-by: Sven Schwermer <sven@svenschwermer.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-05 13:38:39 +01:00
Marek Vasut
8ed378ff78 ARM: dts: imx: Synchronize iMX6QDL DHCOM PDK2 DTs with Linux 5.15.12
Synchronize DH DHCOM DTs with Linux commit 25960cafa06e ("Linux 5.15.12").
There is no functional change to the resulting DTs. The imx6qdl-dhcom-pdk2.dtsi
had to be adjusted with additional headers, gpio.h, pwm.h, input.h, else
the DT cannot be compiled, the same change is likely necessary in Linux.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-05 13:38:39 +01:00
Marek Vasut
2ab0b52841 ARM: dts: imx: Add labels to remaining anatop regulators
Add labels to remaining anatop regulators, so their supplies can be
assigned in board DTs. This is similar to Linux kernel commit
93385546ba369 ("ARM: dts: imx6qdl-sabresd: Assign corresponding power supply for LDOs")
except it does not contain the unrelated sabresd changes.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-05 13:38:39 +01:00
Lukasz Majewski
e2a636082e arm: dts: Enable support for USB on XEA (imx28) board
This change enables the support for USB with DM on the XEA (imx28)
board.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2022-02-05 13:38:39 +01:00
Lukasz Majewski
1e7212ee9f xea: dts: Update the SPI-NOR flash memory partitions description
Now the dts information corresponds to the one available in the kernel.
With this patch applied the 'mtd list' shows proper names and
offsets for MTD partitions.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2022-02-05 13:38:39 +01:00
Lukasz Majewski
014315b2d8 spl: Provide more space to be used for storing SPL on imx28 OCRAM
With the current configuration provided in mxsimage{-spl}.mx28.cfg the
size of SPL binary has been constrained to 32 KiB, due to "LOAD IVT"
command with 0x8000 offset.

The problem was that, the imx28 ROM takes the u-boot.sb and then
extracts from it the IVT header and places it on the 0x8000 OCRAM offset
overwriting any valid (i.e. loaded from eMMC or SPI-NOR) SPL code. This
bug was unnoticed as the overwrite size was just 32 bytes, so the
probability that some important code is altered was low.

However, in the XEA board (where the SPL size is ~39KiB), the overwritten
data was `(struct dm_spi_ops *) 0x800c <mxs_spi_ops>`, which is used
during the boot process.

As a result the SPL execution code hanged with "undefined instruction"
abort as callbacks (with wrong addresses) from it were called.

The fix is to change the OCRAM's offset where IVT is loaded to 0xE000,
so the SPL can grow up to ~57KiB (the maximal size of OCRAM memory
available is 0xE3FC).

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2022-02-05 13:38:39 +01:00
Fabio Estevam
e195550bfd ARM: dts: imx6ull: Use the correct name for ESAI_TX0
According to the i.MX6ULL Reference Manual, pad CSI_DATA07 may
have the ESAI_TX0 functionality, not ESAI_T0.

Also, NXP's i.MX Config Tools 10.0 generates dtsi with the
MX6ULL_PAD_CSI_DATA07__ESAI_TX0 naming, so fix it accordingly.

There are no devicetree users in mainline that use the old name,
so just remove the old entry.

Fixes: f8ca22b8de ("arm: dts: imx6ull: add pinctrl defines")
Reported-by: George Makarov <georgemakarov1@gmail.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
2022-02-05 13:38:39 +01:00
Harald Seiler
12f9b4d086 mx6: Use imx6_src_get_boot_mode() to check boot device
Use imx6_src_get_boot_mode() instead of manually reading SBMR1.  The
existing function has proper handling for software overrides of the
bootdevice which can happen, for example, when booting from an alternate
source using `bmode`.

Signed-off-by: Harald Seiler <hws@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-05 13:38:39 +01:00
Christoph Niedermaier
ca27227c59 ARM: dts: imx6q-dhcom: Use 1G ethernet on the PDK2 board
The PDK2 board is capable of running both 100M and 1G ethernet. However,
the i.MX6 has only one ethernet MAC, so it is possible to configure
either 100M or 1G Ethernet. In case of 100M option, the PHY is on the
SoM and the signals are routed to a RJ45 port. For 1G the PHY is on
the PDK2 board with another RJ45 port. 100M and 1G ethernet use
different signal pins from the i.MX6, but share the MDIO bus.

This SoM board combination is used to demonstrate how to enable 1G
ethernet configuration.

Signed-off-by: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Cc: Stefano Babic <sbabic@denx.de>
2022-02-05 13:38:39 +01:00
Ariel D'Alessandro
c4c1ed68c1 imx8mn_var_som: Add support for Variscite VAR-SOM-MX8M-NANO board
Add support for iMX8MN VAR-SOM-MX8M-NANO board. Enables support for:

- 1GiB DDR4 RAM
- 16 GiB eMMC
- SD card
- Gigabit ethernet
- USBOTG1 peripheral - fastboot

Signed-off-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-05 13:38:39 +01:00
Oleksandr Suvorov
4821074bec colibri-imx8x: add on-module gpio expander fxl6408
The FXL6408 GPIO expander manages critical devices,
including on-module USB hub. Configure the expander to
switch the USB hub into bypass mode, allowing to use
on-carrier-board USB hub.

Signed-off-by: Oleksandr Suvorov <cryosay@gmail.com>
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
2022-02-05 13:38:39 +01:00
Ying-Chun Liu (PaulLiu)
556523b955 arm: imx8m: imx8mm-cl-iot-gate: detect extension board
Extension boards can be added to Compulab's iot-gate-imx8mm.
We implement extension board manager for detecting the extension
boards.

Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: uboot-imx <uboot-imx@nxp.com>
2022-02-05 13:38:39 +01:00
Ying-Chun Liu (PaulLiu)
27ea1c53a3 arm: dts: imx8mm-cl-iot-gate: add Compulab's ied overlays
add the following overlays:
 - IED extension board
 - CAN/TPM/ADC extension board on IED board.

Signed-off-by: Uri Mashiach <uri.mashiach@compulab.co.il>
Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
Cc: uboot-imx <uboot-imx@nxp.com>
2022-02-05 13:38:39 +01:00
Alice Guo
6293b73d0f imx8ulp: implement to obtain the SoC current temperature
Obatin the SoC current temperature in print_cpuinfo().

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05 13:38:39 +01:00
Ye Li
dc77d0f9fc imx8ulp: clock: Handle the DDRLOCKED when setting DDR clock
The DDRLOCKED bit in CGC2 DDRCLK will auto lock up and down by HW
according to DDR DIV updating or DDR CLK halt status change. So DDR
PCC disable/enable will trigger the lock up/down flow. We
need wait until unlock to ensure clock is ready.

And before configuring the DDRCLK DIV, we need polling the DDRLOCKED
until it is unlocked. Otherwise writing ti DIV bits will not set.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05 13:38:39 +01:00
Alice Guo
0f9b10aaba imx8ulp: clock: Support to enable/disable the ADC1 clock
This patch implements enable_adc1_clk() to enable or disable the ADC1
clock on i.MX8ULP.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05 13:38:39 +01:00
Ye Li
484b306b9e imx8ulp: Update ethernet mac to get from fuse
Get the MAC address from fuse bank5 word 3 and 4. It has
MSB first at lowest address, so have a reverse order with other
iMX used in mac.c

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05 13:38:39 +01:00
Ye Li
3b32010691 imx8ulp: clock: Support to reset DCNano and MIPI DSI
When LPAV is allocated to RTD, the LPAV won't be reset. So we have to
reset DCNano and MIPI DSI in u-boot before enabling the drivers

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05 13:38:39 +01:00
Ye Li
55a7e7882d imx8ulp: clock: Reset DDR controller before clock enable
The LPAV is not allocated to APD when dual boot, so LPAV won't
reset when APD is reset. We have to explicitly reset the DDR,
otherwise its initialization will fail.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05 13:38:39 +01:00
Ye Li
9c7fbebe5d imx8ulp: Workaround LPOSC_TRIM fuse load issue
8ULP ROM should read the LPOSC trim BIAS fuse to fill the CGC0
LPOSCCTRL[7:0], but it writes a fixed value on A0.1 revision.

A0.2 will fix the issue in ROM. But A0.1 we have to workaround
it in SPL by setting LPOSCCTRL BIASCURRENT again.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05 13:38:39 +01:00
Ye Li
112b4cac9d imx8ulp: Remove freescale name from CPU revision
Remove the freescale vendor name from CPU revision print to align
with other i.MX platforms

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05 13:38:38 +01:00
Ye Li
bd8b673003 imx8ulp: Fix DCNANO QoS setting
The setting does not have effect because we should set it after
power on the PS16 for NIC AV.

So move it after upower_init which has powered on all PS

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05 13:38:38 +01:00
Ye Li
16062f9b0a imx8ulp: Set DCNANO read QoS on NIC_LPAV to highest
To avoid DCNANO underrun issue on high loading test, set its
read Qos on NIC_LPAV to highest

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05 13:38:38 +01:00
Ye Li
9dde390be6 imx8ulp_evk: Control LPI2C0 PCA6416 and TPM0 for display
The board use IO9 of PCA6416 on LPI2C0 and TPM0 for MIPI DSI MUX and
backlight. However the LPI2C0 and TPM0 are M33 resources, in this
patch we simply access them, but this is a temporary solution.
We will modify it when M33 FW changes to set MIPI DSI panel as default
path and enable backlight after reset.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05 13:38:38 +01:00
Ye Li
608ed200f1 imx8ulp: rdc: allow A35 access flexspi0 mem
For singel boot, set flexspi0 mem to be accessed by A35

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05 13:38:38 +01:00
Ye Li
829e06bf41 imx8ulp: clock: Add MIPI DSI clock and DCNano clock
Add the DSI clock enable and disable with PCC reset used.
Add the LCD pixel clock calculation and configuration for DCNano

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05 13:38:38 +01:00
Ye Li
5ff18da34f imx8ulp: clock: Support LPAV clocks in cgc and pcc
Add the PCC5 clocks support and more LPAV clocks and PLL4 PFD in CGC.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05 13:38:38 +01:00
Peng Fan
99de168f7e imx8ulp: assign PXP/HIFI4/EPDC to APD domain
Assign the PXP/HIFI4/EPDC to APD domain, otherwise APD not
able to receive interrupts from the modules.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05 13:38:38 +01:00
Ye Li
d563d29203 arm: imx8ulp: Allocate LPAV resources to AP domain
When single boot, assign AP domain as the master domain of the LPAV.
Allocates LPAV master and slave resources like GPU, DCNano, MIPI-DSI
eDMA channel and eDMA request to APD

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05 13:38:38 +01:00
Ye Li
961ac78735 imx8ulp: soc: Check the DBD_EN fuse before setting RDC
S400 enables RDC only when the DBD_EN is fused. Otherwise, the RDC
is allowed by all masters.

Current S400 has issue if the XRDC has released to A35, then A35 reset
will fail in ROM due to S400 fails to get XRDC.
So temp work around is checking the DBD_EN, if it is not fused, we
don't need to call release XRDC or TRDC.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-02-05 13:38:38 +01:00
Ricardo Salveti
89ca5a7ee1 ARM: imx8m: support env in fat and ext4
Change boot device logic to also allow environment stored in fat and in
ext4 when booting from SD or from eMMC.

As the boot device check for SD and for eMMC was depending on
ENV_IS_IN_MMC being defined, change the ifdef blocks at env_get_location
to use IS_ENABLED instead for all modes, returning NOWHERE when no valid
mode is found.

Signed-off-by: Ricardo Salveti <ricardo@foundries.io>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-05 13:38:38 +01:00
Pali Rohár
af602631e0 imx: nandbcb: Fix printf format in write_fcb
Correct printf format for unsigned long long is %llx and not %llxx.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-05 13:38:38 +01:00
Lukasz Majewski
91f27f3ba8 mxs: power: Change sequence of enabling DCDC switches
The imx28 uses following voltage supplies hierarchy:

VDD_5V (VDD_BAT) -> VDDIO -> VDDA -> VDDMEM
			     \-----> VDDD

One shall first enable DCDC on the parent source (VDDIO) and then
follow with its children.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-05 13:38:38 +01:00
Tim Harvey
cd0ecb3d80 imx8mm-venice-gw7902: fix M2_RST# gpio pinmux
Fix the invalid gw7902 M2_RST# gpio pinmux.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-05 13:38:38 +01:00
Ricardo Salveti
8b71576f38 mx7ulp_com: add support for SPL
Add EA iMX7ULP COM board support for building SPL.

Signed-off-by: Ricardo Salveti <ricardo@foundries.io>
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
2022-02-05 13:38:38 +01:00
Oleksandr Suvorov
498eedc0d4 mx7ulp: select soc features
Force selecting features present in SoC i.MX7ULP.

Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Reviewed-by: Igor Opaniuk <igor.opaniuk@foundries.io>
2022-02-05 13:38:38 +01:00
Heiko Thiery
6ff55bcd07 arm: imx: imx8mq: add support to get values for more clocks
Return the root clock values for MXC_CSPI_CLK, MXC_I2C_CLK,
MXC_UART_CLK and MXC_QSPI_CLK.

At least for the I2C clock the missing support leads to a wrong
configured I2C frequency. The expected value is 100kHz but the resulting
value is about 1MHz.

Signed-off-by: Heiko Thiery <heiko.thiery@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-02-05 13:38:38 +01:00
Jorge Ramirez-Ortiz
25a91f3005 arm64: zynqmp: Print the secure boot status information
Output the secure boot configuration to the console.

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Link: https://lore.kernel.org/r/20211013170447.10414-1-jorge@foundries.io
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-02-04 13:16:45 +01:00
Codrin Ciubotariu
17a9f3f53d ARM: dts: at91: sama7g5ek: disable slew rate for GMACs non MDIO pins
Non GMAC's MDIO pins should have slew rate disabled for R(G)MII modes. Set
them accordingly in DT.

Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
Tested-by: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2022-02-04 13:53:58 +02:00
Tom Rini
3aaabfe9ff Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi
This is the promised second part of the sunxi PR for 2022.04, albeit
technially outside of the merge window. We were working on this full
steam since the beginning of the year, and it deserves to be merged,
I think.
The main attraction is support for the F1C100s SoC, which sports a
venerable ARM926 core. Support for this SoC and the LicheePi Nano board
has been in Linux for years, and U-Boot patches were posted mid last
year already.
The new SoC using ARMv5 also means that the bulk of the new code should
not touch any existing boards, although we did some refactorings first,
of course, which actually cleans up some existing sunxi code.

Compile tested for all 160 sunxi boards, and briefly tested on BananaPi M1,
OrangePi Zero, Pine64 and Pine-H64. Tested by others on their boards,
including F1C100s and F1C200s devices.
2022-02-03 23:24:31 -05:00
Icenowy Zheng
ce2b6c4481 ARM: dts: suniv: Add device tree files and bindings for F1C100s
Add device tree files for suniv and
Lichee Pi Nano it is a board based on F1C100s.
dt-bindings/dts are synced with 5.16.0

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-02-04 00:09:57 +00:00
Icenowy Zheng
cfe673cda7 mach-sunxi: Add support for SUNIV architecture
Add support for the suniv architecture, which is newer ARM9 SoCs by
Allwinner. The design of it seems to be a mixture of sun3i, sun4i and
sun6i.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-02-04 00:09:57 +00:00
Icenowy Zheng
645ee3c25d sunxi: Add F1C100s DRAM initial support
Add support for F1C100s internal dram controller.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-02-04 00:09:57 +00:00
Icenowy Zheng
5d35f0f254 ARM: sunxi: Add clock and uart to sunxi headers
This patch aims to add header files for the suniv.
The header files included add support for uart, and clocks.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-02-04 00:09:57 +00:00
Icenowy Zheng
88998f7775 arm: arm926ej-s: Add sunxi code
Some Allwinner SoCs use ARM926EJ-S core.

Add Allwinner/sunXi specific code to ARM926EJ-S CPU dircetory.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-02-04 00:09:57 +00:00
Jesse Taube
0d4377fc92 mach-sunxi: Move timer code to mach folder
Both armv7 and arm926ejs use this timer code so move it to mach-sunxi.

Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-02-04 00:09:57 +00:00
Icenowy Zheng
508f75afb5 arm: arm926ej-s: start.S: port save_boot_params support from armv7 code
The ARMv7 start code has support for saving some boot params at the
entry point, which is used by some SoCs to return to BROM.

Port this to ARM926EJ-S start code.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-02-04 00:09:57 +00:00
Andre Przywara
b8cd7f439a armv8: remove no longer needed lowlevel_init.S
When we added Allwinner SoC support to ARMv8, we needed to pull in an
implementation of lowlevel_init() calling the C function s_init(), as
sunxi required it as this time.

The last few patches got rid of this bogus requirement, and as sunxi was
still the only user, we can now remove this lowlevel_init.S from ARMv8
altogether.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2022-02-04 00:09:57 +00:00
Andre Przywara
534b82a1f2 sunxi: move early "SRAM setup" into separate file
Currently we do some magic "SRAM setup" MMIO writes in s_init(), copied
from the original BSP U-Boot. The comment speaks of this being required
before DRAM access gets enabled, but there is no indication that this
would actually be required that early.

Move this out of s_init(), into board_init_f(). Since this actually only
affects a very few older SoCs, the actual code goes into the cpu/armv7
directory, to move it out of the way for all other SoCs.

This also uses the opportunity to convert some #ifdefs over to the fancy
IS_ENABLED() macros used in actual C code.

We keep the s_init() stub around for now, since armv8's lowlevel_init
still relies on it.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2022-02-04 00:09:57 +00:00
Andre Przywara
2564fce7ee sunxi: move Cortex SMPEN setting into start.S
According to their TRMs, Cortex ARMv7 CPUs with SMP support require the
ACTLR.SMPEN bit to be set as early as possible, before any cache or TLB
maintenance operations are done. As we do those things still in start.S,
we need to move the SMPEN bit setting there, too.

This introduces a new ARMv7 wide symbol and code to set bit 6 in ACTLR
very early in start.S, and moves sunxi boards over to use that instead
of the custom code we had in our board.c file (where it was called
technically too late).

In practice we got away with this so far, because at this point all the
other cores were still in reset, so any broadcasting would have been
ignored anyway. But it is architecturally cleaner to do it early, and
we move a core specific piece of code out of board.c.

This also gets rid of the ARM_CORTEX_CPU_IS_UP kludge I introduced a few
years back, and moves the respective logic into the new Kconfig entry.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-02-04 00:09:36 +00:00
Andre Przywara
5bc4cd05d7 sunxi: move non-essential code out of s_init()
So far all Allwinner based boards were doing some not-so-lowlevel-setup
in lowlevel's s_init() routine.
This includes the initial clock, timer and pinmux setup, among other
things. This is clearly out of the "absolute bare minimum to get started"
scope that lowlevel_init.S suggests for this function.

Since we have an SPL, which is called right after s_init(), move those
calls to our board_init_f() function. As we overwrite this only for
the SPL, this has the added benefit of not doing this setup *again*
shortly afterwards, when running U-Boot proper.

This makes gpio_init() to be called from the SPL only, so pull this code
into a CONFIG_SPL_BUILD protected part to avoid build warnings.

Reviewed-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-02-04 00:09:03 +00:00
Andre Przywara
68f08966b0 armv8: start.S: remove CONFIG_SYS_RESET_SCTRL code
There is some code that tries to "reset" the SCTLR_ELx register early in
the boot process. The idea seems to be to guarantee some sane settings
that U-Boot actually relies on, for instance running in little-endian
mode, with the MMU off initially.
However the current code has multiple problems:
- For a start, no platform or config defines the symbol that would
  enable that code.
- The code itself really only works if the bits that it tries to clear
  are already cleared:
  - If we run in big-endian mode initially, any previous loads would have
    been wrong already. That applies to the (optional) relocation code,
    but more prominently to the mask that it uses to clear those bits:
    "ldr x1, =0xfdfffffa" looks innocent, but actually involves a memory
    access to the literal pool, using the current endianness.
  - If we run with the MMU enabled, we are probably doomed already. We
    *could* hope that we are running with an identity mapping, but would
    need to do some cache maintenance to avoid losing dirty cache lines.
- The idea of doing a read-modify-write of SCTLR is somewhat
  questionable to begin with, because as the owner of the current
  exception level we should initialise all bits of this register with a
  certain fixed value.
- The code is unnecessarily complicated, and the function name is
  misspelled.

While those problems *could* admittedly be fixed, the point that is does
not seem to be used at all at the moment tells me we should just remove
this code, and be it to not give a bad example.

If people care, I could introduce some proper SCTLR initialisation code.
We are about to work this out for the boot-wrapper[1] as we speak, but
apparently we got away without doing this in U-Boot ever since, so it
might not be worth the potential trouble.

[1] https://lore.kernel.org/linux-arm-kernel/20220114105653.3003399-7-mark.rutland@arm.com/

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-02-03 12:15:37 -05:00
Alper Nebi Yasak
22eb7ba80e armv8: spl: Fix build with LINUX_KERNEL_IMAGE_HEADER
Setting LINUX_KERNEL_IMAGE_HEADER=y attempts to include an ARM64 Linux
kernel image header at the start of both U-Boot proper and SPL binaries.
However, some definitions that the image header uses are not included by
the SPL linker script, resulting in a build error. Include them the way
they are included in U-Boot proper's linker script to fix the error.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2022-02-03 12:15:33 -05:00
Vladimir Oltean
681adaa466 arm: dts: ls1028a-qds: declare in-band autoneg for Ethernet ports
The commit in the Fixes: tag below broke traffic through switch ports
where the SERDES protocol requires in-band autoneg and this requirement
isn't described in the device tree: SGMII, QSGMII, USXGMII (with
2500Base-X, in-band autoneg isn't supported).

The LS1028A-QDS boards are not yet ready for syncing their device trees
with Linux, since Ethernet is missing there (but has been submitted):
https://lore.kernel.org/lkml/20211112223457.10599-11-leoyang.li@nxp.com/

When agreement is reached for the Ethernet support in Linux, there will
be a sync for these boards as well. For now, just enable in-band autoneg
to fix the breakage.

Fixes: e3789a7262 ("net: dsa: felix: configure the in-band autoneg property based on OF node info")
Cc: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2022-02-01 15:08:07 +05:30
Vladimir Oltean
bee9fd2957 arm: dts: ls1028a-rdb: sync device tree with Linux
Allow device trees to be reused between Linux and U-Boot.
The source for these device trees is linux-next as of commit
bd8a9cd624c6 ("arm64: dts: ls1028a-rdb: update copyright"), which was
chosen because some changes needed to be done to the Linux DTs too,
before they could be shared:
https://lore.kernel.org/linux-arm-kernel/20211202141528.2450169-5-vladimir.oltean@nxp.com/T/#m6f63c92e75fa79a01144b2c2c6dc4776e7971395

There are two more commits on the RDB device tree which haven't been
picked up yet, because they have dependencies on the SoC device tree:

dd3d936a1b17 ("arm64: dts: ls1028a: add ftm_alarm1 node to be used as wakeup source")
b2e2d3e02fb6 ("arm64: dts: ls1028a-rdb: enable pwm0")

These will be picked up on the next resync.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: Michael Walle <michael@walle.cc>
2022-02-01 15:08:07 +05:30
Vladimir Oltean
50c49ef2ff arm: dts: ls1028a-rdb: enable PCIe controllers from U-Boot dtsi
Reuse the scheme implemented by the Kontron SL28 boards in
commit d08011d7f9
("arm: dts: ls1028a: disable the PCIe controller by default")
and move the 'status = "okay"' lines for the PCIe controllers
inside a separate U-Boot dtsi for the LS1028A-RDB board. This way, the
existing Linux device tree can simply be dropped in.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2022-02-01 15:08:07 +05:30
Vladimir Oltean
f33fad6f37 arm: dts: ls1028a-rdb: disable I2C buses 1 through 7
There is no I2C peripheral on these buses on the reference design board,
and the Linux device tree does not enable them either.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2022-02-01 15:08:07 +05:30
Vladimir Oltean
5b0f8eeb3d arm: dts: ls1028a-rdb: disable DSPI nodes
There is no SPI peripheral on the LS1028A-RDB, therefore no reason to
enable these nodes in the U-Boot device tree (and Linux does not enable
them either).

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2022-02-01 15:08:07 +05:30
Vladimir Oltean
4a5362fc10 arm: dts: ls1028a-rdb: sync Ethernet device tree nodes with Linux
In a bit of a blunder, the blamed commit in the Fixes: tag below made
the mscc_felix switch driver look at the 'managed = "in-band-status"'
device tree property, forgetting that the U-Boot device tree had not
been updated to include that property, whereas the Linux one does.

The switch is therefore described in the device tree as not requiring
in-band autoneg, but the PHY driver for VSC8514 (drivers/net/phy/mscc.c)
still enables that feature. This results in a mismatch => no traffic.

This patch is a copy-paste of the Ethernet device tree nodes from Linux,
which resolves that issue. The device tree update also renames the
Ethernet PHY labels.

Fixes: e3789a7262 ("net: dsa: felix: configure the in-band autoneg property based on OF node info")
Cc: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2022-02-01 15:08:07 +05:30
Vladimir Oltean
5009b11bec arm: dts: ls1028a-rdb: sort nodes alphabetically
The nodes in the NXP LS1028A-RDB device tree are out of order, regroup
them alphabetically to have a simple delta when the Linux device tree is
brought in.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2022-02-01 15:08:07 +05:30
Vladimir Oltean
aa0586247b arm: dts: lx2160a-rdb: use Linux compatible string for RTC
During the LS1028A-RDB sync with Linux device trees, it was observed
that the same RTC is present on the two boards, and the wrong compatible
string is used in both places. This change updates the RTC from the
LX2160A-RDB to use the compatible string that was established in Linux.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: Michael Walle <michael@walle.cc>
2022-02-01 15:08:07 +05:30
Vladimir Oltean
41496cc330 arm: dts: ls1028a-rdb: use Linux compatible string for RTC
During this board's sync with Linux device trees, it was observed that
it doesn't use the same compatible string for the RTC node as in U-Boot.
This change makes the RTC compatible strings match, for a smoother sync.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2022-02-01 15:08:07 +05:30
Vladimir Oltean
801f4b0cde arm: dts: ls1028a-qds: use Linux compatible string for RTC
The LS1028A-QDS board won't be synced with the Linux device trees right
now, since those are currently still in progress (Ethernet is missing).

However, while we're at converting the RDB, it can be observed that the
same RTC is present on the two boards, and the wrong compatible string
is used in both places. This change updates the RTC from the QDS to use
the compatible string that was established in Linux.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: Michael Walle <michael@walle.cc>
2022-02-01 15:08:07 +05:30
Vladimir Oltean
246b7e6c9f arm: dts: lx2160a-qds: use Linux compatible string for RTC
During the LS1028A-RDB sync with Linux device trees, it was observed
that the same RTC is present on the two boards, and the wrong compatible
string is used in both places. This change updates the RTC from the
LX2160A-QDS to use the compatible string that was established in Linux.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: Michael Walle <michael@walle.cc>
2022-02-01 15:08:07 +05:30
Vladimir Oltean
5d0b044e96 arm: dts: ls1088a-rdb: use Linux compatible string for RTC
During the LS1028A-RDB sync with Linux device trees, it was observed
that the same RTC is present on the two boards, and the wrong compatible
string is used in both places. This change updates the RTC from the
LS1088A-RDB to use the compatible string that was established in Linux.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: Michael Walle <michael@walle.cc>
2022-02-01 15:08:07 +05:30
Vladimir Oltean
489c428763 arm: dts: ls1088a-qds: use Linux compatible string for RTC
During the LS1028A-RDB sync with Linux device trees, it was observed
that the same RTC is present on the two boards, and the wrong compatible
string is used in both places. This change updates the RTC from the
LS1088A-QDS to use the compatible string that was established in Linux.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: Michael Walle <michael@walle.cc>
2022-02-01 15:08:07 +05:30
Aleksandar Gerasimovski
2e14b1f33f arm/expu1/seli8: adapt dts NOR partition table to the latest used
Even not used by u-boot, this has to be inline with the hw and kernel dts.
U-boot partition table is defined by MTDPARTS_DEFAULT Kconfig.

Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2022-02-01 15:08:07 +05:30
Aleksandar Gerasimovski
7539bb3b7c arm: ls1021a: limit debug eth phy speed to 100Mbps
Beside that mounted rgmii debug phy is 1000Mbps capable, the debug link
between the piggy board and the phy is 100Mbps only.
This leads to longer link establishment time when working in debug mode,
as phy tries to autoneg 1000Mbps.

This patch fixes the speed to 100Mbps and allows smother link establishment
time for the debug interface.

Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachienergy.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2022-02-01 15:04:24 +05:30
Mathew McBride
a1d2fd3874 board: traverse: add initial Ten64 support
The Ten64 is a networking-oriented MiniITX board
using the NXP LS1088A SoC.

This patch provides the bare minimum to support
Ten64 boards under U-Boot for distroboot.

Some related drivers have not yet been submitted
and this basic support lacks some of the
opinionated defaults provided by our firmware
distribution.

Signed-off-by: Mathew McBride <matt@traverse.com.au>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2022-02-01 15:04:24 +05:30
Tony Dinh
71dcfa97fa arm: kirkwood: Pogoplug-V4 : Add Kconfig files
Add Kconfig files for Pogoplug V4 board

Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Pali Rohár <pali@kernel.org>
2022-01-31 10:23:37 +01:00
Tony Dinh
cd1978719c arm: kirkwood: Pogoplug-V4 : Add DTS files
Add DTS files for Pogoplug V4 board

Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Pali Rohár <pali@kernel.org>
2022-01-31 10:23:37 +01:00
Jernej Skrabec
e97943b732 sunxi: Fix H616 DRAM read calibration for dual rank
Although it isn't known what bit 0 in PHY reg 8 does, it's obvious that
it has to be set before read calibration and cleared afterwards. This is
already done for first rank, but not for second (copy & paste error.)

Fix it.

Fixes: f4317dbd06 ("sunxi: Add H616 DRAM support")
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-01-30 01:25:00 +00:00
Jernej Skrabec
18a5927698 sunxi: fix H616 DRAM ODT support
Kconfig symbol is missing CONFIG_ prefix, so compiler will always
skip ODT configuration.

Fix symbol name.

Fixes: f4317dbd06 ("sunxi: Add H616 DRAM support")
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-01-30 01:25:00 +00:00
Chris Morgan
52bcc4f053 sunxi: Add option to prevent booting on power plug-in
For sunxi boards with the AXP209, AXP221, AXP809, and AXP818 PMICs
(plus possibly others, I only confirmed the datasheets for these),
it is sometimes desirable to not boot whenever the device is
plugged in. An example would be when using the NTC CHIP inside a
PocketCHIP.
This provides a configurable option to check if bit 0 of
register 0 of the PMIC says it was powered because of a power button
press (0) or a plug-in event (1). If the value is 1 and this option
is selected, the device shuts down shortly after printing a message
to console stating the reason why it's shutting down. Powering up the
board with the power button is not affected.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
[Andre: reword to speak of boot, remove #ifdefs]
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-01-30 01:25:00 +00:00
Andre Przywara
8695b5111c sunxi: gpio: Fix up pointer arithmetic
The calls for flipping bits in the Allwinner pin controller registers
were using unnecessarily complex pointer arithmetic.

Improve readability by simplifying the expression.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-01-30 01:25:00 +00:00
Samuel Holland
efdd656659 sunxi: gpio: Add per-bank drive and pull setters
The GPIO and pinctrl drivers need these setters for pin configuration.
Since they are DM drivers, they should not be using hardcoded base
addresses. Factor out variants of the setter functions which take a
pointer to the GPIO bank's MMIO registers.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-01-30 01:25:00 +00:00
Samuel Holland
ac5397a219 sunxi: gpio: Return void from setter functions
The return values of these functions are always zero, and they are
never checked. Since they are not needed, remove them.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2022-01-30 01:04:30 +00:00
Vignesh Raghavendra
afe5163449 ARM: dts: k3-am642-sk: Disable cpsw_port1 in SPL
ROM supports cpsw_port2 for Ethernet boot and SPL stages continue to
download images on the same port, therefore there is no need to enable
cpsw_port1. Disable the same.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2022-01-28 17:58:41 -05:00
Heinrich Schuchardt
8e72374feb sandbox: eth-raw: fix building with musl library
The definition of struct udphdr in include netinet/udp.h in the
musl library differs from the definition in the glibc library.

To use the same definition with musl the symbol _GNU_SOURCE has
to be defined.

Reported-by: Milan P. Stanić <mps@arvanta.net>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Tested-by: Milan P. Stanić <mps@arvanta.net>
2022-01-25 14:02:38 -07:00
Simon Glass
9d2adca8c3 x86: Move acpi_get_rsdp_addr() ACPI tables to the writer
Move this over to use a writer file, moving the code from the x86
implementation.

There is no need to store a separate variable since we can simply access
the ACPI context.

With this, the original monolithic x86 function for writing ACPI tables
is gone.

Note that QEMU has its own implementation.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-25 11:44:36 -07:00
Simon Glass
a7e53b93b1 x86: Move device-specific ACPI tables to a writer function
Move this over to use a writer function, moving the code from the x86
implementation.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-25 11:44:36 -07:00
Simon Glass
78031ad431 x86: acpi: Update acpi_fill_csrt() to use acpi_ctx
Update this function to the newer style, so we can avoid passing and
returning an address through this function.

Also move this function out of the x86 code so it can be used by other
archs.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2022-01-25 11:44:36 -07:00
Simon Glass
85b8161b14 x86: Move CSRT table to a writer function
Move this table over to use a writer function, moving the code from the
x86 implementation.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-25 11:44:36 -07:00
Simon Glass
ef55f48788 x86: Move TCPA table to a writer function
Move this table over to use a writer function, for x86 only.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-25 11:44:36 -07:00
Simon Glass
c797f98bcd x86: Move MADT table to a writer function
Move this table over to use a writer function, for x86 only.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-25 11:44:36 -07:00
Simon Glass
9aacd83389 x86: Move TPM2 table to a writer function
Move this table over to use a writer function, for x86 only.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-25 11:44:36 -07:00
Simon Glass
d953137526 x86: Move SSDT table to a writer function
Move this table over to use a writer function, moving the code from the
x86 implementation.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-25 11:44:36 -07:00
Simon Glass
379d3c1fd6 x86: Move FACP table into separate functions
Each board has its own way of creating this table. Rather than calling the
acpi_create_fadt() function for each one from a common acpi_write_fadt()
function, just move the writer into the board-specific code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2022-01-25 11:44:36 -07:00
Simon Glass
138d7ece70 x86: Move FADT table to a writer function
Move this table over to use a writer function, for x86 only.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-25 11:44:36 -07:00
Simon Glass
32af3261f7 x86: Move GNVS table to a writer function
Move this table over to use a writer function, for x86 only. Handle the
two cases

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-25 11:44:36 -07:00
Simon Glass
eacb6d0ba2 x86: Move DSDT table to a writer function
Move this table over to use a writer function, moving the code from the
x86 implementation.

Add a pointer to the DSDT in struct acpi_ctx so we can reference it later.

Disable this table for sandbox since we don't actually compile real ASL
code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-25 11:44:36 -07:00
Simon Glass
a53d38f80a x86: Move FACS table to a writer function
Move this table over to use a writer function, moving the code from the
x86 implementation.

Add a pointer to the DSDT in struct acpi_ctx so we can reference it later.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-25 11:44:36 -07:00
Simon Glass
94ba15a3f1 x86: Move base tables to a writer function
Use the new ACPI writer to write the base tables at the start of the area,
moving this code from the x86 implementation.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-25 11:44:36 -07:00
Simon Glass
31c27eb830 x86: Use the ACPI table writer
Use the new ACPI writer to write the ACPI tables. At present this is all
done in one monolithic function. Future work will split this out.

Unfortunately the QFW write_acpi_tables() function conflicts with the
'writer' version, so disable that for sandbox.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-25 11:44:36 -07:00
Simon Glass
cc1f8c3988 x86: acpi: Split out context creation from base tables
At present acpi_setup_base_tables() both sets up the ACPI context and
writes out the base tables.

We want to use an ACPI writer to write the base tables, so split this
function into two, with acpi_setup_ctx() doing the context set, and
acpi_setup_base_tables() just doing the base tables.

Disable the writer's write_acpi_tables() function for now, to avoid
build errors. It is enabled in a following patch.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-25 11:44:36 -07:00
Simon Glass
383bf1bc9e acpi: Move acpi_fill_header() to the generic header
This function is not x86-specific so move it into the common header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-25 11:44:36 -07:00
Simon Glass
437992d3a9 acpi: Use finer-grained control of ACPI-table generation
Rather than keying everything off ACPIGEN, use the main
GENERATE_ACPI_TABLE option to determine whether the core ACPI code
is included. Make sure these option are not enabled in SPL/TPL since we
never generate tables there.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-25 11:44:36 -07:00
Simon Glass
0679cca507 sandbox: Allow building with GENERATE_ACPI_TABLE
At present this option is missing a header file, a function prototype and
the qfw driver needs a header included.

Fix these problems so we can enable this option on sandbox. This will
increase the build coverage.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-25 11:44:36 -07:00
Simon Glass
27ba6289fe x86: Tidy up use of CONFIG_ACPIGEN
This is enabled for quite a few boards which don't create ACPI tables.
Tidy this up by dropping the option for some boards.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-25 11:44:36 -07:00
Simon Glass
0153723590 arm: Allow supporting ACPI-table generation
Some ARM boards are using ACPI now. It seems that U-Boot should support
this method. Add ARM to the list of archs which can generate ACPI tables.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-25 11:44:36 -07:00
Simon Glass
233f0e35a3 x86: Move the acpi table to generic global_data
Allow this to be used on any arch. Also convert to using macros so that
we can check the CONFIG option in C code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-25 11:44:36 -07:00
Simon Glass
e1722fcb7d x86: Allow any arch to generate ACPI tables
These have sadly found their way to ARM now. Allow any arch to support
generating ACPI tables.

Disable this for the tools build.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-25 11:44:36 -07:00
Patrice Chotard
22c0815eca configs: stm32mp15: Enable OF_BOARD flag
Since commit 9855034397 ("fdt: Don't call board_fdt_blob_setup()
 without OF_BOARD") board_fdt_blob_setup() is no more called on
STM32MP platforms in trusted boot which hangs during boot process.

Enable OF_BOARD flag to fix this issue.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-01-24 11:03:21 +01:00
Patrick Delaunay
94e561f84a stm32prog: add partition name in treat_partition_list error messages
Add the partition name and remove the line number in error messages
of treat_partition_list() to provide correct information to user of
STM32CubeProgrammer.

The "line number" value was confusing because it is incorrect here;
the index in  part_array[] is not aligned with the line number in
the parsed Layout file, because the empty lines and the lines beginning
by '#' are skipped during the first parsing in parse_flash_layout().

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-01-24 11:01:41 +01:00
Marek Vasut
332facce6f ARM: dts: stm32: Synchronize DHCOM DTs with Linux 5.15.12
Synchronize DH DHCOM DTs with Linux commit 25960cafa06e ("Linux 5.15.12").
There is no functional change to the resulting DTs. The eeprom0 alias and
PHY reset GPIO are now reinstated in SoM u-boot dtsi.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-01-24 10:57:56 +01:00
Marek Vasut
6b8bd70904 ARM: dts: stm32: Synchronize DHCOR DTs with Linux 5.15.12
Synchronize DH DHCOR DTs with Linux commit 25960cafa06e ("Linux 5.15.12").
There is no functional change to the resulting DTs. The eeprom0 alias is
now reinstated in SoM u-boot dtsi, the PHY reset GPIO is reinstated in AV96
u-boot dtsi.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2022-01-24 10:57:56 +01:00
Patrick Delaunay
bd485f9bcc arm: dts: stm32mp15: alignment with v5.16
Device tree alignment with Linux kernel v5.16-rc5
- ARM: dts: stm32: set otg-rev on stm32mp151
- ARM: dts: stm32: use usbphyc ck_usbo_48m as USBH OHCI clock on stm32mp151
- ARM: dts: stm32: fix AV96 board SAI2 pin muxing on stm32mp15
- ARM: dts: stm32: fix SAI sub nodes register range
- ARM: dts: stm32: fix STUSB1600 Type-C irq level on stm32mp15xx-dkx

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-01-24 10:57:19 +01:00
Patrick Delaunay
5c68904fe1 stm32mp: correct the dependency for bootcount configs
Default value for CONFIG_SYS_BOOTCOUNT_SINGLEWORD and
CONFIG_SYS_BOOTCOUNT_ADDR are only needed when
CONFIG_BOOTCOUNT_GENERIC is used.

This patch avoids to define these configs when an other bootcount backend
is activated, for example for CONFIG_BOOTCOUNT_ENV.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-01-24 10:56:45 +01:00
Patrick Delaunay
d5e8119bae stm32mp: remove the bootcount activation
Today the bootcount is not managed by the Linux kernel for STM32MP15 as
we don't have driver to update the used backup register in TAMP and the
recovery command still executes the normal bootcmd with
'altbootcmd=run bootcmd'.

So the bootcount feature is never used, the config CONFIG_BOOTCOUNT_LIMIT
and the associated environment variable 'altbootcmd' can be removed to
reduce the U-Boot size.

Each boards can re-enable this feature later in their defconfig, if it is
needed, with the expected backend, for example CONFIG_BOOTCOUNT_GENERIC
or CONFIG_BOOTCOUNT_ENV.

CC: Marek Vasut <marex@denx.de>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-01-24 10:56:45 +01:00
Marek Vasut
3919aa1722 ARM: dts: stm32: Add DFU support for DHCOR recovery
This patch configures U-Boot SPL for DHCOR SoM to permit DFU upload of
SPL and subsequent u-boot.itb for recovery or commissioning purposes.

To start U-Boot on DHCOR based board, e.g. Avenger96, proceed as follows:
- Install dfu-util on the host PC (in debian this is package 'dfu-util')

- Power off the Avenger96 board.
- Connect both USB-serial console and USB-OTG microB ports to host PC.
- Switch Avenger96 to USB boot mode -- BOOT0..2 switches all set to 0.
- Power on the Avenger96 board.
- Verify using '$ dmesg' that a new device has been detected as follows:
    New USB device found, idVendor=0483, idProduct=df11, bcdDevice= 2.00
    New USB device strings: Mfr=1, Product=2, SerialNumber=3
    Product: DFU in HS Mode @Device ID /0x500, @Revision ID /0x0000
    Manufacturer: STMicroelectronics

- Upload U-Boot SPL:
$ dfu-util -a 1 -D u-boot-spl.stm32
- Upload U-Boot proper:
$ dfu-util -a 0 -D u-boot.itb

- At this point, SPL will wait for user to press "Ctrl-C" on serial
  console. When ready to interact with U-Boot, press Ctrl-C to start
  the bootloader.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-01-24 10:55:06 +01:00
Marek Vasut
757c8387be arm: stm32mp: Fix USB boot device report
In case the SoC reports the boot device type is USB, it means the SPL was
loaded via BootROM DFU mode. Currently the spl_boot_device() returns boot
device as USB host, change it to DFU instead, so the SPL can continue the
DFU boot and load U-Boot via DFU.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2022-01-24 10:52:49 +01:00
Tom Rini
d323242b62 Merge https://source.denx.de/u-boot/custodians/u-boot-sh
- rzg2_beacon updates
2022-01-23 09:54:49 -05:00
Adam Ford
16f4d36c7b arm: dts: rz-g2-beacon-u-boot: Enable pinmux for QSPI
When booting from QSPI, the boot ROM appears to mux the QSPI
pins, but it's not guaranteed to be setup when booting from
eMMC.  Fix this by explicitly configuring the pinmux.

Signed-off-by: Adam Ford <aford173@gmail.com>
2022-01-22 23:12:56 +01:00
Tom Rini
da158ec5f2 Pull request for efi-2022-04-rc1-2
Documentation:
 
 * describe printf() format codes
 
 UEFI
 
 * enable more algorithms for UEFI image verification, e.g. SHA256-RSA2048
 
 General
 
 * simplify printing short texts for GUIDs
 * provide a unit test for printing GUIDs
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEEbcT5xx8ppvoGt20zxIHbvCwFGsQFAmHoLnQACgkQxIHbvCwF
 GsQ25Q/9G5REcgmo9Hjv+2ri3VJJueIGRL1QeXDl84TxUYgYAtHj7zo/YaeacHKB
 RVBsQafU6vIuAq5YRJFKCSWCxjPJVUH9QO5QQz6RE14KoBh6OYUQP2wSf/+p6/sb
 47wfVtyAUEpCEz60eDj5EWrSPpH78BNW7MmKoTZWSgE1APaBTAHw/Uo6tnb52Qsv
 vQ73Q9R4s0hpsylVtmwIZ0udDcaJg3SQf/4glhnHxaUW/oMoRd0DU7Dnbbg2oxfd
 Y03J0zarqAdIjzNvADnUz6Ei2+H1TrzRe9tzhuXRuseZdANrUnzDIe6bdz+RCmkl
 sdBCmBDPoChosiAcaX9FkajaAi5XYpZ5Sitdpp9A8ZdVc0Lzr1XLbfLksJRM7WwM
 jSP/JDAGYzJqL86C4hrx46aERUuXgywf/vSM7UoG5OxbtMa/AqbHuXMOnd4jXGYD
 48fLlyMWlZ7+Kd4v3x9QlwSmM0LLsokn93JEWrJhJqFPzdHYUQifU2vlZmrJHWyS
 BjzCJxu+rCmXBO6wlcAvsF9V/kx5IO3CKIGn24UUt/wjSBu4VDO5oSzVseJxPBIQ
 vBV9qZfwKCk9U/F1VN43xvIKvcO+oK+pEE9FB5trffYGmHfSEmBwOq3LuHlyMpeJ
 L+TrJUsZstFtx0ZBmVB3YuERusb2z+x1osnifGJvUHCLqjCgvl0=
 =GoR6
 -----END PGP SIGNATURE-----

Merge tag 'efi-2022-04-rc1-2' of https://source.denx.de/u-boot/custodians/u-boot-efi

Pull request for efi-2022-04-rc1-2

Documentation:

* describe printf() format codes

UEFI

* enable more algorithms for UEFI image verification, e.g. SHA256-RSA2048

General

* simplify printing short texts for GUIDs
* provide a unit test for printing GUIDs
2022-01-22 15:43:36 -05:00
Patrick Delaunay
3425decf52 Convert CONFIG_AT91_EFLASH to Kconfig
This converts the following to Kconfig:
   CONFIG_AT91_EFLASH

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Eugen Hristev <eugen.hristev@microchip.com>
2022-01-21 14:01:35 -05:00
Simon Glass
d3877fba31 Convert CONFIG_BOOTP_SERVERIP to Kconfig
This converts the following to Kconfig:
   CONFIG_BOOTP_SERVERIP

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-21 14:01:35 -05:00
Simon Glass
d6b318de2f Convert CONFIG_TIMESTAMP to Kconfig
This converts the following to Kconfig:
   CONFIG_TIMESTAMP

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-21 14:01:34 -05:00
Tom Rini
2d7a463e82 Merge https://source.denx.de/u-boot/custodians/u-boot-marvell
- fdt_support: Add fdt_for_each_node_by_compatible() helper macro
  (Marek)
- turris_omnia: Fixup SATA or PCIe nodes at runtime in DT blob (Pali)
- pci_mvebu: Add support for Kirkwood PCIe controllers (Pali)
- SPL: More verifications for kwbimage in SPL (Pali)
- mvebu: Remove comphy_update_map() (Pali)
- Minor misc stuff
2022-01-20 12:40:20 -05:00
Tom Rini
280db76f15 Pull request doc-2022-04-rc1
Replace @return by Return: in code comments.
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEEbcT5xx8ppvoGt20zxIHbvCwFGsQFAmHpCv4ACgkQxIHbvCwF
 GsRxNhAAkJXbngwkfdM5O3eZH2zuI0av9GDBLoFoxTWFviwDpCcyzb/XsQgZ8IE5
 Cff9Y6P/SlNPdoE4pvDFqAItvmrvcZ9b/oeAmhVDaMMv1dGEOV9uSQvuQkpJWt/V
 nHtRuCVjSK6qqor3fSTHNMyFcG+gkAG/+8T+KuU8gUDKECQgzJqgixcdKvTjF9jL
 DOIxVKAPRrxlzuJ0u2eovVSZFBB3mik7fnDmOGnbKjj87FvUuOZCX/VWCC5zMGmY
 eOi+C2ONnUleeivWAJrU6AxP28BkCR1q3U1F0LH2LVjolX8WZByYdzlBAOr3RkK0
 0sYxxShdrF+2cYmQP1/wo4z8AySkSBrbr6WTQ58i5vsqFm4sb1FF52cQHQOaFOaV
 Gp/NokHMuzhx7YQr4Ps0TvpROoW6L3Vt2SqA58FoHXzTvWpTi+terdAodL8rH3+1
 yGGNzYW6C79qqMKLclvuLvy/6IWf1UekTo45ocP47vhieRbxyGr8UZ8KMnX6Yx0e
 Y6U34K820fgfTLHM5MOgXMvBXqpskcWnR5hZWdrN9fJyqAZ7AxXQvdDDdIIEMPM9
 MBiFDH8seE62SkTbAEjrSU6RE76WovUISlegmBaB8ihs588au/BQCrsSxmNqT1SV
 SCp8D/GBSjwv+utWlneH6JKAIYxvpsgWeWzr27lA5F3m3j+5gKI=
 =iOT9
 -----END PGP SIGNATURE-----

Merge tag 'doc-2022-04-rc1' of https://source.denx.de/u-boot/custodians/u-boot-efi

Pull request doc-2022-04-rc1

Replace @return by Return: in code comments.
2022-01-20 09:39:45 -05:00
Marek Behún
0d582a461e arm: mvebu: spl: Fix 100 column exceeds
Fix 100 column exceeds in arch/arm/mach-mvebu/spl.c.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-20 11:35:29 +01:00
Marek Behún
37241ce1ba arm: mvebu: spl: Use IS_ENABLED() instead of #ifdef where possible
Use the preferred
  if (IS_ENABLED(X))
instead of
  #ifdef X
where possible.

There are still places where this is not possible or is more complicated
to convert in this file. Leave those be for now.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-20 11:35:29 +01:00
Marek Behún
c894566c5d arm: mvebu: spl: Use preferred types u8/u16/u32 instead of uintN_t
Checkpatch warns about using uint32/16/8_t instead of u32/16/8.

Use the preferred types.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-20 11:35:29 +01:00
Marek Behún
62ee75a30d arm: mvebu: spl: Print srcaddr in error message
Print the wrong srcaddr (spl_image->offset) in error message also for
SATA case.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-20 11:35:29 +01:00
Pali Rohár
402e84ee88 arm: mvebu: Check for kwbimage data checksum
Last 4 bytes of kwbimage boot image is checksum. Verify it via the new
spl_check_board_image() function which is called by U-Boot SPL after
loading kwbimage.

Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-20 11:35:29 +01:00
Pali Rohár
f830703f42 arm: mvebu: Check that kwbimage blockid matches boot mode
Each boot mode has its own kwbimage specified by blockid. So check that
kwbimage is valid by blockid.

Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-20 11:35:29 +01:00
Pali Rohár
2e0429bcc1 SPL: Add struct spl_boot_device parameter into spl_parse_board_header()
Add parameter spl_boot_device to spl_parse_board_header(), which allows
the implementations to see from which device we are booting and do
boot-device-specific checks of the image header.

Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-20 11:35:29 +01:00
Pali Rohár
66f874855c arm: mvebu: Check that kwbimage offset and blocksize are valid
There are certain restrictions for kwbimage offset and blocksize.
Validate them.

Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-20 11:35:29 +01:00
Pali Rohár
4364071362 pci: pci_mvebu: Add support for Kirkwood PCIe controllers
Kirkwood uses macros KW_DEFADR_PCI_MEM and KW_DEFADR_PCI_IO for base
address of PCIe mappings. Size of PCIe windows is not defined in any macro
yet, so export them in new KW_DEFADR_PCI_MEM_SIZE and KW_DEFADR_PCI_IO_SIZE
macros.

Kirkwood arch code already maps mbus windows for io and mem, so avoid
calling mvebu_mbus_add_window_by_id() function which would try to do
duplicate window mapping.

Kirkwood PCIe controllers already use "marvell,kirkwood-pcie" DT compatible
string, so mark pci_mvebu.c driver as compatible for it.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-20 11:35:29 +01:00
Marek Behún
3058e283b8 fdt_support: Add fdt_for_each_node_by_compatible() helper macro
Add macro fdt_for_each_node_by_compatible() to allow iterating over
fdt nodes by compatible string.

Convert various usages of
    off = fdt_node_offset_by_compatible(fdt, start, compat);
    while (off > 0) {
        code();
        off = fdt_node_offset_by_compatible(fdt, off, compat);
    }
and similar, to
    fdt_for_each_node_by_compatible(off, fdt, start, compat)
        code();

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-01-20 11:35:29 +01:00
Heinrich Schuchardt
185f812c41 doc: replace @return by Return:
Sphinx expects Return: and not @return to indicate a return value.

find . -name '*.c' -exec \
sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \;

find . -name '*.h' -exec \
sed -i 's/^\(\s\)\*\(\s*\)@return\(\s\)/\1*\2Return:\3/' {} \;

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-01-19 18:11:34 +01:00
Tom Rini
068415eade Xilinx changes for v2022.04-rc1
gpio:
 - Add modepin driver
 
 net:
 - Save random mac addresses to eth variable
 
 zynqmp gem:
 - Add support for mdio bus DT description
 - Add support for reset and SGMII phy configuration
 - Reduce timeout for MDIO accesses
 
 zynqmp clk:
 - Fix clock handling for gem and usb
 
 phy:
 - Add zynqmp phy/serdes driver
 
 serial:
 - Add one missing compatible string
 
 microblaze:
 - Symbol alignement
 - SPL fixups
 - Code cleanups
 
 zynqmp:
 - Various dt changes, DP pre-reloc, gem resets, gem clocks
 - Switch SOM to shared psu configuration
 - Move dcache handling to firmware driver
 - Workaround gmii2rgmii DT description issue
 - Enable broadcasts again
 - Change firmware enablement logic
 - Small adjustement in firmware driver
 
 versal:
 - Support new mmc@ DT nodes
 - Fix run time variable handling
 - Add missing I2C_PMC ID for power domain
 -----BEGIN PGP SIGNATURE-----
 
 iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCYeg7sQAKCRDKSWXLKUoM
 IVhJAKCAiNx/joEeFBJ0XgThtJzFhCjdMwCfYKY9Ewz4L0n2I56lDgR3UJroct0=
 =HtB+
 -----END PGP SIGNATURE-----

Merge tag 'xilinx-for-v2022.04-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2022.04-rc1

gpio:
- Add modepin driver

net:
- Save random mac addresses to eth variable

zynqmp gem:
- Add support for mdio bus DT description
- Add support for reset and SGMII phy configuration
- Reduce timeout for MDIO accesses

zynqmp clk:
- Fix clock handling for gem and usb

phy:
- Add zynqmp phy/serdes driver

serial:
- Add one missing compatible string

microblaze:
- Symbol alignement
- SPL fixups
- Code cleanups

zynqmp:
- Various dt changes, DP pre-reloc, gem resets, gem clocks
- Switch SOM to shared psu configuration
- Move dcache handling to firmware driver
- Workaround gmii2rgmii DT description issue
- Enable broadcasts again
- Change firmware enablement logic
- Small adjustement in firmware driver

versal:
- Support new mmc@ DT nodes
- Fix run time variable handling
- Add missing I2C_PMC ID for power domain
2022-01-19 11:43:44 -05:00
Heinrich Schuchardt
d3adee1db8 sandbox: imply PARTITION_TYPE_GUID
CONFIG_PARTITION_TYPE_GUID=y is needed for testing some GPT related
functionality.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-01-19 16:16:33 +01:00
Tom Rini
b24b201b60 Merge https://source.denx.de/u-boot/custodians/u-boot-samsung
- Updates for a{3,7}y17lte platforms
2022-01-19 08:09:34 -05:00
Michal Simek
71efd45a5f arm64: zynqmp: Change firmware dependency
In case of mini U-Boot configurations there is no need to enable firmware
driver which just consume space for nothing. That's why add an option to
disable it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/d439399160ff3374f2b39f54f7dd70fa8c8bfea0.1642162121.git.michal.simek@xilinx.com
2022-01-19 11:36:11 +01:00
Shravya Kumbham
d10807a06b arm64: xilinx: dts: Add dma properties to fix dtbs_check warnings
Update dma name and add #dma-cells properties to fix dtbs_check
warnings.

Signed-off-by: Shravya Kumbham <shravya.kumbham@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/fedbf83fd5c682b4d61905d2cb790d33c2f079d6.1642160644.git.michal.simek@xilinx.com
2022-01-19 11:33:50 +01:00
Manish Narani
1d70cc7789 arm64: zynqmp: Update USB node handle from dwc3 to usb
The DWC3 bindings require all USB node handles to be '^usb@[0-9a-f]+$'.
Update the same in ZynqMP device tree.

Signed-off-by: Manish Narani <manish.narani@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/26fc2777eeb92cb5cb1d558d7c19cfb54ac42d0c.1642160613.git.michal.simek@xilinx.com
2022-01-19 11:33:03 +01:00
Michal Simek
59b21d2aea arm64: zynqmp: Change compatible strings for cadence uart
Based on Linux kernel DT binding there should be different compatible
strings used that's why align zynqmp.dtsi with it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/e2404ccd22fd97fe6020be0b3b6eb3c8677f55b0.1642160583.git.michal.simek@xilinx.com
2022-01-19 11:25:54 +01:00
Dylan Hung
abc75897ca ARM: dts: ast2600: Add MDIO devices
There are 4 MDIO bus controllers in AST2600 SOC.  Each of them can
connect to one or more PHY chips and is flexible to work with the 4 MAC
devices in AST2600.  On AST2600 EVB, MDIO 0,1,2,3 connect to the PHY
chips used by MAC 0,1,2,3 respectively.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2022-01-18 12:48:17 -05:00
Amit Singh Tomar
3739cd58a4 ARM: dts: s700: add MMC/SD controller node
This patch adds node for mmc/sd controller found on Action Semi OWL
S700 SoC.

Since, upstream Linux binding has not been merged for S700 MMC/SD
controller, Changes are put in u-boot specific dtsi file.

Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
2022-01-18 12:48:17 -05:00
Amit Singh Tomar
a7e7baea0a ARM: dts: sync Actions Semi S700 DT from Linux v5.16-rc3
This Synchronizes the Actions Semi S700 SoC DT changes from
commit "g58e1100fdc59" ("Linux v5.16-rc3").

Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
2022-01-18 12:48:17 -05:00
Ovidiu Panait
2fd81be11c common: board_r: move init_addr_map() to init.h
asm/mmu.h include is currently guarded by CONFIG_ADDR_MAP ifdef because
the header is only present on arm and powerpc. In order to remove the
dependency on this header and the associated ifdef, move init_addr_map()
declaration to init.h, since it is only called during the common init
sequence.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
2022-01-18 08:31:02 -05:00
Ovidiu Panait
1b212bb9f4 common: board_r: drop initr_addr_map wrapper
Add a return value to init_addr_map and use it directly in the
post-relocation init sequence, rather than using a wrapper stub.

Reviewed-by: Matthias Brugger <mbrugger@suse.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
2022-01-18 08:31:02 -05:00
Ovidiu Panait
485c90c06b common: remove bedbug debugger support
Commit 98f705c9ce ("powerpc: remove 4xx support") removed (in 2017) the
last code that made use of bedbug debugger support. Since there aren't
any boards left that define either CONFIG_CMD_BEDBUG or a real
bedbug_init(), drop this feature from u-boot.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-01-18 08:31:02 -05:00
Ovidiu Panait
027b0e9c16 common: spl: move armv7m-specific code to spl_perform_fixups()
Factor out armv7m fragment to spl_perform_fixups(), which is an arch/board
specific function designed for this purpose.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
2022-01-18 08:31:02 -05:00
Tom Rini
4e81f3be34 Merge branch '2022-01-15-TI-platform-updates'
- Let am335x_evm use the CPSW or PRUSS ethernet.
- Implement timer_get_boot_us in the omap timer driver
- gpmc bitflip, QSPI clock calculation on am437x, da8xx_gpio bugfixes
- Assorted K3 updates
2022-01-17 11:24:43 -05:00
Tom Rini
6d2ebcd7be Second set of u-boot-at91 features for the 2022.04 cycle
-----BEGIN PGP SIGNATURE-----
 
 iQFQBAABCgA6FiEEqxhEmNJ6d7ZdeFLIHrMeAg6sL8gFAmHlNOccHGV1Z2VuLmhy
 aXN0ZXZAbWljcm9jaGlwLmNvbQAKCRAesx4CDqwvyL0JB/4+sKNWPMgOYvP2uLCC
 euRGomhxJ5WmxJVDtJeBIRg0YKSkwnE8JwIN2qqGu15xJnNX9Ck5qnIMPbiZ/io9
 ocW5Z/4C4rfJX/OzD6FtmbMNsvG/umVmZkjRU3ryRXKGyNVpVjLQ2EEECaJfk1WZ
 Nd/J6/Jo8nafb1x4OeY+F6+xwZAuj7Mrun9SsDSyrIvmEqSnaQNioj+lStkauL51
 NwQgBxZBQmbdCgF7Ooy6rYlXZBR6r/rgWB9n3RP8emDCwfCMul9HOMT432oKNbhW
 bGrcMu9AWv/pgzXogxSzYbEdTAnoVEODtU1suCa8LV6KJPEG693gARnRm/KjvPHa
 FfsK
 =39IY
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-at91-2022.04-b' of https://source.denx.de/u-boot/custodians/u-boot-at91

Second set of u-boot-at91 features for the 2022.04 cycle:

This small feature set includes few changes for sama7g5 and sama7g5ek:
turn blue led on at boot, changes required for the Rev4 of the board,
better sync with the Linux DT with regards to the new DT nodes.
2022-01-17 08:36:12 -05:00
Eugen Hristev
e92ebf9f25 ARM: dts: at91: sama7g5ek: move eeproms to flexcom8
The rev4 of the board sama7g5ek has the eeproms on flexcom8 instead of
flexcom1.
Initialize flexcom8 with required pincontrol and move the eeproms accordingly.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2022-01-17 11:18:39 +02:00
Eugen Hristev
4727f954a4 ARM: dts: at91: sama7g5: add flx8 and required nodes
Add Flexcom8 node with required referenced nodes as phandles.
Since Flexcom8 is present in Linux, take the node exactly as-is from Linux.
Some nodes are referenced in Linux as phandles, the dma and the gic.
Add them as well to the file, even if they are unused by Uboot.
This is a step towards having the U-boot DT equivalent with the DT in Linux.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2022-01-17 11:18:39 +02:00
Mark Kettenis
97187d5e37 power: domain: Add Apple pmgr driver
This driver supports power domains for the power management
controller found on Apple SoCs.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-01-17 06:56:01 +09:00
Mark Kettenis
6034c9140f arm: dts: apple: Add u-boot,dm-pre-reloc properties
These are necessary to make sure the power domains needed for the
serial console are availble in the pre-relocation phase.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-01-17 06:56:00 +09:00
Mark Kettenis
c918e2c303 arm: dts: apple: Update Apple M1 device trees
This synchronizes the device trees with those that are in the
process of being upstreamed into Linux. This is mostly the
current state of the device trees on the asahilinux branch
with a few extra bits used by OpenBSD. This includes device
trees for machines that were still missing.

There are still some differences that will hopefully be resolved
soon.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-01-17 06:56:00 +09:00
Vignesh Raghavendra
ef7be5a07b ARM: dts: K3-am642-r5-sk: Enable Second CPSW port in R5/A53 SPL
Enable Second Ethernet port on which ROM support Ethboot.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2022-01-15 21:44:50 -05:00
Vignesh Raghavendra
07252f5c71 mach-k3: am64_spl: Alias Ethernet RGMII boot to CPGMAC
This is required to enables spl_net boot on AM64x

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2022-01-15 10:38:26 -05:00
Vignesh Raghavendra
93c43a8365 mach-k3: am642_init: Probe AM65 CPSW NUSS for R5/A53 SPL
In order to support Ethernet boot on AM64x, probe AM65 CPSW NUSS.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2022-01-15 10:38:26 -05:00
Vignesh Raghavendra
e58d928485 mach-k3: common: Instantiate AM65 CPSW NUSS wrapper
Probe toplevel AM65 CPSW NUSS driver from misc_init_r() when driver
is enabled. Since driver is modeled as UCLASS_MISC, we need to
explicitly probe the driver. Use common misc_init_r() that entire
K3 family of SoCs.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2022-01-15 10:38:26 -05:00
Vignesh Raghavendra
584216315d ARM: mach-k3: sysfw-loader: Copy sysfw.itb to OCRAM in OSPI/SPI bootmode
In case of xSPI bootmode OSPI flash is in DDR mode and needs to be accessed
in multiple of 16bit accesses Hence we cannot parse sysfw.itb FIT image
directly on OSPI flash via MMIO window. So, copy the image to internal
on-chip RAM before parsing the image.

Moreover, board cfg data maybe modified by ROM/TIFS in case of HS platform
and thus cannot reside in OSPI/xSPI and needs to be copied over to
internal OCRAM.

This unblocks OSPI/xSPI boot on HS platforms

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Dave Gerlach <d-gerlach@ti.com>
Tested-by: Keerthy <j-keerthy@ti.com>
Acked-by: Pratyush Yadav <p.yadav@ti.com>
2022-01-15 10:38:26 -05:00
Michael Liebert
67c8678346 arm: mach-k3: am642_init: Unlock MCU PADCFG regs
Currently only the PADCFG registers of the main domain are unlocked.
Also unlock PADCFG registers of MCU domain, so MCU pin muxing can be configured by u-boot or Linux.

Signed-off-by: Michael Liebert <liebert@ibv-augsburg.de>
Tested-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Acked-by: Nishanth Menon <nm@ti.com>
2022-01-15 10:38:26 -05:00
Tom Rini
d71dbe657c Pull request for efi-2022-04-rc1
Documentation:
 
 * Fix building HTML documentation of readthedocs.io
 * Add ARM Juno board documentation
 * Build requirements for Alpine Linux
 * Include DM headers in API documentation
 
 UEFI:
 
 * Fix section alignment of EFI binaries
 * Fix header length of RISC-V EFI binaries allowing to run them on EDK II
 * Remove kaslr-seed from device tree if the EFI_RNG_PROTOCOL is provided
 
 Other:
 
 * Let 'part list' show all 128 GPT partitions
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEEbcT5xx8ppvoGt20zxIHbvCwFGsQFAmHiqKYACgkQxIHbvCwF
 GsTrMA//XQRIS9f8pD3/FsSfVfmtxkCLG9axEe/lRQp7l7109v+m832CJV5Em7pX
 GtRGOSUdj930v1q9fZ/nUx9/IJjf/lnB0eEcMcVai2NVgyuRohGAzX9JWsVLbdOE
 MicDX7D/VZ+86lPxLRJbq61jMj7Dnj+atonJQ3Bc1eBLutUaBOr6aenA99TyLavU
 +guuQmQLpJz6VbyZIYxr7/CZVaVkXS0jmcfEoDHD8BrsBe3pZvNuUC4D9KIFWnLo
 pQYYNuIWiVCPGE/iMbUZGjJfgHnD3qW1DWOfmeWPTysALnTSxx0m8FJrOqlxZk6R
 HkEhcr/RkI2JT89C+07qsXkfvJ7YBg3r6bSNtng4i8VwSm384ffF9Y+cfoBv1285
 7wo+Vbh6LuOlp0OAo3bjAuhW7gpnUkkGoc4sXv7wr560mGOtJAPrp0T1ku17ZANd
 GP0T4TgvL15PAFbK+Yg6NxF+l26Lb5EkvC5bGFlM/5ceafD/B7qA2m8KG9+cR2/t
 UFAyI0FB3yWp1TLfdCRXR4YEHDl3nWjs8GuwdwTPFXLWFPkf73DX/r+ZAnZAY+M+
 FTGJuMZUp71aiqeAs7CHw4ePZMQCt0Hjs9kYbAMekoUncpMCFXwXmp1KxLkHBM+X
 +i6WPflTL/sOSO+3M8fcUeZI7IWerOHZqCu/RTb9W0n3Ee+odBc=
 =NZ+6
 -----END PGP SIGNATURE-----

Merge tag 'efi-2022-04-rc1' of https://source.denx.de/u-boot/custodians/u-boot-efi

Pull request for efi-2022-04-rc1

Documentation:

* Fix building HTML documentation of readthedocs.io
* Add ARM Juno board documentation
* Build requirements for Alpine Linux
* Include DM headers in API documentation

UEFI:

* Fix section alignment of EFI binaries
* Fix header length of RISC-V EFI binaries allowing to run them on EDK II
* Remove kaslr-seed from device tree if the EFI_RNG_PROTOCOL is provided

Other:

* Let 'part list' show all 128 GPT partitions
2022-01-15 07:39:09 -05:00
Simon Glass
081dfcf783 x86: efi: Set the correct link flags for the 64-bit EFI app
At present some 32-bit settings are used with the 64-bit app. Fix this by
separating out the two cases.

Be careful not to break the 64-bit payload, which needs to build a 64-bit
EFI stub with a 32-bit U-Boot.

Signed-off-by: Christian Melki <christian.melki@t2data.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-15 10:57:22 +01:00
Simon Glass
59e8f36dd9 x86: efi: Don't use the 64-bit link script for the EFI app
That script is not intended for use with EFI, so update the logic to avoid
using it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Christian Melki <christian.melki@t2data.com>
2022-01-15 10:57:22 +01:00
Simon Glass
3b4ae096b0 x86: efi: Round out the link script for 64-bit EFI
Make sure the linker lists are in the right place and drop the eh_frame
section, which is not needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-15 10:57:22 +01:00
Simon Glass
450ce56a11 x86: efi: Tweak the code used for the 64-bit EFI app
Add an empty CPU init function to avoid fiddling with low-level CPU
features in the app. Set up the C runtime correctly for 64-bit use
and avoid clearing BSS, since this is done by EFI when U-Boot is loaded.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-15 10:57:22 +01:00
Simon Glass
ce1dc0cc17 x86: efi: Update efi_get_next_mem_desc() to avoid needing a map
At present this function requires a pointer to struct efi_entry_memmap
but the only field used in there is the desc_size. We want to be able
to use it from the app, so update it to use desc_size directly.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-15 10:57:22 +01:00
Heinrich Schuchardt
9ef5ccaa71 efi_loader: fix SectionAlignment, FileAlignment
The alignment of sections in the EFI binaries generated by U-Boot is
incorrect.

According to the PE-COFF specification [1] the minimum value for
FileAlignment is 512. If the value of SectionAlignment is
less then the page size, it must equal FileAlignment.

Let's set both values to 512 for the ARM and RISC-V architectures.

[1] https://docs.microsoft.com/en-us/windows/win32/debug/pe-format

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-01-15 10:57:22 +01:00
Heinrich Schuchardt
dfbc2be47e riscv: revert Complete efi header for RV32/64
EDK II refuses to load the EFI binaries created by U-Boot.
The reason is an incorrect PE-COFF header. The number of
data directories does not match NumberOfRvaAndSizes.
This leads to a failed consistency check in
PeCoffLoaderGetPeHeader():

    SizeOfOptionalHeader - HeaderWithoutDataDir) !=
    NumberOfRvaAndSizes * sizeof(DATA_DIRECTORY))

Fixes: 9afaeec6ef ("riscv: Complete efi header for RV32/64")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2022-01-15 10:57:21 +01:00
Mark Kettenis
3cdfa312c6 armv8: apple: Disable PSCI reset
Apple's ARMv8 cores don't implement EL3 and therefore don't
provide a PSCI implementation.  So don't attempt to use
PSCI to reset on machines using Apple SoCs.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
2022-01-14 13:16:11 -05:00
Pali Rohár
18d85d6e8a arm: mvebu: Enable BootROM output on A38x
BootROMs on pre-A38x SoCs enabled its output on UART by default, but A38x'
BootROM has its output on UART disabled by default.

To enable BootROM output on A38x SoC, it is required to set DEBUG flag
(which only enables BootROM output and nothing more) in kwbimage. For UART
images this DEBUG flag is ignored by BootROM.

Enable kwbimage DEBUG flag for all A38x boards.

With this change BootROM prints the following (success) information on UART
before booting U-Boot kwbimage:

  BootROM - 1.73
  Booting from SPI flash

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-14 11:39:16 +01:00
Pali Rohár
a2b1db41cf arm: mvebu: Correctly set LOAD_ADDRESS for U-Boot SPL binary in kwbimage
U-Boot SPL for mvebu platform is not compiled as position independent.
Therefore it is required to instruct BootROM to load U-Boot SPL at the
correct address. Loading of kwbimage binary code at specific address can be
now achieved by the new LOAD_ADDRESS token as part of BINARY command in
kwbimage config file.

Update mvebu Makefile to put value of $(CONFIG_SPL_TEXT_BASE) into
LOAD_ADDRESS token when generating kwbimage.cfg from kwbimage.cfg.in.

It is required to update regex for sed to find replacement tokens at any
position on a line in kwbimage config file and not only at the beginning of
the line. This is because LOAD_ADDRESS is specified at the end of line
containing the BINARY command.

It looks like all Armada boards set CONFIG_SPL_TEXT_BASE to value
0x40004030 or 0x40000030. Why this value? It is because main kwbimage
header is at address 0x40004030 or 0x40000000 and it is 32 bytes long.
After the main header there is the binary header, which consist of 1 byte
for type, 3 bytes for size, 1 byte for number of arguments, 3 reserved
bytes and then 4 bytes for each argument. After these arguments comes the
executable code.

So arguments start at address 0x40004028 or 0x40000028. Before commit
e6571f38c9 ("arm: mvebu: Remove dummy BIN header arguments for SPL
binary") there were two (dummy) arguments, which resulted in load address
of 0x40004030 or 0x40000030, always. After that commit (which removed dummy
arguments), load address stayed same due to the 128-bit alignment done by
mkimage.

This patch now reflects the dependency between $(CONFIG_SPL_TEXT_BASE),
load address and dummy kwbimage arguments, and allows the user to adjust
$(CONFIG_SPL_TEXT_BASE) config option to some other value.

For unsupported values, when mkimage/kwbimage cannot set chosen load address
as specified by $(CONFIG_SPL_TEXT_BASE), the build process now fails,
instead of silently generating non-working kwbimage.

Removal of this alignment between $(CONFIG_SPL_TEXT_BASE) and LOAD_ADDRESS
can only be done by compiling U-Boot SPL as position independent. But this
currently is not possible for 32-bit ARM version of U-Boot SPL.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-14 11:39:16 +01:00
Pali Rohár
29c6a9c763 arm: mvebu: Set CPU for U-Boot SPL binary in kwbimage
kwbimage needs to know CPU type, so set it in kwbimage config file.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-14 11:39:16 +01:00
Pali Rohár
6329d4402e arm: mvebu: Generate kwbimage.cfg with $(call cmd, ...)
Usage of $(call cmd,...) is standard way to call other commands which
generate things.

It also has the advantage of printing build information in the form
  KWBCFG  arch/arm/mach-mvebu/kwbimage.cfg
if verbosity is disabled, and printing the build command otherwise.

Note that the '#' character needs to be escaped in Makefile when used as
value for make variable assignment.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2022-01-14 11:39:16 +01:00
Pierre Bourdon
c03f4da187 mtd: nand: pxa3xx: use marvell, prefix for custom DT properties
The DT properties for the "enable-arbiter" and "keep-config" config
knobs were previously named inconsistently:

- The u-boot driver used "nand-enable-arbiter" and "nand-keep-config"
  names, without Marvell prefixes.

- The Linux driver uses "marvell,nand-keep-config" ("enable-arbiter"
  does not exist anymore in recent kernels, but it also used to be
  "marvell,nand-enable-arbiter").

- The device trees almost all use "marvell," prefixed names, except for
  one single instance of "nand-enable-arbiter" without vendor prefix.

This commit standardizes on the vendor prefixed version, making the
u-boot driver read from DT props "marvell,nand-enable-arbiter" and
"marvell,nand-keep-config". The one device tree using the unprefixed
version is also changed to use the new naming.

This has the side effect of making the previously no-op "marvell,"
config knobs already present in some DTs actually do something. This was
likely the original intention of the DT authors, but note that this
commit was not tested on every single impacted board.

Signed-off-by: Pierre Bourdon <delroth@gmail.com>
2022-01-14 07:47:57 +01:00
Pali Rohár
94c30f9c8f arm: mvebu: a38x: serdes: Move non-serdes PCIe code to pci_mvebu.c
As explained in commit 3bedbcc3aa ("arm: mvebu: a38x: serdes: Don't
overwrite read-only SAR PCIe registers") it is required to set Maximum Link
Width bits of PCIe Root Port Link Capabilities Register depending of number
of used serdes lanes. As this register is part of PCIe address space and
not serdes address space, move it into pci_mvebu.c driver.

Read number of PCIe lanes from DT property "num-lanes" which is used also
by other PCIe controller drivers in Linux kernel. If this property is
absent then it defaults to 1. This property needs to be set to 4 for every
mvebu board which use PEX_ROOT_COMPLEX_X4 or PEX_BUS_MODE_X4.

Enabling of PCIe port needs to be done afer all registers in PCIe address
space are properly configure. For this purpose use new mvebu-reset driver
(part of system-controller) and remove this code from serdes code.

Because some PCIe ports cannot be enabled individually, it is required to
first setup all PCIe ports and then enable them.

This change contains also all required "num-lanes" and "resets" DTS
properties, to make pci_mvebu.c driver work correctly.

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-01-14 07:47:57 +01:00
Pali Rohár
35e29e89a3 arm: mvebu: Implement simple mvebu-reset driver for enabling/disabling PCIe ports
Enabling and disabling PCIe ports is done via address space of system
controller. All 32-bit Armada SoCs use low 4 bits in SoC Control 1 Register
for enabling and disabling some or more PCIe ports. Correct mapping needs
to be set in particular DTS files.

DT API for mvebu-reset is prepared for implementing resets also for other
HW blocks, but currently only PCIe is implemented via index 0.

Currently this driver is not used as PCIe ports are automatically enabled
by SerDes code executed by U-Boot SPL. But this will change in followup
patches.

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-01-14 07:47:57 +01:00
Pali Rohár
537b0142b0 pci: pci_mvebu: Fix PCIe MEM and IO resources assignment and mbus mapping
Do not call pci_set_region() for resources which were not properly mapped.
This prevents U-Boot to access unmapped memory space.

Update MBUS_PCI_MEM_SIZE and MBUS_PCI_IO_SIZE macros to cover all PCIe MEM
and IO ranges. Previously these macros covered only address ranges for the
first PCIe port. Between MBUS_PCI_IO_BASE and MBUS_PCI_MEM_BASE there is
space for six 128 MB long address ranges. So set MBUS_PCI_MEM_SIZE to value
of 6*128 MB. Similarly set MBUS_PCI_IO_SIZE to 6*64 KB.

Function resource_size() returns zero when start address is 0 and end
address is -1. So set invalid resources to these values to indicate that
resource has no mapping.

Split global PCIe MEM and IO resources (defined by MBUS_PCI_*_* macros)
into PCIe ports in mvebu_pcie_bind() function which allocates per-port
based struct mvebu_pcie, instead of using global state variables
mvebu_pcie_membase and mvebu_pcie_iobase. This makes pci_mvebu.c driver
independent of global static variables (which store the state of
allocation) and allows to bind and unbind the driver more times.

Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
2022-01-14 07:47:57 +01:00
Pali Rohár
8f9e0f4d20 arm: mvebu: Convert board_pex_config() to CONFIG_SPL_BOARD_INIT
The only user of board_pex_config() weak function is A385 controlcenterdc
board. It looks like that code in its board_pex_config() function needs to
be executed after PCIe link is up. Therefore put this code into
spl_board_init() function which is called after a38x serdes initialization,
and therefore it is after the serdes hws_pex_config() function finishes
(which is the state before this change).

With this change completely remove board_pex_config() function as it is not
used anymore.

Signed-off-by: Pali Rohár <pali@kernel.org>
2022-01-14 07:47:57 +01:00
Simon Glass
7f3b79af54 bloblist: Rename the SPL tag
Add a U_BOOT prefix to this tag since it is specific to the U-Boot
project.

Signed-off-by: Simon Glass <sjg@chromium.org>
2022-01-13 09:13:41 -07:00
Heinrich Schuchardt
880dbc5f80 sandbox: compatibility of os_get_filesize()
U-Boot define loff_t as long long. But the header
/usr/include/linux/types.h may not define it.
This has lead to a build error on Alpine Linux.

So let's use long long instead of loff_t for
the size parameter of function os_get_filesize().

Reported-by: Milan P. Stanić <mps@arvanta.net>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Tested-by: Milan P. Stanić <mps@arvanta.net>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-01-13 09:13:41 -07:00
Tom Rini
743c562d0c Merge https://source.denx.de/u-boot/custodians/u-boot-marvell
- Add Apple M1 watchdog timer (Mark)
2022-01-13 08:00:02 -05:00
Vagrant Cascadian
d1cab4f5f0 arch/arm/mach-keystone/ddr3.c: Fix spelling of "resetting". 2022-01-13 07:57:50 -05:00
Vagrant Cascadian
9413e3a175 arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c: Fix spelling of "resetting". 2022-01-13 07:57:49 -05:00
Vagrant Cascadian
11872975fd arch/arm/mach-bcm283x/msg.c: Fix spelling of "Failed". 2022-01-13 07:57:49 -05:00
Mark Kettenis
9a8e3736da arm: apple: Use watchdog timer for system reset
Rely on the new watchdog timer driver and the sysreset uclass to
reset the system.  This gets rid of hard-coded addresses and
should work on systems based on the new M1 Pro and M1 Max SoCs
as well.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-on: Apple M1 Macbook
Tested-by: Simon Glass <sjg@chromium.org>
2022-01-13 06:55:46 +01:00
Mark Kettenis
b0e6c73a79 arm: dts: apple: Add watchdog timer node
Add a node for the watchdog timer based on the proposed Linux
device tree bindings.

Remove the old reboot node which was a watchdog timert node in
disguise using a preliminary device tree binding.

Signed-off-by: Sven Peter <sven@svenpeter.dev>
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-on: Apple M1 Macbook
Tested-by: Simon Glass <sjg@chromium.org>
2022-01-13 06:55:46 +01:00
Henrik Grimler
00809bd4e9 board: samsung: fix menu entries for a{3,7}y17lte
a7y17lte is called SM-A720F, and a3y17lte SM-A320F.  a3y17lte also
should select PINCTRL_EXYNOS78x0, not the (non-existent)
PINCTRL_EXYNOS7880, and it has an Exynos 7870 SoC and not 7880.

Fixes: 3e2095e960 ("board: samsung: add support for Galaxy A series
of 2017 (a5y17lte)")
Signed-off-by: Henrik Grimler <henrik@grimler.se>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
2022-01-13 14:33:00 +09:00
Pali Rohár
c49f1fa892 m68k: mcf5445x: pci: Use PCI_CONF1_ADDRESS() macro
mcf5445x platform uses standard format of Config Address for PCI
Configuration Mechanism #1. So use new U-Boot macro PCI_CONF1_ADDRESS().

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-01-12 14:21:24 -05:00
Pali Rohár
7598759d19 x86: pci: Use PCI_CONF1_ADDRESS() macro
x86 platform uses standard format of Config Address for PCI Configuration
Mechanism #1. So use new U-Boot macro PCI_CONF1_ADDRESS().

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-01-12 14:21:24 -05:00
Tom Rini
fe04d885fb Merge branch 'next'
Signed-off-by: Tom Rini <trini@konsulko.com>
2022-01-10 14:01:57 -05:00
Tom Rini
0dadad6d7c - disable CONFIG_NET_RANDOM_ETHADDR when unnecessary on amlogic based configs
- meson64_android: add board specific env settings, in order to support VIM3/L for android
 - add changes to support VIM3/L android boot by using meson64_android.h config
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEPVPGJshWBf4d9CyLd9zb2sjISdEFAmHYV8MACgkQd9zb2sjI
 SdELkA/+LjyjJB1KI6/KLLg43zyFeeZX/SjQd5BUIx6EfaCgyTkuq2lzQnErGmbi
 HoyMoNLpBxLIL27/5TXPzmKYAeOfKPxA/sXTTtx/l7PG8ncSZIoU0+utqjycdUsK
 tSi7EdFzk7/kDDRkqqA7q9nxsPn/7GQNh/ZC9zstMXKaTO/TEb/sZWCMcvQ0MNoB
 ynZKOCg5t60UkIYIRwZwC/OS/ssn86dovv/Aa/8D6qpL2AbS5DoCXHuAr8Dnz7fJ
 q4rV7oLh7a+WHe/qC7R6ylYFIVVqY5JaIgbLDwuvk1z9o7txchMMQnGgllZ35sN9
 LECD2iSDGjhPaHuGCvQwl3TWtIpvtdcP4sQTyJhsXNPxCG6HHvRz7xY4erUohR1I
 LIddwCCHeCrBiaamXNbCzph2+JhfPSQ5ETCL9M6iBMxNUPunlCxjfjDzlT/pg11p
 EO9PIPjRMR9QhxKtd3gZpyAqPuMBEmIwhDtHI6dL3DNOOsF44ObE4swnzS6qXIDn
 jRZzFCC2f/Vyg11YnzFtV3A5eWwJahGDWAGAnnlg6Y8GCLlLmDJitcgA/rWSALko
 T5fC8L8IFUx2RnHczyitJ/wqJl9FqOAnIaoB3Trpwp8gFQ15dQjbvoXldQnAjSS2
 9bns3zOrx79EF4lbHhwNE9UDLm6OjK5vR3h4bGJvyZBmasVsA90=
 =dLEg
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-amlogic-20220107' of https://source.denx.de/u-boot/custodians/u-boot-amlogic into next

- disable CONFIG_NET_RANDOM_ETHADDR when unnecessary on amlogic based configs
- meson64_android: add board specific env settings, in order to support VIM3/L for android
- add changes to support VIM3/L android boot by using meson64_android.h config
2022-01-09 07:56:31 -05:00
Patrick Wildt
b05cebb5f2 imx8mq: Generate a single bootable flash.bin again
All i.MX8MQ boards have been converted to binman, which makes it
necessary to flash both flash.bin and u-boot.itb to get a bootable
system. Prior to the conversion, only flash.bin was needed.

Such new requirement breaks existing distro mechanisms to generate the
final binary because the extra u-boot.itb is now required.

Generate a final flash.bin that can be used again as a single bootable
binary to keep the original behavior.

After this change the SPL binary is called spl.bin, which is a more
descriptive name for its purpose, and can still be used standalone (for
example, for secure boot purposes).

Also update imx8mq_evk.rst to remove the u-boot.itb copy step.

This is a cherry-pick of 028abfd9b1 ("imx8mm-evk: Generate a single
bootable flash.bin again") adjusted to apply to i.MX8MQ.

Signed-off-by: Patrick Wildt <patrick@blueri.se>
Reviewed-by: Fabio Estevam <festevam@denx.de>
2022-01-08 11:16:03 -05:00
Fabio Estevam
7ad0cee754 udoo: Select CMD_DM
CMD_DM is useful for showing the whole DM tree.

Enable it via "imply CMD_DM".

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
2022-01-08 11:16:03 -05:00
Fabio Estevam
6869bab6a1 ARM: dts: imx6qdl-udoo: Properly describe the SD card detect
GPIO7_IO00 is used as SD card detect.

Properly describe this in the devicetree.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
2022-01-08 11:16:03 -05:00
Adam Ford
c225601c60 imx: imx8mm: imx8mm-kontron-n801x-s: Fix binman error
The binman node is part of the imx8mm-u-boot.dtsi file which
is duplicated in imx8mm-kontron-n801x-s-u-boot.dtsi and causes
a build error.  Remove the duplicate.

Fixes: 3cbb31f0e848 ("arm64: dts: imx8mm: use common binman configuration")
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-01-07 17:38:01 -05:00
Adam Ford
83514ca08b board: phytec: imx8mm-phycore: Remove duplicate binman node
The binman node is part of the imx8mm-u-boot.dtsi file which
is duplicated in phycore-imx8mm-u-boot.dtsi and causes a build
error.  Remove the duplicate.

Fixes: 3cbb31f0e848 ("arm64: dts: imx8mm: use common binman configuration")
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-01-07 17:38:01 -05:00
Tim Harvey
7d926c9544 imx8mm_venice: switch to use binman to pack images
Use binman to pack images.

Note that imx8mm_venice supports several boards via multiple DTB's thus
in the fit node we must use:
- fit,fdt-list = "of-list"
- fdt-SEQ
- config-SEQ

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-01-07 15:49:13 -05:00
Marcel Ziswiler
f17fb6cae4 arm64: dts: imx8mm-u-boot.dtsi: improve odd blob-ext naming
Rather than using odd implicit blob-ext naming, explicitly specify the
type to be of blob-ext and therefore also simplify the node naming.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-01-07 15:42:42 -05:00
Marcel Ziswiler
86b7f2069c arm64: dts: imx8mm-u-boot.dtsi: explicitly add spl filename
Explicitly add SPL aka u-boot-spl.bin filename.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-01-07 15:42:42 -05:00
Marcel Ziswiler
f08c3fee57 arm64: dts: imx8mm-u-boot.dtsi: alphabetically re-order properties
Alphabetically re-order properties.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-01-07 15:42:42 -05:00
Marcel Ziswiler
7cf5597b84 arm64: dts: imx8mm: use common binman configuration
With the move to using binman to generate SPL aka u-boot-spl-ddr.bin and
U-Boot proper aka u-boot.itb every board now covers such configuration
in its own U-Boot specific device tree include. Move the comon part of
that configuration to the common imx8mm-u-boot.dtsi include file.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-01-07 15:42:42 -05:00
Marcel Ziswiler
e9c63ab0e3 arm64: dts: imx8mm-cl-iot-gate-u-boot.dtsi: use common imx8mm-u-boot.dtsi
Use common imx8mm-u-boot.dtsi.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-01-07 15:42:42 -05:00
Marcel Ziswiler
2dc3ac5772 arm64: dts: imx8mm-cl-iot-gate-u-boot.dtsi: alphabetically re-order
Alphabetically re-order nodes and properties.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2022-01-07 15:42:42 -05:00
Peng Fan
ea6ad1a42a imx: imx8mq use common imximage.cfg
After all these board switch to binman, we could use common imximage.cfg

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Patrick Wildt <patrick@blueri.se>
2022-01-07 15:42:41 -05:00
Peng Fan
ddc890bc7e imx: pico-imx8mq: switch to use binman
Switch to use binman to pack images

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Patrick Wildt <patrick@blueri.se>
2022-01-07 15:42:41 -05:00
Peng Fan
f7f70ea216 imx: imx8mq_phanbell: switch to binman
Switch to binman to pack images

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Patrick Wildt <patrick@blueri.se>
2022-01-07 15:42:41 -05:00
Peng Fan
c1ecd03d90 imx: imx8mq_evk: switch to binman
Switch to use binman to pack images

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2022-01-07 15:42:41 -05:00
Adam Ford
2baacc75a5 imx8mn_beacon: Fix booting hang and switch to binman
Somewhere along the line, the board stopped being able to boot.
Rather than just fixing the issue, let's fix the issue and migrate
to binman to eliminate a warning when using custom imx tools for
generating the binary.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-01-07 15:41:58 -05:00
Adam Ford
80efad1342 imx8mm_beacon: Switch to binman for generating image
To eliminate a warning when using custom imx tools for generating
a binary, use binman to generate flash.bin.

Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2022-01-07 12:10:59 -05:00
Peter Robinson
2bbe1ba0c7 udoo_neo: Fixes for booting from the mSD card
This fixes booting from the mSD card from both SPL and when
using it for the OS booting. It also cleans up a few mmc
booting bits that are no longer needed.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2022-01-07 09:30:44 -05:00
Ovidiu Panait
fc7220f0c4 microblaze: branch to base vector address on reset
Current code assumes that the vector base address is always at 0x0.
However, this value is configurable for MicroBlaze using the
CONFIG_XILINX_MICROBLAZE0_VECTOR_BASE_ADDR Kconfig option. Update the
reset routines to branch to this location instead.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Link: https://lore.kernel.org/r/20211130163358.2531677-10-ovidiu.panait@windriver.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-01-05 10:22:03 +01:00
Ovidiu Panait
f149ee4c36 microblaze: start.S: add support for configurable vector base address
Current code assumes that the vector base address is always at 0x0.
However, this value is configurable for MicroBlaze, so update the
__setup_exceptions routine to work with any vector base address.

The r4 register is reserved for the vector base address inside
__setup_exceptions and the function prologe/epilogue are also updated to
save and restore r4.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Link: https://lore.kernel.org/r/20211130163358.2531677-9-ovidiu.panait@windriver.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-01-05 10:22:03 +01:00
Ovidiu Panait
83b175be16 microblaze: migrate CONFIG_SYS_USR_EXCEP to Kconfig
Migrate CONFIG_SYS_USR_EXCEP to Kconfig. Also, rename it to
XILINX_MICROBLAZE0_USR_EXCEP in order to match the naming convention of
microblaze-generic Kconfig options.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Link: https://lore.kernel.org/r/20211130163358.2531677-7-ovidiu.panait@windriver.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-01-05 10:22:03 +01:00
Ovidiu Panait
70c68712ef microblaze: drop CONFIG_SYS_RESET_ADDRESS macro
Microblaze is one the last two users of the CONFIG_SYS_RESET_ADDRESS
macro (the other is arch/powerpc/cpu/mpc8xx/cpu.c, but the macro is not
defined anywhere in powerpc code, so it should be removed there too).

Replace CONFIG_SYS_RESET_ADDRESS usage in start.S with
CONFIG_SYS_TEXT_BASE. If the reset address should really be
user-configurable, a new Kconfig option could be added.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Link: https://lore.kernel.org/r/20211130163358.2531677-6-ovidiu.panait@windriver.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-01-05 10:22:03 +01:00
Ovidiu Panait
48039c333f microblaze: start.S: use stack space as scratch memory for endian offset
To simpify the code, use stack space as scratch memory for endian offset
calculation, rather than saving/restoring the first unused MB vector.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Link: https://lore.kernel.org/r/20211130163358.2531677-5-ovidiu.panait@windriver.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-01-05 10:22:03 +01:00
Ovidiu Panait
7a971dfbeb microblaze: Kconfig: SPL dependencies fixup
Enable SPL_LIBCOMMON_SUPPORT and SPL_LIBGENERIC_SUPPORT if CONFIG_SPL=y, in
order to fix the following link failures:
common/spl/spl.o: in function `board_init_r':
common/spl/spl.c:755: undefined reference to `puts'
...
common/spl/spl.o: in function `board_init_r':
common/spl/spl.c:756: undefined reference to `hang'
common/spl/spl.c:740: undefined reference to `memset'

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Link: https://lore.kernel.org/r/20211130163358.2531677-4-ovidiu.panait@windriver.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-01-05 10:22:03 +01:00
Ovidiu Panait
b3fe1e8ff3 microblaze: spl: add board_boot_order() implementation
Microblaze has three boot modes defined in microblaze/include/asm/spl.h,
but only booting from NOR flash is currently useable. Add a custom
board_boot_order() implementation so that RAM and SPI boot modes can also
be selected if the corresponding load-image support is present.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Link: https://lore.kernel.org/r/20211130163358.2531677-3-ovidiu.panait@windriver.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-01-05 10:22:02 +01:00
Ovidiu Panait
edf0f9b15e microblaze: u-boot.lds: replace __end symbol with _end
board_fdt_blob_setup() uses the _end symbol to find the dtb in the non-spl
case. In order to allow microblaze builds to compile successfully with
CONFIG_OF_SEPARATE, the _end symbol must be defined. Align microblaze with
the other architectures and use _end symbol rather than __end to mark the
end of the u-boot binary.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Link: https://lore.kernel.org/r/20211130163358.2531677-2-ovidiu.panait@windriver.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2022-01-05 10:22:02 +01:00
Michal Simek
ca44216941 arm64: zynqmp: Remove clock-names from GEM in zynqmp-clk-ccf.dtsi
Remove clock-names from GEM nodes from clk-ccf because they should be only
present in zynqmp.dtsi. And as is visible both clock-names defined didn't
really match.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/d6045d81b3e7e97df0ba3eeacb9f3f75ed7cff18.1637239345.git.michal.simek@xilinx.com
2022-01-05 10:22:02 +01:00
Michal Simek
87b50f9aea arm64: zynqmp: Add resets to all GEMs
There is a need to get IP out of reset to operate properly.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/041362197e8de8e9c696da64429107505bdc0c73.1637239345.git.michal.simek@xilinx.com
2022-01-05 10:22:02 +01:00
Michal Simek
19645a11de arm64: zynqmp: Add u-boot,dm-pre-reloc to dpsub node
u-boot,dm-pre-reloc is necessary for DP driver to allocate enough space for
framebuffer before relocation.
Power domain driver is called when video console is used for example by
loading BMP image.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/5e93acee1746913a6e42741e5e797f0b4ab98d44.1637239230.git.michal.simek@xilinx.com
2022-01-05 10:22:02 +01:00
T Karthik Reddy
3b441cf4e4 zynqmp: gpio: Add support for zynqmp gpio modepin driver
ZynqMP modepin driver has capability to get/set/check status of modepin
gpios. These modepins are accessed using xilinx firmware. In modepin
register, [3:0] bits set direction, [7:4] bits read IO, [11:8] bits
set/clear IO.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/2d802d98fd56d95d764532a33e844d935e0cebb3.1635505900.git.michal.simek@xilinx.com
2022-01-05 10:22:02 +01:00
Tom Rini
5fec3c853d Pull request of efi-next
Documentation:
 
 * Add Sunxi board description
 
 UEFI:
 
 * Improvements to U-Boot running on top of UEFI
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEEbcT5xx8ppvoGt20zxIHbvCwFGsQFAmHOp5gACgkQxIHbvCwF
 GsTonA//Y8wwlaXA1TD6B0fIEcQiZucDJQD0nbHugx+1xw/7w9wHX1qfM4Tskqc4
 y4RA3QyoyUp7tvesP6/EA3mAUSEUp0nrtLPyCJjjXV1lrOaXhwvbdqrhOCqUQLen
 h6RNjhujVtbC90wBWYPal3Ip0hdIUROe3qp9Mk2p4zAru8jBEShn+PTRIeHvf6UV
 9BZ8j9LCivC7hUAG3Cyv+KFhW1s47IN54WddedIREEWk4vIdrUMRLjW/kW8ZbDxx
 gi1Eec25Rte6+p5k/+TJkvCwA8GC1kW+MFMYWxcAARZlUd0yr/S6ru5yaW8km0KQ
 kKgcYGp878hVB41JFEhiGUf9CkwU2oo+3NZGIfNv/vG45J4UppyqNffm9c3ZudWC
 S6DqRVPSp1YQEs45SIVZGx+LK6s1iTBn3DJ/dX68NavuUIYX2nnveUBgtW5vdzGf
 ba0yh4a0EU36hcjd2o3y3sEAjiy+PF8SAZ+f2HQ7JaLjsCWF1zNFGsiAxaEStHp8
 aVrUN0cWQPKnnI2A8DCqjmMaSBDKZDK59k6EeC1ZFdMmGivHEO61A0sDiUTz+IRW
 U7XLvjAA5IVKAtij6T/iab6qvhgwABJRL9lZI5DMiFxJRSl4uSYe9YviG7+EzUg0
 XMIs5nK6jBB74HPKqhBouiSUiRa9UHY/rdyNhJACHQ8GODzCf04=
 =YdSB
 -----END PGP SIGNATURE-----

Merge tag 'efi-next' of https://source.denx.de/u-boot/custodians/u-boot-efi into next

Pull request of efi-next

Documentation:

* Add Sunxi board description

UEFI:

* Improvements to U-Boot running on top of UEFI
2021-12-31 07:28:36 -05:00
Simon Glass
40b172314b x86: efi: Show the system-table revision
Show the revision of this table as it can be important.

Also update the 'efi table' entry to show the actual address of the EFI
table rather than our table that points to it. This saves a step and the
intermediate table has nothing else in it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2021-12-31 07:34:34 +01:00
Simon Glass
7f5419a647 x86: efi: Add room for the binman definition in the dtb
At present only 4KB of spare space is left in the DTB when building the
EFI app. Increase this to 32KB so there is plenty of space to insert the
binman definition. This cannot be expanded later (as with OF_SEPARATE)
because the ELF image has already been built.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviwed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2021-12-31 06:45:01 +01:00
Simon Glass
440c6645aa x86: Don't process the kernel command line unless enabled
If the 'bootm' command is not enabled then this code is not available and
this causes a link error. Fix it.

Note that for the EFI app, there is no indication of missing code. It just
hangs!

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2021-12-31 06:45:01 +01:00
Simon Glass
6e7ad4a45f x86: Allow booting a kernel from the EFI app
At present this is disabled, but it should work so long as the kernel does
not need EFI services. Enable it and add a note about remaining work.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-31 06:45:01 +01:00
Tom Rini
87a9aa604d - various fixes to the sandbox display support
- support for showing a logo without splash screen config
 - support for BMP drawing to depths other than 16bpp
 - tests for the different types of supported BMP images
 - support showing a logo when running coreboot via qemu
 -----BEGIN PGP SIGNATURE-----
 
 iGwEABECACwWIQSC4hxrSoIUVfFO0kRM6ATMmsalXAUCYcsdCQ4cYWd1c3RAZGVu
 eC5kZQAKCRBM6ATMmsalXCLhAJ9pLJE3SpQRzpm+Nu4EMbCDzZKr+wCfbxnAZ9LC
 zS1XZ6u9Se4ysDb+PYs=
 =Hf5j
 -----END PGP SIGNATURE-----

Merge tag 'video-next-20211228' of https://source.denx.de/u-boot/custodians/u-boot-video into next

- various fixes to the sandbox display support
- support for showing a logo without splash screen config
- support for BMP drawing to depths other than 16bpp
- tests for the different types of supported BMP images
- support showing a logo when running coreboot via qemu
2021-12-28 11:28:31 -05:00
Tom Rini
440c00de69 Convert CONFIG_SYS_KWD_CONFIG to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_KWD_CONFIG

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 16:20:19 -05:00
Tom Rini
f98b3be287 Convert CONFIG_88F5182 et al to Kconfig
This converts the following to Kconfig:
   CONFIG_88F5182
   CONFIG_BOARD_IS_OPENRD_BASE
   CONFIG_BOARD_IS_OPENRD_CLIENT
   CONFIG_BOARD_IS_OPENRD_ULTIMATE
   CONFIG_D2NET_V2
   CONFIG_FEROCEON
   CONFIG_FEROCEON_88FR131
   CONFIG_INETSPACE_V2
   CONFIG_KW88F6192
   CONFIG_KW88F6281
   CONFIG_KW88F6702
   CONFIG_NET2BIG_V2
   CONFIG_NETSPACE_LITE_V2
   CONFIG_NETSPACE_MAX_V2
   CONFIG_NETSPACE_MINI_V2
   CONFIG_NETSPACE_V2
   CONFIG_SHEEVA_88SV131

At this point mv-plug-common.h is now only an include of mv-common.h so
remove that indirection.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 16:20:19 -05:00
Tom Rini
e7b7c6761a Convert CONFIG_CPU_FREQ_HZ to Kconfig
This converts the following to Kconfig:
   CONFIG_CPU_FREQ_HZ

Cc: Michal Simek <monstr@monstr.eu>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 16:20:19 -05:00
Tom Rini
855e76b5cb Convert CONFIG_CPU_SH7751 to Kconfig
This converts the following to Kconfig:
   CONFIG_CPU_SH7751

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 16:20:19 -05:00
Tom Rini
3aca2b6bd7 Convert CONFIG_CPU_PXA27X to Kconfig
This converts the following to Kconfig:
   CONFIG_CPU_PXA27X

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 16:20:19 -05:00
Tom Rini
3569ac7afa ppc: mpc83xx: Remove unused CONFIG symbols
Neither of these symbols are referenced anywhere else, so remove them.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 16:20:18 -05:00
Tom Rini
86e4c4f7b3 Convert CONFIG_83XX_PCICLK to Kconfig
This converts the following to Kconfig:
   CONFIG_83XX_PCICLK

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 16:20:18 -05:00
Tom Rini
2f8a6db5d8 Finish conversion of CONFIG_SYS_CLK_FREQ to Kconfig
In order to finish moving this symbol to Kconfig for all platforms, we
need to do a few more things.  First, for all platforms that define this
to a function, introduce CONFIG_DYNAMIC_SYS_CLK_FREQ, similar to
CONFIG_DYNAMIC_DDR_CLK_FREQ and populate clock_legacy.h.  This entails
also switching all users from CONFIG_SYS_CLK_FREQ to get_board_sys_clk()
and updating a few preprocessor tests.

With that done, all platforms that define a value here can be converted
to Kconfig, and a fall-back of zero is sufficiently safe to use (and
what is used today in cases where code may or may not have this
available).  Make sure that code which calls this function includes
<clock_legacy.h> to get the prototype.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 16:20:18 -05:00
Tom Rini
e4c3ce7e28 CONFIG_SYS_CLK_FREQ: Consistently be static or get_board_sys_clk()
This CONFIG option is used in one of two ways.  The first way is that it
is defined to a static value, of an unsigned long size.  The second way
is that it is defined to something, typically a function, to determine
this value at run time.

However, in a few cases that function returns a static value.  Change
that to using the static value directly.

In the case of using something at run time, convert everything to using
a function of the same name and prototype.  This will allow for further
cleanups.

Finally, we have a few cases where the function is just not used, so
drop it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 16:20:18 -05:00
Tom Rini
2196a4a7ef arm: s5pc1xx: Move CONFIG_SYS_CLK_FREQ_C1x0 out of CONFIG namespace
The values CONFIG_SYS_CLK_FREQ_C100 and CONFIG_SYS_CLK_FREQ_C110 are
only used in one place and not changed by the board config file.  Move
these out of the CONFIG namespace and in to the CFG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 16:20:18 -05:00
Tom Rini
ba1ed5b022 Convert CONFIG_ARCH_MAP_SYSMEM to Kconfig
This converts the following to Kconfig:
   CONFIG_ARCH_MAP_SYSMEM

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 16:20:18 -05:00
Tom Rini
1b46518736 Convert CONFIG_TPL_TEXT_BASE to Kconfig
This converts the following to Kconfig:
   CONFIG_TPL_TEXT_BASE

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 16:20:18 -05:00
Tom Rini
ada261f19a Finish converting CONFIG_SYS_FSL_CLK to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_FSL_CLK

We move the exiting option to common/Kconfig near the other options to
control the contents of board_init_f() and note that this is a legacy
option.  We further restrict this to where the call is going to be
non-empty, for the SoCs that had only been using this for some
MMC-related clocks.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 16:20:18 -05:00
Tom Rini
7856cd5a6d Convert CONFIG_SYS_PCI_64BIT to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_PCI_64BIT

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 16:20:17 -05:00
Tom Rini
d06e4b7e25 Finish CONFIG_VID et al conversion to Kconfig
This converts the following to Kconfig:
   CONFIG_VID
   CONFIG_VOL_MONITOR_INA220
   CONFIG_VOL_MONITOR_IR36021_READ
   CONFIG_VOL_MONITOR_IR36021_SET
   CONFIG_VOL_MONITOR_LTC3882_READ
   CONFIG_VOL_MONITOR_LTC3882_SET

To finish this migration, we first need to introduce CONFIG_SPL_VID as
some platforms only use this code in full U-Boot while others use it in
SPL as well.  To make the Kconfig logic clearer, guard all of the
sub-options with a if VID || SPL_VID check.  Finally, add Kconfig
options for the remaining related options that did not previously have
one.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 08:41:38 -05:00
Tom Rini
be7dbb60c5 Convert CONFIG_SYS_IMMR to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_IMMR

We do this by consolidating the SYS_IMMR options we have and providing
defaults.

We also, in the few places where M68K was also sharing code with these
platforms, define it within the file to CONFIG_SYS_MBAR to match usage.
This should be cleaned up longer term.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 08:41:38 -05:00
Tom Rini
3847ba94f0 Finish converting CONFIG_WATCHDOG, HW_WATCHDOG and WDT to Kconfig
Because of how these symbols work, and the remaining board config.h file
uses, we need to do these at the same time.  In some cases we just get
to move rather directly to the defconfigs.  A few cases require manual
intervention.

For the case of the eb_cpu5282 we need to select HW_WATCHDOG for the
target, given how it's implemented.

For the cases of m53menlo, dh_imx6, display5, and display5_factory we
disable SPL watchdog support as the particular combination of options
they want would require either more symbols or enabling SPL_DM.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 08:41:38 -05:00
Tom Rini
f76750d111 Convert CONFIG_CONS_INDEX et al to Kconfig
This converts the following to Kconfig:
   CONFIG_CONS_INDEX
   CONFIG_DEBUG_UART_CLOCK
   CONFIG_FSL_TZPC_BP147
   CONFIG_GENERIC_ATMEL_MCI
   CONFIG_IDENT_STRING
   CONFIG_LIBATA
   CONFIG_LNX_KRNL_IMG_TEXT_OFFSET_BASE
   CONFIG_LPC32XX_GPIO
   CONFIG_MP
   CONFIG_MPC8XXX_GPIO
   CONFIG_MTD_PARTITIONS
   CONFIG_MVGBE
   CONFIG_MXC_GPIO
   CONFIG_NR_DRAM_BANKS
   CONFIG_OF_BOARD_SETUP
   CONFIG_OF_STDOUT_VIA_ALIAS
   CONFIG_OF_SYSTEM_SETUP
   CONFIG_PREBOOT
   CONFIG_ROCKCHIP_SERIAL
   CONFIG_RTC_ENABLE_32KHZ_OUTPUT
   CONFIG_RTC_MV
   CONFIG_SCSI_AHCI
   CONFIG_SF_DEFAULT_BUS
   CONFIG_SF_DEFAULT_CS
   CONFIG_SF_DEFAULT_SPEED
   CONFIG_SOFT_SPI
   CONFIG_SPI_FLASH_EON
   CONFIG_SPI_FLASH_MACRONIX
   CONFIG_SPI_FLASH_MTD
   CONFIG_SPI_FLASH_SPANSION
   CONFIG_SPI_FLASH_SST
   CONFIG_SPI_FLASH_STMICRO
   CONFIG_SUPPORT_RAW_INITRD
   CONFIG_SYS_ARCH_TIMER
   CONFIG_SYS_BOARD
   CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
   CONFIG_SYS_DCACHE_OFF
   CONFIG_SYS_FDT_SAVE_ADDRESS
   CONFIG_SYS_FLASH_CFI
   CONFIG_SYS_FSL_ERRATUM_ESDHC135
   CONFIG_SYS_HAS_SERDES
   CONFIG_SYS_L2CACHE_OFF
   CONFIG_SYS_LITTLE_ENDIAN
   CONFIG_SYS_LOAD_ADDR
   CONFIG_SYS_MMCSD_FS_BOOT_PARTITION
   CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
   CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR
   CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
   CONFIG_SYS_NS16550
   CONFIG_SYS_PLLFIN
   CONFIG_SYS_SPI_U_BOOT_OFFS
   CONFIG_TIMER_SYS_TICK_CH
   CONFIG_USB_EHCI_FSL
   CONFIG_U_QE
   CONFIG_VERSION_VARIABLE

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 08:41:38 -05:00
Tom Rini
98ab831da7 Convert CONFIG_FSL_IFC to Kconfig
This converts the following to Kconfig:
   CONFIG_FSL_IFC

This is done via select statements to match previous logic.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-27 08:40:33 -05:00
Simon Glass
8657ad43f3 sandbox: video: Add BMP tests for 32bpp and 8bpp modes
Add a few more tests for BMP rendering. Use a back door into the sandbox
SDL driver to adjust the resolution at runtime.

The truetype code does not support 8bpp. Add this so that the display is
not blank when running in this mode.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-26 23:02:19 +01:00
Simon Glass
250e735c69 video: sandbox: Avoid duplicate display windows
When unit tests are run they currently create a new window. Update the
code so that the old one is removed first. This avoids the confusion as to
which one is active.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-26 23:02:19 +01:00
Simon Glass
0fe5e9481e sandbox: video: Support 8bpp depth
At present sandbox only supports 16 and 32bpp depths, since those are the
easy ones with SDL.

We can support other depths by manually converting the pixel formats. Add
support for this, to enable an 8ppp (monochrome) format.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-26 23:02:19 +01:00
John Keeping
eaee44aaaa rockchip: boot_mode: fix fastboot command
The USB controller index must be separated from the type argument,
otherwise the preboot command fails with the error:

	Error: Wrong USB controller index format

Add the missing space to fix fastboot mode here.

Signed-off-by: John Keeping <john@metanate.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-12-24 15:17:51 +08:00
Jagan Teki
0ade02526b engicam: px30: Add Engicam PX30.Core C.TOUCH 2.0 10.1" OF
PX30.Core is an EDIMM SOM based on Rockchip PX30 from Engicam.

C.TOUCH 2.0 is a general purpose carrier board with capacitive
touch interface support.

10.1" OF is a capacitive touch 10.1" Open Frame panel solutions.

PX30.Core needs to mount on top of C.TOUCH 2.0 carrier with pluged
10.1" OF for creating complete PX30.Core C.TOUCH 2.0 10.1" Open Frame.

Add support for it.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-12-24 14:56:58 +08:00
Jagan Teki
19a4d31c12 arm64: dts: rockchip: Sync px30 from linux-next
Sync the px30 devicetree files from linux-next tree.

commit <14ce8069f48b> ("lib/stackdepot: allow optional init and
stack_table allocation by kvmalloc() - fixup3")

Note, this path even sync rk3326 files as it depends on px30.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-12-24 14:56:58 +08:00
Jagan Teki
43419b936c arm64: dts: rockchip: px30: Move dmc into -u-boot.dtsi
dmc node is specific to U-Boot, it is always better practice
to maintain U-Boot specific nodes into -u-boot.dtsi files
in order to maintain Linux dts file sync compatibility.

Move the dmc into px30-u-boot.dtsi, also add dmc node
explicitly in rk3326-odroid-go2-u-boot.dtsi since it is
using px30.dts.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-12-24 14:56:58 +08:00
Yifeng Zhao
f8b36089af dts: rockchip: rk3399: enable emmc phy for spl
adapting commit ac804143cf ("mmc: rockchip_sdhci: add phy and clock
config for rk3399") to fix the issue "Not found emmc phy device".

Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Reviewed-by: Peter Robinson <pbrobinson@gmail.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com> - on a Rock960
Reviewed-by: Patrick Wildt <patrick@blueri.se>
Tested-by: Patrick Wildt <patrick@blueri.se> - on a Pinebook Pro
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-12-24 14:46:25 +08:00
Nico Cheng
ef7f43084f rockchip: rk3568: add arch_cpu_init()
We configured the drive strength and security of EMMC in
arch_cpu_init().

Signed-off-by: Nico Cheng <nico.cheng@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-12-24 11:10:24 +08:00
Nico Cheng
6b97f2d0ed arm: dts: rockchip: rk3568: Enable sdhci and sdmmc0 node
Enable sdhci and sdmmc0 node in rk3568-u-boot.dtsi

Signed-off-by: Nico Cheng <nico.cheng@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-12-24 11:10:24 +08:00
Nico Cheng
daec31e5cc rockchip: Kconfig: Enable SPL support for rk3568
Enable SPL support in Kconfig and add some related option in
rk3568_common.h

Signed-off-by: Nico Cheng <nico.cheng@rock-chips.com>
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-12-24 11:10:24 +08:00
Chris Morgan
b774be9de5 rockchip: px30: add support for HW RNG for Odroid Go Advance
The Odroid Go Advance has a hardware random number generator present.
The device does not have an upstream Linux driver, but does have a
U-Boot driver. Add the appropriate node so that the hardware RNG can be
used in U-Boot.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-12-24 10:58:59 +08:00
Simon Glass
239d22c795 fdt: Enable OF_HAS_PRIOR_STAGE for most boards with OF_BOARD
Use this new Kconfig instead of OF_BOARD, so we know for sure which boards
obtain their devicetree from a prior stage. Leave sandbox alone since it
does not. Also don't touch xilinx_versal_virt since it does not have a
specific TARGET Kconfig.

This option implies OF_BOARD for now, but with future work standard
passage may be used instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Add rpi_4_32b and rpi_arm64 to the list of boards converted]
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-23 11:19:17 -05:00
Simon Glass
975e0e04bb arm: highbank: Add devicetree files
Add an empty version of this file, so that we can at least build this
board when devicetrees are required.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-23 10:24:39 -05:00
Simon Glass
c4607665da arm: qemu-ppce500: Add a devicetree file
This uses QEMU virt which creates its own devicetree.

Add an empty version of this file, so that we can at least build this
board when devicetrees are required.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-23 10:24:39 -05:00
Simon Glass
142918807d arm: bcm7xxx: Add a devicetree file
Add an empty devicetree file for these boards. It seems to be possible to
obtain a real one from another bootloader called 'bolt' but I will leave
this to the maintainer.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-23 10:24:39 -05:00
Simon Glass
50d857ebc4 arm: xilinx_versal_virt: Add a devicetree file
Add an empty file to prevent build errors when building with
CONFIG_OF_SEPARATE enabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-23 10:24:39 -05:00
Simon Glass
56a47ba21b arm: octeontx: Add an empty devicetree file
Add an empty file to prevent build errors when building with
CONFIG_OF_SEPARATE enabled.

Unfortunately there are no build instructions in the U-Boot tree to enable
a real file to be created.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-23 10:24:39 -05:00
Simon Glass
e5e6cc7cfa arm: xenguest_arm64: Add a empty devicetree file
Add an empty version of this file, so that we can at least build this
board when devicetrees are required.

The real devicetree is created by the Xen project on-the-fly.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-23 10:24:39 -05:00
Simon Glass
aa26948b58 arm: vexpress: Add a devicetree files for juno
Sync these file, obtained from Linux v5.15.

Add a note for the maintainer, and SPDX lines where they are missing.
The added lines are:

   SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause

Note, this matches the text in those files, but is not the same as the
GPL-2.0 of some files.

[1] https://releases.linaro.org/android/reference-lcr/juno/7.1-17.05/

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
2021-12-23 10:24:39 -05:00
Simon Glass
9ae600e9e2 arm: rpi: Sync rpi dts files from Linux
Sync these files, obtained from Linux v5.15.

This adds a devicetree file for rpi_4 which was not there before.

Testing shows no change so far as I can see:
- boots to U-Boot prompt on rpi0, rpi2
- boots to distro on rpi3
- boots to distro on rpi4

I am assuming that syncing with Linux is safe, but the maintainer should
know for sure.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-23 10:24:39 -05:00
Simon Glass
4027792090 riscv: qemu: Split devicetree files for qemu_riscv32/64
This uses QEMU virt which creates its own devicetree.

Copy the existing empty version of this file, so splitting the existing
qemu-virt into two, since anyone actually trying to use this will need a
different devicetree for 32- and 64-bit machines.

Tested-by: Heinrich Schuchardt <heinrich.schuchardt@canaonical.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-23 10:24:39 -05:00
Simon Glass
9f4f5f1f4a arm: qemu: Add a devicetree file for qemu_arm64 virt
This uses QEMU virt which creates its own devicetree.

Add an empty version of this file, so that we can at least build this
board when devicetrees are required.

Tested-by: Heinrich Schuchardt <heinrich.schuchardt@canaonical.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-23 10:24:39 -05:00
Simon Glass
4dc1d8318b arm: qemu: Add a devicetree file for qemu_arm
This uses QEMU virt which creates its own devicetree.

Add an empty version of this file, so that we can at least build this
board when devicetrees are required.

Tested-by: Heinrich Schuchardt <heinrich.schuchardt@canaonical.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-23 10:24:39 -05:00
Tom Rini
4afab30cae Prepare v2022.01-rc4
-----BEGIN PGP SIGNATURE-----
 
 iQGzBAABCgAdFiEEGjx/cOCPqxcHgJu/FHw5/5Y0tywFAmHArDwACgkQFHw5/5Y0
 tyzxyAv/SjZjoEwG8nu7ptVZqTsZfm+tVwwWmQEBAA40MXy/KSccDtbUwB5GCO6f
 Uvk+qFFDbCkbGZh5VKbQusMmUoB02Xu9zUoSxKxcXL4WfC6Bg5GV/UWN9s8G3Tm6
 4wcP0l8WFcQjjr89UfXugiZH58psvFu6PBbWVY4rMH9gZ5ds0AkNOF0L+HbdVmMR
 a5HBfrcySRY2kiTQuKF+RVlMW6BtaOqJp/XIyy8w6bH09ykMomj/u7z3JP3y9ZzL
 w3FXqCLlIEnvdDcqfWvfjoJ/gm0WcLulgSVpTFGS0jgJpnbeAURtZcuVgj6aPRUW
 FRon+u0tj3wpFjibs2cpyXWd+gw/bLLFpDXx78AUAPjxG31tEKbnR1j8R8wBZJ0B
 TqWZ3pCne/LPOT90y2KW2z6ty2n/yEn6qEFFT9MN9R4L0N+U0er//sYJC/nn/e6u
 fjvQ9OPLbnAfHVrad3ZeIkePrLOIF6XYwNQpsjt9aE2kU9IvV5sTa8TxZuQgasBU
 A46FgXtC
 =MEG2
 -----END PGP SIGNATURE-----

Merge tag 'v2022.01-rc4' into next

Prepare v2022.01-rc4
2021-12-20 17:12:04 -05:00
Pali Rohár
2e5d0aa396 arm: mvebu: Use printf for printing fatal errors
There is no point to hide/disable fatal errors via debug() macro.
Print fatal errors loudly.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-12-19 09:50:47 +01:00
Pali Rohár
9c0642d89b arm: mvebu: Remove commented example code
Include file debug_uart.h already contains documentation how to use it.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-12-19 09:50:47 +01:00
Stefan Eichenberger
50b5544c05 arm: mvebu: a38x: serdes: improve USB3 electrical configuration
This is a backport from Marvell U-Boot:
https://github.com/MarvellEmbeddedProcessors/u-boot-marvell
commit 381d029e7a ("fix: serdes: a38x, a39x: Improve USB3 electrical
configuration")

Improves electrical USB3 receiver jitter tolerance test:

- De-Emphasize force, in functional mode the transmitter should always
have 3.5db de-emphasize, so we are forcing it.

- After forcing De-Emphasize, choose 3.5db (After forcing, default is
6dB so need to change it to 3.5dB).

- Align90 set to 0x58 - this is the sample point in the receiver, after
the clock is recovered this sampler samples at the chosen value, usually
it is supposed to be 0x60(which is the center of the eye), but sometimes
after adding jitter and ISI the center of the eye can move slightly and
the sample point is not necessarily the exact center, and after
optimization (searching the middle of the eye manually) it was seen that
the center of the eye is actually 0x58 and not 0x60.

- FFE Res and FFE Cap set to 0xE & 0xF respectively: improves this
settings is adequate according to how the USB3 spec defines the
interconnect, thus improves USB3 jitter tolerance settings.

- Change the resolution of the DFE to 0x3 which is 6mV(highest
resolution) , this avoids the DFE to saturate and cease to work.

- HPF set to 0x3 which is 5Khz high pass filter, the function of the HPF
is to filter the low frequency patterns(below 5Khz) to make sure that
the signal is not a noise, the setting before was 0x1(205Khz), and the
change came since the USB3 CP0 pattern, that is used in the USB3 jitter
tolerance testing, is similar to PRBS15, which has 2^15=32768bits which
is 32768*200ps (200ps is one Unit interval in USB3(5Gbps)) = 6.5us,
which is in frequency terms: 152Khz. since the PRBS15 is a random
pattern and can theoretically have once in a while a pattern that will
be at frequency of 152Khz, hence the previous setting (205khz HPF) can
possibly filter this pattern which can cause to an error in the
receiver, thus this change to avoid such scenarios.

Signed-off-by: Stefan Eichenberger <eichest@gmail.com>
Signed-off-by: René Straub <rene.straub@netmodule.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-12-19 09:50:47 +01:00
Stefan Eichenberger
d61f3ee9bb arm: mvebu: a38x: serdes: fix serdes config for USB3
The electrical serdes configuration for USB3 expects an array as data
argument. For USB3 the second value is used (see data_arr_idx = USB3 =
1). However, because only one value is inside the array mv_seq_exec is
accessing an invalid element and the serdes is configured wrongly.

This wrong initialization is leading to an unreliable detection
mechanism for some USB3 devices. We were able to reproduce the issue
regularly with an LTE modem from Sierra Wireless (SM7455) where it was
not detected as USB3 device in 1/3 of all tests.

This commit fixes the issue by setting data_arr_idx to 0. This is the
same value as the original U-Boot from Marvell is using. There it is
called FIRST_CELL which is a define for 0.
See: https://github.com/MarvellEmbeddedProcessors/u-boot-marvell
commit 56f963ce4c ("fix: serdes: a38x, a39x: Fix USB3 serdes DB
initialization")

Signed-off-by: Stefan Eichenberger <eichest@gmail.com>
Signed-off-by: René Straub <rene.straub@netmodule.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-12-19 09:50:47 +01:00
Pali Rohár
d368e10705 phy: marvell: a3700: Convert to official DT bindings in COMPHY driver
Convert A3720 common PHY driver to official DT bindings.

This puts us closer to be able to synchronize A3720 device-trees with
those from Linux.

Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Cc: Konstantin Porotchkin <kostap@marvell.com>
Cc: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Marcin Wojtas <mw@semihalf.com>
Cc: Grzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-12-19 09:50:47 +01:00
Marek Behún
2105cd0421 fdt_support: Remove FDT_STATUS_FAIL_ERROR_CODE
Since no one uses this feature and I am not aware of any parsers of this
in Linux, remove it.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Pratyush Yadav <p.yadav@ti.com>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Michael Walle <michael@walle.cc>
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-12-19 09:50:47 +01:00
Stefan Roese
4ee7dfba2f arm: mvebu: armada-xp-theadorable.dts: Add I2C DT nodes
Now with DM I2C support enabled we need to describe the I2C busses and
devices in the DT.

Signed-off-by: Stefan Roese <sr@denx.de>
2021-12-19 09:50:47 +01:00
Stefan Roese
4a86ec48ac arm: mvebu: axp/high_speed_env_lib: Switch to DM_I2C API
After all Armada XP boards have been switched over from legacy I2C
support to DM I2C, let's now also convert this serdes code to use
the DM I2C API.

Signed-off-by: Stefan Roese <sr@denx.de>
2021-12-19 09:50:47 +01:00
Ivan Mikhaylov
1c11b5e6f6 iot2050: binman: add missing-msg for blobs
Add the 'missing-msg' for blobs for more detailed output on missing system
firmware and SEBoot blobs.

Signed-off-by: Ivan Mikhaylov <ivan.mikhaylov@siemens.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Fix minor typos:
Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-17 09:44:59 -07:00
Simon Glass
6405ab7ad5 Convert CONFIG_PHYSMEM to Kconfig
This converts the following to Kconfig:
   CONFIG_PHYSMEM

Signed-off-by: Simon Glass <sjg@chromium.org>
Suggested-by: Sean Anderson <seanga2@gmail.com>
2021-12-17 09:44:59 -07:00
Tom Rini
b9c9ce8a40 First set of u-boot-at91 features for the 2022.04 cycle
-----BEGIN PGP SIGNATURE-----
 
 iQFQBAABCgA6FiEEqxhEmNJ6d7ZdeFLIHrMeAg6sL8gFAmG8PNIcHGV1Z2VuLmhy
 aXN0ZXZAbWljcm9jaGlwLmNvbQAKCRAesx4CDqwvyN4NCACbdi5EFjoNkGhCWLIX
 SobXNcBGaL9Zpr5qZq77uFqFeFPeiAClk9X+TcSHhBTSWPugzNCdXEdENEGdiiOR
 Yxe/QvBL7ZsKkhGBw5W8sb81NBPlpnVY7DWufjYvWq7S3C3bIDahQpCeWHKXDO0H
 ZzIX1413kfHRKsAIT+IbufmC1dcWY8SWQEArSkL2KhTQyHnLVGAaholgEGXoKMoC
 0ACXO+uhqaAY0/1eWvvYjcfotlz881ROajSRITh+Gu0UuHyRr2Fvj7jZvF5E4Q4f
 Cu8iciDsimYSDGLZsOJjPIDTfsx9jbA8IcYIAMxOLW8OYbIL6QAUKsJ2LLKao1q5
 SYXP
 =YXsB
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-at91-2022.04-a' of https://source.denx.de/u-boot/custodians/u-boot-at91 into next

First set of u-boot-at91 features for the 2022.04 cycle:

This feature set includes : support for the new QSPI hardware on
sama7g5, small fixes on sam9x60 and sama7g5, some additions of commands
and PIO controller on sam9x60/sam9x60ek.
2021-12-17 07:25:34 -05:00
Tien Fong Chee
4720b83d2c arm: socfpga: arria10: Enable double peripheral RBF configuration
Double peripheral RBF configuration are needed on some devices or boards
to stabilize the IO configuration system.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Sin Hui Kho <sin.hui.kho@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2021-12-17 12:58:01 +08:00
Tien Fong Chee
3b4ee40f20 arm: socfpga: arria10: Reset MPFE NoC after program periph / combined RBF
This patch triggers warm reset to recover the MPFE NoC from corruption
due to high frequency transient clock output from HPS EMIF IOPLL at
VCO startup after peripheral RBF is programmed.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Sin Hui Kho <sin.hui.kho@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2021-12-17 12:58:01 +08:00
Tien Fong Chee
2f27754eb7 arm: socfpga: arria10: Setting image magic value to romcode initswstate reg
The romcode_initswstate register need to be set with FSBL_IMAGE_IS_VALID
value if the current FSBL image is found valid, otherwise BootROM will
look for next subsequent valid FSBL image when warm reset is triggered.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Sin Hui Kho <sin.hui.kho@intel.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@intel.com>
2021-12-17 12:58:01 +08:00
Hari Prasath
9bf459c23d ARM: mach-at91: Add compile time option to choose proper timer
New SoC's of AT91 family with ARM-9 core includes a regular timer and a 64-bit
timer.This patch adds a compile time option to the Makefile such that the old
timer driver is chosen and compiled as default if none of timer configuration
options are explicitly defined in the board configs.

Signed-off-by: Hari Prasath <Hari.PrasathGE@microchip.com>
Reviewed-by: Eugen Hristev <eugen.hristev@microchip.com>
2021-12-16 11:41:45 +02:00
Tom Rini
cfbd2bc695 - enable KSZ90x1 PHY driver on DHCOR
- DHSOM boards:
   - increase USB power-good delay
   - add update_sf script to install U-Boot into SF
   - increase PHY auto-negotiation timeout to 20 seconds
   - fix SoM and board coding strap GPIO handling
 -----BEGIN PGP SIGNATURE-----
 
 iQJQBAABCgA6FiEEXyrViUccKBz9c35Jysd4L3sz/6YFAmG3TqYcHHBhdHJpY2Uu
 Y2hvdGFyZEBmb3NzLnN0LmNvbQAKCRDKx3gvezP/puhJEACl9lNg7+0GDd6eoi73
 NR4+r1JYPDkYKbbBWjHVueIwKYbpk1uSzYLB70lchUVbdvu3fczJc7uOXTDRnrCN
 13BuMa45HAWxvb/9UuHz3AnrLEsSvEgGCRCXK0FrE0mu1yBZK+6iO1ysuQEJA78j
 7tyBs6i+IzuAusejx8NiqjYughIFZKBzfztLe3OSxDhEam+vCCEAIUoTx7FSq1jp
 TumZULkfx0SCSL86vPnzczjtucrtKiaWhjNLDbg0Ilf28qYYTCdlDcpi7ySpr43u
 VJTAKAXYVQq4Ye3qsth6GSsTZ1pONBoSaaOo2z/hoQu+/Y4+yUrzkLB+0dSrqgsW
 FPosN9/OPSRcBIfhFEV9RojhHK9OxYXr0WjBctb6fZKzHK52neVv819Ixy5WBJvq
 gXo6jK78ILxzOUx1PzRj2safKhArAuPrxD2Lv0wNKqNCWJJZbT037L6p5CFG30UI
 7yltaYm1ukAT6q6MeergHAAcdgYV+nyFOUs7udQY5HltzLpBJkdIGHKJpioAhvYJ
 KNHMwANd499/edL/FdXXN7X8sfb7ylaUaqDfkHPJgfDDFmF4lQ591k+jWeD8H1lo
 LYUhd4/7EvNAS02fvwmrdTWYCCFyxL1HFxwOlFqrkthFJnJj70shBJsB786pvihq
 wd9npDIUFJGSTCTA4uXCu3YHlA==
 =Qgdj
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-stm32-20211213' of https://source.denx.de/u-boot/custodians/u-boot-stm

- enable KSZ90x1 PHY driver on DHCOR
- DHSOM boards:
  - increase USB power-good delay
  - add update_sf script to install U-Boot into SF
  - increase PHY auto-negotiation timeout to 20 seconds
  - fix SoM and board coding strap GPIO handling

# gpg verification failed.
2021-12-13 10:20:25 -05:00
Marek Vasut
98fe251a24 ARM: dts: stm32: Add custom PHY reset bindings on AV96
The ethernet PHY must be reset on AV96, however DWMAC currently does
not support the MDIO-bus PHY GPIO reset bindings and the ethernet MAC
PHY reset property is going away on next DT sync. Add PHY specific
reset bindings to trigger the PHY reset and fix sporadic ethernet
malfunctions, until the next DT sync.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-12-13 14:34:11 +01:00
Hari Prasath
85bffb8185 ARM: mach-at91: update alternate function of signal PD20
The alternate function of PD20 is 4 as per the datasheet of
sama7g5 and not 5 as defined earlier.

Fixes: 558378a4cd ("ARM: mach-at91: add support for new SoC sama7g5")
Signed-off-by: Hari Prasath <Hari.PrasathGE@microchip.com>
Reviewed-by: Eugen Hristev <eugen.hristev@microchip.com>
2021-12-13 10:11:36 +02:00
Adam Ford
61b3a0101a arm: dts: Create common rz-g2-beacon-u-boot file
The rzg2_beacon_defconfig creates an image for RZ/G2[MNH] and
as such creates three different device trees and each of them
have a corresponding -u-boot.dtsi file which are basically
copies of each other.  Create a common include file to be
referenced by each of the respective board-u-boot.dtsi files
to reduce duplicate code and simplify support going forward.
This also restores some lost functionality from the device
tree re-sync and updates the MAINTAINER file to include all
beacon-renesom device tree files.

Signed-off-by: Adam Ford <aford173@gmail.com>
2021-12-13 00:37:28 +01:00
Adam Ford
1eaf61c84d arm: dts: beacon-rzg2: Resync device trees with Linux 5.16-rc3
The device trees for the Beacon RZ/G2[MNH] boards have undergone
some changes over time, so resync them now.

Signed-off-by: Adam Ford <aford173@gmail.com>
2021-12-13 00:37:28 +01:00
Simon Glass
42b7f4212a efi: Add uclass for devices provided by UEFI firmware
UCLASS_EFI_LOADER is used for devices created by applications and
drivers loaded by U-Boots UEFI implementation.

This patch provides a new uclass (UCLASS_EFI_MEDIA) to be used for devices
that provided by a UEFI firmware calling U-Boot as an EFI application.

If the two uclasses can be unified, is left to future redesign.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
2021-12-09 11:43:25 -08:00
Andre Przywara
e32dad292a sunxi: dts: Fix typoed eMMC check
Commit 03510bf621 ("sunxi: only include alias for eMMC when mmc2
used") protected the eMMC alias in U-Boot's DT stub the with the
associated Kconfig symbol, but was actually using the wrong name.

Fix the name of the symbol to match what's defined in Kconfig and what
the defconfig files actually use.

Fixes: 03510bf621 ("sunxi: only include alias for eMMC when mmc2 used")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reported-by: 5kft@5kft.org
Reviewed-by: Icenowy Zheng <icenowy@aosc.io>
2021-12-08 23:06:56 +00:00
Tudor Ambarus
e87afb6e9d ARM: dts: at91: sama7g5ek: Add QSPI0 node
QSPI0 has a MX66LM1G45G SPI NOR flash connected.
Enable the controller and describe the flash.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2021-12-07 12:22:52 +02:00
Tudor Ambarus
79eeb91693 ARM: dts: at91: sama7g5: Add QSPI0 and OSPI1 nodes
sama7g5 embedds an OSPI and a QSPI controller:
1/ OSPI0 Supporting Up to 200 MHz DDR. Octal, TwinQuad, Hyperflash
   and OctaFlash Protocols Supported.
2/ QSPI1 Supporting Up to 90 MHz DDR/133 MHz SDR.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
2021-12-07 12:22:34 +02:00
Simon Glass
7ee2016d61 ide: Drop unused CONFIG options
CONFIG_SYS_ATA_PORT_ADDR is not used in the code anymore. Drop it and use
ATA_PORT_ADDR() locally instead.

Drop CONFIG_IDE_RESET_ROUTINE and CONFIG_IDE_SWAP_IO which are also
unused.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-05 09:26:26 -07:00
Simon Glass
93e1edffb0 Convert CONFIG_KEYBOARD to Kconfig
This converts the following to Kconfig:
   CONFIG_KEYBOARD

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-05 09:26:26 -07:00
Simon Glass
5ae2578a55 Convert CONFIG_SYS_FDT_LOAD_ADDR to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_FDT_LOAD_ADDR

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-12-05 09:23:15 -07:00
Heinrich Schuchardt
34bee10e00 sandbox: replace putchar(ch) by fputc(ch, stdout)
When compiled with -Og for better debugability u-boot ends up in a stack
overflow using

    gcc (Ubuntu 11.2.0-7ubuntu2) 11.2.0
    GNU Binutils for Ubuntu 2.37

putchar(ch) is defined as a macro which ends up calling U-Boot's putc()
implementation instead of the glibc one, which calls os_putc() ...

Let's use fputc(ch, stdout) instead as fputc() does not exist in U-Boot.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-12-02 09:15:43 -07:00
Thomas Skibo
c0ffc12a70 riscv: Enable SPI flash env for SiFive Unmatched.
Enable saving environment to SPI flash memory on SiFive
Unmatched.

Signed-off-by: Thomas Skibo <thomas-git@skibo.net>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-12-02 16:43:56 +08:00
Thomas Skibo
6a863894ad riscv: Support booting SiFive Unmatched from SPI.
Configure SPI flash devices into SPL.  Add SPI boot option to spl.c.
Document how to format flash for booting.

Signed-off-by: Thomas Skibo <thomas-git@skibo.net>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-12-02 16:43:56 +08:00
Padmarao Begari
06142d6874 riscv: dts: Split Microchip device tree
The device tree split into .dtsi and .dts files, common
device node for eMMC/SD, enable I2C1, UART1 for console
instead of UART0, enable the DDR 2GB memory and in
that 288MB memory is reserved for fabric buffer.

Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-12-02 16:43:51 +08:00
Tom Rini
33b02e93ec Convert CONFIG_FSL_DDR_BIST et al to Kconfig
This converts the following to Kconfig:
   CONFIG_FSL_DDR_BIST
   CONFIG_FSL_DDR_INTERACTIVE

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-01 10:58:11 -05:00
Tom Rini
c7fad78ec0 Convert CONFIG_SYS_BR0_PRELIM et al to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_BR0_PRELIM
   CONFIG_SYS_OR1_PRELIM
   CONFIG_SYS_BR1_PRELIM
   CONFIG_SYS_OR2_PRELIM
   CONFIG_SYS_BR2_PRELIM
   CONFIG_SYS_OR2_PRELIM
   CONFIG_SYS_BR3_PRELIM
   CONFIG_SYS_OR3_PRELIM
   CONFIG_SYS_BR4_PRELIM
   CONFIG_SYS_OR4_PRELIM
   CONFIG_SYS_BR5_PRELIM
   CONFIG_SYS_OR5_PRELIM
   CONFIG_SYS_BR6_PRELIM
   CONFIG_SYS_OR6_PRELIM
   CONFIG_SYS_BR7_PRELIM
   CONFIG_SYS_OR7_PRELIM

This also introduces CONFIG_SYS_BR0_PRELIM_BOOL as not all platforms
that can set these values do so.  Add the relevant SYS_BRx_PRELIM_BOOL
to platforms that had not been previously migrated.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-12-01 10:58:10 -05:00
Patrick Delaunay
9819fe345c stm32mp1: ram: remove the support of calibration result
The support of a predefined DDR PHY tuning result is removed for
STM32MP1 driver because it is not needed at the supported frequency
when built-in calibration is executed.

The calibration parameters were provided in the device tree by the
optional node "st,phy-cal", activated in ddr helper file by the
compilation flag DDR_PHY_CAL_SKIP and filled with values generated
by the CubeMX DDR utilities.

This patch
- updates the binding file to remove "st,phy-cal" support
- updates the device trees and remove the associated defines
- simplifies the STM32MP1 DDR driver and remove the support of
  the optional parameter "st,phy-cal"

After this patch, the built-in calibration is always executed
and the calibration registers are moved in the phy dynamic part;
that allows manual tests.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-11-30 16:43:28 +01:00
Marek Vasut
77d043cac6 ARM: dts: stm32: Auto-detect DHSOM with uSD level translator
The uSD level translator on DHSOM and Avenger96 are optional, however it
is possible to auto-detect it. This is done by setting SD CMD line high,
and then testing whether signal level on CK line matches the signal level
on CKIN line. If so, the uSD level translator is present, otherwise it is
not populated.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-11-30 16:43:28 +01:00
Marek Vasut
312011e8e7 ARM: dts: stm32: Add custom PHY reset bindings on AV96
The ethernet PHY must be reset on AV96, however DWMAC currently does
not support the MDIO-bus PHY GPIO reset bindings and the ethernet MAC
PHY reset property is going away on next DT sync. Add PHY specific
reset bindings to trigger the PHY reset and fix sporadic ethernet
malfunctions, until the next DT sync.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-11-30 16:43:28 +01:00
Patrice Chotard
0c6079c2a9 ARM: dts: stm32: Use lower-case hex for address for stm32429i-eval-u-boot.dtsi
Replace upper-case hex with lower-case hex for address.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-11-30 11:15:59 +01:00
Patrice Chotard
a2f823e49e ARM: dts: stm32: Use lower-case hex for address for stm32f746g-eval-u-boot.dtsi
Replace upper-case hex with lower-case hex for address.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-11-30 11:15:59 +01:00
Patrice Chotard
fbe6b99d96 ARM: dts: stm32: Use lower-case hex for address for stm32f429-disco-u-boot.dtsi
Replace upper-case hex with lower-case hex for address.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-11-30 11:15:59 +01:00
Patrice Chotard
e114ddc385 ARM: dts: stm32: Use lower-case hex for address for stm32f469-disco-u-boot.dtsi
Replace upper-case hex with lower-case hex for address.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-11-30 11:15:59 +01:00
Patrice Chotard
e447a18095 ARM: dts: stm32: Use lower-case hex for address for stm32f7-u-boot.dtsi
Replace upper-case hex with lower-case hex for address.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-11-30 11:15:59 +01:00
Patrice Chotard
4aace3da3c ARM: dts: stm32: Use lower-case hex for address for stm32746-disco-u-boot.dtsi
Replace upper-case hex with lower-case hex for address.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-11-30 11:15:59 +01:00
Patrice Chotard
f1a3eb59c8 ARM: dts: stm32: Use lower-case hex for address for stm32f769-disco-u-boot.dtsi
Replace upper-case hex with lower-case hex for address.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-11-30 11:15:59 +01:00
Patrice Chotard
b9a0cc8752 ARM: dts: stm32: Use lower-case hex for address for stm32mp15-u-boot.dtsi
Replace upper-case hex with lower-case hex for address.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-11-30 11:15:58 +01:00
Tom Rini
2402c93130 Prepare v2022.01-rc3
-----BEGIN PGP SIGNATURE-----
 
 iQGzBAABCgAdFiEEGjx/cOCPqxcHgJu/FHw5/5Y0tywFAmGk/4sACgkQFHw5/5Y0
 tyyjtgwAo0jCRa1Vyc5z2RrINGdARoPhNcCnBNMYEVTjH9uP0/Mzlpo4i1IWX5qP
 nEuVmP01KjtWDRNy7Cpr45/j2PkTZ0THqXGZKpTG/yALdUKZw0wbzeh/CMllWh0A
 9yJfMbv2/IV79rbb6osxItjusSr5PnrU5fHsR+zUfC8NRZpzWGfpH8a6NpfGvGYo
 3OUKNJrGv930C3MqVnUEHPIuz+vL9fWLSs/rK/JHVZt+ALU45uYtz4cKycMoElVd
 IUJe3mhKhw0k8dO8R+p3UAEFrP+LZdcBLgCt8wRQK6Yl4lcxYOtZgYuJuM9Kp20s
 abqIuky3TWwFjpNM60Gmo63Yf967jOeI/lfITq2juZ5TBlNKOO6Z/NRVUsHkNKFG
 7qJC14/NxuSdN4u9s2h+rJBBGYc+BzWVO/ikigHnsCeFQYfafJpGTnPSJr55OU5X
 eeB6l3blx6jwxOPAz0JhLecZb4e027R+eKionirMEnVPENtnJjF1d+CulkekahUO
 LvdqKaBE
 =h4j5
 -----END PGP SIGNATURE-----

Merge tag 'v2022.01-rc3' into next

Prepare v2022.01-rc3

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-11-29 12:00:57 -05:00
Simon Glass
fb933d070e dm: core: Add tests for stringlist functions
These functions currently lack tests so add some. The error handling
differs betwee livetree and flattree at present, so only check the error
codes with livetree.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-11-28 16:51:51 -07:00
Simon Glass
a0ff280a89 sandbox: Support unmapping a file
Add the opposite of mapping, so that we can unmap and avoid running out of
address space.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-11-28 16:51:51 -07:00
Heinrich Schuchardt
7a001e0f3d sandbox: poweroff in efi_system_reset()
efi_system_reset() should exit if called with EFI_RESET_SHUTDOWN.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-11-26 21:30:59 +01:00
Vladimir Oltean
39dd4f628f arm: dts: ls1021a-tsn: add sja1105 and eth2 bindings
The eth aliases are for correct probing order, so that each Ethernet
port will get a predictable MAC address from the environment.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-11-23 09:57:56 +02:00
Mihai Sain
62cf34d51e ARM: dts: at91: sam9x60: add pioC node
Add node for pioC.

Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
2021-11-22 12:39:55 +02:00
Marek Vasut
b1f3f982fa arm64: Add missing GD_FLG_SKIP_RELOC handling
In case U-Boot enters relocation with GD_FLG_SKIP_RELOC, skip the
relocation. The code still has to set up new_gd pointer and new
stack pointer.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
2021-11-18 18:20:19 -05:00
Kishon Vijay Abraham I
326ee2b0bc arm: dts: am642-sk: Add and Enable USB SuperSpeed Host Port in SPL
Add and Enable USB SuperSpeed Host Port in SPL.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2021-11-17 17:09:47 -05:00
Chia-Wei Wang
e3aab73989 ast2600: spl: Locate load buffer in DRAM space
Return CONFIG_SYS_LOAD_ADDR pointing to DRAM space for
spl_get_load_buffer() to allow generic SPL image loading
code (e.g. FIT and Ymodem) to store data in DRAM.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
2021-11-17 17:05:00 -05:00
Chia-Wei Wang
f05522749c ARM: dts: ast2600: Add ACRY to device tree
Add ACRY DTS node and enable it for AST2600 EVB.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
2021-11-17 17:05:00 -05:00
Chia-Wei Wang
af6451187c clk: ast2600: Add RSACLK control for ACRY
Add RSACLK enable for ACRY, the HW RSA/ECC crypto engine
of ASPEED AST2600 SoCs.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
2021-11-17 17:05:00 -05:00
Joel Stanley
a2f16d0073 ARM: dts: ast2600: Add HACE to device tree
Add HACE DTS node and enable it for AST2600 EVB.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
2021-11-17 17:05:00 -05:00
Joel Stanley
4080714f5e clk: ast2600: Add YCLK control for HACE
Add YCLK enable for HACE, the HW hash engine of
ASPEED AST2600 SoCs.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
2021-11-17 17:05:00 -05:00
Chia-Wei Wang
3d99be97f1 aspeed: ast2600: Enlarge SRAM size
The AST2600 SRAM has been extended to 88KB since A1
chip revision. This patch updates the SRAM size to
offer more space for early stack/heap use.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
2021-11-17 17:04:59 -05:00
Simon Glass
55de0c1931 rk3399: Don't enable the debug UART if there is no driver
Some boards do not enable SPL_SERIAL so cannot use the debug UART. Add
this condition to the code and drop use of the preprocessor while we are
here.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
2021-11-17 17:04:59 -05:00
Simon Glass
0dba45864b arm: Init the debug UART
At present we don't init the debug UART in the generic ARM code, but
instead leave it to individual machines to handle. This is not the
way it is supposed to work.

Add the required init to the crt files. This ensures that the UART
is available as early as possible and that the announcement appears
when it should, if enabled.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-11-17 17:04:59 -05:00
Mark Kettenis
b814e0007e pinctrl: Add Apple pinctrl driver
This driver supports both pin muxing and GPIO support for the
pin control logic found on Apple SoCs.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
2021-11-17 17:04:58 -05:00
Tom Rini
3144ba23bf Merge branch '2021-11-15-assorted-fixes'
- Rename "tqc" to "tq" and related updates
- Assorted minor ARM updates, build updates and documentation updates
2021-11-16 14:23:30 -05:00
Tom Rini
2ffa0e87df Xilinx changes for v2022.01-rc3
sdhci:
 - Fix emmc mini case with missing firmware interface
 
 zynqmp:
 - Restore JTAG interface if required
 - Allow overriding board name
 - Add support for DLC21
 - Fix one fallthrought statement description
 - Use config macro instead of name duplication
 - Save multiboot to variable
 
 firmware:
 - Handle ipi_req errors better
 - Use local buffer in case user doesn't need it instead of NULL/0 location
 
 spi:
 - gqsi: Fix write issue at low frequencies
 
 net:
 - gem: Disable broadcasts
 -----BEGIN PGP SIGNATURE-----
 
 iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCYZPDrwAKCRDKSWXLKUoM
 IS9GAJ93T/uprhLcKWMb+284YMb2caWgOACfZ02nTlzvZKNNXVretJgZaHXqj1M=
 =cwTL
 -----END PGP SIGNATURE-----

Merge tag 'xilinx-for-v2022.01-rc3' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2022.01-rc3

sdhci:
- Fix emmc mini case with missing firmware interface

zynqmp:
- Restore JTAG interface if required
- Allow overriding board name
- Add support for DLC21
- Fix one fallthrought statement description
- Use config macro instead of name duplication
- Save multiboot to variable

firmware:
- Handle ipi_req errors better
- Use local buffer in case user doesn't need it instead of NULL/0 location

spi:
- gqsi: Fix write issue at low frequencies

net:
- gem: Disable broadcasts
2021-11-16 09:51:04 -05:00
Pierre-Clément Tosi
38de2bad64 arm: Fix bad memcpy.S str8w macro argument count
Remove the extra (empty) argument passed to str8w, causing the following
error:

   <instantiation>:40:47: error: too many positional arguments
     str8w r0, r3, r4, r5, r6, r7, r8, r9, ip, , abort=19f
                                                 ^
   u-boot/arch/arm/lib/memcpy.S:240:5: note: while in macro instantiation
   17: forward_copy_shift pull=16 push=16
       ^

Note: no functional change intended.

Fixes: d8834a1323 ("arm: Use optimized memcpy and memset from linux")
Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
2021-11-15 14:33:32 -05:00
Matthias Schiffer
a5e305256b board: tq: fix spelling of "TQ-Systems"
"TQ-Systems" is written with a dash.

Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
2021-11-15 14:33:32 -05:00
Matthias Schiffer
679530c3c6 board: rename "tqc" vendor to "tq"
The subdivision name "TQ Components" hasn't been in use for a long time.
Rename the vendor directory to "tq", which also matches our Device Tree
vendor prefix.

Signed-off-by: Matthias Schiffer <matthias.schiffer@ew.tq-group.com>
2021-11-15 14:33:32 -05:00
Tom Rini
d3fb2e3991 Remove CONFIG_SERIAL_MULTI
This symbol has been functionally dead for a long time.  Remove the last
and recent re-introductions of setting it, and update the whitelist so
it will not be re-introduced again.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-11-12 14:18:17 -05:00
Tom Rini
75c995a1be Convert CONFIG_FSL_LAYERSCAPE to Kconfig
This converts the following to Kconfig:
   CONFIG_FSL_LAYERSCAPE

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-11-12 14:18:17 -05:00
Marcin Niestroj
33fa496aea ARM: dts: am335x-chiliboard: add /chosen/tick-timer
Commit 4b2be78ab6 ("time: Fix get_ticks being non-monotonic") has
broken boot on chiliboard platform, as it requires '/chosen/tick-timer'
in device-tree. This resulted in following panic message:

  Could not initialize timer (err -19)

Provide missing chosen property in device-tree to fix chiliboard
support.

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
2021-11-11 19:02:44 -05:00
Tom Rini
1e72ad6b38 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq
- device-tree sync-up with Linux for ls1028a
- fixes/update in fsl-ddr driver, fsl-validate, lx2162a, fsl-mc,
  spintable code, configs, qspi node, pci
- enable EFI_SET_TIME support in sl28
- powerpc: Drop -mstring
2021-11-11 09:04:20 -05:00
Tom Rini
166a77b34b - DHSOM update:
- Remove nWP GPIO hog
    - Increase SF bus frequency to 50Mhz and enable SFDP
    - Disable video output for DHSOM
    - Disable EFI
    - Enable DFU_MTD support
 - Create include file for STM32 gpio driver private data
 - Split board and SOC STM32MP15 configuration
 - Device tree alignement with v5.15-rc6 for STM32MP15
 - Add binman support for STM32MP15x
 - Normalise newlines for stm32prog
 - Update OTP shadow registers in SPL
 -----BEGIN PGP SIGNATURE-----
 
 iQJQBAABCgA6FiEEXyrViUccKBz9c35Jysd4L3sz/6YFAmGL7ykcHHBhdHJpY2Uu
 Y2hvdGFyZEBmb3NzLnN0LmNvbQAKCRDKx3gvezP/pl1iD/45ARfQCdlq5Iq8VbAf
 NV1TjRguoLU6zR5XhyGAIoDkg87Bsty2ayFyAfz8pHkpEQAFkj9bhiaRZEQj2SSi
 avb2slYGC6iLBEgVBfHjnih4hf0JPTJWcCx+0IO298IknJ49qFfujBFdb3LCbXzt
 zc6QE4mvWWdQHQfNym5UjHqJvI2seHbarEmltAQNn1hqYevFFQYH6vMtgYtZGH18
 c63HeW6uDuGdxGJ9/dzuV/M5bZUAQOI2jJ9OFv7UYQyrzkvLd4M5Qeb52OZ7xNYZ
 xNPCUtNnWUMUnGlpb/ANIUtqBYfcBj1iOMedchLtL9EANObFew/ktk0L1mdjLpQ4
 neB8Im6KmcZkzPyNDs4ha8bSiwOGhrSMg+B49bpp01JvnmzMW3cFtexXL6nKAZyL
 Iohv5MNp7Cf4Fn68v04RBzrAzcvBNPQUnN/19VMN+bqidAzN9y9N7Jc8JgVSOEWN
 OU45X5N840CjqWr8xZ9znICqCdgnY4QtCI9zi6JLHuvWMG3+c10fzyozRfh/OWkE
 3RSyjf9zSjlzYsOEIe8e5Kz/FqLhYqrhdJz2Aqoz5E3k7YQke8WU/OadOU7BWs5U
 QoIMpq8jcAiNZqoMW/V5pxW2nqIB4VIX7LDYuT2TEnVt+hhLP59NtzFTMEjY68Rk
 cH+alF5WHbnqIXgMh5BokUwgxA==
 =lqEG
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-stm32-20211110' of https://source.denx.de/u-boot/custodians/u-boot-stm

- DHSOM update:
   - Remove nWP GPIO hog
   - Increase SF bus frequency to 50Mhz and enable SFDP
   - Disable video output for DHSOM
   - Disable EFI
   - Enable DFU_MTD support
- Create include file for STM32 gpio driver private data
- Split board and SOC STM32MP15 configuration
- Device tree alignement with v5.15-rc6 for STM32MP15
- Add binman support for STM32MP15x
- Normalise newlines for stm32prog
- Update OTP shadow registers in SPL
2021-11-10 14:11:30 -05:00
Patrick Delaunay
c8b2eef52b stm32mp15: tidy up #ifdefs in cpu.c
We should avoid #ifdef in C modules and the unused functions
are eliminated by the linker.

Use the more readable IS_ENABLE() instead.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-11-10 17:07:31 +01:00
Patrick Delaunay
f42045b2e7 stm32mp15: replace CONFIG_TFABOOT when it is possible
In some part of STM32MP15 support the CONFIG_TFABOOT can be replaced
by other config: CONFIG_ARMV7_PSCI and CONFIG_ARM_SMCCC.

This patch also simplifies the code in cpu.c, stm32mp1_ram.c and
clk_stml32mp1.c as execution of U-Boot in sysram (boot without SPL and
without TFA) is not supported: the associated initialization code is
present only in SPL.

This cleanup patch is a preliminary step to support SPL load of OP-TEE
in secure world, with SPL in secure world and U-Boot in no-secure world.

Reported-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-11-10 17:07:31 +01:00
Patrick Delaunay
17aeb589fa stm32mp15: remove configs dependency on CONFIG_TFABOOT
Remove the dependency on CONFIG_TFABOOT in stm32mp Kconfig
- always activate the ARCH config: CONFIG_ARCH_SUPPORT_PSCI
  and CONFIG_CPU_V7_HAS_NONSEC
- CONFIG_ARMV7_NONSEC is deactivated in trusted defconfig
- the correct sysreset driver is activated in each defconfig:
  CONFIG_SYSRESET_PSCI or SYSRESET_SYSCON

Reported-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-11-10 17:07:30 +01:00
Patrick Delaunay
9788708f03 arm: stm32mp: bsec: Update OTP shadow registers in SPL
Currently the upper OTP (after 57) are shadowed in U-Boot proper,
when TFABOOT is not used.

This choice cause an issue when U-Boot is not executed after SPL,
so this BSEC initialization is moved in SPL and no more executed in U-Boot,
so it is still executed only one time.

After this patch this BSEC initialization is done in FSBL: SPL or TF-A.

To force this initialization in all the case, the probe of the BSEC
driver is forced in SPL in the arch st32mp function: spl_board_init().

Even if today BSEC driver is already probed in STM32MP15x clock driver
clk_stm32mp1.c because get_cpu_type() is called in
stm32mp1_get_max_opp_freq() function.

Reported-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-11-10 17:06:51 +01:00
Marek Vasut
eb319d8795 ARM: dts: stm32: Drop nWP GPIO hog on DHSOM
The nWP GPIO hog was used to unlock the SPI NOR write protect when U-Boot
used to operate the SPI NOR in 1-1-1 mode. Now that the SPI NOR is operated
in 1-1-4 mode, the hog has adverse effects and causes transfer corruption,
since the hogged pin is also the IO2 pin. Remove the hogs.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-11-10 17:03:59 +01:00
Patrick Delaunay
56a368f661 gpio: stm32: create include file for driver private data
The stm32 gpio driver private data are not needed in arch include files,
they are not used by code except for stm32 gpio and pincontrol drivers,
using the same IP; the defines for this IP is moved in a new file
"stm32_gpio_priv.h" in driver/gpio.

This patch avoids to have duplicated file gpio.h for each SOC
in MPU directory mach-stm32mp and in each MCU directory arch-stm32*
and allows to remove CONFIG_GPIO_EXTRA_HEADER for all STM32.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-11-10 17:03:36 +01:00
Patrick Delaunay
784c567317 arm: dts: stm32mp15: alignment with v5.15-rc6
Device tree alignment with Linux kernel v5.15-rc6
- Set {bitclock,frame}-master phandles on ST DKx
- Add coprocessor detach mbox on stm32mp15x-dkx boards
- Add coprocessor detach mbox on stm32mp157c-ed1 board

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-11-10 17:03:36 +01:00
Patrick Delaunay
5564b4cd4d stm32mp: add binman support for STM32MP15x
Use binman to add the stm32image header on SPL binary for basic boot
or on U-Boot binary when it is required, i.e. for TF-A boot without FIP
support, when CONFIG_STM32MP15x_STM32IMAGE is activated.

The "binman" tool is the recommended tool for specific image generation.
This patch allows to suppress the config.mk file and it is a preliminary
step to manage FIT generation with binman.

The init_r parsing of U-Boot device tree to search the binman
information is not required for STM32MP15, so the binman library
can be removed in U-Boot (CONFIG_BINMAN_FDT is deactivated).

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-11-10 15:12:16 +01:00
William Grant
3067971aa9 stm32mp: stm32prog: Normalise newlines
The missing trailing newline could confuse check-config.sh if the
definition of an option was on the first line of the next file that
find(1) happened to return.

Signed-off-by: William Grant <wgrant@ubuntu.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-11-10 15:11:15 +01:00
Tom Rini
e8e9c6f484 Merge https://source.denx.de/u-boot/custodians/u-boot-samsung
[trini: Migrate CONFIG_EXYNOS7420 as part of merging, so espresso7420
still builds]

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-11-09 15:05:33 -05:00
Michael Walle
cdf8534b8a armv8: layerscape: use memalign() to allocate spintable code
Don't use efi_allocate_pages(). The allocated memory isn't carved out of
the lmb allocations. The memory might then be allocated twice.
Particulary, this might happened with the fdt_high/initrd_high feature
which will relocate the fdt/ramdisk. This might then overlap with the
spin table.

Instead use memalign() which allocates on memory on the heap which is
correctly carved out by lmb.

Please note, that the memory is later reserved in the device tree as
well as in the EFI memory map in ft_fixup_cpu() (in
arch/arm/cpu/armv8/fsl-layerscape/fdt.c).

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 17:18:23 +05:30
Michael Walle
f53e102e12 armv8: fsl-layerscape: rework the dwc3 snooping enable code
Instead of looking at all USB (host) devices, just search all DWC3
device tree nodes. This will (1) fix a panic if of_match is zero and (2)
also apply the fixup if the controller is in peripheral mode. Both
happen when the DWC3 USB controller driver is used.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 17:18:23 +05:30
Michael Walle
c7155d29fb arm: dts: sl28: sync dtbs
Copy the board device tree files from linux v5.14. On top of the v5.14
dtbs the changes of these two patches are included here which are needed
for u-boot:
  https://lore.kernel.org/linux-devicetree/20210831134013.1625527-7-michael@walle.cc/
  https://lore.kernel.org/linux-devicetree/20210831134013.1625527-8-michael@walle.cc/

At the time of this writing the patches were accepted and will be
included in 5.15.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 17:18:23 +05:30
Michael Walle
7f900eabf7 arm: dts: ls1028a: sync the fsl-ls1028a.dtsi with linux
Now that everything is prepared, copy the fsl-ls1028a.dtsi from the
linux kernel v5.14.12.

Notable changes:
 - second watchdog added
 - the number of chip selects of the SPI controller is now correct and
   reflects what the hardware offers
 - the LPUARTs have the correct clock parent
 - USB controllers are enabled by default, which was already the case
   before this sync because all board enabled all the USB controller
   nodes. A linux patch to fix this is pending.
 - the eSDHC controller changes from big-endian to little-endian, but
   that property seems to be not used at all.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 17:18:23 +05:30
Michael Walle
d08011d7f9 arm: dts: ls1028a: disable the PCIe controller by default
Disable the PCIe controllers by default, just like in the linux device
tree. But there is one catch, for linux they are enabled in-place by the
bootloader. Obviously, this doesn't work for the bootloader. Thus we
explicitly enable the controllers in the -u-boot.dtsi files.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 17:18:23 +05:30
Michael Walle
938d9355e6 arm: dts: ls1028a: move the PCI I/O window to match
To make the synchronization of the u-boot device tree with the one from
linux easier, move the I/O window to the one which is specified in the
linux device tree. The actual value shouldn't matter as long as it
mapped to the corresponding memory window of the PCIe controller which
is a 32GiB window at 80_0000_0000h (first controller) or 88_0000_0000h
(second controller).

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 17:18:23 +05:30
Michael Walle
d4a64821fb arm: dts: ls1028a: remove num-lanes in the PCIe controller nodes
This property is unused in the layerscape PCIe controller driver and not
present in the linux device tree. Remove it to be similarly.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 17:18:23 +05:30
Michael Walle
e10da1f985 pci: layerscape: add official ls1028a binding support
The official bindind of the PCIe controller of the ls1028a has the
following compatible string:
  compatible = "fsl,ls1028a-pcie";

Additionally, the resource names and count are different. Update the
driver to support this binding and change the entry in the ls1028a
device tree.

Cc: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 17:18:23 +05:30
Michael Walle
8f176eb8ac usb: xhci: fsl: add new compatible fsl,ls1028a-dwc3
The official ls1028a binding of the driver uses the following as
compatibles:
  compatible = "fsl,ls1028a-dwc3", "snps,dwc3";

Change the ls1028a device tree and add this new compatible to the fsl
specific xhci driver, otherwise the generic dwc3 driver will be used
with the compatibles above.

Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 17:18:23 +05:30
Michael Walle
cde9b147ba scsi: ceva: rename the resource name to match the linux kernel one
The driver will look for a named resource "ecc-addr", but this isn't the
official binding. In fact, the official device tree binding
documentation doesn't mention any resource names at all. But it is safe
to assume that it's the linux ones we have to use if we want to be
compatible with the linux device tree. Thus rename "ecc-addr" to
"sata-ecc" and convert all the users in u-boot.

While at it, also rename "sata-base" to "ahci" although its not used at
all.

This change doesn't affect the SATA controller on the ZynqMP.

Cc: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 17:18:23 +05:30
Michael Walle
c9bf9af9a7 serial: lpuart: add new compatible fsl, ls1028a-lpuart
The official ls1028a binding of the driver uses the following as
compatibles:
  compatible = "fsl,ls1028a-lpuart";

Add the missing compatible to the driver and update the device tree.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 17:18:23 +05:30
Michael Walle
8c58089287 spi: fsl_dspi: rename num-cs to spi-num-chipselects
The official devicetree bindings specifies spi-num-chipselects as the
name. Use it.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 17:18:23 +05:30
Michael Walle
765afe7fb3 spi: fsl_dspi: add new compatible fsl, ls1021a-v1.0-dspi
The official ls1028a binding of the driver uses the following as
compatibles:
  compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";

Add the missing compatible to the driver and update the device tree.
We can use the fallback "fsl,ls1021a-v1.0-dspi", because the endianness
is determined by the little-endian property and not by the compatible
string itself. Further, we won't need and specific details on the DMA
configuration (which is different on the LS1021A). If it's ever needed,
we can later add the more specific "fsl,ls1028a-dspi" compatible to the
driver.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 17:18:23 +05:30
Michael Walle
5709a858c0 watchdog: sp805_wdt: use correct compatible string
According to the linux device tree specification the compatible string
is:
  compatible = "arm,sp805", "arm,primecell";

Fix all users in u-boot.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 17:18:23 +05:30
Michael Walle
c816dd0324 arm: dts: ls1028a: update the labels
Update the labels of the nodes to match the kernel ones.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 17:18:23 +05:30
Michael Walle
f3f41f6c5c arm: dts: ls1028a: move the iRC node and its devices into /soc
While inserting them into the new location, keep them sorted by the
register base offset just like in the linux kernel device tree.

While at it fix the indentation.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 17:18:23 +05:30
Michael Walle
575205c9cc arm: dts: ls1028a: move the watchdog node into /soc
While inserting it into the new location, keep it sorted by the
register base offset just like in the linux kernel device tree.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 17:18:23 +05:30
Michael Walle
3c5c47777c arm: dts: ls1028a: move the PCIe controller nodes into /soc
While inserting them into the new location, keep them sorted by the
register base offset just like in the linux kernel device tree.

While at it fix the indentation.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 17:18:23 +05:30
Michael Walle
659fafc3fd arm: dts: ls1028a: move SATA and USB controller nodes into /soc
While inserting them into the new location, keep them sorted by the
register base offset just like in the linux kernel device tree.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 17:18:23 +05:30
Michael Walle
65da65f6e2 arm: dts: ls1028a: move the GPIO controller nodes into /soc
While inserting them into the new location, keep them sorted by the
register base offset just like in the linux kernel device tree.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 17:18:23 +05:30
Michael Walle
ebcd6d77ca arm: dts: ls1028a: move the low-power UART nodes into /soc
While inserting them into the new location, keep them sorted by the
register base offset just like in the linux kernel device tree.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 17:18:23 +05:30
Michael Walle
44800f2b4f arm: dts: ls1028a: move the UART controller nodes into /soc
While inserting them into the new location, keep them sorted by the
register base offset just like in the linux kernel device tree.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 17:18:23 +05:30
Michael Walle
fbddc2701d arm: dts: ls1028a: move the SPI and eSDHC controller nodes into /soc
While inserting them into the new location, keep them sorted by the
register base offset just like in the linux kernel device tree.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 17:18:23 +05:30
Michael Walle
f02f2f93a5 arm: dts: ls1028a: move the FlexSPI controller node
While inserting it into the new location, keep it sorted by the
register base offset just like in the linux kernel device tree.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 17:18:23 +05:30
Michael Walle
fb19c6b159 arm: dts: ls1028a: move I2C controller nodes into /soc
While inserting them into the new location, keep them sorted by the
register base offset just like in the linux kernel device tree.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 17:18:23 +05:30
Michael Walle
9b38ba5846 arm: dts: ls1028a: move the clockgen node into /soc
Populate the /soc node with the first device node.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 17:18:23 +05:30
Michael Walle
cd80d5d924 arm: dts: ls1028a: add an empty /soc
To keep the device tree similar to the linux kernel one, we need to move
all CCSR related devices into the /soc node. To keep the patches easy to
review, we initially add an empty /soc node and populate it piece by
piece.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 17:18:23 +05:30
Michael Walle
541deeea59 arm: dts: ls1028a-{rdb, qds}: remove dm-pre-reloc property
Nowadays, both boards boot using the TF-A BL1/BL2 and SPL isn't used at
all. The property is not needed, remove it.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 17:18:23 +05:30
Michael Walle
d89fa39227 arm: dts: ls1028a: remove /memory node
This node is some hodgepodge between the ddr controller node at SoC
offset 0x1080000 and some static memory size of 2GiB. Remove this bogus
node because it doesn't seem to be used at all.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 17:18:23 +05:30
Michael Walle
fb5ff321d0 armv8: ls1028a: use the official compatible string for the GPU
There is no "fsl,ls1028a-gpu" compatible string. It is solely for the
proprietary driver which will never be open source. Lately, linux gained
support for the open source etnaviv driver for the GPU (although there
is still support for the DisplayPort PHY missing to get actual graphics
output). Thus, instead of supporting some proprietary driver, switch
over to the open source one, which also have an official device tree
binding.

Cc: Andy Tang <andy.tang@nxp.com>
Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 17:18:23 +05:30
Tom Rini
a48492679c ppc: mpc8xx: Drop -mstring from PLATFORM_CPPFLAGS
This has not been supported by toolchains for some time and has been
putting out a warning.  Drop this.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 14:50:22 +05:30
Kuldeep Singh
f5402117ad arm: dts: ls1088a: Update qspi node properties
Remove "num-cs" property from device-tree as it is no longer used by
qspi driver anymore.

Also, specify status as "disabled" and enable qspi support in respective
board dts files. This will also help in aligning node properties with
other board properties.

Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 14:50:22 +05:30
Michael Walle
d8ffd938f1 board: sl28: generate FIT update image
Generate a FIT update image during build. The image will be called
"u-boot.update" and can be used to build an EFI UpdateCapsule or during
DFU mode. Although, the latter isn't supported because there is no USB
OTG driver yet.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 14:43:24 +05:30
Alban Bedel
2a98944b43 armv8: fsl-layerscape: Erratum A010315 needs PCIE support
Disabling PCIE support currently lead to a crash because the code for
erratum A010315 is still run. Add a conditional to only select
CONFIG_SYS_FSL_ERRATUM_A010315 when CONFIG_PCIE_LAYERSCAPE is enabled.

Signed-off-by: Alban Bedel <alban.bedel@aerq.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2021-11-09 14:43:24 +05:30
Minkyu Kang
a80f582688 exynos: mmu: use CONFIG_IS_ENABLED
to fix following checkpatch warnings.
Use 'if (IS_ENABLED(CONFIG...))' instead of '#if or #ifdef' where
possible

Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Cc: Dzmitry Sankouski <dsankouski@gmail.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
2021-11-09 14:07:46 +09:00
Tom Rini
b842340a10 Merge https://source.denx.de/u-boot/custodians/u-boot-riscv 2021-11-08 21:44:02 -05:00
Wei Fu
41635cca6e riscv: add #define in asm/io.h for some device drivers
This patch adds memcpy_fromio and memcpy_toio definitions for some device
drivers which have these definitions, like cadence_qspi_apb.c

Signed-off-by: Wei Fu <wefu@redhat.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-11-08 15:35:55 +08:00
Heinrich Schuchardt
afb8e1f067 riscv: function to retrieve SBI implementation version
Provide function sbi_get_impl_version() to retrieve the SBI implementation
version.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2021-11-08 15:35:55 +08:00
Simon Glass
1834c081d3 efi: Add video support to the app
The current EFI video driver only works when running in the stub. In that
case the stub calls boot services (before jumping to U-Boot proper) and
copies the graphics info over to the efi table. This is necessary because
the stub exits boot services before jumping to U-Boot.

The app maintains access to boot services throughout its life, so does not
need to do this. Update the driver to support calling boot services
directly.

Enable video output for the app. Note that this uses the
EFI_GRAPHICS_OUTPUT_PROTOCOL protocol, even though it mentions vesa.

A sample qemu command-line for this case is:

   qemu-system-x86_64 -bios /usr/share/edk2.git/ovmf-ia32/OVMF-pure-efi.fd
   -drive id=disk,file=try.img,if=none,format=raw -nic none
   -device ahci,id=ahci -device ide-hd,drive=disk,bus=ahci.0

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-11-07 18:36:55 +01:00
Simon Glass
9c297a3dab x86: Don't duplicate global_ptr in 64-bit EFI app
This variable is already defined by the EFI code. Drop the duplicate
definition when building a 64-bit EFI app.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-11-07 18:36:55 +01:00
Simon Glass
e16c47fa3d efi: Create a 64-bit app
Most modern platforms use 64-bit EFI so it is useful to have a U-Boot app
that runs under that. Add a (non-functional) build for this.

Note that --whole-archive causes the gcc 9.2 linker to crash, so disable
this for now. Once this is resolved, things should work.

For now, avoid mentioning the documentation for the 64-bit app, since it
does not work.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-11-07 18:36:55 +01:00
Simon Glass
f4d227c99f x86: Create a 32/64-bit selection for the app
Most EFI implementations use 64-bit but U-Boot only supports running as
a 32-bit app at present. While efi-x86_payload64 does boot from 64-bit
UEFI it immediately changes back to 32-bit before starting U-Boot.

In order to support a 64-bit U-Boot app, update the Kconfig to add an
option for 32/64 bit. Update the prompt for the existing option so it is
clear it relates to the stub. Move both up to just under the choice that
controls them, since this looks better and the menu.

Use CONFIG_EFI_APP in the Makefile instead of CONFIG_TARGET_EFI_APP,
since the latter is specific to a single target and we will have two.

Memory size is set to 32MB for now so that it can run on qemu without
increasing the default memory size. We may need to increase the default
later.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-11-07 18:36:55 +01:00
Tom Rini
1a77da4b33 Convert CONFIG_SYS_HZ to Kconfig
This converts the following to Kconfig:
	CONFIG_SYS_HZ

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-11-05 11:23:29 -04:00
Tom Rini
7115007ccf spl: Make use of CONFIG_IS_ENABLED(OS_BOOT) in SPL/TPL common code paths
When building a system that has both TPL and SPL_OS_BOOT, code which
tests for CONFIG_SPL_OS_BOOT will be built and enabled in TPL, which is
not correct.  While there is no CONFIG_TPL_OS_BOOT symbol at this time
(and likely will not ever be) we can use CONFIG_IS_ENABLED(OS_BOOT) in
these common paths to ensure we only compile these parts in the SPL
case.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-11-05 11:23:29 -04:00
Samuel Holland
40edc320b1 sunxi: Use sysreset framework for poweroff/reset
Instead of hardcoding the watchdog for reset, and the PMIC for poweroff,
use the sysreset framework to manage the available poweroff/reset
backends. This allows (as examples) using the PMIC to do a cold reset,
and using a GPIO to power off H3/H5 boards lacking a PMIC. Furthermore,
it removes the need to hardcode watchdog MMIO addresses, since the
sysreset backends can be discovered using the device tree.

Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-11-04 08:57:19 +01:00
Samuel Holland
6e19dc84c1 sunxi: Avoid duplicate reset_cpu with SYSRESET enabled
The sysreset uclass unconditionally provides a definition of the
reset_cpu() function. So does the sunxi board code. Fix the build with
SYSRESET enabled by omitting the function from the board code in that
case. The code still needs to be kept around for use in SPL.

Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-11-04 08:57:19 +01:00
Tom Rini
b8bfe05282 - add sm efuse write support and cmd for read/write efuse
- add JetHub D1 eth mac generation with manufacturer OUI
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEPVPGJshWBf4d9CyLd9zb2sjISdEFAmGA+fwACgkQd9zb2sjI
 SdGGmg/+JNrKt/9yJ5giKwklLMEzSccKG23lQA2bZiYCP3I8j3t6spkHvHRRfgbX
 ZJIZjz9zhJ4bvaoiVa64fWoSxx8LpFDnTA1yQugDMxci9djXs2lnq1OdB3t9H4y3
 duy4+9U8H0lgpQosZwtLeI2FJvEnkrPlWyUAV9oMoFnyCllfjj0DfGqu9wm7mBlS
 q4VMBBVi3z8fhEs/lBoQ0psRHhfqY3ztI7PUCk1j15QSzaEt2RgNFYuVWW9QLi5f
 C0PB7/3mh004N6WkjrThT310dKoRNrTA30n4svnZDAtRkeligHe4krJBgJGWy0hk
 i6b4Cg1DPWVi5gfsyWsdO4nqJ2SEvmeGJ6EWPkzk3WxvHzVLj0+xBLIEhG+QgLgF
 GyoUhsy+crxmEmmE2NXpCnu0hZ+ouldGJXLqC+s/cy1dsXMtBgBfqbz8sfCSP2Qu
 w+FqpnwzAFBALB6DoA51Y/yxBwNTs9TtMRnR1kH99Gu7ekcNSZDCuLrrASp1+NiT
 axOQFJtopEuPTqBzR7Z/7NV5KjVMhUC9znQEHBmbmIKzr/27go0QF/267E4yEXlS
 fi1b0uPGSN+lfSwL2jau/CxRCFJmfTtI6flrkN7dBYWGYc98b1ISxa8U9OnJj/EA
 eYywK2BfzL5F2jKVCemJ441riImCZcrnIToWevnWUCLJV07LIcE=
 =UyL3
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-amlogic-20211102' of https://source.denx.de/u-boot/custodians/u-boot-amlogic

- add sm efuse write support and cmd for read/write efuse
- add JetHub D1 eth mac generation with manufacturer OUI
2021-11-02 08:56:42 -04:00
Andy Shevchenko
5270bee9b2 x86: tangier: pinmux: Move error message to the caller
Move error message to the caller of mrfld_pinconfig*() in order
to unify them in the future.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-11-01 10:19:05 +08:00
Andy Shevchenko
74bf2048e6 x86: tangier: pinmux: Move is_protected assignment closer to its user
Move is_protected assignment closer to its user.
This increases readability and makes maintenance easier.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-11-01 10:10:11 +08:00
Andy Shevchenko
144cb06083 x86: edison: Don't take SD card detect pin into consideration
There are two PCB designs in the wild which use the opposite
signaling for SD card detection. This makes U-Boot working
in one case and failing in the other. Quirk this out by
disconnecting SD card detection pin from the PCB by switching
it to mode 3. In the disconnected state the read value is always
the same and inverted to what we are expecting in the code.

BugLink: https://github.com/edison-fw/meta-intel-edison/issues/136
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-11-01 09:50:55 +08:00
Andy Shevchenko
90cc2c5c64 x86: tangier: Enable support for SD/SDIO family in the pinmux driver
We would need to quirk out the Card Detect case and for that we allow
configuring the SD/SDIO family of pins.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-11-01 09:50:55 +08:00
Alistair Delva
9bcd51b838 x86: Fix i8254 ifdef include guard
When building U-Boot with clang, it notices that the i8254.h include
guard does not work correctly due to a typo. Fix it.

Signed-off-by: Alistair Delva <adelva@google.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fixed the other same typo at the end of the same file]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2021-11-01 09:50:55 +08:00
Alistair Delva
daf26a6bc2 x86: chromebook_coral: fix C block comment
Fix a warning seen when compiling this dts file.

Signed-off-by: Alistair Delva <adelva@google.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-11-01 09:50:55 +08:00
Andy Shevchenko
d3023b8139 x86: tangier: Replace Method() by Name() for _STA object
There is no point to use Method() for the constant.
Replace it with Name() defined object. For the _STA
case it saves 3 bytes per each entry.

Before: 2881
After: 2833

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-11-01 09:50:55 +08:00
Tom Rini
360e392274 Environment tidy-ups
patman 'postfix' support
 fix binman test race condition causing a timeout error
 -----BEGIN PGP SIGNATURE-----
 
 iQFFBAABCgAvFiEEslwAIq+Gp8wWVbYnfxc6PpAIreYFAmF+8FcRHHNqZ0BjaHJv
 bWl1bS5vcmcACgkQfxc6PpAIreYP+AgApwZWYteNQu/OKwCFrZq0QIQYZwJQqe93
 9CdQtpKH2boakfNcvsbPP5dXk8GNz5cEky1Whk2kIH1b11FHgklnIPFtFxzMesm8
 oYET1w0iItp+4P4ZsQmVgJpynz4yUmUnMEOBNqwI2zeo7dMgx8Zw+cWz8FDo4e6K
 pDKHAx9UmiCRu6h+IbsAzeMcq/HqAvFOzoWbp/LkmaWnwIjASCM4UUVoz1+UtoFU
 0ENn/7vn70WOLw0JoEib8M7qy+IT7Mz42eZwDVGzYKSDlTZmXNwKLLzgJpEqW4hw
 lYIEBUK3sr0q+kcKI776JeFaFhI6k71uVJcjkkUgGuF1hda1kc0Msw==
 =E8s4
 -----END PGP SIGNATURE-----

Merge tag 'dm-pull-boo21' of https://source.denx.de/u-boot/custodians/u-boot-dm

Environment tidy-ups
patman 'postfix' support
fix binman test race condition causing a timeout error

# gpg: Signature made Sun 31 Oct 2021 03:36:55 PM EDT
# gpg:                using RSA key B25C0022AF86A7CC1655B6277F173A3E9008ADE6
# gpg:                issuer "sjg@chromium.org"
# gpg: Good signature from "Simon Glass <sjg@chromium.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: B25C 0022 AF86 A7CC 1655  B627 7F17 3A3E 9008 ADE6
2021-10-31 15:48:43 -04:00
Marek Vasut
b55881ddb4 bootstage: Add SPL support
Allow usage of the bootstage facilities in SPL.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-10-31 12:26:44 -06:00
Tom Rini
286a1595fb sandbox: Migrate ARCH_MAP_SYSMEM to Kconfig
Move this from a hard-coded define in config.mk to Kconfig.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-10-31 12:26:44 -06:00
Tom Rini
e63a3130e9 Merge https://source.denx.de/u-boot/custodians/u-boot-sh
- rzg2_beacon updates
2021-10-31 12:47:35 -04:00
Dzmitry Sankouski
3e2095e960 board: samsung: add support for Galaxy A series of 2017 (a5y17lte)
Samsung Galaxy A3, A5, A7 (2017) - middle class Samsung smartphones.
U-boot can be used as chain-loaded bootloader to gain control
on booting vanilla linux(and possibly others) kernels

Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
2021-10-31 11:25:39 -04:00
Dzmitry Sankouski
69bde0410a SoC: exynos: add support for exynos 78x0
Samsung Exynos 7880 \ 7870 - SoC for mainstream smartphones and tablets
introduced on March 2017.
Features:
- 8 Cortex A53 cores
- ARM Mali-T830 MP3 GPU
- LTE Cat. 7 (7880) or 6 (7870) modem

Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
2021-10-31 11:25:39 -04:00
Dzmitry Sankouski
80565ec6f0 board: samsung: add Samsung Galaxy S9/S9+(SM-G96x0) board
Samsung S9 SM-G9600 - Snapdragon SDM845 version of the phone,
for China \ Hong Kong markets.
Has unlockable bootloader, unlike SM-G960U (American market version),
which allows running u-boot as a chain-loaded bootloader.

Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
2021-10-31 11:25:38 -04:00
Dzmitry Sankouski
4cbc16ceb2 SoC: qcom: add support for SDM845
Hi-end qualcomm chip, introduced in late 2017.
Mostly used in flagship phones and tablets of 2018.
Features:
- arm64 arch
- total of 8 Kryo 385 Gold / Silver cores
- Hexagon 685 DSP
- Adreno 630 GPU

Tested only as second-stage bootloader.

Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Stephan Gerhold <stephan@gerhold.net>
2021-10-31 08:46:44 -04:00
Dzmitry Sankouski
90496afc27 clocks: qcom: add clocks for SDM845 debug uart
Allows to change clock frequency of debug uart,
thus supporting wide range of baudrates.
Enable / disable functionality is not implemented yet.
In most use cases of SDM845 (i.e. mobile phones and tablets)
it's not needed, because qualcomm first stage bootloader leaves it
initialized, and on the other hand there's no possibility to
replace signed first stage bootloader with u-boot.

Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
2021-10-31 08:46:44 -04:00
Dzmitry Sankouski
7964c30541 pinctrl: qcom: add pinctrl and gpio drivers for SDM845 SoC
Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Stephan Gerhold <stephan@gerhold.net>
[trini: Add CONFIG_SDM845 around sdm845_data usage]
2021-10-31 08:46:44 -04:00
Mark Kettenis
3dfef53610 arm: dts: apple: Add preliminary device trees
Add preliminary device trees for the Apple M1 mini (2020) and
Apple M1 Macbook Pro 13" (2020).  Device tree bindings for
the Apple M1 SoC are still being formalized and these device
trees will be synchronized with the Linux kernel as needed.

The device trees in this commit are based on the initial Apple
M1 device trees from Linux 5.13, nodes for dart, pcie, pinctrl,
pmgr, usb based on bindings on track for inclusion in Linux
5.15 and 5.16 and nodes for i2c, mailbox, nvme, pmu, spmi and
watchdog that don't have a proposed binding yet.

These device trees are provided as a reference only as U-Boot
uses the device tree passed by the m1n1 bootloader.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-10-31 08:46:44 -04:00
Mark Kettenis
785cfde5b3 iommu: Add Apple DART driver
The DART is an IOMMU that is used on Apple's M1 SoC.  This driver
configures the DART such that it operates in bypass mode which is
enough to support DMA for the USB3 ports integrated on the SoC.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-10-31 08:46:44 -04:00
Mark Kettenis
d520e1fb72 serial: s5p: Add Apple M1 support
Apple M1 SoCs include an S5L UART which is a variant of the S5P
UART.  Add support for this variant and enable it by default
on Apple SoCs.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-10-31 08:46:44 -04:00
Mark Kettenis
003b657edc arm: apple: Add initial support for Apple's M1 SoC
Add support for Apple's M1 SoC that is used in "Apple Silicon"
Macs.  This builds a basic U-Boot that can be used as a payload
for the m1n1 boot loader being developed by the Asahi Linux
project.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
[trini: Add MAINTAINERS entry]
2021-10-31 08:46:44 -04:00
Mark Kettenis
fb57462437 test: Add tests for IOMMU uclass
Add a set of tests for the IOMMU uclass.

Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-10-31 08:46:44 -04:00
Pali Rohár
d73db30427 arm: mvebu: Fix booting from SATA
Use proper SATA macro for boot_device switch in spl_boot_device() function.

Signed-off-by: Pali Rohár <pali@kernel.org>
Fixes: 2226ca1734 ("arm: mvebu: Load U-Boot proper binary in SPL code based on kwbimage header")
2021-10-31 08:46:44 -04:00
Michael Walle
60b9b47d29 Revert "arch: arm: use dt and UCLASS_SYSCON to get gic lpi details"
Stop using the device tree as a source for ad-hoc information.

This reverts commit 2ae7adc659.

Signed-off-by: Michael Walle <michael@walle.cc>
[trini: Also make board/broadcom/bcmns3/ns3.c fail clearly now]
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-31 08:46:29 -04:00
Tom Rini
a84cea06bb Revert "arm64: Layerscape: Survive LPI one-way reset workaround"
Ad-hoc bindings that are not part of the upstream device tree / bindings
are not allowed in-tree.  Only bindings that are in-progress with
upstream and then re-synced once agreed upon are.

This reverts commit af288cb291.

Cc: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Reported-by: Michael Walle <michael@walle.cc>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Marc Zyngier <maz@kernel.org>
2021-10-30 23:07:51 -04:00
Adam Ford
5c5437b81e ARM: rmobile: beacon: Enable reference clocks for USB and AVB
Both Ethernet and USB drivers get their reference clocks from
the versaclock.  Enable that driver and the common clock driver
by default.

Signed-off-by: Adam Ford <aford173@gmail.com>
2021-10-29 21:52:20 +02:00
Adam Ford
cde373f04f ARM: rmobile: beacon: Remove duplicated for RZ/G2 M/N/H
Now that TARGET_BEACON_RZG2M can handle all the work that
was done with TARGET_BEACON_RZG2N and TARGET_BEACON_RZG2H,
remove them since they just create more duplicate code.

Signed-off-by: Adam Ford <aford173@gmail.com>
2021-10-29 21:52:19 +02:00
Adam Ford
0d115694ab ARM: rmobile: beacon: Support RZ/G2 [M/N/H] on TARGET_BEACON_RZG2M
The three different boards share the same board file and only differ
in terms of which SoC is being used.  By enabling FIT on
TARGET_BEACON_RZG2M, it can support all three boards and elimate
duplicate code.

Signed-off-by: Adam Ford <aford173@gmail.com>
2021-10-29 21:51:54 +02:00
Vyacheslav Bocharov
52195ba5f5 ARM: amlogic: add sm efuse write support and cmd for read/write efuse
This adds support for amlogic efuse write and provides two subcommands
of "sm" command: "efuseread" and "efusewrite" to read/write bytes between
memory and efuse.

Signed-off-by: Vyacheslav Bocharov <adeep@lexina.in>
[narmstrong: fixed indent at end of patch]
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-10-29 14:06:45 +02:00
Tom Rini
aafc378a6c Merge https://source.denx.de/u-boot/custodians/u-boot-marvell
- mvebu: Fix usage of BIN header arguments (Pali)
- mvebu: turris_omnia: Fix MTD partitions order for Linux (Pali)
- mvebu: nandpagesize support for kwbimage v1 (Pali)
2021-10-28 07:57:54 -04:00
Pali Rohár
7af368f471 arm: mvebu: Fix comments about kwbimage structures
kwbimage v1 is used on more SoCs.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-10-28 10:33:32 +02:00
Pali Rohár
33cdd9eeaa arm: mvebu: Update name of kwbimage v1 field at offset 0x2-0x3
At this offset is stored nand page size.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-10-28 10:33:32 +02:00
Pali Rohár
e6571f38c9 arm: mvebu: Remove dummy BIN header arguments for SPL binary
U-Boot SPL binary does not read BIN header arguments, so passing some dummy
values 0000005b and 00000068 has no effect for U-Boot SPL code.

Probably these two values comes from old Marvell DDR training code which
was separated from U-Boot and used it for some configuration.

Seems that two 32-bit values were specified here to ensure SPL code
alignment to 128-bit boundary as it is required e.g. for A370 or AXP
processors. Main kwbimage header is 64-byte long which is aligned to
128-bit boundary. Optional kwbheader is 32-bit long, number of BIN header
arguments is stored in 32-bit number. So for alignment to 128-bit boundary
is needed 64-bit padding which exactly these two 32-bit dummy arguments
provided.

Now when mkimage correctly aligns start of executable code in BIN header to
128-bit boundary, there is no requirement to put dummy argument values into
kwbimage. So remove them.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-10-28 10:33:32 +02:00
Pali Rohár
701769d87e arm: mvebu: Add documentation for save_boot_params() function
Important detail is availability of kwbimage BIN header arguments passed
via r0 and r1 registers by BootROM.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-10-28 10:33:32 +02:00
Ilias Apalodimas
e7fb789612 sandbox: Remove OF_HOSTFILE
OF_HOSTFILE is used on sandbox configs only.  Although it's pretty
unique and not causing any confusions,  we are better of having simpler
config options for the DTB.

So let's replace that with the existing OF_BOARD.  U-Boot would then
have only three config options for the DTB origin.
- OF_SEPARATE, build separately from U-Boot
- OF_BOARD, board specific way of providing the DTB
- OF_EMBED embedded in the u-boot binary(should not be used in production

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-10-27 16:38:26 -04:00
Ricardo Salveti
949eb228f3 arm: spl: prepare for jumping to OPTEE
Make sure to (if applicable) flush the D-cache, invalidate I-cache,
and disable MMU and caches before jumping to OPTEE.
This fixes the SDP->SPL->OPTEE boot flow on iMX6Q and most likely on
some other ARM SoCs.

Signed-off-by: Ricardo Salveti <ricardo@foundries.io>
Co-developed-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
2021-10-25 17:17:24 -04:00
Tom Rini
397b35f097 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-sunxi
- Add and enable watchdog driver
- Prepare for SYSRESET driven AXP poweroff
- Prepare for SoCs without MMC2
- Some fixes for extending SPL (SPL-DM for RISC-V)
- Some preparations for proper VBUS management
- Fix secure monitor move
2021-10-25 12:09:57 -04:00
Icenowy Zheng
03510bf621 sunxi: only include alias for eMMC when mmc2 used
Some Allwinner SoCs (e.g. R329) doesn't have a MMC2 controller at all,
and on boards that we do not utilize MMC2, the alias for it is just
useless.

Only include the alias when we specify CONFIG_MMC_SUNXI_EXTRA_SLOT to 2.

Signed-off-by: Icenowy Zheng <icenowy@sipeed.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-25 14:54:50 +01:00
Samuel Holland
08bdb976b7 sunxi: dts: H616: Enable the watchdog
For some reason, the watchdog was disabled in the H616 device tree. Most
likely this is a copy-paste from the H6 device tree: the H6 watchdog is
disabled because it is broken in some chips. However, there is no
evidence of issues with the H616 watchdog.

Enable the watchdog node so it can be used by the driver.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-25 14:54:42 +01:00
Tom Rini
35a7677e38 u-boot-imx-20211022
-------------------
 
 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/9561
 
 - i.MX8:
 	- Toradex Verdin (switch to binman, cleanup, etc.)
 	- Phytec phycore_imx8mm (fixes, boot from SPI-NOR)
 	- fixes for imx8mp_evk
 - doc (i.MX): MX8MM with Fast boot
 - i.MX6:
 	- Toradex : colibri-imx6ull with eMMC, fixes
 - i.MX7ULP :
 	- preparation for OPTEE + Serial Number
 - generic:
 	- imx8m_image: Support ddr3 firmware
 -----BEGIN PGP SIGNATURE-----
 
 iG0EABECAC0WIQS2TmnA27QKhpKSZe309WXkmmjvpgUCYXat2A8cc2JhYmljQGRl
 bnguZGUACgkQ9PVl5Jpo76ZMQQCeO3RELcie75bMjKbazAYLcfXvmm0AniuuWM/0
 gtxxC0ObQue2LpkQMAVU
 =plVt
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-imx-20211022' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

u-boot-imx-20211022
-------------------

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/9561

- i.MX8:
	- Toradex Verdin (switch to binman, cleanup, etc.)
	- Phytec phycore_imx8mm (fixes, boot from SPI-NOR)
	- fixes for imx8mp_evk
- doc (i.MX): MX8MM with Fast boot
- i.MX6:
	- Toradex : colibri-imx6ull with eMMC, fixes
- i.MX7ULP :
	- preparation for OPTEE + Serial Number
- generic:
	- imx8m_image: Support ddr3 firmware
2021-10-25 09:54:36 -04:00
Samuel Holland
b147bd3607 sunxi: Enable watchdog timer support by default
A watchdog helps recover from hangs or failure to boot an OS. It can
also be used by the sysreset framework to intentionally reset the
system. Now that a driver is available, let's enable this functionality
on sunxi boards.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-25 14:54:36 +01:00
Andre Przywara
0ec88323da sunxi: SPL SPI: Allow larger SPL
The more recent Allwinner SoCs BootROMs can actually load SPL images
larger than 32KB. We use this on the H616 to fit the extra code needed
for the PMIC into the image, and have provisions in board.c to respect
that larger SPL size when booting from MMC.

However the sunxi SPL SPI loader has a hardcoded load offset of 32KB,
which will fail on the H616.

To fix this, use the same algorithm we use for MMC: if the SPL size is
smaller than 32KB, we use 32KB, otherwise we expect the U-Boot payload
directly after the SPL code.

This prepares for SPI booting with larger SPLs like on the H616.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2021-10-25 14:48:58 +01:00
Samuel Holland
a3010bcfed sunxi: Select SPL_SEPARATE_BSS
sunxi-common.h defines CONFIG_SPL_BSS_START_ADDR to put SPL's BSS in
DRAM. Due to this, we must select SPL_SEPARATE_BSS, or else SPL will
attempt to load its DTB from the wrong address (after BSS in DRAM).

This change fixes booting with SPL_OF_CONTROL=y.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-25 14:48:58 +01:00
Tom Rini
f055f2e5a2 Pull request for efi-2022-01-rc1
Documentation:
 	Use Sphinx 3.43.
 	Move system reset documentation to HTML
 
 UEFI:
 	Fix linking EFI apps with LLVM
 	Fix alignment of loaded image
 	Correct simple network protocol test
 	Code cleanup
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEEK7wKXt3/btL6/yA+hO4vgnE3U0sFAmFyqecACgkQhO4vgnE3
 U0vdwA//Vwg4q3fbMB/FeoI4cbdSJl1+IYnPdbZC1+TAnyv9kLuPlYON54GMwBo5
 K4qbvuzn8clAohJUPjUqPJumFLSzUqdVxCKqg4gFxfufTSH8T+LvmcooSbZW3y6d
 S4lgybbg5i5cwhi141sbL3wxQibNeFDhY3aIA6v8cKYtH+37MDFsTJ4rwq93r+bF
 cZlN6vHPZsklgTs66jJnlZs809ECH/3+BurM3+NQBz+AJFpKhxIpHkE/He16Yt/t
 6vLBfux4iRYF8OtEP1/7pPu4NKXfXOE3MkGTTzoYAiG7LM3kIuGn+De2dY/Z3CGE
 6WXTt7trzkwW1z1sXafMFFiV8n0Gj/ubDLTD3X9AVVWvp7LAIJmcU8dx79C0eKzJ
 HWHZqwAl4ZYlaxUbf7n/C6Mlhjnis0WUNiqc/OSgGhVmn4HeOOgrjVted3uvvm/9
 enR2HlSqibF8KOzcZec5fsPt9GxS/ZlGcUKMiYO1+wKbM+EQG0bz0v2uiers/U8o
 ixurj0Hj0tJEvaOEcHCQH99ug2PKpFDysOPc31lOrmg8jfD1Bxq728UWxfFYDSmI
 2cxv3G8K65imCrI7eTMTDG3AmdF142CET7MzNOMUlwcnqCskax2UhPVncXJdvFlT
 z00DdMF5Z6/gHfIYGu7KRt1MZ/yBWJOjt8J78ttIo40o1jJP4Rk=
 =EhtP
 -----END PGP SIGNATURE-----

Merge tag 'efi-2022-01-rc1' of https://source.denx.de/u-boot/custodians/u-boot-efi

Pull request for efi-2022-01-rc1

Documentation:
	Use Sphinx 3.43.
	Move system reset documentation to HTML

UEFI:
	Fix linking EFI apps with LLVM
	Fix alignment of loaded image
	Correct simple network protocol test
	Code cleanup
2021-10-22 12:43:30 -04:00
Heinrich Schuchardt
737fd142de sandbox: provide /chosen/boot-hartid property
On RISC-V the sandbox must provide the /chosen/boot-hartid in the
devicetree.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-10-21 12:50:48 -06:00
Ricardo Salveti
b5a2a76454 mx7ulp: add getting a board serial number
Get Unique ID of SoC iMX7ULP, using the logic described in Fusemap
(IMX7ULPRMB2_Rev0_Fusemap) attached in the i.MX 7ULP APRM [1].

[1]
https://www.nxp.com/docs/en/reference-manual/IMX7ULPRMB2.pdf

Signed-off-by: Ricardo Salveti <ricardo@foundries.io>
Co-developed-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2021-10-21 13:59:26 +02:00
Ye Li
35813490d6 arm: dts: imx8mp: Delete default clocks for clock controller node
Since SPL has initialized clocks for bus and core. We don't need to
set the default clocks for clock controller node.

Signed-off-by: Ye Li <ye.li@nxp.com>
Tested-by: Teresa Remmet <t.remmet@phytec.de>
Tested-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
2021-10-21 13:59:26 +02:00
Ye Li
a65b7fb2a5 arm: dts: imx8mp-evk: Enable the EQoS ethernet port
i.MX8MP EVK has two ethernet ports. Add relevant nodes and properties
for EQoS port to the EVK DTS file.
In -u-boot.dtsi, change the u-boot eqos compatible string, add PHY
reset gpio and remove assigned clocks as not supported in CCF.

Signed-off-by: Ye Li <ye.li@nxp.com>
2021-10-21 13:59:26 +02:00
Ye Li
5d3ba244d7 arm: mach-imx: Allow to build mac.c for EQoS driver
i.MX8MP has one DWC EQoS controller, so allow to build mac.c when
only this driver is enabled.

Signed-off-by: Ye Li <ye.li@nxp.com>
2021-10-21 13:59:26 +02:00
Ye Li
6daa6a97d1 arm: mach-imx: Update MAC fuse for i.MX8MP
i.MX8MP has two ENET controllers, have to update the function to
enable loading two MAC addresses.

Signed-off-by: Ye Li <ye.li@nxp.com>
Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2021-10-21 13:59:26 +02:00
Stefano Babic
5fac11e6d5 Merge branch 'master' of git://git.denx.de/u-boot
Signed-off-by: Stefano Babic <sbabic@denx.de>
2021-10-21 13:58:13 +02:00
Tom Rini
f200a4bcec Merge https://source.denx.de/u-boot/custodians/u-boot-marvell
- Turris MOX and Omnia changes, mostly moving to Kconfig (Marek)
- a37xx: pci: Misc smaller fixes (Pali)
- cmd: tlv_eeprom: Fix building with DEBUG enabled (Sven)
- termios_linux.h: Fix tcsendbreak() implementation (Pali)
- mvebu: Add missing "if SPL" (Tom)
2021-10-21 07:52:15 -04:00
Michal Simek
599becb0ae arm64: zynqmp: Fix sgmii clock input freq for p-a2197
Input frequency for sgmii is 125MHz on all Xilinx designs.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/87153c59cc526f5955b3bff3db11027b5848c042.1634302099.git.michal.simek@xilinx.com
2021-10-21 08:52:30 +02:00
Michal Simek
d2d14383ba arm64: zynqmp: Add support for DLC21 (Smartlynq+) board
DLC21 is used as fast jtag cable. The patch adds support for this board
from PS perspective. The most interesting part on the board is seps525 oled
display. Also i2c, gpio, ethernet, uart, SD and eMMC are tested.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/3d35cd6a11cffc7456e21a88b214cc965734e852.1634231268.git.michal.simek@xilinx.com
2021-10-21 08:51:33 +02:00
Liam Beguin
181419446a arm64: zynqmp: allow overriding board name
There is no need to use zynqmp name as SYS_BOARD for all boards.
The patch is adding an option to change it.

Signed-off-by: Liam Beguin <liambeguin@gmail.com>
Link: https://lore.kernel.org/r/20211020152518.3511912-1-liambeguin@gmail.com
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-10-21 08:51:00 +02:00
Jorge Ramirez-Ortiz
398a74ae33 zynqmp: restore the jtag interface
When boot.bin is configured for secure boot the CSU will disable the
JTAG interface on all cases.

Some boards might rely on this interface for flashing to QSPI in which
case those systems might end up bricked during development.

This commit will restore the interface under CSU control

Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Link: https://lore.kernel.org/r/20211013134800.19452-1-jorge@foundries.io
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-10-21 08:51:00 +02:00
Tom Rini
7609e02a25 arm: mvebu: Add missing "if SPL"
We can only select SPL_SKIP_LOWLEVEL_INIT if SPL is enabled, otherwise
we get a warning about unmet dependencies on platforms that don't use
SPL.

Fixes: cf47a8cf8f ("arm: mvebu: Select SPL_SKIP_LOWLEVEL_INIT on ARMADA_32BIT")
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-10-21 07:39:05 +02:00
Marek Behún
6d7bfb658e arm: mvebu: turris_omnia: Move CONFIG_SPL_DRIVERS_MISC to Kconfig
Instead of declaring CONFIG_SPL_DRIVERS_MISC in board config header,
select it in Kconfig.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-10-21 07:39:05 +02:00
Marek Behún
2c8a4e4d76 arm: mvebu: turris_omnia: Move SPL's SYS_MALLOC_SIMPLE to Kconfig
Instead of declaring CONFIG_SYS_MALLOC_SIMPLE dependant on
CONFIG_SPL_BUILD in board config header, select
CONFIG_SPL_SYS_MALLOC_SIMPLE in Kconfig.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-10-21 07:39:05 +02:00
Simon Glass
567dfef2fe x86: Show some EFI info with the bdinfo command
It is useful to see some basic EFI info with the command as it forms part
of the information about a board.

Add a hook for this and show the table address as a start.

While here, fix an invalid cast in setup_efi_info(). Note that this
function is using a data structure defined by Linux so we cannot change
it. Also note that ulong is used since this is the standard in U-Boot
(>6k uses), despite there being quite a bit of the more verbose uintptr_t
(930 uses).

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-10-21 03:46:03 +02:00
Simon Glass
e70be676eb x86: Create a new header for EFI
The setup routines are called from zimage but don't really belong in the
zimage header. Add a new EFI header to house these. Add comments so it is
clear what the functions do.

Note that these functions are x86-specific. The zimage business is not
used on other architectures.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-10-21 03:46:03 +02:00
Simon Glass
8d76744e50 x86: Keep symbol information in u-boot ELF file
At present this information is stripped when linking. It is useful to keep
it around. Strip it from the .efi files instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2021-10-21 03:46:03 +02:00
Tom Rini
79b8849d4c u-boot-imx-20211020
-------------------
 
 First PR from u-boot-imx for 2022.01
 
 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/9535
 
 - new board: kontron-sl-mx8mm
 - imx8m:
 	- fix secure boot
 - imx ESDHC: fixes
 - i.MX53: Support thum2, bmode and fixes for Menlo board
 	  usbarmory switch to Ethernet driver model
 - imx6 :
 	- DDR calibration for Toradex boards
 - imx7:
 	- Fixes
 - Updated gateworks boards (ventana / venice)
 -----BEGIN PGP SIGNATURE-----
 
 iG0EABECAC0WIQS2TmnA27QKhpKSZe309WXkmmjvpgUCYXAPLA8cc2JhYmljQGRl
 bnguZGUACgkQ9PVl5Jpo76ZZdwCfQBZyd9IWYk3vY0lYgCZsBYl8oXoAn0o9BjVu
 tMJRAcFOLxegM4CJAeqC
 =zg72
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-imx-20211020' of https://source.denx.de/u-boot/custodians/u-boot-imx

u-boot-imx-20211020
-------------------

First PR from u-boot-imx for 2022.01

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/9535

- new board: kontron-sl-mx8mm
- imx8m:
	- fix secure boot
- imx ESDHC: fixes
- i.MX53: Support thum2, bmode and fixes for Menlo board
	  usbarmory switch to Ethernet driver model
- imx6 :
	- DDR calibration for Toradex boards
- imx7:
	- Fixes
- Updated gateworks boards (ventana / venice)

# gpg verification failed.
2021-10-20 14:24:09 -04:00
Max Krummenacher
80ef6926e7 colibri-imx6ull: add emmc variant
Add code to build the eMMC variant of the Colibri iMX6ULL, i.e. the
'Colibri iMX6ULL 1GB' which has a eMMC instead of the raw NAND used
on other SKUs.

Related-to: ELB-4056, ELB-4057
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2021-10-20 17:54:31 +02:00
Fabio Estevam
028abfd9b1 imx8mm-evk: Generate a single bootable flash.bin again
After the conversion to binman in commit 8996e6b7c6 ("imx8mm_evk: switch
to use binman to pack images"), it is necessary to flash both flash.bin and
u-boot.itb to get a bootable system. Prior to this commit, only flash.bin
was needed.

Such new requirement breaks existing distro mechanisms to generate the
final binary because the extra u-boot.itb is now required.

Generate a final flash.bin that can be used again as a single
bootable binary to keep the original behavior.

After this change the SPL binary is called spl.bin, which is a more
descriptive name for its purpose, and can still be used standalone
(for example, for secure boot purposes).

Also update imx8mm_evk.rst to remove the u-boot.itb copy step.

Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Heiko Thiery <heiko.thiery@gmail.com>
2021-10-20 17:46:09 +02:00
Teresa Remmet
463a01c7e4 board: phytec: imx8mm-phycore: Switch to binman
Use binman for image creation.

Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
2021-10-20 15:10:13 +02:00
Teresa Remmet
f38b1da8bb board: phytec: phycore-imx8mm: Add SPI-NOR flash support
Adds SPI-NOR flash support to erase, read and write in bootloader.

Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
2021-10-20 15:09:26 +02:00
Teresa Remmet
115732170e arm: dts: phycore-imx8mm: Fix property
Fix misspelled property "stdout-path".

Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
2021-10-20 15:09:26 +02:00
Teresa Remmet
5eee18d848 arm: dts: phycore-imx8mm-u-boot: Add wdog pinctrl entry
Add missing pinctrl entry in spl.

Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
2021-10-20 15:09:25 +02:00
Marcel Ziswiler
f254a46809 verdin-imx8mm: fix watchdog pinctrl issue
Finally, found the root cause of the issue already once mentioned back
here [2] which caused the following error message during boot:

imx_wdt watchdog@30280000:
 pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19

Turns out while the watchdog node itself was already u-boot,dm-spl its
pinctrl node was not which caused it to be unavailable at that early
stage. Note that any and all other boards I checked also seem to be
missing this. However, I can't judge whether or not they might indeed
need a similar fix or not.

[2] https://marc.info/?l=u-boot&m=161786572422973

Fixes: commit d304e7ace3
 ("ARM: imx8m: Fix reset in SPL on Toradex iMX8MM Verdin")
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2021-10-20 15:08:26 +02:00
Max Krummenacher
8da72960ed verdin-imx8mm: enable sleep_moci output
This powers some peripherals on the carrier board e.g. the USB hub.

Related-to: ELB-3206
Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2021-10-20 15:08:26 +02:00
Marcel Ziswiler
5cfa55930b verdin-imx8mm: switch to use binman to pack images
Use binman to pack images.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Heiko Thiery <heiko.thiery@gmail.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2021-10-20 15:08:26 +02:00
Marcel Ziswiler
088eb75407 arm64: dts: imx8mm-verdin-u-boot.dtsi: alphabetically re-order
Alphabetically re-order nodes and properties.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
2021-10-20 15:08:25 +02:00
Marcel Ziswiler
8d060e4a66 ARM: dts: imx8mm-verdin: prepare for dek blob encapsulation
Prepare for DEK blob encapsulation support through "dek_blob" command.
On ARMv8, u-boot runs in non-secure, thus cannot encapsulate a DEK blob
for encrypted boot.
The DEK blob is encapsulated by OP-TEE through a trusted application
call. U-boot sends and receives the DEK and the DEK blob binaries
through OP-TEE dynamic shared memory.

To enable the DEK blob encapsulation, add to the defconfig:
CONFIG_SECURE_BOOT=y
CONFIG_FAT_WRITE=y
CONFIG_CMD_DEKBLOB=y

Taken from NXP's commit 56d2050f40 ("imx8m: Add DEK blob encapsulation
for imx8m").

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2021-10-20 15:08:25 +02:00
Marcel Ziswiler
4b3abe5972 imx8m: clean-up kconfig indentation
Replace spurious spaces with proper tabs.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2021-10-20 15:08:25 +02:00
Nick Hu
ddf4972834 riscv: Avoid io read/write cause wrong result
io read/write may cause wrong result because they may read/write data
from/to register instead of memory. Add 'volatile' to avoid it.

Signed-off-by: Nick Hu <nick.hu@sifive.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-10-20 10:59:17 +08:00
Ilias Apalodimas
2ea63271e5 board: arm: Remove OF_PRIOR_STAGE from the remaining Arm boards
At some point back in 2018 prior_stage_fdt_address and OF_PRIOR_STAGE got
introduced,  in order to support a DTB handed over by an earlier stage boo
loader.  However we have another option in the Kconfig (OF_BOARD) which has
identical semantics.

So let's remove the option in an effort to simplify U-Boot's config and DTB
management,  and use OF_BOARD instead.

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-10-18 13:19:50 -04:00
Ilias Apalodimas
2e8d2f8843 riscv: Remove OF_PRIOR_STAGE from RISC-V boards
At some point back in 2018 prior_stage_fdt_address and OF_PRIOR_STAGE got
introduced,  in order to support a DTB handed over by an earlier stage boo
loader.  However we have another option in the Kconfig (OF_BOARD) which has
identical semantics.

On RISC-V some of the boards pick up the DTB from a1 and copy it in their
private gd_t.  Apart from that they copy it to prior_stage_fdt_address,  if
the Kconfig option is selected, which is unnecessary.

So let's switch the config option for those boards to OF_BOARD and define
the required board_fdt_blob_setup() for them.

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
2021-10-18 13:19:50 -04:00
Tom Rini
d990f7d75d Merge tag 'u-boot-rockchip-20211015' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
- Fix for Rockchip mmc HS400 mode;
- Fix for px30 board Odroid Go;
- rockchip_sfc update;
- rk3568 clk update;
- doc fix;
2021-10-17 21:13:49 -04:00
Tom Rini
6a86f12126 Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-tegra
On merge, fixup order of fdtdec_add_reserved_memory parameters in
arch/arm/cpu/armv8/fsl-layerscape/soc.c

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-15 18:30:33 -04:00
Marek Behún
56882dc4cb Convert CONFIG_USB_EHCI_IS_TDI to Kconfig
On mvebu this is defined if and only if !ARM64.

Otherwise it is defined for boards with ARCH_MX23, ARCH_TEGRA and
ARCH_ZYNQ, and also for SOC_AR934X (tplink_wdr4300).

Signed-off-by: Marek Behún <marek.behun@nic.cz>
2021-10-15 09:42:22 -04:00
Marek Behún
92832045c5 Rename CONFIG_EHCI_IS_TDI to CONFIG_USB_EHCI_IS_TDI
In preparation for moving this option to Kconfig, rename it to be
consistent with other USB EHCI Kconfig options.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
2021-10-15 09:42:22 -04:00
Elaine Zhang
f2cdd44adb clk: rockchip: rk3568: update clks
fix up ppll init freq.
support tclk_emmc.
add freq (26M) for mmc device.
fix up the sfc clk rate unit error.

Change in V2:
remove change id.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-10-15 20:57:31 +08:00
Chris Morgan
193ab22797 rockchip: px30: sync serial flash controller bindings with mainline
The devicetree submitted and approved for the mainline linux kernel is
slightly different than the one present here. This syncs both
devicetrees (for the Rockchip SFC node at least) present on the PX30
and the Odroid Go Advance. Changes include renaming the flash node,
reordering the values in the SFC node for the rk3326-odroid-go2,
changing the name of the cs pinctrl node to cs0, and updating the
u-boot specific tree to utilize the new flash node value.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-10-15 20:56:55 +08:00
Chris Morgan
8d43e2412a rockchip: board: remove SCLK_GPU from U-Boot DT
Starting with commit 92f1e9a4b3 ("clk: Detect failure to set
defaults") the clk driver for the PX30 would fail to probe for the
Odroid Go Advance. This patch is to remove the clock for the GPU from
the U-Boot specific devicetree, as that clock is not supported by the
U-Boot clk_px30 driver.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2021-10-15 20:56:09 +08:00
Patrick Delaunay
ff07cc9ed1 scripts: remove some configs in config_whitelist.txt
Remove some config finishing by _ badly added by
scripts/build-whitelist.sh when joker is used in comments.

for example:
  doc/uImage.FIT/command_syntax_extensions.txt:
     ... #ifdef CONFIG_OF_*  |	...

  cmd/nvedit.c:# error Define one of CONFIG_ENV_IS_IN_{EEPROM| \
     FLASH|MMC|FAT|EXT4|\

Remove also configs only used in comments:
- CONFIG_BOOGER in include/linux/kconfig.h
- CONFIG_COMMANDS
- CONFIG_INIT_IGNORE_ERROR
- CONFIG_REG_*
- CONFIG_HOTPLUG : drivers/watchdog/omap_wdt.c:18

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
2021-10-15 07:55:17 -04:00
Thierry Reding
a0ba216ed4 ARM: tegra: Copy memory-region-names property
If multiple entries are present in the memory-region property, this new
memory-region-names property can be used to specify names for each of
them so that they can be more easily distinguished.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2021-10-13 14:18:30 -07:00
Thierry Reding
77409c7f83 ARM: tegra: Refactor DT update helpers
Rather than duplicate the Ethernet MAC address and carveout updating
code for each board, move it to a common location and make it more
reusable.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2021-10-13 14:18:30 -07:00
Thierry Reding
b9aad37591 fdtdec: Support reserved-memory flags
Reserved memory nodes can have additional flags. Support reading and
writing these flags to ensure that reserved memory nodes can be properly
parsed and emitted.

This converts support for the existing "no-map" flag to avoid extending
the argument list for fdtdec_add_reserved_memory() to excessive length.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2021-10-13 14:18:30 -07:00
Thierry Reding
46cb067803 fdtdec: Support compatible string list for reserved memory
Reserved memory nodes can have a compatible string list to identify the
type of reserved memory that they represent. Support specifying an
optional compatible string list when creating these nodes.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
2021-10-13 14:18:30 -07:00
Tom Rini
776bf6a545 - Disable ATAGS for STM32 MCU and MPU boards
- Disable bi_boot_params for STM32 MCU and MPU boards
 - Update stm32-usbphyc node management
 - Convert CONFIG_STM32_FLASH to Kconfig for STM32 MCU boards
 - Convert some USB config flags to Kconfig for various boards
 - Convert CONFIG_BOOTCOMMAND flag to Kconfig for STM32 F429 board
 - Remove specific CONFIG_STV0991 flags
 - Remove unused CONFIG_USER_LOWLEVEL_INIT flag
 - Add ofdata_to_platdata() callback for stm32_spi driver
 - Update for stm32f7_i2c driver
 - Remove gpio_hog_probe_all() from STM32 MP1 board
 - Fix bind command
 -----BEGIN PGP SIGNATURE-----
 
 iQJQBAABCgA6FiEEXyrViUccKBz9c35Jysd4L3sz/6YFAmFlgsIcHHBhdHJpY2Uu
 Y2hvdGFyZEBmb3NzLnN0LmNvbQAKCRDKx3gvezP/plnND/4q9HSlvddybIPjBHlW
 rXz1ISwj8JZPp7R4MJcB4RiHofYZzjTXx3dDYUif6oQMpCDp64KPfcUDW0kaq8U7
 ZFwJvt59boV1XWlonIXMb3gAkY6gFa5PnYAE/YXEqKvPPvUb7FkT7BWxm4LxCGsj
 mEmboR8u87s6e4ZP03HJsSVa5FnNwJUZU8b+58Vxp10YC0PPf7kpmgCucDhrghvY
 TORlk259KUFoZXz4J4My0VzDdxE05gDqq1m6Xw1CzqcUbGysMvjNEHlxGdYbWD/U
 maamP19DUmKUREmpj3kO/JZvacLJlQP/mdGJ0OWKNbIr/3ha4dYagxDoRodEVo0m
 DYaaVPGvG24G78d5meB2q9wT0aGdTyaqm+XRBQMvMN2LlaGmu9duA1t6yBuyMcFk
 BeA7d0eHMo1ezD9FFZMxwIOAWhJlcYQEAMFhUwkR1B322w0NU4nbl9KRCGuGV2Zp
 ZFQV4BoMvb0NwAdo66xwZ+gSq4Wp1y46VM6x2Mw52v2F4p3teeAqR906TdQVYO8+
 hlYChO9+qK4JO7LPX/5wQ4FIzcq1HnTzTpuOSf28hsemiPMu0OkAQv1J7DohNZix
 wELBA+ZIjGXksmDTPjpXg5CSvVALa/l2G816hp7/XTJ1XRBSz/pzjhp5rwm42zmw
 x7EPnwzpAlQCSqTQ0sgO+fgoRA==
 =S4kl
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-stm32-20211012' of https://source.denx.de/u-boot/custodians/u-boot-stm

- Disable ATAGS for STM32 MCU and MPU boards
- Disable bi_boot_params for STM32 MCU and MPU boards
- Update stm32-usbphyc node management
- Convert CONFIG_STM32_FLASH to Kconfig for STM32 MCU boards
- Convert some USB config flags to Kconfig for various boards
- Convert CONFIG_BOOTCOMMAND flag to Kconfig for STM32 F429 board
- Remove specific CONFIG_STV0991 flags
- Remove unused CONFIG_USER_LOWLEVEL_INIT flag
- Add ofdata_to_platdata() callback for stm32_spi driver
- Update for stm32f7_i2c driver
- Remove gpio_hog_probe_all() from STM32 MP1 board
- Fix bind command

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-12 12:01:00 -04:00
Tom Rini
618c77d99a Second set of u-boot-at91 features for the 2022.01 cycle
-----BEGIN PGP SIGNATURE-----
 
 iQFQBAABCgA6FiEEqxhEmNJ6d7ZdeFLIHrMeAg6sL8gFAmFlfXAcHGV1Z2VuLmhy
 aXN0ZXZAbWljcm9jaGlwLmNvbQAKCRAesx4CDqwvyHzuB/4pV2iAeFBjNf6YYsuk
 uvBQm7+j+AQzy0J337bDwulvw8wTKKlaid4qfOpEjW316DI9oXN1bXTlwNsjtQvO
 zTILW7MoBjDRhZHsSkeSfIuD+Sc80juAoLBv+GXskQdZOTQUbWdmi2o60gdY5Ba4
 WN0i4zOGVqd7xoDuDgM3XC1M2RnKerxDeVt20Ji+5dFfmes11m7br6sWj2j/45f+
 q3G1ufHl+ea+8oRLZGjn2ddKCb1wLLOrNZA+74dsZ5SN0LCN0vFsE3+JAk4RZ2A5
 omiHVApjE+J3vAjwiVY7apjcIdVEeyb5AioiXSBAEZiq1l1UI7eKDQT75bDkaKSs
 4wBV
 =78ME
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-at91-2022.01-b' of https://source.denx.de/u-boot/custodians/u-boot-at91

Second set of u-boot-at91 features for the 2022.01 cycle:

This small feature set adds the support for PWM driver for the sama5d2
SoC. It also adds a node in the DT for this SoC.
2021-10-12 11:49:15 -04:00
Tom Rini
2aab77f726 Merge https://source.denx.de/u-boot/custodians/u-boot-sunxi
The bulk of it is Samuel's DM_I2C rework, which removes the nasty I2C
deprecation warnings for most 32-bit boards. It also includes some
smaller refactorings that pave the way for more changes, mostly driven
by needing to support the Allwinner RISC-V SoC later on.

Board wise we gain support for the FriendlyARM NanoPi R1S H5 router
board and official Pinetab support.

Build-tested for all 160 sunxi boards, and boot tested on a A64, A20,
H3, H6, and H616 board. USB, SD card, eMMC, and Ethernet all work there
(where applicable).
2021-10-12 11:45:00 -04:00
Dan Sneddon
1f83bda788 ARM: dts: sama5d2: Add pwm0 definition
Add node for the PWM0 on the SAMA5D2 SoC.

Signed-off-by: Dan Sneddon <dan.sneddon@microchip.com>
2021-10-12 15:18:39 +03:00
Samuel Holland
f9437b00c0 sunxi: Enable DM_I2C for all sunxi boards
Now that the last users of legacy I2C (outside of SPL) have been
resolved, we can enable DM_I2C at the sunxi architecture level.

Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-12 11:01:27 +01:00
Samuel Holland
2421497cb7 sunxi: video: Convert panel I2C to use DM_I2C
Two displays supported by the sunxi display driver (each one used by a
single board) require initialization over I2C. Both previously used
i2c_soft; replace this with the i2c-gpio instance that already exists in
those boards' device trees (sun5i-a13-utoo-p66 and sun6i-a31-colombus).

Since the i2c-gpio nodes are not referenced by any other node in the
device trees (the device trees have no panel node), the I2C bus is
selected by its node name.

This panel initialization code was the only i2c_soft user, so the
i2c_soft GPIO setup code can be removed now as well.

Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-12 11:01:17 +01:00
Samuel Holland
8b0eacdf2b sunxi: pmic_bus: Use the DM PMIC interface when possible
The pmic_bus functions are used in both SPL (for regulator setup) and
U-Boot proper (for regulator setup, SID access, GPIO, and poweroff).

Currently, pmic_bus conflicts with DM_I2C because it uses the legacy I2C
interface. This commit makes pmic_bus dual-compatible with either the
legacy I2C functions or the newly-added PMIC_AXP driver (which uses
DM_I2C). In turn, this allows platforms to start transitioning to DM_I2C
in U-Boot proper, without breaking boards that still depend on the
legacy I2C interface for other reasons.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-12 10:48:37 +01:00
Samuel Holland
d3b02987cb sunxi: pmic_bus: Clean up preprocessor conditions
Instead of using the SoC symbols to decide the bus type, use whichever
bus driver is actually enabled. This allows collapsing all of the AXP2xx
and AXP8xx variants into one "else" case. It also has the advantage of
falling back to I2C when the other bus drivers are disabled; this works
because all of the PMICs support I2C in addition to other interfaces.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-12 10:30:19 +01:00
Samuel Holland
3227c85fe7 i2c: Add a DM_I2C driver for the sun8i RSB controller
This bus controller is used to communicate with an X-Powers AXP PMIC.
Currently, various drivers access PMIC registers through a platform-
specific non-DM "pmic_bus" interface, which depends on the legacy I2C
framework. In order to convert those drivers to use DM_PMIC, this bus
needs a DM_I2C driver.

Refactor the rsb functions to take the base address as a parameter,
and implement both the existing interface (which is still needed in
SPL) and the DM_I2C interface on top of them.

The register for switching between I2C/P2WI/RSB mode is the same across
all PMIC variants, so move that to the common header.

There are only a couple of pairs of hardware/runtime addresses used
across all PMIC variants. So far the code expected only the "primary"
pair, but some PMICs like the AXP305 and AXP805 use the secondary pair,
so add support for that to the DM driver as well.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-12 10:19:18 +01:00
Samuel Holland
104950a7fe i2c: Add a DM_I2C driver for the sun6i P2WI controller
This bus controller is used to communicate with an X-Powers AXP PMIC.
Currently, various drivers access PMIC registers through a platform-
specific non-DM "pmic_bus" interface, which depends on the legacy I2C
framework. In order to convert those drivers to use DM_PMIC, this bus
needs a DM_I2C driver.

Refactor the p2wi functions to take the base address as a parameter,
and implement both the existing interface (which is still needed in
SPL) and the DM_I2C interface on top of them.

The register for switching between I2C/P2WI/RSB mode is the same across
all PMIC variants. Move that to the common header, so it can be used by
both interface implementations.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-12 09:50:56 +01:00
Samuel Holland
4ab39e74b6 sunxi: pmic_bus: Fix Kconfig dependencies
AXP_PMIC_BUS enables communication with a specific AXP PMIC at a
PMIC-dependent I2C/P2WI/RSB bus address. It is automatically selected
as a dependency of the PMIC driver. It should not be selectable by the
user when no PMIC is chosen.

AXP_GPIO uses the pmic_bus functions, and also depends on a specific
PMIC header to pick up register definitions.

Both of these changes have no impact on any existing configs, since
the code does not compile if the dependencies are not met.

Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-12 09:50:27 +01:00
Samuel Holland
abd2e783f1 sunxi: Select SUN8I_RSB more carefully
SUN8I_RSB should not be selected by MACH_SUN8I, because the hardware
is not present in half of those SoCs (H3/H5, R40, and V3s). Move the
selection to the SoCs where the hardware actually exists.
As it currently stands, selecting that option also requires using it in
some way, which is not the case for one A80 board. Since we have only
three A80 boards in total, we select it their via their defconfigs.

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
[Andre: fixing up Sunchip_CX-A99 build]
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-12 09:50:21 +01:00
Samuel Holland
ea261fdeb2 sunxi: Only initialize legacy I2C when enabled
CONFIG_SPL_I2C is the wrong symbol to use here. It is the top-level
Kconfig symbol (not specific to either legacy or DM I2C), whereas the
i2c_init() function is specific to legacy I2C. This change fixes a
build failure when enabling SPL_I2C but not SPL_SYS_I2C_LEGACY.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-by: Andre Przywara <andre.przywara@arm.com>
2021-10-12 09:49:09 +01:00
Jan Kiszka
08ad739f38 arm: dts: Update IOT2050 device tree files
This fixes the usage of the USB 3.0-capable port under U-Boot as USB
2.0-only port.

Original patch by Chao Zeng.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2021-10-11 15:02:50 -04:00
Jan Kiszka
ce543d0d4e board: siemens: iot2050: Adjust to changes in DT and configuration
Account for the changes done between merge proposal and the final merge.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2021-10-11 15:02:50 -04:00
Dario Binacchi
165e8fe5db clk: ti: add am33xx/am43xx spread spectrum clock support
The patch enables spread spectrum clocking (SSC) for MPU and LCD PLLs.
As reported by the TI spruh73x/spruhl7x RM, SSC is only supported for
the DISP/LCD and MPU PLLs on am33xx/am43xx. SSC is not supported for
DDR, PER, and CORE PLLs.

Calculating the required values and setting the registers accordingly
was taken from the set_mpu_spreadspectrum routine contained in the
arch/arm/mach-omap2/am33xx/clock_am33xx.c file of the u-boot project.

In locked condition, DPLL output clock = CLKINP *[M/N]. In case of
SSC enabled, the reference manual explains that there is a restriction
of range of M values. Since the clk_ti_am3_dpll_round_rate() attempts
to select the minimum possible N, the value of M obtained is not
guaranteed to be within the range required. With the new "ti,min-div"
parameter it is possible to increase N and consequently M to satisfy the
constraint imposed by SSC.

Link: https://lore.kernel.org/r/20210606202253.31649-6-dariobin@libero.it
Signed-off-by: Dario Binacchi <dariobin@libero.it>
2021-10-11 14:27:32 -04:00
Dario Binacchi
15a0411787 ARM: dts: am43xx-clocks: add spread spectrum support
Registers for adjusting the spread spectrum clocking (SSC) have been
added. As reported by the TI spruhl7x RM, SSC is supported only for LCD
and MPU PLLs, but the PRCM_CM_SSC_DELTAMSTEP_DPLL_XXX and
PRCM_CM_SSC_MODFREQDIV_DPLL_XXX registers, as well as the enable field
in the PRCM_CM_CLKMODE_DPLL_XXX registers are mapped for all PLLs (CORE,
MPU, DDR, PER, DISP, EXTDEV).

Link: https://lore.kernel.org/r/20210606202253.31649-5-dariobin@libero.it

Signed-off-by: Dario Binacchi <dariobin@libero.it>
2021-10-11 14:27:32 -04:00
Dario Binacchi
bf4a54fa78 ARM: dts: am33xx-clocks: add spread spectrum support
Registers for adjusting the spread spectrum clocking (SSC) have been
added. As reported by the TI spruh73x RM, SSC is supported only for LCD
and MPU PLLs, but the CM_SSC_DELTAMSTEP_DPLL_XXX and
CM_SSC_MODFREQDIV_DPLL_XXX registers, as well as the enable field in the
CM_CLKMODE_DPLL_XXX registers are mapped for all PLLs (CORE, MPU, DDR,
PER, DISP).

Link: https://lore.kernel.org/r/20210606202253.31649-4-dariobin@libero.it
Signed-off-by: Dario Binacchi <dariobin@libero.it>
2021-10-11 14:27:32 -04:00
Chukun Pan
e7510d24ca sunxi: Add support for FriendlyARM NanoPi R1S H5
This adds support for the NanoPi R1S H5 board.

Allwinner H5 SoC
512MB DDR3 RAM
10/100/1000M Ethernet x 2
RTL8189ETV WiFi 802.11b/g/n
USB 2.0 host port (A)
MicroSD Slot
Reset button
Serial Debug Port
WAN - LAN - SYS LED

The dts file is taken from Linux 5.14 tag.

Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-11 10:46:44 +01:00
Samuel Holland
8fe8ff3411 sunxi: gpio: Remove bank-specific size macros
Since the beginning, all banks have had space for 32 pins, even when
not all pins were implemented. Let's use a single constant for the GPIO
bank size here, like the GPIO driver is already doing.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-11 10:46:44 +01:00
Samuel Holland
4d9958b642 sunxi: gpio: Remove name_to_gpio macro
This clarifies which callers must be updated to complete the DM_GPIO
conversion.

The only remaining caller of name_to_gpio in generic code is inside the
!DM_GPIO block in cmd/gpio.c. DM_GPIO is always selected on sunxi, so
that code cannot be reached. And after this commit, there are only two
remaining implementations of name_to_gpio.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Acked-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-11 10:46:44 +01:00
Samuel Holland
425084610e sunxi: Clean up inclusions of asm/arch/gpio.h
As part of migrating to DM_GPIO and DM_PINCTRL, eventually we will
remove the asm/arch/gpio.h header. In preparation, clean up the various
files that include it.

Some files did not contain any GPIO code at all, so this header was
completely unused.

A few files contained only legacy platform-specific GPIO code for
setting up pin muxes. They were left unchanged, as that code will be
completely removed by the DM_PINCTRL migration.

The remaining files contain some combination of DM_GPIO and legacy GPIO
code. For those, switch to including asm/gpio.h (if it wasn't included
already). Right now, this header provides both sets of functions,
because ARCH_SUNXI selects GPIO_EXTRA_HEADER. This will still be the
right header to include once the DM_GPIO migration is complete and
GPIO_EXTRA_HEADER is no longer needed.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-11 10:46:44 +01:00
Samuel Holland
14c8c631e9 gpio: sunxi: Remove the sunxi_name_to_gpio_bank function
The only caller of this function was the MMC pinmux code, which used it
to parse a string given from a Kconfig symbol. As the Kconfig symbol has
been converted to a Boolean, this function is no longer needed.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-11 10:46:44 +01:00
Samuel Holland
dda9fa734f sunxi: Simplify MMC pinmux selection
Only one board, Yones Toptech BD1078, actually uses a non-default MMC
pinmux. All other uses of these symbols select the default value or an
invalid value. To simplify things, remove support for the unused pinmux
options, and convert the remaining option to a Boolean.

This allows the pinmux to be chosen by the preprocessor, instead of
having the code parse a string at runtime (for a build-time option!).
Not only does this reduce code size, but it also allows this Kconfig
option to be used in a table-driven DM pinctrl driver.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-11 10:46:44 +01:00
Samuel Holland
21d314a661 clk: sunxi: Move header out of arch directory
The CCU header is only used by the DM drivers, not any platform code.
Its current location adds an artificial dependency on CONFIG_ARM and
ARCH_SUNXI, which will be problematic when adding the CCU driver for
a RISC-V sunxi platform.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2021-10-11 10:46:44 +01:00
Simon Glass
0c303f9a66 image: Drop IMAGE_ENABLE_OF_LIBFDT
Add a host Kconfig for OF_LIBFDT. With this we can use
CONFIG_IS_ENABLED(OF_LIBFDT) directly in the tools build, so drop the
unnecessary indirection.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2021-10-08 15:53:26 -04:00
Simon Glass
bf371b4cf5 image: Drop IMAGE_ENABLE_FIT
Make use of the host Kconfig for FIT. With this we can use
CONFIG_IS_ENABLED(FIT) directly in the host build, so drop the unnecessary
indirection.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2021-10-08 15:53:26 -04:00
Patrice Chotard
2aaac1787a arm: dts: stm32: Add i2c-analog-filter property in I2C nodes for stm32h743
Add i2c-analog-filter property in I2C nodes to enable analog
filter feature.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-10-08 08:42:40 +02:00
Patrice Chotard
5d59bd553b arm: dts: stm32: Add i2c-analog-filter property in I2C nodes for stm32f746
Add i2c-analog-filter property in I2C nodes to enable analog
filter feature.

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-10-08 08:42:40 +02:00
Robert Marko
cfb7102d8d arm: mvebu: dts: m801: correct CP1 pinctrl
Current CP1 pinctrl that is set on the Puzzle M801 is incorrect.
CP1 pins are only used for the SMI bus and the MSS I2C, all other
pins are just GPIO-s.

Due to this being set completely wrong, the pinctrl was actually
ended up being hardcoded in the board_early_init_f() step so that
SMI would work.

That is obviously not the right thing to do, so convert the register
hex values that were being written to individual pin modes and set it
in the DTS.
Add the SMI pins to the CP1 MDIO node as otherwise CP1 pinctrl does
not get probed without an consumer.

Fixes: 2ae2b8a2 ("arm: mvebu: Initial iEi Puzzle-M801 support")
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-10-08 08:37:55 +02:00
Stefan Roese
cf47a8cf8f arm: mvebu: Select SPL_SKIP_LOWLEVEL_INIT on ARMADA_32BIT
Select SPL_SKIP_LOWLEVEL_INIT on 32bit Armada platforms via Kconfig,
as this was removed from mach/config.h in a2ac2b96 ("Convert
CONFIG_SKIP_LOWLEVEL_INIT et al to Kconfig").

Signed-off-by: Stefan Roese <sr@denx.de>
Fixes: a2ac2b96 ("Convert CONFIG_SKIP_LOWLEVEL_INIT et al to Kconfig")
Cc: Tom Rini <trini@konsulko.com>
Cc: Marek Behún <kabel@kernel.org>
Cc: Pali Rohár <pali@kernel.org>
Tested-by: Pali Rohár <pali@kernel.org>
2021-10-08 08:37:55 +02:00
Pali Rohár
de72930433 arm: mvebu: a38x: serdes: Update comment about PCIE*_ENABLE_* defines
These are part of SOC_CONTROL_REG1 register, not PEX_CAPABILITIES_REG.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-10-08 08:33:52 +02:00
Pali Rohár
28c935b5ee arm: mvebu: a38x: serdes: Remove unused PCIe macros and functions
Remove unused PCIe functions from SerDes code. They are unused and are
duplicated either from generic PCIe code or from pci_mvebu.c.

Remove also unused PCIe macros from SerDes code. They are just obfuscated
variants of standards macros in include/pci.h or in pci_mvebu.c.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-10-08 08:33:52 +02:00
Pali Rohár
177ee6c77e arm: mvebu: a38x: serdes: Don't configure PCIe cards in SerDes init code
This code is trying to parse PCIe config space of PCIe card connected on
the other end of link and then is trying to force 5.0 GT/s speed via Target
Link Speed bits in PCIe Root Port Link Control 2 Register on the local part
of link if it sees that card supports 5.0 GT/s via Max Link Speed bits in
Link Capabilities Register.

The code is incorrect for more reasons:
- Accessing config space of an endpoint card cannot be done immediately.
  If the PCIe link is not up, reading vendor/device ID registers will
  return all ones.
- Parsing is incomplete, so it can cause issues even for working cards.

Moreover there is no need to force speed to 5.0 GT/s via Target Link Speed
bits on PCIe Root Port Link Control 2 Register. Hardware changes speed from
2.5 GT/s to 5.0 GT/s autonomously when it is supported.

Most importantly, this code does not change link speed at all, since
because after updating Target Link Speed bits on PCIe Root Port Link
Control 2 Register, it is required to retrain the link, and the code for
that is completely missing.

The code was probably needed for making buggy endpoint cards work. Such a
workaround, though, should be implemented via PCIe subsystem (via quirks,
for example), as buggy cards could also affect other PCIe controllers.

Note that this code is fully unrelated to a38x SerDes code and really
should not have been included in SerDes initialization. Usage of magic
constants without names and comments made this SerDes code hard to read and
understand.

Remove this PCIe application code from low level SerDes code. As this code
is configuring only 5.0 GT/s part, in the worst case, it could leave buggy
cards at the initial speed of 2.5 GT/s (if somehow before this change they
could have been "upgraded" to 5.0 GT/s speed even with missing link
retraining). Compliant cards which just need longer initialization should
work better after this change.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-10-08 08:33:52 +02:00
Pali Rohár
db5ea818ce arm: mvebu: a38x: serdes: Don't overwrite PCI device ID
PCI device ID is part of the PCIe controller SoC / revision. For Root
Complex mode (which is the default and the only mode supported currently
by U-Boot and Linux kernel), it is PCI device ID of PCIe Root Port device.

If there is some issue with this device ID, it should be set / updated by
PCIe controller driver (pci_mvebu.c), as this register resides in address
space of the controller. It shouldn't be done in SerDes initialization
code.

In the worst case (a specific board for example) it could be done via
U-Boot's weak function board_pex_config().

But it should not be overwritten globally for all A38x devices.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-10-08 08:33:52 +02:00
Pali Rohár
3fc8b90d68 arm: mvebu: a38x: serdes: Don't set PCIe Common Clock Configuration
Enabling Common Clock Configuration bit in PCIe Root Port Link Control
Register should not be done unconditionally. It is enabled by operating
system as part of ASPM. Also after enabling Common Clock Configuration it
is required to do more work, like retraining link. Some cards may be broken
due to this incomplete Common Clock Configuration and some cards are broken
and do not support ASPM at all.

Remove this incomplete code for Common Clock Configuration. It really
should not be done in SerDes code as it is not related to SerDes, but to
PCIe subsystem.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-10-08 08:33:52 +02:00
Pali Rohár
3bedbcc3aa arm: mvebu: a38x: serdes: Don't overwrite read-only SAR PCIe registers
Device/Port Type bits of PCIe Root Port PCI Express Capabilities Register
are read-only SAR registers and are initialized according to current mode
configured by PCIe controller. Changing PCIe controller mode (from Root
Complex mode to Endpoint mode or the other way) is possible via PCI
Express Control Register (offset 0x41A00), bit 1 (ConfRoot Complex). This
has to be done in PCIe controller driver (in our case pci_mvebu.c). Note
that default mode is Root Complex.

Maximum Link Speed bits of PCIe Root Port Link Capabilities Register are
platform specific and overwriting them does not make sense. They are set by
PCIe controller according to current SerDes configuration. For A38x it is
5.0 GT/s if SerDes supports appropriate speed.

Maximum Link Width bits of PCIe Root Port Link Capabilities Register are
read-only SAR registers, but unfortunately if this is not set correctly
here, then access PCI config space of the endpoint card behind this Root
Port does not work.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-10-08 08:33:52 +02:00
Pali Rohár
2d5f51f680 arm: mvebu: a38x: serdes: Add comments for hws_pex_config() code
Add comments to understand what this magic code is doing.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-10-08 08:33:52 +02:00
Pali Rohár
eb5d31645e arm: mvebu: a38x: serdes: Remove duplicate macro SOC_CTRL_REG
SoC Control 1 Register (offset 0x18204) is already defined by macro
SOC_CONTROL_REG1.

Use macro SOC_CONTROL_REG1 instead of macro SOC_CTRL_REG in ctrl_pex.c
code and remove the other definition.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-10-08 08:33:52 +02:00
Pali Rohár
cfd4a8ad0f arm: mvebu: a38x: serdes: Add comments and use macros in PCIe code
Replace magic register offsets by macros to make code more readable.
Add comments about what this code is doing.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-10-08 08:33:52 +02:00
Pali Rohár
646a152247 arm: a37xx: pci: Increase PCIe IO size from 64 KiB to 1 MiB
Commit 079b35a261 ("arm: a37xx: pci: Increase PCIe MEM size from 16 MiB
to 127 MiB") increased size of PCIe MEM to 127 MiB, which is the maximal
possible size for allocated 128 MiB PCIe window. PCIe IO size in that
commit was unchanged.

Armada 3720 PCIe controller supports 32-bit IO space mapping so it is
possible to assign more than 64 KiB if address space for IO.

Currently controller has assigned 127 MiB + 64 KiB memory and therefore
there is 960 KiB of unused memory. So assign it to IO space by increasing
IO window from 64 KiB to 1 MiB.

Signed-off-by: Pali Rohár <pali@kernel.org>
Fixes: 079b35a261 ("arm: a37xx: pci: Increase PCIe MEM size from 16 MiB to 127 MiB")
Reviewed-by: Stefan Roese <sr@denx.de>
2021-10-08 08:33:52 +02:00
Patrick Delaunay
20a3969d33 stv0991: remove specific CONFIG_STV0991 configs
Remove the following STV0991 specific configs:
- CONFIG_STV0991 (never used, only defined in CONFIG_SYS_EXTRA_OPTIONS)
- CONFIG_STV0991_HZ (replaced by generic CONFIG_SYS_HZ)
- CONFIG_STV0991_HZ_CLOCK (replaced by generic CONFIG_SYS_HZ_CLOCK)

This patch allows to reduce the file config_whitelist.txt.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-10-08 08:30:18 +02:00
Tim Harvey
a31de24473 arm64: dts: imx8mm-venice-gw7902: use imx8mm-venice-u-boot.dtsi
Use the common imx8mm-venice-u-boot.dtsi (dtb for the
'DEFAULT_DEVICE_TREE) so that it inherits things like binman.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-10-07 17:45:01 +02:00
Tim Harvey
129c0c57b5 arm64: dts: imx8mm-venice-gw7901: use imx8mm-venice-u-boot.dtsi
Use the common imx8mm-venice-u-boot.dtsi (dtb for the
'DEFAULT_DEVICE_TREE) so that it inherits things like binman.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-10-07 17:45:00 +02:00
Tim Harvey
75c337cf2b arm64: dts: imx8mm-venice-gw700x: use imx8mm-venice-u-boot.dtsi
Use the common imx8mm-venice-u-boot.dtsi (dtb for the
'DEFAULT_DEVICE_TREE) so that it inherits things like binman.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-10-07 17:45:00 +02:00
Peng Fan
68de913c12 imx: makefile: drop the use of imx8mimage.sh
After switch to use binman, no need to use the bash script
to check file exsiting or not. And there is bug that
the script will be executed everytime Makefile is used which is
confusing people.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2021-10-07 17:45:00 +02:00
Frieder Schrempf
9cab87f184 imx: imx8mm: Add support for Kontron Electronics SL/BL i.MX8M-Mini boards (N801x)
The Kontron SoM-Line i.MX8MM (N801x) by Kontron Electronics GmbH is a SoM
module with an i.MX8M-Mini SoC, 1/2/4 GB LPDDR4 RAM, SPI NOR, eMMC and PMIC.

The matching evaluation boards (Board-Line) have 2 Ethernets, USB 2.0, HDMI/LVDS,
SD card, CAN, RS485 and much more.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Tested-by: Heiko Thiery <heiko.thiery@gmail.com>
2021-10-07 17:31:58 +02:00
Tim Harvey
073b105e79 imx: ventana: fix USB hub reset
Remove board_ehci_hcd_init function that is not used with DM_USB
and replace its functionality with device-tree configuraton that treats
USB HUB RST# as a gpio enable for the usbh1 vbus regulator.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-10-07 16:53:50 +02:00
Frieder Schrempf
e6f48aad15 imx: imx6ul: Add support for Kontron Electronics SL/BL i.MX6UL/ULL boards (N63xx/N64xx)
This adds support for i.MX6UL/ULL-based evaluation kits with SoMs by
Kontron Electronics GmbH.

Currently there are the following SoM flavors (SoM-Line):
  * N6310: SOM with i.MX6UL-2, 256MB RAM, 256MB SPI NAND
  * N6311: SOM with i.MX6UL-2, 512MB RAM, 512MB SPI NAND
  * N6411: SOM with i.MX6ULL, 512MB RAM, 512MB SPI NAND

And the according evaluation boards (Board-Line):
  * N6310-S: Baseboard with SOM N6310, eMMC, display (optional), ...
  * N6311-S: Baseboard with SOM N6311, eMMC, display (optional), ...
  * N6411-S: Baseboard with SOM N6411, eMMC, display (optional), ...

Currently U-Boot describes i.MX6UL and i.MX6ULL through separate config
options at compile-time. Though the differences are so minor, that for
the scope of these SoMs we just use a single defconfig that is compatible
with both SoCs.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2021-10-07 16:53:50 +02:00
Oleksandr Suvorov
cdb18048f9 ARM: dts: imx: use generic name bus
Synchronize the u-boot and kernel imx device trees, using tuned
script from commit c0157bdcafa1 ("ARM: dts: imx: use generic name bus")

Per devicetree specification, generic names are recommended to be
used, such as bus.

i.MX AIPS is an AHB - IP bridge bus, so we could use bus as node
name.

Script:
sed -i "s/\<aips@/bus@/" arch/arm/dts/imx*.dtsi
sed -i "s/\<aips@/bus@/" arch/arm/dts/vf*.dtsi
sed -i "s/\<aips-bus@/bus@/" arch/arm/dts/imx*.dtsi
sed -i "s/\<aips-bus@/bus@/" arch/arm/dts/vf*.dtsi

Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2021-10-07 16:53:50 +02:00
Ye Li
64fe0ffca0 mx7ulp: Update wdog disable sequence
Update the mx7ulp wdog disable sequence to avoid potential reset
issue in unlock or refresh sequence. Both sequence need two words
write to wdog CNT register in 16 bus clocks window, if miss the
window, the write will cause violation in wdog and reset the chip.

Current u-boot code is using writel() function which has a DMB
barrier to order the memory access. The DMB between two words write
may introduce some delay in certain circumstance, causing the wdog
reset due to 16 bus clock window requirement.

Also, WDOG1 might have been enabled already depending on FUSE hence
we need to be as close as possible to its reconfiguration timing
requirement of 128 bus clock limit.

This patch replaces writel() function by __raw_writel() to avoid such
issue, and improve to check if watchdog is already disabled or
unlocked.

Signed-off-by: Ye Li <ye.li@nxp.com>
Co-developed-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Co-developed-by: Ricardo Salveti <ricardo@foundries.io>
Signed-off-by: Ricardo Salveti <ricardo@foundries.io>
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
2021-10-07 16:53:50 +02:00
Ricardo Salveti
5089d2fc8e ARM: dts: imx6-apalis: enable watchdog
Add u-boot.dtsi specific to imx6-apalis with a watchdog enabled.

If OP-TEE is loaded by SPL, it may use a watchdog to handle fails of
u-boot running. Enable the watchdog in SPL to use it by OP-TEE.

Signed-off-by: Ricardo Salveti <ricardo@foundries.io>
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Reviewed-by: Igor Opaniuk <igor.opaniuk@foundries.io>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2021-10-07 16:53:50 +02:00
Marek Vasut
af2d3c91d8 ARM: dts: imx8mm-verdin: Set PHY mode to RGMII-ID
Since c6df0e2ffd ("net: phy: micrel: add support for DLL setup on ksz9131")
the Micrel PHY driver correctly configures the delay register. The Verdin PHY
is RGMII-ID, so reflect that in DT, otherwise the ethernet no longer works.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Max Krummenacher <max.krummenacher@toradex.com>
Cc: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
2021-10-07 16:53:50 +02:00
Teresa Remmet
42cef89e86 arm: dts: imx8mp: Generate single bootable binary
binman conversion made flashing flash.bin
and u-boot.itb necessary. Update binman config
to create a single flash.bin image again.

This updates imx8mp_evk and phyCORE-i.MX8MP as they share the
same binman config.

Updated also imx8mp_evk documentation.

Tested on phyCORE-i.MX8MP.

Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
2021-10-07 16:53:50 +02:00
Andrey Zhizhikin
d9a6f0eed6 tree: imx: remove old fit generator script
Since derivatives are moving to binman from usage of the FIT generator
script, and considering the warning introduced in f4a43d2925
("Makefile: Warn against using CONFIG_SPL_FIT_GENERATOR"), usage of FIT
generator is discouraged.

Current FIT generator also generates broken output, since commit
3f04db891a ("image: Check for unit addresses in FITs") prohibits using
'@' for unit addresses but the generator script still emits the old
sematics.

Remove the generator script and corresponding call in Makefile, all
derivatives should be migrated to binman in order to provide binary
images.

Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2021-10-07 16:53:50 +02:00
Fabio Estevam
53a24dee86 imx8mm-cl-iot-gate: Split the defconfigs
Currently imx8mm-cl-iot-gate_defconfig fails to produce a working boot
binary due to the lack of fip.bin:

"  BINMAN  all
Image 'main-section' is missing external blobs and is non-functional: blob-ext

Some images are invalid"

To make the build process more consistent with the other i.MX8M targets,
split the defconfig in two:

- imx8mm-cl-iot-gate_defconfig: standard defconfig that only
requires ATF / DDR firmware.

- imx8mm-cl-iot-gate-optee_defconfig: "more advanced" defconfig that
requires ATF / Optee / mbedtls / DDR firmware.

Signed-off-by: Fabio Estevam <festevam@denx.de>
Tested-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
2021-10-07 16:53:50 +02:00
Ricardo Salveti
88f4f50989 mx7ulp: Allow to enable CONFIG_IMX_HAB
Secure boot support on mx7ulp was added in the
commit 27117b2024 ("mx7ulp: Add HAB boot support").

Allow selecting CONFIG_IMX_HAB for ARCH_IMX7ULP.

Fixes: 27117b2024 ("mx7ulp: Add HAB boot support")
Signed-off-by: Ricardo Salveti <ricardo@foundries.io>
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2021-10-07 16:53:50 +02:00
Ying-Chun Liu (PaulLiu)
5a6af8c19a imx8m: Restrict usable memory based on rom_pointer[0]
When TEE is loaded, we need to restrict the memory usage based
on rom_pointer[0]

Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Frieder Schrempf <frieder.schrempf@kontron.de>
Cc: uboot-imx <uboot-imx@nxp.com>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
2021-10-07 16:53:50 +02:00
Tim Harvey
0cf5622998 arm: dts: imx8mm-venice*: remove thermal zone overrides
Remove the unnecessary thermal zone overrides.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-10-07 16:53:50 +02:00
Tim Harvey
cd7f37666a arm: dts: imx8mm-venice-gw700x: fix mp5416 pmic config
Fix various MP5416 PMIC configurations:
 - Update regulator names per dt-bindings
 - ensure values fit among valid register values
 - add required regulator-max-microamp property
 - add regulator-always-on prop

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
2021-10-07 16:53:50 +02:00
Andrej Rosano
aaac39218d imx53: usbarmory: Add card detect configuration
After the enforcement of DM_MMC the microSD card is not detected. Fix by
correctly configuring the card detect in the devicetree.

Signed-off-by: Andrej Rosano <andrej.rosano@f-secure.com>
2021-10-07 16:53:50 +02:00
Ye Li
ae3f752919 arm: imx8m: Fix pad DSE issue for i.MX8MM/MN/MP
According to 8MM/MN/MP reference manual, their pad registers only have
4 valid DSE values. And DSE2 and DSE4 are different with current
definitions in iomux-v3.h. Fix the issue to align with manual.

Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
2021-10-07 16:53:50 +02:00
Heiko Schocher
deb80ec023 imx: spl: fix imx8m secure boot
cherry-picked from NXP code:
719d665a87c6: ("MLK-20467 imx8m: Fix issue for booting signed image through uuu")

which fixes secure boot on imx8m based boards. Problem was
that FIT header and so IVT header too, was loaded to
memallocated address. So the ivt header address coded
in IVT itself does not fit with the real position.

Signed-off-by: Heiko Schocher <hs@denx.de>
Tested-by: Tim Harvey <tharvey@gateworks.com>
2021-10-07 16:53:50 +02:00
Heiko Schocher
9de3544858 imx: spl: implement spl_load_simple_fit_fix_load
read the address where the IVT header must sit
from IVT image header, loaded from SPL into
an malloced buffer and copy the IVT header
to this address

May make this dependend on SoC ?

Signed-off-by: Heiko Schocher <hs@denx.de>
2021-10-07 16:53:50 +02:00
Tom Rini
7a508a7245 - Add new SoC ID for S905Y2 found in Radxa Zero
- pcie_dw_meson: fix usb fail when pci link fails to go up
 - Sync Amlogic DT from Linux 5.14
 - dwc3-meson-gxl: add AXG compatible
 - dts: keep back HW order for MMC devices since change in Upstream Linux
 - Cleanup local AXG DT USB nodes now everything is upstream
 - distro_bootcmd: run pci enum for scsi_boot just like it is done for nvme_boot
 - New Boards:
   - Odroid-HC4: a variant of Odroid-C4 with 2 SATA ports (via PCIe-SATA bridge)
   - Beelink GS-King X: A variant of the other Beelink board with 2 SATA ports (via USB3-SATA bridge)
   - Banana Pi M5: another credit card SBC
   - JetHub D1/H1: home automation controllers
   - Radxa Zero: another RPi Zero sized SBC
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCgAdFiEEPVPGJshWBf4d9CyLd9zb2sjISdEFAmFe7jcACgkQd9zb2sjI
 SdGrHhAAw2pN+4fzO/NdKa1DdRoZMXidv6nSLfIKHizvdZIoGfQo2c5FfYhDR/mz
 oQeqYpLZZSONXFOd5V2idvlVPHljruV3MTSadiNb5d1Gd41HT7a/tnQ/SOpuWGlh
 Jt146Zli09z55DMkUQGMv94UtCcRkNKjnaibb+ysmU8iqBk2/xstRUGvRwwxUoPv
 hHlEL59VAiHwSNGzu8pUk+EyWOiixD5sNs50YgbXXnErYtVhhXqJCAhkTDGC3c+w
 eU+0wK3g7imruYo9nWRZm13oNC6+HjBceODXwXhUDlP7SN82Q7Q2K9iCgMo3vhNL
 fn6M/EOLqJRa3vVnFL6env7aJ+68iIS1IKEkPjQ0zuyGhDLhQ12zVf+pBFpeaLpC
 ZnYCD1AE1UHlJn7kEWq+lNhXVZYIuDRIPh489YzQM3kv7ctkvsFz53jmv2nxy9a6
 xz3E4Y5pTC8AXZrtxEbP0CKW+33EHFYUpiUVfTNY1tk1y848mRhYBJ9BCjSd+gK1
 NYbjPcM9O/2OnnmvzCwvSijkStCges8Ma3knHmUQFcIi+kGEduyGsLDgB2GTsYdn
 oTIFj0NiiSRS0TVBm6Si4tCo+Mxqv5RPx3Bd6sYC9dERSAou1UrkbX29+yROr+a2
 nYMsXSDPEs51aJx5tZ+CWrB4EY1xQEo5OBEDHL0t5ZZkh8y7Njg=
 =pDip
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-amlogic-20211007' of https://source.denx.de/u-boot/custodians/u-boot-amlogic

- Add new SoC ID for S905Y2 found in Radxa Zero
- pcie_dw_meson: fix usb fail when pci link fails to go up
- Sync Amlogic DT from Linux 5.14
- dwc3-meson-gxl: add AXG compatible
- dts: keep back HW order for MMC devices since change in Upstream Linux
- Cleanup local AXG DT USB nodes now everything is upstream
- distro_bootcmd: run pci enum for scsi_boot just like it is done for nvme_boot
- New Boards:
  - Odroid-HC4: a variant of Odroid-C4 with 2 SATA ports (via PCIe-SATA bridge)
  - Beelink GS-King X: A variant of the other Beelink board with 2 SATA ports (via USB3-SATA bridge)
  - Banana Pi M5: another credit card SBC
  - JetHub D1/H1: home automation controllers
  - Radxa Zero: another RPi Zero sized SBC
2021-10-07 09:02:22 -04:00
Christian Hewitt
b1463cbb54 ARM: dts: add support for Radxa Zero
Import the initial dts queued for Linux 5.16.y

Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-10-07 13:45:35 +02:00
Christian Hewitt
8ee224bfe4 ARM: dts: sort Amlogic Makefile section
Alpha sort the Amlogic dtb list (same as the kernel).

Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-10-07 13:45:35 +02:00
Vyacheslav Bocharov
de19baef68 ARM: amlogic: add JetHub D1/H1 device support
Add support for new home automation devices.

JetHome Jethub D1 (http://jethome.ru/jethub-d1) is a home automation controller with the following features:
- DIN Rail Mounting case
- Amlogic A113X (ARM Cortex-A53) quad-core up to 1.5GHz
- no video out
- 512Mb/1GB DDR3
- 8/16GB eMMC flash
- 1 x USB 2.0
- 1 x 10/100Mbps ethernet
- WiFi / Bluetooth AMPAK AP6255 (Broadcom BCM43455) IEEE 802.11a/b/g/n/ac, Bluetooth 4.2.
- TI CC2538 + CC2592 Zigbee Wireless Module with up to 20dBm output power and Zigbee 3.0 support.
- 2 x gpio LEDS
- GPIO user Button
- 1 x 1-Wire
- 2 x RS-485
- 4 x dry contact digital GPIO inputs
- 3 x relay GPIO outputs
- DC source with a voltage of 9 to 56 V / Passive POE

JetHome Jethub H1 (http://jethome.ru/jethub-h1) is a home automation controller with the following features:
- Square plastic case
- Amlogic S905W (ARM Cortex-A53) quad-core up to 1.5GHz
- no video out
- 1GB DDR3
- 8/16GB eMMC flash
- 2 x USB 2.0
- 1 x 10/100Mbps ethernet
- WiFi / Bluetooth RTL8822CS IEEE 802.11a/b/g/n/ac, Bluetooth 5.0.
- TI CC2538 + CC2592 Zigbee Wireless Module with up to 20dBm output power and Zigbee 3.0 support.
- MicroSD 2.x/3.x/4.x DS/HS cards.
- 1 x gpio LED
- ADC user Button
- DC source 5V microUSB with serial console

Patches from:
- JetHub H1
  https://lore.kernel.org/r/20210915085715.1134940-4-adeep@lexina.in
  https://git.kernel.org/amlogic/c/abfaae24ecf3e7f00508b60fa05e2b6789b8f607
- JetHub D1
  https://lore.kernel.org/r/20210915085715.1134940-5-adeep@lexina.in
  https://git.kernel.org/amlogic/c/8e279fb2903990cc6296ec56b3b80b2f854b6c79

Signed-off-by: Vyacheslav Bocharov <adeep@lexina.in>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
[narmstrong: removed unused variable value]
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-10-07 13:45:35 +02:00
Neil Armstrong
fe8b4c1080 ARM: amlogic: add Banana Pi M5
Banana Pi BPI-M5 is a credit card format SBC with the following features:
- Amlogic S905X3 quad core Cortex-A55
- Mali-G31 GPU
- 4GB LPDDR4
- 16GB eMMC flash
- 4 USB 3.0
- 1 GbE ethernet
- HDMI output
- 2x LEDS
- SDCard
- 2.5mm Jack with Stereo Audio + CVBS
- Infrared Received
- ADC Button
- GPIO Button
- 40 pins header + 3pins debug header

[narmstrong: add missing CONFIG_SYS_LOAD_ADDR from defconfig]
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-10-07 13:45:35 +02:00
Neil Armstrong
2c9269b14b ARM: meson: add Beelink GS-King X board
The Beelink GS-King X is a variant of the GS King boards but with an internal
USB to SATA bridge and advanced audio features.

[narmstrong: add missing CONFIG_SYS_LOAD_ADDR from defconfig]
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-10-07 13:45:32 +02:00
Neil Armstrong
a4b553e31b ARM: amlogic: add support for Odroid-HC4 device
The Odroid-HC4 is a variant of the Odroid-C4 board but with a PCIe-SATA bridge
instead of the USB3 ports.

[narmstrong: add missing CONFIG_SYS_LOAD_ADDR from defconfig]
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-10-07 13:45:28 +02:00
Neil Armstrong
3da675a93b ARM: meson-axg: remove local USB nodes
Drop the local USB nodes after Linux 5.14 sync.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-10-07 10:14:50 +02:00
Neil Armstrong
535dcb55a5 ARM: meson: keep HW order for MMC devices
Since Linux commmit [1], the order is fixed with aliases, in order to keep the
MMC device order, set it back to HW order in U-Boot dtsi files.

[1] ab547c4fb39f ("arm64: dts: amlogic: Assign a fixed index to mmc devices")

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-10-07 10:14:50 +02:00
Neil Armstrong
2e8d47c641 ARM: meson: Sync Amlogic DT from Linux 5.14
Import Amlogic DT changes from Linux commit 7d2a07b76933 ("Linux 5.14"),
dt-bindings clock changes and new meson-g12b-gsking-x.dts,
meson-sm1-bananapi-m5 & odroid-hc4 boards.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-10-07 10:14:50 +02:00
Christian Hewitt
ea36f110f7 ARM: meson: Add S905Y2 SOC ID
Add the SOC ID for the S905Y2 to board info, see below for before/after
tested with a Radxa Zero board:

SoC:   Amlogic Meson G12A (Unknown) Revision 28:b (30:2)
SoC:   Amlogic Meson G12A (S905Y2) Revision 28:b (30:2)

Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-10-07 10:14:50 +02:00
Leo Yu-Chi Liang
1b2b52f294 riscv: ae350: enable Coherence Manager for ae350
If Coherence Manager were not set in the beginning,
u-boot-spl would sometimes fail to boot to u-boot proper.

Enable CM and I/D cache at the same time in harts_early_init

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2021-10-07 16:08:23 +08:00
Heinrich Schuchardt
24ed5317d4 sysreset: provide SBI based sysreset driver
Provide sysreset driver using the SBI system reset extension.

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Samuel Holland <samuel@sholland.org>
2021-10-07 16:08:23 +08:00
Heinrich Schuchardt
3fbcfaa6f3 riscv: add missing SBI extension definitions
Add the System Reset Extension and the Hart State Management Extension
definitions.

Add missing RFENCE Extension enum values.

The SBI 0.1 extension constants are needed for the sbi command. Remove
an #ifdef.

Cf. https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc

Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-10-07 16:08:23 +08:00
Samuel Holland
0d625f400b riscv: Fix setting no-map in reserved memory nodes
The no-map property is wrongly skipped if a no-map reserved memory
node follows one without that property. Fix this by not remembering
the absence of a no-map property across loop iterations.

Fixes: d4ea649f17 ("riscv: Provide a mechanism to fix DT for reserved memory")
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
2021-10-07 16:08:23 +08:00
Tom Rini
53f06134ed Convert CONFIG_NAND_FSL_ELBC et al to Kconfig
This converts the following to Kconfig:
   CONFIG_NAND_FSL_ELBC
   CONFIG_NAND_FSL_IFC

Note that a number of PowerPC platforms had previously enabled
CONFIG_NAND_FSL_ELBC without CONFIG_MTD_RAW_NAND, and now they no longer
enable the option, reducing the size of a few functions.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-06 09:16:24 -04:00
Tom Rini
1cefed1e39 nand.h: Cleanup linux/mtd/rawnand.h usage
We only include <linux/mtd/rawnand.h> in <nand.h> for the forward
declaration of struct nand_chip, so do that directly.  Then, include
<linux/mtd/rawnand.h> where required directly.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-06 09:16:23 -04:00
Tom Rini
9d9f59dd0a Convert CONFIG_SYS_NAND_BAD_BLOCK_POS to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_NAND_BAD_BLOCK_POS

In order to do this, introduce a choice for HAS_LARGE/SMALL_BADBLOCK_POS
as those are the only valid values.  Use LARGE as the default as no
in-tree boards use SMALL, but it is possible.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-06 09:16:23 -04:00
Tom Rini
8db73ec106 Convert CONFIG_SYS_NAND_PAGE_COUNT to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_NAND_PAGE_COUNT

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-06 09:16:23 -04:00
Tom Rini
a0de075392 Convert CONFIG_SPL_NAND_LOAD et al to Kconfig
This converts the following to Kconfig:
   CONFIG_SPL_NAND_LOAD
   CONFIG_SYS_NAND_BLOCK_SIZE
   CONFIG_SYS_NAND_PAGE_SIZE
   CONFIG_SYS_NAND_OOBSIZE

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-06 09:16:23 -04:00
Alexandru Gagniuc
c5b68ef8af arm: imx: mx7: Move CONFIG_OPTEE_TZDRAM_SIZE from lib/optee
This config is only used by three boards with this SOC. Most other
platforms derive this information from devicetree, and are unlikely
to ever need this config.

Moreover, it is confusing when Kconfig asks for this value under
"Support OPTEE images", but does not do anything with the value.
Move it to imx7 for those boards who still make use of it.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2021-10-05 08:50:14 -04:00
Patrick Delaunay
4f53ac2adb tee: add a stub for tee_find_device
Add stub for tee_find_device function when CONFIG_TEE is not activated
to simplify the caller code.

This patch allows to remove the CONFIG_IS_ENABLED(OPTEE) tests
for stm32 platform.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Acked-by: Etienne Carriere <etienne.carriere@inaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
2021-10-05 08:44:48 -04:00
Patrick Delaunay
51827f9a8b lib: optee: remove the duplicate CONFIG_OPTEE
The configuration CONFIG_OPTEE is defined 2 times:
1- in lib/optee/Kconfig for support of OPTEE images loaded by bootm command
2- in drivers/tee/optee/Kconfig for support of OP-TEE driver.

It is abnormal to have the same CONFIG define for 2 purpose;
and it is difficult to managed correctly their dependencies.

Moreover CONFIG_SPL_OPTEE is defined in common/spl/Kconfig
to manage OPTEE image load in SPL.

This definition causes an issue with the macro CONFIG_IS_ENABLED(OPTEE)
to test the availability of the OP-TEE driver.

This patch cleans the configuration dependency with:
- CONFIG_OPTEE_IMAGE (renamed) => support of OP-TEE image in U-Boot
- CONFIG_SPL_OPTEE_IMAGE (renamed) => support of OP-TEE image in SPL
- CONFIG_OPTEE (same) => support of OP-TEE driver in U-Boot
- CONFIG_OPTEE_LIB (new) => support of OP-TEE library

After this patch, the macro have the correct behavior:
- CONFIG_IS_ENABLED(OPTEE_IMAGE) => Load of OP-TEE image is supported
- CONFIG_IS_ENABLED(OPTEE) => OP-TEE driver is supported

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-10-05 08:44:48 -04:00
Jan Kiszka
26fa063c6e iot2050: Enable watchdog support, but do not auto-start it
This allows to use the watchdog in custom scripts but does not enforce
that the OS has to support it as well.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2021-10-03 14:40:56 -04:00
Jan Kiszka
a2db09e269 board: siemens: Add support for SIMATIC IOT2050 devices
This adds support for the IOT2050 Basic and Advanced devices. The Basic
used the dual-core AM6528 GP processor, the Advanced one the AM6548 HS
quad-core version.

Both variants are booted via a Siemens-provided FSBL that runs on the R5
cores. Consequently, U-Boot support is targeting the A53 cores. U-Boot
SPL, ATF and TEE have to reside in SPI flash.

Full integration into a bootable image can be found on
https://github.com/siemens/meta-iot2050

Based on original board support by Le Jin, Gao Nian and Chao Zeng.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2021-10-03 14:40:56 -04:00
Jan Kiszka
c3a879510a arm: dts: Add IOT2050 device tree files
Prepares for the addition of the IOT2050 board which is based on the TI
AM65x. The board comes in four variants, Basic and Advanced, each as
product generation 1 (SR1.0) and 2 (SR2.x), so there are separate dts
files needed. Furthermore, the SPL has its own device tree.

Based on original board support by Le Jin, Gao Nian and Chao Zeng.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2021-10-03 14:40:56 -04:00
Chia-Wei Wang
8e1ebdcfd7 ARM: dts: ast2600: Make WDT by default disabled
The WDT devices described in the general .dtsi file
should be marked as "disabled" by default.

A WDT should be then enabled in the board specific
.dts file on demands.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
2021-10-03 11:59:22 -04:00
Tom Rini
fa09b12dc5 arm: ti: k3: Resync dts files and bindings with Linux Kernel v5.14
This resyncs the dts files for all of the currently in-tree K3
platforms, along with relevant bindings, with the v5.14 Linux Kernel
release.  Of note are that the main-navss/mcu-navss nodes were renamed
to main_navss / mcu_navss and so the u-boot.dtsi files needed to be
updated to match.

Tested on j721e_evm and am65x_evm.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-03 11:59:22 -04:00
Tom Rini
fae2ea5951 ppc: Remove MPC8349EMDS board and ARCH_MPC8349 support
This board has not been converted to CONFIG_DM by the deadline.
Remove it.

Cc: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-01 21:08:19 -04:00
Tom Rini
4987658be5 arm: Remove bg0900 board
This board has not been converted to CONFIG_DM by the deadline.
Remove it.

Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-01 21:08:19 -04:00
Tom Rini
8ba59608dc arm: Remove zmx25 board and ARCH_MX25
This board has not been converted to CONFIG_DM by the deadline.
Remove it.  As this is the last ARCH_MX25 platform, remove those
references as well.

Cc: Matthias Weisser <weisserm@arcor.de>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-01 21:08:18 -04:00
Tom Rini
d9be8606bb arm: Remove aspenite board
This board has not been converted to CONFIG_DM by the deadline.
Remove it.  As this is the last armada100 platform, remove that support
as well.

Cc: Prafulla Wadaskar <prafulla@marvell.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-10-01 12:10:09 -04:00
Tom Rini
14b38cb0c2 arm: Remove flea3 board
This board has not been converted to CONFIG_DM by the deadline.
Remove it.  As this is the last mx35 platform, remove that support as
well.

Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Stefano Babic <sbabic@denx.de>
2021-10-01 12:08:19 -04:00
Tom Rini
8bef036836 Xilinx changes for v2022.01-rc1
zynq:
 - Enable capsule update for qspi and mmc
 - Update zed DT qspi compatible string
 
 zynqmp:
 - Add missing modeboot for EMMC
 - Add missing nand DT properties
 - List all eeproms for SC on vck190
 - Add vck190 SC psu_init
 
 clk:
 - Handle only GATE type clock for Versal
 
 watchdog:
 - Update versal driver to handle system reset
 -----BEGIN PGP SIGNATURE-----
 
 iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCYVWWZgAKCRDKSWXLKUoM
 IY3MAJ43Mlut5tK9gv45bp4HpyVOMuSvJwCfTiVr7ZxrBE8I8QC5+zHzBTmuM6g=
 =aQtT
 -----END PGP SIGNATURE-----

Merge tag 'xilinx-for-v2022.01-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next

Xilinx changes for v2022.01-rc1

zynq:
- Enable capsule update for qspi and mmc
- Update zed DT qspi compatible string

zynqmp:
- Add missing modeboot for EMMC
- Add missing nand DT properties
- List all eeproms for SC on vck190
- Add vck190 SC psu_init

clk:
- Handle only GATE type clock for Versal

watchdog:
- Update versal driver to handle system reset
2021-09-30 11:29:41 -04:00
Wolfgang Denk
0cf207ec01 WS cleanup: remove SPACE(s) followed by TAB
Signed-off-by: Wolfgang Denk <wd@denx.de>
2021-09-30 09:08:16 -04:00
Wolfgang Denk
0a50b3c97b WS cleanup: remove trailing white space
Signed-off-by: Wolfgang Denk <wd@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-09-30 08:08:56 -04:00
Wolfgang Denk
c72231d272 WS cleanup: remove excessive empty lines
Signed-off-by: Wolfgang Denk <wd@denx.de>
2021-09-30 08:08:56 -04:00
Wolfgang Denk
66356b4c06 WS cleanup: remove trailing empty lines
Signed-off-by: Wolfgang Denk <wd@denx.de>
2021-09-30 08:08:56 -04:00
Michal Simek
876b854a22 arm64: zynqmp: Define all eeproms for SC on vck190
There are multiple eeproms on vck190 that's why list all of them.
FMC eeproms are present only when fmcs are plugged.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/96902661e3ab9e20b59d626e6129ccf6f3317c4d.1632488695.git.michal.simek@xilinx.com
2021-09-30 12:29:49 +02:00
Michal Simek
3482ed6faf arm: zynq: Use s25fl256s1 compatible string on zedboard
Use compatible string which is listed in the Linux kernel.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/49bc6b056b0f6f69d4d90351dc875a66b7e37619.1631715748.git.michal.simek@xilinx.com
2021-09-30 12:29:08 +02:00
Amit Kumar Mahapatra
1a94d0554d arm64: zynqmp: Add device tree properties for nand flash
Add ecc strength & ecc step size properties for nand flash devices,
when operating in software-ecc mode.

Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Link: https://lore.kernel.org/r/866f4b888129ff0213df9cdb51b5529b199fb7b7.1631713594.git.michal.simek@xilinx.com
2021-09-30 12:28:34 +02:00
Tom Rini
67ae289723 - fix usb stopt; usb start; bug
- update Nicolas email address
 -----BEGIN PGP SIGNATURE-----
 
 iQJGBAABCAAwFiEEUdvKHhzqrUYPB/u8L21+TfbCqH4FAmFUbkgSHG1icnVnZ2Vy
 QHN1c2UuY29tAAoJEC9tfk32wqh+jWUQAIkce5475TgqcnrYfFzqnLrQwnocnsD4
 Z0mjq7gWrkt+dOy2whxY5ETXXqAJEqVdHYc5AJpmFWfgWlSryW+WVMbOCig8g5ce
 M2lXzWkGUufVlW8OBXYtSAAF6PWsFcPFgtY4XCFZYBpDbYaxOF6TeLTl9I3KsOGT
 tZk4rRkDFe0DpA5+aR2IDSK1w68QvobhSQgMPvQpH0r93qVkwDZBvpS0zK1ZvTrS
 T+UoJ3t2pR+Idj8bv/XneIfFdA7iO2vdq8AIIqndLNDHa0Xc5LboBSWjGk7QHmNn
 qmhbmCUkEdIEUZT1rGshXqXJmPw8/0UU40TfbcuvFBmBE99g0WJ+JK1yh8cEwFBM
 5efpmuwUFADRJyL5xhHmUh+h4ToG8kM/2LI2dhk42ce4Bb+sOFkgpnhdl+TbSjWy
 ysYD0BsynED+pBJN6NwoJnDXvPBEhJM5VOKCCOfh9GPLjPJTEZJM+0x11R+3Y9pc
 FxoInmgdh2I31AugPtq5jmMSkJRU5Z7hto6yotEG4WSc1F2BWPkyNzEiS28Wif3H
 3EFW3h68RtEbR+FmdFtEw9vaOWn1d8Noxn2rK9EC7lfF+YezUZCDHFg96lh6RlUk
 JLIYk8bO1nHOIGZCkBcHpvRrMlpI0X98cEj8RIW7S+rcPtFoHIZfFqESenBSIRse
 kqPpXzL3UlhL
 =yTvU
 -----END PGP SIGNATURE-----

Merge tag 'rpi-next-2021.10.2' of https://source.denx.de/u-boot/custodians/u-boot-raspberrypi

- fix usb stopt; usb start; bug
- update Nicolas email address
2021-09-29 15:13:35 -04:00
Marek Szyprowski
33166054c7 arm: rpi: perform XHCI firmware upload only once
XHCI firmware upload must be performed only once after initializing the
PCI bridge. This fixes USB stack initialization after calling "usb stop;
usb start" on Raspberry Pi 4B.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Nicolas Saenz Julienne <nsaenz@kernel.org>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2021-09-29 15:44:16 +02:00
Tom Rini
6eecaf5d0f Merge branch 'network_master' of https://source.denx.de/u-boot/custodians/u-boot-net into next
- Fix some non-NULL terminated strings in the networking subsystem
- net: tsec: Mark tsec_get_interface as __maybe_unused
2021-09-29 07:58:20 -04:00
Robert Marko
65513f3c18 arm: dts: armada8040: Fix CP0 eMMC/SDIO support
During the migration to a single DTSI for the CP110-s specific pinctrl
compatibles were moved to the SoC DTSI as CP0 and CP1 have some specifics.
Namely, CP0 eMMC/SDIO support depends on the mvebu-pinctrl driver setting
the BIT(0) in eMMC PHY IO Control 0 Register to 0 in order for the connect
the eMMC/SDIO PHY to the controller and not use it as a MPP pin multiplexor.

So, the mvebu-pinctrl driver check specifically for the
"marvell,armada-8k-cpm-pinctrl" compatible to clear the that bit.

Issue is that compatibles in the 8040 DTSI were set to "marvell,8k-cpm-pinctrl"
for CP0 and "marvell,8k-cps-pinctrl" for the CP1.
This is obviously incorrect as the pinctrl driver does not know about these.

So fix the regression by applying correct compatibles to the DTSI.
Regression found and tested on the Puzzle M801 board.

Fixes: a0ba97e5 ("arm: armada: dts: Use a single dtsi for cp110 die description")
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-09-29 07:13:27 +02:00
Rasmus Villemoes
24ea366add imx: imx7d-sdb: fix ethernet, sync .dts with linux
Commit 0d52bab46 (mx7dsabre: Enable DM_ETH) changed these flags from 0
(aka GPIO_ACTIVE_HIGH) to GPIO_ACTIVE_LOW. It claimed to "Also sync
device tree with v5.5-rc1", but in the linux tree, these gpios have
always been GPIO_ACTIVE_HIGH ever since this node was introduced
around v4.13 (linux commit 184f39b5).

I'm guessing that the reason for the GPIO_ACTIVE_LOW was to work
around the behaviour of the soft-spi driver back then, which
effectively defaulted to spi-mode 3 and not 0. That was arguably a bug
in the soft-spi driver, which then got fixed in 0e146993bb (spi: add
support for all spi modes with soft spi), but that commit then broke
ethernet on this board.

Fix it by setting the gpios as active high, which as a bonus actually
brings us in sync with the .dts in the linux source tree.

Without this, one gets

    Net:   Could not get PHY for FEC0: addr 0
    No ethernet found.

With this, ethernet (at least ping and tftp) works as expected from
the U-Boot shell.

Cc: Fabio Estevam <festevam@gmail.com>
Cc: Joris Offouga <offougajoris@gmail.com>
Cc: "Christian Bräuner Sørensen" <yocto@bsorensen.net>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2021-09-28 12:03:21 -04:00
Vladimir Oltean
19ef59f1e0 arch: powerpc: mpc85xx: free MDIO bus if mdio_register fails
If mdio_register fails, it is nice to not leave behind dangling
allocated memory.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-09-28 18:50:57 +03:00
Vladimir Oltean
fca315a382 arch: powerpc: mpc85xx: ensure mdiodev->name is NULL terminated after MDIO_NAME_LEN truncation
strncpy() simply bails out when copying a source string whose size
exceeds the destination string size, potentially leaving the destination
string unterminated.

One possible way to address is to pass MDIO_NAME_LEN - 1 and a
previously zero-initialized destination string, but this is more
difficult to maintain.

The chosen alternative is to use strlcpy(), which properly limits the
copy len in the (srclen >= size) case to "size - 1", and which is also
more efficient than the strncpy() byte-by-byte implementation by using
memcpy. The destination string returned by strlcpy() is always NULL
terminated.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-09-28 18:50:56 +03:00
Vladimir Oltean
7c2d5d1642 net: freescale: replace usage of phy-mode = "sgmii-2500" with "2500base-x"
After the discussion here:
https://lore.kernel.org/netdev/20210603143453.if7hgifupx5k433b@pali/

which resulted in this patch:
https://patchwork.kernel.org/project/netdevbpf/patch/20210704134325.24842-1-pali@kernel.org/

and many other discussions before it, notably:
https://patchwork.kernel.org/project/linux-arm-kernel/patch/1512016235-15909-1-git-send-email-Bhaskar.Upadhaya@nxp.com/

it became apparent that nobody really knows what "SGMII 2500" is.
Certainly, Freescale/NXP hardware engineers name this protocol
"SGMII 2500" in the reference manuals, but the PCS devices do not
support any "SGMII" specific features when operating at the speed of
2500 Mbps, no in-band autoneg and no speed change via symbol replication
. So that leaves a fixed speed of 2500 Mbps using a coding of 8b/10b
with a SERDES lane frequency of 3.125 GHz. In fact, "SGMII 2500 without
in-band autoneg and at a fixed speed" is indistinguishable from
"2500base-x without in-band autoneg", which is precisely what these NXP
devices support.

So it just appears that "SGMII 2500" is an unclear name with no clear
definition that stuck.

As such, in the Linux kernel, the drivers which use this SERDES protocol
use the 2500base-x phy-mode.

This patch converts U-Boot to use 2500base-x too, or at least, as much
as it can.

Note that I would have really liked to delete PHY_INTERFACE_MODE_SGMII_2500
completely, but the mvpp2 driver seems to even distinguish between SGMII
2500 and 2500base-X. Namely, it enables in-band autoneg for one but not
the other, and forces flow control for one but not the other. This goes
back to the idea that maybe 2500base-X is a fiber protocol and SGMII-2500
is an MII protocol (connects a MAC to a PHY such as Aquantia), but the
two are practically indistinguishable through everything except use case.

NXP devices can support both use cases through an identical configuration,
for example RX flow control can be unconditionally enabled in order to
support rate adaptation performed by an Aquantia PHY. At least I can
find no indication in online documents published by Cisco which would
point towards "SGMII-2500" being an actual standard with an actual
definition, so I cannot say "yes, NXP devices support it".

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-09-28 18:50:56 +03:00
Vladimir Oltean
77b11f7604 net: replace the "xfi" phy-mode with "10gbase-r"
As part of the effort of making U-Boot work with the same device tree as
Linux, there is an issue with the "xfi" phy-mode. To be precise, in
Linux there was a discussion (for those who have time to read:
https://lore.kernel.org/netdev/1576768881-24971-2-git-send-email-madalin.bucur@oss.nxp.com/)

which led to a patch:
https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git/commit/?id=c114574ebfdf42f826776f717c8056a00fa94881

TL;DR: "xfi" was standardized in Linux as "10gbase-r".

This patch changes the relevant occurrences in U-Boot to use "10gbase-r"
instead of "xfi" wherever applicable.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-09-28 18:50:56 +03:00
Vladimir Oltean
66fd01fe59 net: update NXP copyright text
NXP Legal insists that the following are not fine:

- Saying "NXP Semiconductors" instead of "NXP", since the company's
  registered name is "NXP"

- Putting a "(c)" sign in the copyright string

- Putting a comma in the copyright string

The only accepted copyright string format is "Copyright <year-range> NXP".

This patch changes the copyright headers in the networking files that
were sent by me, or derived from code sent by me.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-09-28 18:50:56 +03:00
Marek Vasut
4a60d3571b arm: socfpga: vining: Fix UDC controller phandle in DT
The USB peripheral controller is the DWC2 controller 1, not 0.
Update the phandle to fix UDC support on this board.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
2021-09-28 18:50:55 +03:00
Marek Vasut
4527568e3f arm: socfpga: vining: Un-disable WDT in DT
The WDT on this system should be enabled, make it so.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
2021-09-28 18:50:55 +03:00
Andy Shevchenko
5501fadb45 x86: tangier: acpi: Add GPIO card detection to SDHCI #2
On Intel Tangier the SDHCI #2 provides SD card connection.
Add GPIO card detection for it.

Fixes: 39665beed6 ("x86: tangier: Enable ACPI support for Intel Tangier")
BugLink: https://github.com/edison-fw/meta-intel-edison/issues/135
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
2021-09-28 18:50:55 +03:00
Andy Shevchenko
2f025b96bc x86: edison: Mark eMMC non-removable
eMMC is non-removable on Intel Edison board. Fix the DTS accordingly.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-09-28 18:50:54 +03:00
Tom Rini
4b62ba8fa2 ti: keystone: Migrate CONFIG_SOC_K2* to Kconfig
Move the individual keystone 2 SoC symbols to the mach Kconfig file,
select them as needed.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-27 21:38:34 -04:00
Tom Rini
f899cc1432 ti: keystone: Move away from CONFIG_SOC_KEYSTONE
We have individual SOC symbols for each keystone 2 platform.  Use the
existing CONFIG_ARCH_KEYSTONE rather than CONFIG_SOC_KEYSTONE to
encompass all of the keystone families.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-27 21:38:34 -04:00
Tom Rini
1d1f98c8ee Various of-platdata improvements, including CONFIG_OF_REAL
-----BEGIN PGP SIGNATURE-----
 
 iQFFBAABCgAvFiEEslwAIq+Gp8wWVbYnfxc6PpAIreYFAmFR2fMRHHNqZ0BjaHJv
 bWl1bS5vcmcACgkQfxc6PpAIreaAnAf/ZKPy3CRphbgAmbLhNQhQGpLosLcFp343
 cv53gfsv1DakLRrhqMSnOQSVoTg9P22uHbooDDR9WHfZyEL6tvGZ+dgN2/wlDhDj
 wbvvsM7FB+uvLVfMF3MURQBvy4dPO+FyCm/uHmry2V2uqWPw4ss+aVhxeQ5s4/oI
 LpS6yaiM8UAj2GTUZSqJ1+/W7YG9N6tL73n0PDyCvSrdCkyPWqpww1rtST88SfFI
 bBEWc6ksna/29haOwHQ2xopEbVxtHv2byULfqUtnsbtE4Ozw8o0fx66tdwPHTQlM
 7eSuRiEbqjlJuUZFIbMat7nb7inZkaWupZ/Sr1HUUiDdKMygrRsQhg==
 =x8Uf
 -----END PGP SIGNATURE-----

Merge tag 'dm-pull-next-27sep21' of https://source.denx.de/u-boot/custodians/u-boot-dm into next

Various of-platdata improvements, including CONFIG_OF_REAL
2021-09-27 11:09:23 -04:00
Tom Rini
e908d20fcb Prepare v2021.10-rc5
-----BEGIN PGP SIGNATURE-----
 
 iQGzBAABCgAdFiEEGjx/cOCPqxcHgJu/FHw5/5Y0tywFAmFRyIMACgkQFHw5/5Y0
 tyz1jgv/aTtHWVcGiw+nvvnnlgdrY4h9yVP5AfBLhOR7ogYOw2B9xHmdh+9oCas9
 Rt45AC4nFvUszxCPJqg36kjljTKRVapemHqhCbgGGeb9GYMkNb1zjk79WnuqgeJy
 ydBUCh1NQI5pOvrpDv7kWRx1IyDi/gUgQO3RBdufbunNmn4Zj4jlw5RmMTgDACRC
 cvTr39gVQq1LOzL2W7+XkSfiEejtGERNs32Nt+jzyAm5a2PkngULUnPW6WsHu+qy
 5YJTR50TK55QgPIdoiqY14BUDpqEbHlNKsE7p6hHkDf6XSS7gLHYW2tVVt2Z8ocg
 9cW35Qotov7MeiSClc3SIEPiIefwh2oTVf0uYoP+uvlRAComvcIzphq68NIQe6Av
 es+ZJI1Qx5ERvDQMMW3xOHTlcBGgpqA0Y/QVr62rE8bEzK/1gvTiP+hVVqzUrnHJ
 f3ZAVt16clIfXKAxGsW4Am05iMmT+rtcS5IrUMuEzmkb0KK58YXsOVmsKHLX9aI1
 T74ewXfu
 =y67Q
 -----END PGP SIGNATURE-----

Merge tag 'v2021.10-rc5' into next

Prepare v2021.10-rc5
2021-09-27 09:45:36 -04:00
Heinrich Schuchardt
8ae8da10b3 sandbox: correct cpu nodes
The cpu nodes in arch/sandbox/dts/test.dts should conform to the devicetree
specification:

* property device_type must be set to "cpu"
* the reg property must be provided
* the cpu nodes must have an address

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2021-09-25 09:46:15 -06:00
Simon Glass
48609d0789 dm: gpio: Add of-platdata support
Add support for accessing GPIOs using of-plata. This uses the same
mechanism as for clocks, but allows use of the xlate() method so that
the driver can interpret the parameters.

Update the condition for GPIO_HOG so that it is not built into SPL,
since it needs SPL_OF_REAL which is not enabled in sandbox_spl.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-25 09:46:15 -06:00
Simon Glass
3e57ad907c irq: Tidy up of-platdata irq support
This function is available but not exported. More generally it does not
really work as intended.

Reimplement it and add a sandbox test too.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-25 09:46:15 -06:00
Simon Glass
dcfc42b12f treewide: Try to avoid the preprocessor with OF_REAL
Convert some of these occurences to C code, where it is easy to do. This
should help encourage this approach to be used in new code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-25 09:46:15 -06:00
Simon Glass
9539738509 treewide: Use OF_REAL instead of !OF_PLATDATA
Now that we have a 'positive' Kconfig option, use this instead of the
negative one, which is harder to understand.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-25 09:46:15 -06:00
Simon Glass
414cc15144 treewide: Simply conditions with the new OF_REAL
Use this new Kconfig to simplify the compilation conditions where
appropriate.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-25 09:46:15 -06:00
Simon Glass
7de8bd03c3 treewide: fdt: Move fdt_get_config_... to ofnode_conf_read...
The current API is outdated as it requires a devicetree pointer.

Move these functions to use the ofnode API and update this globally. Add
some tests while we are here.

Correct the call in exynos_dsim_config_parse_dt() which is obviously
wrong.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-25 09:46:15 -06:00
Kristian Amlie
15e30106ce ARM: vexpress_ca9x4: Reintroduce board in order to use with QEMU.
vexpress_ca9x4 is seemingly the only board except for qemu_arm which
is able to run U-Boot correctly, using the `-M vexpress-a9` option to
QEMU. Building for qemu_arm and running qemu-system-arm with the `-M
virt` argument has a number of downsides, most importantly that it
only supports virtio storage drivers. This significantly reduces its
usefulness in testing memory card and Flash solutions, especially when
the tested images are from a third party source.

So therefore we reintroduce the vexpress_ca9x4 board in this commit,
with the explicit goal of using it with QEMU.

A number of differences to note from the original:

* Since the board was apparently unmaintained, I have now set myself
  as the maintainer.

* The board has been converted to use the driver model, which was the
  reason it was removed in the first place.

* The vexpress_ca15_tc2 and vexpress_ca5x2 boards, which were removed
  in the same commit, are not necessary for the QEMU use case, and
  have been omitted.

* An `mmc0` alias was introduced in the dts file. The mmc is not
  detected correctly without this, now that it's based on the device
  tree instead of the board's init function.

* A couple of other nodes were removed because they were problematic
  when trying to run the UEFI bootmgr. Once again, the primary use
  case here is QEMU, and these nodes are not needed for that to work.

* Unnecessary board init code has been removed, thanks to driver model
  and device tree.

* `CONFIG_OF_EMBED` has been enabled. I know this goes against
  recommended practice, but there doesn't seem to be any other way to
  pass the dtb to U-Boot in the QEMU scenario. Using the -dtb argument
  does not work, I suppose because U-Boot doesn't use the same
  mechanics as the kernel when it's booting.

* Load addresses have been changed to fit QEMU use case.

People wanting to get a more detailed, yet somewhat isolated, diff
between this and the original, can run this command:

  git diff c6c26a05b89f25a06e7562f8c2071b60fd0c9eac~1 -- \
      $( git diff-tree --diff-filter=A -r --name-only HEAD~1 HEAD)

(Make sure to either check out this commit first, or replace HEAD with
the commit ID of this commit)

Signed-off-by: Kristian Amlie <kristian.amlie@northern.tech>
2021-09-24 14:30:46 -04:00
Patrick Delaunay
6493fa4c3d arm: use CONFIG_SUPPORT_PASSING_ATAGS
Simplify the bootm and the spl code by using the new config
CONFIG_SUPPORT_PASSING_ATAGS.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2021-09-24 14:30:46 -04:00
Stefan Roese
4e062fc955 arm64: Kconfig: Enable usage of optimized memset/memcpy/memmove
This patch enables the use of the optimized memset(), memmove() &
memcpy() versions recently added on ARM64.

Please note that these optimized functions are now only enabled for
recent GCC versions (>= 9.4), as earlier GCC versions throw these
errors:

aarch64-linux-ar: warning: arch/arm/lib/memset-arm64.o: unsupported GNU_PROPERTY_TYPE (5) type: 0xc0000000
...

Signed-off-by: Stefan Roese <sr@denx.de>
[trini: Make this default to off as it causes problems on some platforms still]
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-24 07:49:16 -04:00
Stefan Roese
1e43bb6732 arm64: memset-arm64: Use simple memset when cache is disabled
The optimized memset uses the dc opcode, which causes problems when the
cache is disabled. This patch adds a check if the cache is disabled and
uses a very simple memset implementation in this case. Otherwise the
optimized version is used.

Signed-off-by: Stefan Roese <sr@denx.de>
2021-09-24 07:48:06 -04:00
Stefan Roese
dbf6b14e0a arm64: arch/arm/lib: Add optimized memset/memcpy/memmove functions
Ported from https://github.com/ARM-software/optimized-routines

These files are included from this repository, including the latest
git commit ID:
string/aarch64/memcpy.S: afd6244a1f8d
string/aarch64/memset.S: e823e3abf5f8
string/asmdefs.h: e823e3abf5f8

Note that memmove is also handled by the memcpy function.

Please note that when adding these optimized functions as default memset
memcpy functions in U-Boot, U-Boot fails to boot on the LX2160ARDB.
After the initial ATF output, no U-Boot output is shown on the serial
console. Some exception is triggered here in the very early boot process
as some of the assembler opcodes need the caches to be enabled.

Because of this, a follow-up patch will add a check to use a simple
non-optimized memset for the "cache disabled" case.

Note:
I also integrated and tested with the Linux versions of these optimized
functions. They are similar to the ones now integrated but these ARM
versions are still a small bit faster.

Signed-off-by: Stefan Roese <sr@denx.de>
2021-09-24 07:48:06 -04:00
Guillaume La Roque
df3ab898f6 arm: mediatek: merge board Kconfigs into mach-mediatek
On MediaTek boards we cannot override the SYS_BOARD / SYS_CONFIG_NAME
variables from defconfig.
This is because in board/mediatek/mtXXXX/Kconfig this value was override
by default due to the if CONFIG_TARGET_MTXXXX condition.

Merge all the Kconfigs to the mach-medatek/Kconfig.

This way:
- we only define SYS_{SOC,VENDOR} once
- all board definitions are in a single place, simplifying the build logic.

Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
2021-09-23 14:15:32 -04:00
Marek Vasut
a69753f31d lmb: x86: Add arch_lmb_reserve()
Add arch_lmb_reserve() implemented using arch_lmb_reserve_generic().
It is rather likely this architecture also needs to cover U-Boot with
LMB before booting Linux.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
2021-09-23 14:15:32 -04:00
Marek Vasut
7996b7e9f5 lmb: xtensa: Add arch_lmb_reserve()
Add arch_lmb_reserve() implemented using arch_lmb_reserve_generic().
It is rather likely this architecture also needs to cover U-Boot with
LMB before booting Linux.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Zankel <chris@zankel.net>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
2021-09-23 14:15:32 -04:00
Marek Vasut
1e0e557774 lmb: sh: Add arch_lmb_reserve()
Add arch_lmb_reserve() implemented using arch_lmb_reserve_generic().
This architecture also needs to cover U-Boot with LMB before booting
Linux.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
2021-09-23 14:15:32 -04:00
Marek Vasut
eeaa3fe652 lmb: riscv: Add arch_lmb_reserve()
Add arch_lmb_reserve() implemented using arch_lmb_reserve_generic().
It is rather likely this architecture also needs to cover U-Boot with
LMB before booting Linux.

Reviewed-by: Rick Chen <rick@andestech.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Atish Patra <atish.patra@wdc.com>
Cc: Leo <ycliang@andestech.com>
Cc: Rick Chen <rick@andestech.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
2021-09-23 14:15:32 -04:00
Marek Vasut
6a0890a61e lmb: nds32: Add arch_lmb_reserve()
Add arch_lmb_reserve() implemented using arch_lmb_reserve_generic().
It is rather likely this architecture also needs to cover U-Boot with
LMB before booting Linux.

Reviewed-by: Rick Chen <rick@andestech.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Rick Chen <rick@andestech.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
2021-09-23 14:15:32 -04:00
Marek Vasut
a02c18f31f lmb: nios2: Add arch_lmb_reserve()
Add arch_lmb_reserve() implemented using arch_lmb_reserve_generic().
It is rather likely this architecture also needs to cover U-Boot with
LMB before booting Linux.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Thomas Chou <thomas@wytron.com.tw>
Cc: Tom Rini <trini@konsulko.com>
2021-09-23 14:15:32 -04:00
Marek Vasut
c16de86ec0 lmb: Remove imx board_lmb_reserve()
This function is clearly architecture specific code, not board specific
code. The only difference from the previous arm arch_lmb_reserve() is the
extra reservation of 16k of memory below the stack bottom, rather than
the 4k. The common code now also uses 16k alignment. Remove this custom
implementation, as it now behaves exactly as the common code.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Alexey Brodkin <alexey.brodkin@synopsys.com>
Cc: Angelo Dureghello <angelo@sysam.it>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Cc: Hai Pham <hai.pham.ud@renesas.com>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Ye Li <ye.li@nxp.com>
2021-09-23 14:15:32 -04:00
Marek Vasut
b1d0487cfe lmb: arm: Increase LMB alignment to 16k in arch_lmb_reserve_generic()
According to input NXP, the 4k alignment is not always sufficient.
Currently iMX works around this problem by implementing board specific
LMB reservation, however it is likely this could also occur on other
systems. Increase the LMB reservation alignment to 16k by default.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Alexey Brodkin <alexey.brodkin@synopsys.com>
Cc: Angelo Dureghello <angelo@sysam.it>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Cc: Hai Pham <hai.pham.ud@renesas.com>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2021-09-23 14:15:32 -04:00
Marek Vasut
1f391c3454 lmb: Switch to generic arch_lmb_reserve_generic()
Switch arc/arm/m68k/microblaze/mips/ppc arch_lmb_reserve() to
arch_lmb_reserve_generic().

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Alexey Brodkin <alexey.brodkin@synopsys.com>
Cc: Angelo Dureghello <angelo@sysam.it>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Cc: Hai Pham <hai.pham.ud@renesas.com>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Wolfgang Denk <wd@denx.de>
2021-09-23 14:15:32 -04:00
Marek Vasut
cfa1971977 lmb: Always compile arch_lmb_reserve() into U-Boot on arc
The arch_lmb_reserve() is called by lib/lmb.c lmb_reserve_common() even
if CMD_BOOTM is not enabled. However, the arc variant of arch_lmb_reserve()
is only compiled in if CMD_BOOTM is enabled.

This currently does not trigger build error, because there is an empty
weak implementation of arch_lmb_reserve(), however that is not the
function that should be used on arc.

Fix this by moving the arch_lmb_reserve() implementation into common
code and always compile it in.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
2021-09-23 14:15:32 -04:00
Marek Vasut
8120e0681c lmb: Always compile arch_lmb_reserve() into U-Boot on arm
The arch_lmb_reserve() is called by lib/lmb.c lmb_reserve_common() even
if CMD_BOOT{I,M,Z} is not enabled. However, the arm32/arm64 variant of
arch_lmb_reserve() is only compiled in if CMD_BOOT{I,M,Z} is enabled.

This currently does not trigger build error, because there is an empty
weak implementation of arch_lmb_reserve(), however that is not the
function that should be used on arm32/arm64.

Fix this by moving the arch_lmb_reserve() implementation into common
code and always compile it in.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tom Rini <trini@konsulko.com>
2021-09-23 14:15:32 -04:00
Marek Vasut
270f8710f9 crc32: Add crc32 implementation using __builtin_aarch64_crc32b
ARMv8.0 has optional crc32 instruction for crc32 calculation. The
instruction is mandatory since ARMv8.1. The crc32 calculation is
faster using the dedicated instruction, e.g. 1.4 GHz iMX8MN gives:

  => time crc32 0x50000000 0x2000000
  time: 0.126 seconds # crc32 instruction
  time: 0.213 seconds # software crc32

Add implementation using the compiler builtin wrapper for the crc32
instruction and enable it by default, since we don't support any
platforms which do not implement this instruction.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
[trini: Make crc32_table guarded by CONFIG_ARM64_CRC32]
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-23 14:15:32 -04:00
Pierre-Clément Tosi
37479e65a3 armv8/cache.S: Triple with single instruction
Replace the current 2-instruction 2-step tripling code by a
corresponding single instruction leveraging ARMv8-A's "flexible second
operand as a register with optional shift". This has the added benefit
(albeit arguably negligible) of reducing the final code size.

Fix the comment as the tripled cache level is placed in x12, not x0.

Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
2021-09-23 08:55:06 -04:00
Pierre-Clément Tosi
f050bfacc5 armv8/cache.S: Read sysreg fields through ubfx
Improve the file's readability and conciseness by using the appropriate
Aarch64 instruction: ubfx (unsigned bitfield extract). This makes the
code easier to follow as it directly manipulates the offsets and widths
of the fields read from system registers, as they are expressed in the
Standard (ARM ARM). This has the added benefit (albeit arguably
negligible) of reducing the final code size.

Signed-off-by: Pierre-Clément Tosi <ptosi@google.com>
2021-09-23 08:55:06 -04:00
Tom Rini
7b57e56739 First set of u-boot-at91 features for the 2022.01 cycle
-----BEGIN PGP SIGNATURE-----
 
 iQFQBAABCgA6FiEEqxhEmNJ6d7ZdeFLIHrMeAg6sL8gFAmFKxpEcHGV1Z2VuLmhy
 aXN0ZXZAbWljcm9jaGlwLmNvbQAKCRAesx4CDqwvyBLaB/0XsIdkGAvcHLWW8yUg
 27GiRznikNKwn9/qIj2ByraoUd4BvxdQV4gKHR1R9n0sgYh/8VMyLbmhRoCRKFwP
 3mQ0MUyjaeU5sEWzasovJVpXhuUapEiV0jEg6t3Lgwd3mp2QK2Pk87zoleQfZNkb
 VAVCnt1T+kb3y0W9oa3XZbuH2wam9T5pNWRGW70JbgzdwJNKLO1Qo7MfcUNiDxJu
 Jf7uXtYwwILlN38G1KSk1ymMjfaotCqj7RzNaV3Ero57MVj3VzerKGb7H+XPOYf2
 nYXyietYLJJkzvHzSDwIdCSVlOSQL8QqVB8GCmLiNQD4tG830RcvSJnYpRLylWQK
 6F+Y
 =Q/aS
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-at91-2022.01-a' of https://source.denx.de/u-boot/custodians/u-boot-at91 into next

First set of u-boot-at91 features for the 2022.01 cycle:

This feature set includes : the support for CPU driver for arm926
(sam9x60 device); changes required for OP-TEE boot for sama5d2_xplained
and sama5d27_som1_ek boards; QSPI boot configuration for sama5d2_icp;
starting to remove old Kconfig unused symbols from config_whitelist.txt
(work will take more time); also small fixes and updates in mach, DT,
configs, etc.
2021-09-22 21:17:39 -04:00
Marek Vasut
c3880e6597 arm: socfpga: vining: Fix UDC controller phandle in DT
The USB peripheral controller is the DWC2 controller 1, not 0.
Update the phandle to fix UDC support on this board.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
2021-09-22 21:30:39 +02:00
Marek Vasut
e21bbffa1d arm: socfpga: vining: Un-disable WDT in DT
The WDT on this system should be enabled, make it so.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
2021-09-22 21:30:39 +02:00
Andy Shevchenko
57e2c0a86f x86: tangier: acpi: Add GPIO card detection to SDHCI #2
On Intel Tangier the SDHCI #2 provides SD card connection.
Add GPIO card detection for it.

Fixes: 39665beed6 ("x86: tangier: Enable ACPI support for Intel Tangier")
BugLink: https://github.com/edison-fw/meta-intel-edison/issues/135
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
2021-09-22 21:50:35 +08:00
Andy Shevchenko
e45066f48f x86: edison: Mark eMMC non-removable
eMMC is non-removable on Intel Edison board. Fix the DTS accordingly.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-09-22 21:50:35 +08:00
Patrick Delaunay
cf39d0c29d arm: dts: stm32mp1: use ssbl partition name for U-Boot
Continue to use the "ssbl" name for GPT partition of secondary boot
stage = U-Boot for basic boot with SPL to avoid to disturb existing user.

The "fip" partition name is only used for TFA_BOOT with FIP, it is a TF-A
BL2 requirement; it the default configuration for STMicroelectronics
boards.

Fixes: b73e8bf453 ("arm: stm32mp: add defconfig for trusted boot with FIP")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
2021-09-21 09:22:01 +02:00
Eugen Hristev
d65b84a1d0 ARM: dts: at91: update flexcom defines using include file
Replace the number in the flexcom-mode property with the define from the
include file.
This corresponds to the approach in Linux kernel.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2021-09-21 10:08:24 +03:00
Eugen Hristev
a6bbb8b596 ARM: at91: remove references to RM9200DK
The AT91 RM9200DK board was removed long time ago.
Remove existing references that were not cleaned up.

Fixes: 1c85752258 ("ARM: remove broken "at91rm9200dk" board")
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2021-09-21 10:08:24 +03:00
Eugen Hristev
26671aabcc ARM: dts: at91: sama5d2: fix dtc warning for ohci and ehci
Fixed the following DTC build warning (reproducible with W=1)

arch/arm/dts/at91-sama5d2_icp.dtb: Warning (unit_address_format): /ahb/ohci@00400000: unit name should not have leading 0s
arch/arm/dts/at91-sama5d2_icp.dtb: Warning (unit_address_format): /ahb/ehci@00500000: unit name should not have leading 0s

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Reviewed-by: Alexander Dahl <ada@thorsis.com>
2021-09-21 10:05:38 +03:00
Eugen Hristev
b6a8cce941 ARM: dts: at91: sama5d2_icp: cosmetic arrangement of the nodes
Reorder the nodes following the kernel rules: nodes in a range are sorted
by ascending bus address, and when referenced by phandle, are ordered
alphabetically.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2021-09-21 10:05:38 +03:00
Mihai Sain
5b43508419 ARM: dts: at91: sama5d2_icp: add QSPI1 device
Add support for sst26vf064b 64Mbit qspi-flash that is
present on sama5d2_icp board.

Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
[eugen.hristev@microchip.com: move u-boot properties to sama5d2_icp-u-boot.dtsi]
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2021-09-21 10:05:38 +03:00
Clément Léger
b25d7618be ARM: dts: at91: sama5d2_xplained: Add memory node in devicetree
sama5d2_xplained DRAM detection code will be modified to use device tree
instead of hardcoded addresses. In order to prepare that, add the memory
node to at91-sama5d2_xplained.dts.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
2021-09-21 10:05:38 +03:00
Clément Léger
094f19c527 ARM: mach-at91: armv7: fix multiple cpu_reset definition when enabling SYSRESET
When SYSRESET is enabled, cpu_reset function is also defined in
sysreset-uclass.c which lead to multiple definitions of this function
since reset.c is build unconditionally. Add a check in Makefile to build
this file only if SYSRESET isn't enabled.
SYSRESET can be enabled when building SYSRESET_PSCI for instance on this
platform.

Signed-off-by: Clément Léger <clement.leger@bootlin.com>
2021-09-21 10:05:37 +03:00
Claudiu Beznea
63ba551d70 ARM: dts: at91: sam9x60: add bindings for CPU
Add bindings for CPU. This will allow displaying correctly the crystal,
CPU and master clock.

Reported-by: Eugen Hristev <eugen.hristev@microchip.com>
Fixes: a64862284f ("clk: at91: sam9x60: add support compatible with
CCF")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
2021-09-21 10:05:37 +03:00
Hari Prasath
6beb4a3a59 ARM: at91: Add chip ID of SAMA5D29
Add SAMA5D29 SoC for identification during the boot up.

Signed-off-by: Hari Prasath <Hari.PrasathGE@microchip.com>
2021-09-21 10:05:37 +03:00
Nishanth Menon
ee91d46557 arm: mach-k3: common: Make sure firmware sections are loaded prior to armv8 startup
With Device Manager firmware in an elf file form, we cannot load the FIT
image to the exact same address as any of the executable sections of the
elf file itself is located.

However, the device tree descriptions for the ARMV8 bootloader/OS
includes DDR regions only the final sections in DDR where the Device
Manager firmware is actually executing out of.

As the R5 uC is usually operating at a slower rate than an ARMv8 MPU,
by starting the Armv8 ahead of parsing the elf and copying the correct
sections to the required memories creates a race condition where the
ARMv8 could overwrite the elf image loaded from the FIT image prior to
the R5 completing parsing and putting the correct sections of elf in
the required memory locations. OR create rather obscure debug conditions
where data in the section is being modified by ARMV8 OS while the elf
copy is in progress.

To prevent all these conditions, lets make sure that the elf parse and
copy operations are completed ahead of ARMv8 being released to execute.

We will pay a penalty of elf copy time, but that is a valid tradeoff in
comparison to debug of alternate scenarios.

Signed-off-by: Nishanth Menon <nm@ti.com>
2021-09-17 14:48:53 -04:00
Roger Quadros
6887f8e00b arm: mach-k3: am6_init: Prioritize MSMC traffic over DDR in NAVSS Northbridge
NB0 is bridge to SRAM and NB1 is bridge to DDR.

To ensure that SRAM transfers are not stalled due to delays during DDR
refreshes, SRAM traffic should be higher priority (threadmap=2) than
DDR traffic (threadmap=0).

This fixup is critical to provide deterministic access latency to
MSMC from ICSSG, it applies to all AM65 silicon revisions and is due
to incorrect reset values (has no erratum id) and statically setting
things up should be done independent of usecases and board.

This specific style of Northbridge configuration is specific only to
AM65x devices, follow-on K3 devices have different data prioritization
schemes (ASEL and the like) and hence the fixup applies purely to
AM65x.

Without this fix, ICSSG TX lock-ups due to delays in MSMC transfers in
case of SR1 devices, on SR2 devices, lockups were not observed so far
but high retry rates of ICSSG Ethernet (icssg-eth) and, thus, lower
throughput.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Acked-by: Andrew F. Davis <afd@ti.com>
Acked-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Acked-by: Benoit Parrot <bparrot@ti.com>
[Jan: rebased, dropped used define, extended commit log]
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
[Nishanth: Provide relevant context in the commit message]
Signed-off-by: Nishanth Menon<nm@ti.com>
2021-09-17 14:47:03 -04:00
Suman Anna
cfd50dfb72 clk: ti: k3: Update driver to account for divider flags
The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in
turn serve as inputs to other HSDIV output clocks. These clocks use
the actual value to compute the divider clock rate, and need to be
registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk
driver and data lacks the infrastructure to pass in divider flags.
Update the driver and data to account for these divider flags.

Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-09-17 14:47:03 -04:00
Dave Gerlach
ae8d3d236a arm: mach-k3: Add note to auto-generated files
Add a note to the automatically generated clk-data and dev-data files
for j721e and j7200 to indicate that they are in fact auto-generated and
should not be hand edited.

Also adjust TI URL to use https instead of http and also add an empty
line before first header inclusion.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-09-17 14:47:03 -04:00
Suman Anna
326c03b548 arm: mach-k3: j7200: Fix clk-data parenting for postdiv PLL clocks
The TI K3 Fractional PLLs use two programmable POSTDIV1 and POSTDIV2
divisors to generate the final FOUTPOSTDIV clock. These are in sequence
with POSTDIV2 following the POSTDIV1 clock. The current J7200 clock data
has the POSTDIV2 clock as the parent for the POSTDIV1 clock, which is
opposite of the actual implementation. Fix the data by simply adjusting
the register bit-shifts.

The Main PLL1 POSTDIV clocks were also defined incorrectly using Main PLL0
register values, fix these as well.

Fixes: 277729eaf3 ("arm: mach-k3: Add platform data for j721e and j7200")
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-09-17 14:47:03 -04:00
Suman Anna
f1a815d068 arm: mach-k3: j721e: Fix clk-data parenting for postdiv PLL clocks
The TI K3 Fractional PLLs use two programmable POSTDIV1 and POSTDIV2
divisors to generate the final FOUTPOSTDIV clock. These are in sequence
with POSTDIV2 following the POSTDIV1 clock. The current J721E clock data
has the POSTDIV2 clock as the parent for the POSTDIV1 clock, which is
opposite of the actual implementation. Fix the data by simply adjusting
the register bit-shifts.

The Main PLL1 POSTDIV clocks were also defined incorrectly using Main PLL0
register values, fix these as well.

Fixes: 277729eaf3 ("arm: mach-k3: Add platform data for j721e and j7200")
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2021-09-17 14:47:03 -04:00
Suman Anna
d86a089d29 arm: mach-k3: common: Add a release_resources_for_core_shutdown() stub
Add a weak release_resources_for_core_shutdown() stub implementation
that can be overridden by actual implementation if a SoC supports that
function.

Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
2021-09-17 14:47:03 -04:00
Pali Rohár
121a165c51 Remove including timestamp.h in version.h
Header file version.h does not use anything from timestamp.h. Including of
timestamp.h has side effect which cause recompiling object file at every
make run because timestamp.h changes at every run.

So remove timestamp.h from version.h and include timestamp.h in files
which needs it.

This change reduce recompilation time of final U-Boot binary when U-Boot
source files were not changed as less source files needs to be recompiled.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Add in lib/acpi/acpi_table.c and test/dm/acpi.c, rework a few others]
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-17 12:10:44 -04:00
Pali Rohár
fd00495080 x86: quark: MRC: Remove U_BOOT_DATE and U_BOOT_TIME from debug log
U_BOOT_DATE and U_BOOT_TIME are updated on every run of make command.
Therefore mrc.c file is recompiled every time when running make which means
that whole U-Boot binary is recompiled on every run of make command.

Simplify it and do not recompile U-Boot binary on every run of make command
by not depending on macros U_BOOT_DATE and U_BOOT_TIME.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-09-17 12:10:44 -04:00
Tom Rini
d502c5f3b4 powerpc: Drop version_string placement optimization
As explained by Wolfgang, historically PowerPC would do a number of
things to hand-optimize placement of the binary on NOR flash in order to
maximize utilization of very scarce resources.  These days, we simply
aren't optimizing our binary layout for NOR flash placement and it's
quite likely this wasn't working as intended.  Furthermore, this level
of optimization makes it difficult to have version_string be a global,
instead of a weak and overridden value, and so make more progress on
reproducible builds, which is a current concern.

Move to having PowerPC no longer store version_string in the early part
of text so that it might be part of the first page of NOR and instead
use the same declaration everyone else does.

Link: https://lore.kernel.org/r/96716.1629798400@gemini.denx.de/
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-17 12:10:44 -04:00
Pali Rohár
ad5720a357 m68k: mcf: Remove overloading version_string
There is no need to overload version_string at the end of start.S files.
Common implementation of version_string should be fine.

Signed-off-by: Pali Rohár <pali@kernel.org>
[trini: Keep the align, it's important for the rest of linkage]
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-17 12:10:44 -04:00
Pali Rohár
a79f823314 Remove #include <version.h> from files which do not need it
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2021-09-17 12:10:44 -04:00
Pali Rohár
0072f5fce3 Remove #include <timestamp.h> from files which do not need it
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2021-09-17 12:10:44 -04:00
Tom Rini
6252fd05a2 m68k: Add missing ENTRY entry in linker script
Currently, there is no ENTRY() entry in the m68k linker script.
However, since they currently contain a version_string symbol, which
then overrides the default weak version_string symbol, the linker
decides we must keep start.o in the resulting link.  Add an ENTRY() line
so that the linker will know to keep this, even when version_string is
no longer provided in start.S

Cc: Huan Wang <alison.wang@nxp.com>
Cc: Angelo Dureghello <angelo@sysam.it>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-17 12:10:44 -04:00
Simon Glass
b9274095c2 sandbox: Add a way to map a file into memory
It is useful to map a file into memory so that it can be accessed using
simple pointers. Add a function to support this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-16 13:19:25 -04:00
Simon Glass
b4467fae06 sandbox: Add a way to find the size of a file
Add a function to return the size of a file. This is useful in situations
where we need to allocate memory for it before reading it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
2021-09-16 13:19:25 -04:00
Simon Glass
7dcc2f7e7a sandbox: Add license headers to the dts files
Many of these files are missing a header. Fix this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-16 13:19:25 -04:00
Simon Glass
130401e017 sandbox: Correct handling of --rm_memory
This option has no argument so we should not trip to skip one.

Fix it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-16 13:19:25 -04:00
Tom Rini
6674edaabf Prepare v2021.10-rc4
-----BEGIN PGP SIGNATURE-----
 
 iQGzBAABCgAdFiEEGjx/cOCPqxcHgJu/FHw5/5Y0tywFAmFBKRgACgkQFHw5/5Y0
 tyw/PwwAtGB3rBeYW4rjWuMC5WP1UDTnvZIAok5ImWumWDahjDm8Yq2VCzAe9adw
 EYBjuNmaNl9aQvGVqlVJeIcLku5MLuLQu2za8vhc1R8X9VTPPY+LLTcdOokOmB8y
 8JiaE7fJsb1bZeV+diF9tss3B0IkUrwSJtW1d+qfdz/4UiRvwK5BhnZgzIobDldO
 g1Ldz/xiR2GOAXlUMwDrNAi6qNvmeAqRsQxySVrjltAV2ST7LJnOiHuWvJX6g6VS
 l796Hleh/kULfEW6n+1ZaTNqvVRcJ8xYSOG8w8y9u6HuPBA3JrYH1p1Eo5n7PPDv
 US71Iy/ncweTyfTMEBThWLqjHOQ05sVkWX/r4fj2iJRli+Og53lE1fVJ4ajIx7vz
 Tc76wI43i0I5lr2yTErjUG6EzDDoueqd+c8BwxihNLUK/+QG31xoCEMfC80C25ro
 QhYVFgiPWN0ySUD5M5tbGXODvfNNIDKXpY5oSOTVtemZtDEMpO2zBM1s/K3RV7Ud
 Je9Pj0Cu
 =Me42
 -----END PGP SIGNATURE-----

Merge tag 'v2021.10-rc4' into next

Prepare v2021.10-rc4

Signed-off-by: Tom Rini <trini@konsulko.com>

# gpg: Signature made Tue 14 Sep 2021 06:58:32 PM EDT
# gpg:                using RSA key 1A3C7F70E08FAB1707809BBF147C39FF9634B72C
# gpg: Good signature from "Thomas Rini <trini@konsulko.com>" [ultimate]

# Conflicts:
#	board/Arcturus/ucp1020/spl.c
#	cmd/mvebu/Kconfig
#	common/Kconfig.boot
#	common/image-fit.c
#	configs/UCP1020_defconfig
#	configs/sifive_unmatched_defconfig
#	drivers/pci/Kconfig
#	include/configs/UCP1020.h
#	include/configs/sifive-unmatched.h
#	lib/Makefile
#	scripts/config_whitelist.txt
2021-09-16 10:29:40 -04:00
Marek Szyprowski
d28e127171 ARM: bcm283x: change the virtual address of the XHCI PCI device base
Move the XHCI PCI device base up in the virtual address space. This fixes
initialization failure observed with newer Raspberry Pi firmware, later
than 63b1922311 ("firmware: arm_loader: Update armstubs with those from
PR 117). It looks that chosing 0xff800000 as the XHCI PCI device base
conflicts with the updated ARM/VideoCore firmware.

This also requires to reduce the size of the mapped PCI device region
from 8MiB to 4MiB to fit into 32bit address space. This is still enough
for the XHCI PCI device.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Reviewed-by: Nicolas Saenz Julienne <nsaenz@kernel.org>
Tested-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2021-09-15 13:18:23 +02:00
Matthias Brugger
3304197272 arm: dts: bcm283x: Add minimal smbios information
At present SMBIOS tables are empty, which breaks some use-cases that
rely on that. Add some minimal information to fulfill this.

Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2021-09-15 12:29:26 +02:00
Simon Glass
3232bdf0b3 pci: Drop DM_PCI
This option has not effect now. Drop it, using PCI instead where needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-13 18:23:13 -04:00
Simon Glass
46596c653b ppc: Remove UCP1020 board
This board has not been converted to CONFIG_DM_PCI by the deadline.
Remove it.

Note that we have to add CONFIG_SPIFLASH to scripts/config_whitelist.txt
because it's not really migrated at this point.

Acked-by: Michael Durrant <mdurrant@arcturusnetworks.com>
Acked-by: Oleksandr Zhadan <oleks@arcturusnetworks.com>
Acked-by: Oleksandr Zhadan and Michael Durrant <arcsupport@arcturusnetworks.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Handle CONFIG_SPIFLASH differently and delete Kconfig file]
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-13 18:22:50 -04:00
Aswath Govindraju
fa7a14576d arm: dts: k3-j721e-r5-*.dts: Fix clock-names property in the usb0 instance
In the cdns3 usb driver, the clock name looked for is ref. Therefore, fix
the clock-names property in usb0 instance for proper initialization of
cdns3 usb gadget driver.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2021-09-10 20:10:20 -04:00
Roger Quadros
72f78c6918 ARM: dts: Fix node status to "okay" on TI boards
As per Device Tree Specification [1], the status parameter of nodes can
be "okay", "disabled", etc. "ok" is not a valid parameter.

U-boot Driver Model does not recognize status="ok" either and treats
the node as disabled.

[1] https://github.com/devicetree-org/devicetree-specification/releases/tag/v0.3

Signed-off-by: Roger Quadros <rogerq@kernel.org>
Reviewed-by: Nishanth Menon <nm@ti.com>
2021-09-10 20:10:20 -04:00
Aswath Govindraju
7ca1af635a arm: dts: k3-am642-evm-u-boot: Add u-boot, dm-spl tag in the pinmux node of mmc1
Add u-boot,dm-spl tag in the pinmux device tree node, required for MMCSD1
subsystem.

Fixes: b6059ddc45 ("arm: dts: k3-am642: Add r5 specific dt support")
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
2021-09-10 20:10:20 -04:00
Matwey V. Kornilov
4c9289f52f am33xx: Fix USB for am335x boards
USB nodes were mistakenly disabled in

    commit 942853dd96 ("arm: dts: Resync BeagleBone device trees")

This commit is to fix the following issue:

    starting USB...
    No working controllers found
    USB is stopped. Please issue 'usb start' first.
    starting USB...
    No working controllers found

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=0782e8572ce43f521ed6ff15e4a7ab9aa5acdc85
Fixes: 942853dd96 ("arm: dts: Resync BeagleBone device trees")
Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Reviewed-by: Paul Barker <paul.barker@sancloud.com>
2021-09-10 20:10:20 -04:00
Sven Auhagen
88426bd6b0 arm: mvebu: dts: Armada8k enable mdio
Since mvpp2 is using the new mdio driver and the cp110 has been
synced with the linux upstream, the mdio has to enabled in the
device tree file.
This is missing for some device tree files and therefore the
network cards do not come online.

Signed-off-by: Sven Auhagen <sven.auhagen@voleatech.de>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-09-10 09:01:51 +02:00
Alexandru Gagniuc
e60e449931 lib: Drop SHA512_ALGO in lieu of SHA512
SHA512_ALGO was used as a "either SHA512 or SHA384", although the
implementations of these two algorithms share a majority of code.

From a Kconfig interface perspective, it makes sense to present two
distinct options. This requires #ifdefing out the SHA512
implementation from sha512.c. The latter doesn't make any sense.

It's reasonable to say in Kconfig that SHA384 depends on SHA512, and
seems to be the more polite way to handle the selection.

Thus, automatically select SHA512 when SHA384 is enabled.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2021-09-08 16:11:46 -04:00
Tom Rini
87e8d38a39 arm: Add Kconfig entry for MACH_TYPE
As part of migrating support for ATAGs to Kconfig, add an option for
setting and passing MACH_TYPE.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-07 16:22:31 -04:00
Tom Rini
9774462e34 arm: Disable ATAGs support
With the exceptions of ds109, ds414, icnova-a20-swac, nokia_rx51 and
stemmy, disable ATAG support.  A large number of platforms had enabled
support but never supported a kernel so old as to require it.  Further,
some platforms are old enough to support both, but are well supported by
devicetree booting, and have been for a number of years.  This is
because some of the ATAGs related functions have been re-used to provide
the same kind of information, but for devicetree or just generally to
inform the user.  When needed still, rename these functions to
get_board_revision() instead, to avoid conflicts.  In other cases, these
functions were simply unused, so drop them.

Cc: Andre Przywara <andre.przywara@arm.com>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Phil Sutter <phil@nwl.cc>
Cc: Stefan Bosch <stefan_b@posteo.net>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-07 16:22:30 -04:00
Tom Rini
b9d66a061b imx: Convert SERIAL_TAG support to ENV_VARS_UBOOT_RUNTIME_CONFIG
No iMX platforms have supported ATAG-based booting.  They have however
re-used the CONFIG_SERIAL_TAG option as a way to enable support of
reading the OTP fuses and setting the serial# environment variable in
some cases.  Change the warp7 support to use this symbol, use this for
updating the rest of the imx7 code, and update the imx8 conditionals.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-07 13:04:52 -04:00
Zong Li
30fa33dc80 riscv: lib: modify the indent
We usually use a space in function declaration, rather than a tab.

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2021-09-07 10:34:29 +08:00
Zong Li
835210a125 board: sifive: use ccache driver instead of helper function
Invokes the common cache_init function to initialize ccache.

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2021-09-07 10:34:29 +08:00
Zong Li
213ed175b0 riscv: lib: implement enable_caches for sifive cache
The enable_caches is a generic hook for architecture-implemented, we
define this function to enable composable cache of sifive platforms.

In sifive_cache, it invokes the generic cache_enable interface of cache
uclass to execute the relative implementation in SiFive ccache driver.

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2021-09-07 10:34:29 +08:00
Zong Li
4d4222d074 common: board_r: support enable_caches for RISC-V
The enable_caches is a generic hook for architecture-implemented, we
leverage this function to enable caches for RISC-V

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2021-09-07 10:34:29 +08:00
Heinrich Schuchardt
f6431e8fb3 riscv: show code leading to exception
To make analyzing exceptions easier output the code that leads to it.
We already do the same on the ARM platform.

Here is an example:

    => exception ebreak
    Unhandled exception: Breakpoint
    EPC: 000000008ff5d50e RA: 000000008ff5d62c TVAL: 0000000000000000
    EPC: 000000008020b50e RA: 000000008020b62c reloc adjusted

    Code: 2785 0693 07a0 dce3 fef6 47a5 d563 00e7 (9002)

To disassemble the code we can use the decodecode script:

    $ echo 'Code: 2785 0693 07a0 dce3 fef6 47a5 d563 00e7 (9002)' | \
      CROSS_COMPILE=riscv64-linux-gnu- scripts/decodecode

    Code: 2785 0693 07a0 dce3 fef6 47a5 d563 00e7 (9002)
    All code
    ========
       0:   2785                    addiw   a5,a5,1
       2:   07a00693                li      a3,122
       6:   fef6dce3                bge     a3,a5,0xfffffffffffffffe
       a:   47a5                    li      a5,9
       c:   00e7d563                bge     a5,a4,0x16
      10:*  9002                    ebreak         <-- trapping instruction
            ...

    Code starting with the faulting instruction
    ===========================================
       0:   9002                    ebreak
            ...

As it is not always clear if the first 16 bits are at the start or in the
middle of a 32bit instruction it may become necessary to strip the first
u16 from the output before calling decodecode to get the correct
disassembled code.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
2021-09-07 10:34:29 +08:00
Patrice Chotard
c8510e397f stm32mp: Fix board_get_usable_ram_top()
When booting in EFI, lib/efi_loader/efi_memory.c calls
board_get_usable_ram_top(0) which returns by default
gd->ram_base + gd->ram_size which is the top of DDR.

In case of OPTEE boot, the top of DDR is currently reserved by OPTEE,
board_get_usable_ram_top(0) must return an address outside OPTEE
reserved memory.

gd->ram_top matches this constraint as it has already been initialized
by substracting all DT reserved-memory (included OPTEE memory area).

Fixes: 92b611e8b0 ("stm32mp: correctly handle board_get_usable_ram_top(0)")

Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
2021-09-06 10:00:11 +02:00
Simon Glass
f7560376ae sata: Rename SATA_SUPPORT to SATA
Rename this options so that CONFIG_IS_ENABLED can be used with it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-04 12:26:02 -04:00
Simon Glass
ea2ca7e17e spi: Rename SPI_SUPPORT to SPI
Rename these options so that CONFIG_IS_ENABLED can be used with them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-04 12:26:02 -04:00
Simon Glass
2a73606668 serial: Rename SERIAL_SUPPORT to SERIAL
Rename these options so that CONFIG_IS_ENABLED can be used with them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-04 12:26:01 -04:00
Simon Glass
15042e7b9b pch: Rename PCH_SUPPORT to PCH
Rename these options so that CONFIG_IS_ENABLED can be used with them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2021-09-04 11:42:41 -04:00
Simon Glass
103c5f1806 mmc: Rename MMC_SUPPORT to MMC
Rename these options so that CONFIG_IS_ENABLED can be used with them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
[trini: Fixup some incorrect renames]
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-04 11:42:41 -04:00
Tom Rini
0017931971 Revert most of the series for adding vexpress_aemv8r support
Per a request from Andre Przywara and agreed with by Peter Hoyes, the
vexpress aemv8r support wasn't quite ready to be merged, but the
discussion had moved off list.  We should keep the first patch in the
series for now, but revert the rest.  This reverts the following
commits:

e0bd6f31ce doc: Add documentation for the Arm vexpress board configs
30e5a449e8 arm: Use armv8_switch_to_el1 env to switch to EL1
b53bbca63b vexpress64: Add BASER_FVP vexpress board variant
2f5b7b7490 armv8: Add ARMv8 MPU configuration logic
37a757e227 armv8: Ensure EL1&0 VMSA is enabled

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-03 10:42:15 -04:00
Oleksandr Suvorov
7befc8490a psci: fix double declaration
The prototype of psci_features() duplicated. Remove extra declaration.

Fixed: e21e3ffdd1 ("psci: Fix warnings when compiling with W=1")
Reported-by: Michael Scott <mike@foundries.io>
Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
2021-09-02 11:19:58 -04:00
Samuel Holland
f43312c974 ARM: Prevent the compiler from using NEON registers
For ARMv8-A, NEON is standard, so the compiler can use it even when no
special target flags are provided. For example, it can use stores from
NEON registers to zero-initialize large structures. GCC 11 decides to
do this inside the DRAM init code for the Allwinner H6.

However, GCC 11 has a bug where it generates misaligned NEON register
stores even with -mstrict-align. Since the MMU is not enabled this early
in SPL, the misaligned store causes an exception and breaks booting.

Work around this issue by restricting the compiler to using GPRs only,
not vector registers. This prevents any future surprises relating to
NEON use as well.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Acked-by: Andre Przywara <andre.przywara@arm.com>
2021-09-02 11:19:58 -04:00
Peter Hoyes
30e5a449e8 arm: Use armv8_switch_to_el1 env to switch to EL1
Use the environment variable armv8_switch_to_el1 to determine whether
to switch to EL1 at runtime. This is an alternative to the
CONFIG_ARMV8_SWITCH_TO_EL1 compile-time option.

The environment variable will be ineffective if the ARMV8_MULTIENTRY
config is used.

This is required by the Armv8r64 architecture, which must be able to
boot at S-EL1 for Linux but may need to boot at other ELs for other
systems.

Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
2021-09-02 10:17:45 -04:00
Peter Hoyes
b53bbca63b vexpress64: Add BASER_FVP vexpress board variant
The BASER_FVP board variant is implemented on top of the BASE_FVP board
config (which, in turn, is based on the Juno Versatile Express board
config). They all share a similar memory map - for BASER_FVP the map is
inverted from the BASE_FVP
(https://developer.arm.com/documentation/100964/1114/Base-Platform/Base---memory/BaseR-Platform-memory-map)

 * Create new TARGET_VEXPRESS64_BASER_FVP target, which uses the same
   board config as BASE_FVP and JUNO
 * Adapt vexpress_aemv8a.h header file to support BASER_FVP (and rename
   to vexpress_aemv8.h)
 * Enable config to switch to EL1 for the BASER_FVP
 * Create vexpress_aemv8r defconfig
 * Provide an MPU memory map for the BASER_FVP

For now, only single core boot is supported.

Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
[trini: Add MAINTAINERS, move BOOTCOMMAND to defconfig]
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-09-02 10:17:45 -04:00
Peter Hoyes
2f5b7b7490 armv8: Add ARMv8 MPU configuration logic
Armv8r64 is the first Armv8 platform that only has a PMSA at the
current exception level. The architecture supplement for Armv8r64
describes new fields in ID_AA64MMFR0_EL1 which can be used to detect
whether a VMSA or PMSA is present. These fields are RES0 on Armv8a.

Add logic to read these fields and, for the protection of the memory
used by U-Boot, initialize the MPU instead of the MMU during init, then
clear the MPU regions before transition to the next stage.

Provide a default (blank) MPU memory map, which can be overridden by
board configurations.

Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
2021-09-02 10:17:45 -04:00
Peter Hoyes
37a757e227 armv8: Ensure EL1&0 VMSA is enabled
On Armv8-R, the EL1&0 memory system architecture is configurable as a
VMSA or PMSA, and resets to an "architecturally unknown" value.

Add code to armv8_switch_to_el1_m which detects whether the MSA at
EL1&0 is configurable using the id_aa64mmfr0_el1 register MSA fields.
If it is we must ensure the VMSA is enabled so that a rich OS can boot.

The MSA and MSA_FRAC fields are described in the Armv8-R architecture
profile supplement (section G1.3.7):
https://developer.arm.com/documentation/ddi0600/latest/

Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
2021-09-02 10:17:45 -04:00
Peter Hoyes
53b40e8d54 armv8: Disable pointer authentication traps for EL1
The use of ARMv8.3 pointer authentication (PAuth) is governed by fields
in HCR_EL2, which trigger a 'trap to EL2' if not enabled. The reset
value of these fields is 'architecturally unknown' so we must ensure
that the fields are enabled (to disable the traps) if we are entering
the kernel at EL1.

The APK field disables PAuth instruction traps and the API field
disables PAuth register traps

Add code to disable the traps in armv8_switch_to_el1_m. Prior to doing
so, it checks fields in the ID_AA64ISAR1_EL1 register to ensure pointer
authentication is supported by the hardware.

The runtime checks require a second temporary register, so add this to
the EL1 transition macro signature and update 2 call sites.

Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
2021-09-02 10:17:45 -04:00
Stephan Gerhold
15dd941202 arm: mach-snapdrgon: misc: Simplify msm_generate_mac_addr()
The logic in msm_generate_mac_addr() was originally taken from the LK
bootloader where the serial number is a string and must be parsed first.
However, in U-Boot msm_board_serial() returns an u32 and
msm_generate_mac_addr() has quite complicated code that will first
print it as a hex string and then immediately parse it again.

What this function actually does at the end is to put the serial number
encoded as big endian (the order used for the hex string) into the u8 *mac.
Use put_unaligned_be32() to do that with bit shifts instead of going
through the string format.

This should be slightly more efficient and cleaner but does not result
in any functional difference.

Cc: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2021-09-02 09:48:20 -04:00
Stephan Gerhold
1eb006249e arm: mach-snapdragon: misc: Initialize eMMC if necessary
At the moment U-Boot produces an empty MAC address (02:00:00:00:00:00)
if the eMMC is not used by anything in U-Boot (e.g. with
CONFIG_ENV_IS_NOWHERE=y instead of having the environment on eMMC).
This happens because then there is nothing that actually initializes
the eMMC and reads the "cid" that is later accessed.

To fix this, call mmc_init() to ensure the eMMC is initialized.
There is no functional difference if the eMMC is already initialized
since then mmc_init() will just return without doing anything.

Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
2021-09-02 09:48:20 -04:00
Chia-Wei Wang
cd82f19985 armv7: Add Position Independent Execution support
A U-Boot image could be loaded and executed at a different
location than it was linked at.

For example, Aspeed takes a stable release version of U-Boot image
as the golden one for recovery purposes. When the primary storage
such as flash is corrupted, the golden image would be loaded to any
SRAM/DRAM address on demands through ethernet/UART/etc and run for
rescue.

To deal with this condition, the PIE is needed as there is only one
signed, golden image, which could be however executed at different
places.

This patch adds the PIE support for ARMv7 platform.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
2021-09-02 09:48:20 -04:00
Chia-Wei Wang
aa29b21d62 arm: Fix option dependency with Kconfig language
Use Kconfig 'depends on' instead of #if macro to
express the option depdencies.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
2021-09-02 09:48:20 -04:00
Stephan Gerhold
8956854d48 arm: u8500: Prefer building in thumb mode by default
Enabling CONFIG_SYS_THUMB_BUILD produces a significantly smaller
U-Boot binary (250 KiB vs 320 KiB) that still seems to be fully
functional. Make use of that by default but keep it as "imply" so it
can be disabled for testing in case this causes trouble for someone.

Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
2021-09-01 19:25:37 -04:00
Stephan Gerhold
f629895fa3 board: stemmy: Update documentation
Over the time, the "stemmy" U-Boot board was tested on several other
Samsung smartphones based on ST-Ericsson NovaThor Ux500. Convert the
documentation to reStructuredText at doc/board/ste/stemmy.rst and
make the device list complete. Also note that the board now boots
into USB Fastboot instead of just ending up at the U-Boot prompt.

The device table is mostly taken from the postmarketOS wiki article
(https://wiki.postmarketos.org/wiki/ST-Ericsson_NovaThor_U8500).
All the newly added devices were tested by Linus Walleij.

Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
2021-09-01 19:25:37 -04:00
Stephan Gerhold
f64011e11e board: stemmy: Add basic Fastboot support
Make use of the new drivers for ARM U8500 introduced in the U-Boot
2021.10 merge window by adding basic support for USB Fastboot with
the "stemmy" board. As a first step this will always boot directly
into USB Fastboot for now with the console displayed on the screen
to make that obvious.

Samsung uses quite strange GPT partition labels on these boards,
so also add a bunch of fastboot_partition_alias_* to make this more
easy to use.

Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
2021-09-01 19:25:37 -04:00
Stephan Gerhold
fc9d4b123d arm: dts: u8500: u-boot: Add fixed clock for eMMC
So far there is no need for a clock driver in U-Boot because the
previous boot stage leaves all the necessary clocks on. However,
some drivers in U-Boot (e.g. arm_pl180_mmci) depend on having a clock
driver to obtain the clock frequency.

Setting up the clock drivers properly is a bit tricky on U8500,
so for now add a simple fixed-clock for the eMMC that allows obtaining
the clock frequency. This should be replaced eventually if some board
actually requires enabling some of the clocks.

Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
2021-09-01 19:25:37 -04:00
Stephan Gerhold
1ae43a0e23 arm: dts: u8500: Update from Linux ux500-dts-for-v5.15
Update ste-dbx5x0.dtsi, ste-ab8500.dtsi and ste-ab8505.dtsi with
the changes made in upstream Linux. They are taken from
https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik.git/
branch "ux500-dts-for-v5.15" (pending merge for Linux 5.15).

The only relevant change for U-Boot here is
"ARM: dts: ux500: ab8500: Link USB PHY to USB controller node" [1]
which links the USB PHY to the USB controller. This is necessary on
U-Boot because the PHY driver is implemented as part of the generic
PHY subsystem that makes use of these bindings.

[1]: https://lore.kernel.org/linux-arm-kernel/20210709182234.47232-1-stephan@gerhold.net/

Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
2021-09-01 19:25:37 -04:00
Stephan Gerhold
9f78ccf186 arm: u8500: Imply options for new drivers
Imply the options for new drivers added for ARM U8500 during the
U-Boot 2021.10 merge window. Adding these as "imply" in the Kconfig
avoids having to add them to all the board defconfigs but still allows
disabling them if wanted.

Also select DM_USB_GADGET if DM_USB is selected because otherwise
the Ux500 MUSB glue driver does not show up in the configuration.

Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
2021-09-01 19:25:37 -04:00
Tom Rini
48cf96fbdf Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell
- mvebu: a38x: Define supported UART baudrates (Pali)
- kwbimage: Misc improvements (Pali)
- espressobin/turris_mox/turris_omnia: Enable some more devices
  like SATA via PCIe, SATA & NVMe (Pali)
- a37xx: Remove unused CONFIG_DEBUG_UART_SHIFT options (Pali)
- turris_omnia: Disable MCU watchdog in SPL when booting over
  UART (Marek)
- kwbimage: Fix some Coverity issue (Heinrich)
2021-09-01 10:11:21 -04:00
Marek Behún
dc595e3e45 arm: mvebu: Move get_boot_device() to cpu.c and make visible
Move the function get_boot_device() from spl.c to cpu.c.

Make it visible, so that it may be used from other files.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-09-01 08:09:24 +02:00
Pali Rohár
3404aa4646 arm: mvebu: axp: Properly check for Armada XP in mach/soc.h
File mach/soc.h is included also in 64-bit mvebu processors, so define
Armada XP related macros only when compiling for Armada XP.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-09-01 08:07:04 +02:00
Tom Rini
e2e5eec6ce Merge branch 'next' of https://gitlab.denx.de/u-boot/custodians/u-boot-marvell into next
- Handling all DM watchdogs in watchdog_reset() (Rasmus)
2021-08-31 19:11:15 -04:00
Tom Rini
b15a17be0c Merge https://gitlab.denx.de/u-boot/custodians/u-boot-sh 2021-08-31 18:37:25 -04:00
Michal Simek
b4c2c151b1 Kconfig: Remove all default n/no options
default n/no doesn't need to be specified. It is default option anyway.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
[trini: Rework FSP_USE_UPD portion]
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-31 17:47:49 -04:00
Tom Rini
a2ac2b964b Convert CONFIG_SKIP_LOWLEVEL_INIT et al to Kconfig
This converts the following to Kconfig:
   CONFIG_SKIP_LOWLEVEL_INIT
   CONFIG_SKIP_LOWLEVEL_INIT_ONLY

In order to do this, we need to introduce SPL and TPL variants of these
options so that we can clearly disable these options only in SPL in some
cases, and both instances in other cases.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-31 17:47:49 -04:00
Tom Rini
ab92b38a01 Finish converting CONFIG_SYS_CACHELINE_SIZE to Kconfig
We move the SYS_CACHE_SHIFT_N options from arch/arm/Kconfig to
arch/Kconfig, and introduce SYS_CACHE_SHIFT_4 to provide a size of 16.
Introduce select statements for other architectures based on current
usage.  For MIPS, we take the existing arch-specific symbol and migrate
to the generic symbol.  This lets us remove a little bit of otherwise
unused code.

Cc: Alexey Brodkin <alexey.brodkin@synopsys.com>
Cc: Anup Patel <anup.patel@wdc.com>
Cc: Atish Patra <atish.patra@wdc.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Leo <ycliang@andestech.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>
Cc: Sean Anderson <seanga2@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2021-08-31 17:47:49 -04:00
Tom Rini
148b8bb4b6 imx: Finish migration of IMX_CONFIG to Kconfig
- Provide a default Kconfig value of the default script
- Largely continue to define this via the board Kconfig file
- For the boards that select a script based on defconfig rather than
  TARGET, keep this within the defconfig.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-31 17:46:37 -04:00
Tom Rini
0c2729edad imx: Introduce CONFIG_MACH_IMX
Currently, there is no over-arching symbol for access to
arch/arm/mach-imx nor the CONFIG symbols that are common over all of
these related platforms.  This new CONFIG symbol will allow us to start
down this path.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-31 17:46:37 -04:00
Tom Rini
fcadcaa521 Convert CONFIG_MX7D to Kconfig
This converts the following to Kconfig:
   CONFIG_MX7D

Cc: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-31 17:46:37 -04:00
Tom Rini
95372165ae nxp: Migrate a number of DDR related symbols to Kconfig
- Guard most of the options in drivers/ddr/fsl/Kconfig with
  SYS_FSL_DDR || SYS_FSL_MMDC.
- Migrate FSL_DMA, DDR_ECC, DDR_ECC_CMD, and ECC_INIT_VIA_DDRCONTROLLER
  to Kconfig.
- Clean up the logic for including the DDR_ECC_CMD code.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-31 17:46:37 -04:00
Tom Rini
efb5dab7ba nxp: Migrate CONFIG_DDR_CLK_FREQ to Kconfig
As this symbol can either be a fixed value or the function
get_board_ddr_clk, migration is tricky.  Introduce a choice of DYNAMIC
or STATIC_DDR_CLK_FREQ.  If DYNAMIC, we continue to use the board
defined get_board_ddr_clk function.  If STATIC, set CONFIG_DDR_CLK_FREQ
to that value and now include/clock_legacy.h contains the function
prototype or defines get_board_ddr_clk() to that static value.  Update
callers to test for DYNAMIC or STATIC.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-31 17:46:37 -04:00
Tom Rini
222d22a39a ddr: Migrate DDR_SPD to Kconfig
Move the symbol that controls building some JEDEC SPD support functions
to Kconfig.  This is required on the TI keystone 2 platforms and very
frequently (but not always) used on large number of Freescale/NXP
platforms, so use imply there.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-31 17:46:37 -04:00
Tom Rini
f66a3fde38 mvebe: Migrate CONFIG_DDR_LOG_LEVEL to Kconfig
Move this specific option to Kconfig.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-31 17:46:37 -04:00
Tom Rini
5b527c505f mvebu: Migrate CONFIG_DDR_32BIT/64BIT to Kconfig
Move CONFIG_DDR_32BIT/64BIT to Kconfig as a choice for Armada XP
platforms.  Make 64bit the default as this mirrors the current code.

Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2021-08-31 17:46:37 -04:00
Rasmus Villemoes
4171c57472 sandbox: add test of wdt-uclass' watchdog_reset()
Check that the watchdog_reset() implementation in wdt-uclass behaves
as expected:

- resets all activated watchdog devices
- leaves unactivated/stopped devices alone
- that the rate-limiting works, with a per-device threshold

Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2021-08-31 12:04:03 +02:00
Rasmus Villemoes
a9346b93b4 sandbox: add test of wdt_gpio driver
It seems that no other test has claimed gpio_a:7 yet, so use that.

The only small wrinkle is modifying the existing wdt test to use
uclass_get_device_by_driver() since we now have two UCLASS_WDT
instances in play, so it's a little more robust to fetch the device by
driver and not merely uclass+index.

Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2021-08-31 12:04:03 +02:00
Tom Rini
8897bf4288 global: Remove unused or unnecessary CONFIG symbols related to DDR
These symbols are now either unused or were only used within the config
file to determine other logic, which could be done in a way that doesn't
further pollute the CONFIG namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-30 19:49:22 -04:00
Tom Rini
809c4f242f Kconfig: Use spaces not tabs in Kconfig entires
While the Kconfig language seems to accept either form of whitespace, we
use a space throughout the project, except in these spots.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-30 14:13:28 -04:00
Tom Rini
d1240b6ab2 global: Remove dead code that starts with CONFIG_[0-9A]
This removes a number of spots of dead code based on symbols that start
with CONFIG_[0-9] or CONFIG_A.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-30 14:13:28 -04:00
Tom Rini
5afdcca019 arm: Migrate GICV2 / GICV3 to Kconfig
Migrate CONFIG_GICV2 and CONFIG_GICV3 to Kconfig.  We still have the GIC
related registers that need to be handled more cleanly but start by
moving this symbol to Kconfig.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-30 14:13:26 -04:00
Tom Rini
6aa075432e rcar: i2c: Migrate SYS_I2C_SH to Kconfig
- Migrate SYS_I2C_SH and related defines to Kconfig
- Remove currently unused SYS_I2C_SH related defines
- Cleanup related README section.

Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-30 14:10:07 -04:00
Tom Rini
15e7b76824 Convert CONFIG_SYS_I2C_MXC et al to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_I2C_MXC
   CONFIG_SYS_I2C_MXC_I2C1
   CONFIG_SYS_I2C_MXC_I2C2
   CONFIG_SYS_I2C_MXC_I2C3
   CONFIG_SYS_I2C_MXC_I2C4

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-30 14:10:07 -04:00
Tom Rini
a5752f8a25 Convert CONFIG_SYS_I2C_SPEED et al to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_I2C_SPEED
   CONFIG_SYS_I2C_SLAVE

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-30 14:10:07 -04:00
Tom Rini
14376b8e6c ti: i2c: Convert CONFIG_SYS_OMAP24_I2C to CONFIG_SYS_I2C namespace
The omap24xx I2C driver uses its own CONFIG namespace for common I2C
variables.  Rather than convert more of them to Kconfig, rename these to
the common I2C ones and remove the entirely unused functionality.  As
part of this, we make the am335x_shc platforms consistent with their
intended speed values.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-30 14:10:07 -04:00
Tom Rini
52c7e37596 Convert CONFIG_SYS_I2C_EARLY_INIT to Kconfig
Convert SYS_I2C_EARLY_INIT to Kconfig, and make it depend on
SPL_SYS_I2C_LEGACY.  Remove the weak implementation as it's either
something that needs to exist for real, or shouldn't be called.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-30 14:10:07 -04:00
Tom Rini
55dabcc8f2 Convert CONFIG_SYS_I2C_LEGACY to Kconfig and add CONFIG_[ST]PL_SYS_I2C_LEGACY
First, we convert CONFIG_SYS_I2C_LEGACY to Kconfig.  Next, as you cannot
have SYS_I2C_LEGACY and DM_I2C at the same time, introduce
CONFIG_SPL_SYS_I2C_LEGACY so that we can enable the legacy option only
in SPL.  Finally, for some PowerPC cases we also need
CONFIG_TPL_SYS_I2C_LEGACY support.  Convert all of the existing users to
one or more symbols.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-30 14:10:07 -04:00
Tom Rini
2656145224 Convert CONFIG_SYS_I2C_MVTWSI to Kconfig
This converts the following to Kconfig:
   CONFIG_SYS_I2C_MVTWSI

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-30 14:10:06 -04:00
Tom Rini
d7d40f614d Convert CONFIG_ID_EEPROM to Kconfig
This converts the following to Kconfig:
   CONFIG_ID_EEPROM

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-30 14:10:05 -04:00
Tom Rini
20815ecdcf davinci: Drop CONFIG_MAC_ADDR_IN_EEPROM
Looking over the current boards, there are no users of
CONFIG_MAC_ADDR_IN_EEPROM.  Further, omapl138_lcdk uses
CONFIG_NET_RANDOM_ETHADDR.  Drop various unused code paths.

Cc: Adam Ford <aford173@gmail.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-30 14:10:05 -04:00
Tom Rini
c347e42f43 powerpc: Remove unused FCC ethernet code
This code is no longer used, remove it.

Signed-off-by: Tom Rini <trini@konsulko.com>
2021-08-30 14:10:05 -04:00
Tom Rini
b9cb74a5aa Xilinx changes for v2021.10-rc3
xilinx:
 - Disable CONFIG_ARCH_FIXUP_FDT_MEMORY
 - Print information about cpu via soc drivers and enable DISPLAY_CPUINFO
 - Wire infrastructure for DTB_RESELECT and MULTI_DTB_FIT
 
 zynq:
 - Wire single QSPI
 - Use power-source instead of io-standard properties
 - Enable nor on zc770-xm012
 
 zynqmp:
 - Change handling around multi_boot()
 - Setup offset for u-boot.itb in spi
 - Generate run time dfu_alt_info for capsule update
 - Use explicit values for enums (zynqmp_firmware.h)
 - Enable RTC/SHA1/BUTTON/BUTTON_GPIO command
 - Disable WDT driver by default
 - Bind usb/scsi via preboot because of EFI
 - DT updates/fixes
 - Add soc driver
 - Fix SPL SPI boot mode
 
 versal:
 - Add soc driver
 
 sdhci:
 - Update tap delay programming for zynq_sdhci driver
 
 cmd:
 - Fix RTC uclass handling in date command
 - Update pwm help message
 - Update reset help message
 
 watchdog:
 - Fix wwdt compilation
 
 rtc:
 - Deal with seq alias in rtc uclass
 - Add zynqmp RTC driver
 
 fdt:
 - Add kernel-doc for fdt_fixup_memory_banks()
 -----BEGIN PGP SIGNATURE-----
 
 iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCYSilpgAKCRDKSWXLKUoM
 Id2JAJ9jY19JiEpOd3vuRCT5CE/pzX4yDACeP8DiXDzSi5tLHwDWUCBobUTze2s=
 =5lnj
 -----END PGP SIGNATURE-----

Merge tag 'xilinx-for-v2021.10-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2021.10-rc3

xilinx:
- Disable CONFIG_ARCH_FIXUP_FDT_MEMORY
- Print information about cpu via soc drivers and enable DISPLAY_CPUINFO
- Wire infrastructure for DTB_RESELECT and MULTI_DTB_FIT

zynq:
- Wire single QSPI
- Use power-source instead of io-standard properties
- Enable nor on zc770-xm012

zynqmp:
- Change handling around multi_boot()
- Setup offset for u-boot.itb in spi
- Generate run time dfu_alt_info for capsule update
- Use explicit values for enums (zynqmp_firmware.h)
- Enable RTC/SHA1/BUTTON/BUTTON_GPIO command
- Disable WDT driver by default
- Bind usb/scsi via preboot because of EFI
- DT updates/fixes
- Add soc driver
- Fix SPL SPI boot mode

versal:
- Add soc driver

sdhci:
- Update tap delay programming for zynq_sdhci driver

cmd:
- Fix RTC uclass handling in date command
- Update pwm help message
- Update reset help message

watchdog:
- Fix wwdt compilation

rtc:
- Deal with seq alias in rtc uclass
- Add zynqmp RTC driver

fdt:
- Add kernel-doc for fdt_fixup_memory_banks()
2021-08-27 08:33:02 -04:00
Michal Simek
060fa0e11b xilinx: zynqmp: Update descriptions for u-boot.its
Use TF-A instead of ATF in description. And update generic description with
removing ATF because also configurations without it are supported.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:14:43 +02:00
Michal Simek
52ff1626cf xilinx: common: Enabling generic function for DT reselection
U-Boot support board detection at run time and based on it change DT.
This feature is implemented for SOM Kria platforms which contain two
eeproms which contain information about SOM module and CC (Carrier card).
Full U-Boot starts with minimal DT file defined by
CONFIG_DEFAULT_DEVICE_TREE which is available in multi DTB fit image.
It is using default setup of board_name variable initializaed to
DEVICE_TREE which corresponds to CONFIG_DEFAULT_DEVICE_TREE option.

When DTB_RESELECT is enabled board_detection() is called. Keep it your mind
that this code is called before relocation. board_detection() is calling
xilinx_read_eeprom() which fills board_info (xilinx_board_description)
structure which are parsed in board_name_decode().
Based on DT configuration and amount of nvmemX aliases name of the board is
composed by concatenating CONFIG_SYS_BOARD "-" <board_name> "-rev"
<board_revision> "-" <cc_name> "-rev" <cc_revision>.

If CC is not present or more are available it keeps going.

When board name is composed and returned from board_name_decode() it is
assigned to board_name variable which is used by
board_fit_config_name_match() which is called via fdtdec_setup() when it
goes over config options in multi dtb FIT image.

From practical point of view multi DTB image is key point here which has to
contain configs for detected combinations. Unfortunately as of now they
have to be full DTBs and DTBOs are not supported.

That's why configuration like:
config_X {
	description = "zynqmp-board-cc";
	fdt = "board", "cc";
};

needs to be squashed together with:
fdtoverlay -o zynqmp-board-cc -i arch/arm/dts/zynqmp-board.dtb \
arch/arm/dts/zynqmp-cc.dtbo

and only one dtb is in fit:
config_X {
	description = "zynqmp-board-cc";
	fdt = "board-cc";
};

For creating multi DTBs fit image use mkimage -E, e.g.:
mkimage -E -f all.its all.dtb

When DTB_RESELECT is enabled xilinx_read_eeprom() is called before
relocation and it uses calloc for getting a buffer. Because this is dynamic
memory it is not relocated that's why xilinx_read_eeprom() is called again
as the part of board_init(). This second read with calloc buffer placed in
proper position board_late_init_xilinx() can setup u-boot variables as
before.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:14:43 +02:00
Michal Simek
e69213611e xilinx: zynqmp: Generate different u-boot.itb for MULTI_DTB_FIT
When MULTI_DTB_FIT is enabled fit-dtb.blob fit image is created which
contain all DTBs listed by CONFIG_OF_LIST. And with DTB_RELESELECT there is
a need to handle it as one file with DTBs in it not as separate DTBs in
u-boot.its/itb.
That's why extend mkimage_fit_atf.sh to generate u-boot.itb correctly.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:14:43 +02:00
Michal Simek
f28a22d55a arm64: dts: Make sure that all DTBs are 64bit aligned
Start of DTB should be 64bit aligned that's why also make sure that end is
also 64bit aligned. It is not required but it is nice thing to do.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:14:43 +02:00
T Karthik Reddy
42e20f52d9 soc: xilinx: versal: Add soc_xilinx_versal driver
soc_xilinx_versal driver allows identification of family & revision
of versal SoC. This driver is selected by CONFIG_SOC_XILINX_VERSAL.
Probe this driver using platdata U_BOOT_DEVICE structure which is
defined at mach-versal/cpu.c.
Add this config to xilinx_versal_virt_defconfig &
xilinx_versal_mini_ospi_defconfig file to select this driver.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Reviewed-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:08:11 +02:00
T Karthik Reddy
a890a53ad2 soc: xilinx: zynqmp: Add soc_xilinx_zynqmp driver
soc_xilinx_zynqmp driver allows identification of family & revision
of zynqmp SoC. This driver is selected by CONFIG_SOC_XILINX_ZYNQMP.
Add this config to xilinx_zynqmp_virt_defconfig file.
Probe this driver using platdata U_BOOT_DEVICE structure which is
specified in mach-zynqmp/cpu.c.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Reviewed-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:08:11 +02:00
Michal Simek
c2b7244322 ARM: zynq: Enable smcc and nor for zc770-xm012
Enable cfi flash on zc770-xm012 configuration.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:08:11 +02:00
Michal Simek
0df062bf04 ARM: zynq: Wire single qspi on couple of boards
Single configuration is working fine and no issue to enable it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:08:11 +02:00
Sai Krishna Potthuri
b9c4e8d439 ARM: zynq: Replace 'io-standard' with 'power-source' property
Replace 'io-standard' property with 'power-source' property in all
zynq dts files to be in sync with Zynq Pinctrl driver.

Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:08:11 +02:00
Raju Kumar Pothuraju
bc353102a0 xilinx: Add jedec compatible string for QSPI (Zynq/ZynqMP)
Add missing "jedec, spi-nor" compatible string for QSPI flash node.
Spi-nor framework uses this compatibility string to probe &
initialize flash. With missing compatibility string we are observing
below error:

Zynq> sf probe 0 0 0
 jedec_spi_nor spi_flash@0:0: unrecognized JEDEC id bytes:
00, 00, 00  Failed to initialize SPI flash at 0:0 (error -2)

Signed-off-by: Raju Kumar Pothuraju <raju.kumar-pothuraju@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:08:11 +02:00
Michal Simek
1759a31288 arm64: zynqmp: Update comment style sm-k26
Trivial style patch.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:08:11 +02:00
Michal Simek
464f6558ca arm64: zynqmp: Fix header alignment on kv260 boards
Fix header alignment.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:08:11 +02:00
Michal Simek
4cec057ff9 arm64: zynqmp: Fix node name for ds35/36 leds
By dt-binding specs led nodes should have -led suffix that's why add it.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2021-08-26 08:08:11 +02:00
Siew Chin Lim
31b51cb1d2 arm: socfpga: Enable Intel N5X device build
Add defconfig for N5X to support legacy, ATF and VAB boot flow.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-08-25 15:26:38 +08:00
Siew Chin Lim
8208e9a914 arm: dts: Add base dtsi and devkit dts for Intel N5X device
Add device tree for N5X.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Reviewed-by: Ley Foon Tan <lftan.linux@gmail.com>
2021-08-25 15:04:44 +08:00
Siew Chin Lim
00a990e9a9 arm: socfpga: Add SPL for Intel N5X device
Add SPL for N5X.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-08-25 14:43:29 +08:00
Tien Fong Chee
59d4230429 ddr: altera: Add SDRAM driver for Intel N5X device
The DDR subsystem in Diamond Mesa is consisted of controller, PHY,
memory reset manager and memory clock manager.

Configuration settings of controller, PHY and  memory reset manager
is come from DDR handoff data in bitstream, which contain the register
base addresses and user settings from tool.

Configuration settings of memory clock manager is come from the HPS
handoff data in bitstream, however the register base address is defined
in device tree.

The calibration is fully done in HPS, which requires IMEM and DMEM
binaries loading to PHY SRAM for running this calibration, both
IMEM and DMEM binaries are also part of bitstream, this bitstream
would be loaded to OCRAM by SDM, and configured by DDR driver.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2021-08-25 13:47:05 +08:00
Siew Chin Lim
37529cf285 arm: socfpga: Changed misc_s10.c to misc_soc64.c
Rename to common file name to used by all SOC64 devices.
No functionality change.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-08-25 13:37:01 +08:00
Siew Chin Lim
c2b733c0f0 arm: socfpga: Add clock manager for Intel N5X device
Add clock manager for N5X.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-08-25 13:32:50 +08:00
Siew Chin Lim
d6fee20d5f arm: socfpga: Move cm_get_mpu_clk_hz function declaration to clock_manager.h
Move cm_get_mpu_clk_hz function declaration from individual device's
clock manager header file to common clock_manager.h.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-08-25 13:31:40 +08:00
Siew Chin Lim
d694c7d46b arm: socfpga: Get clock manager base address for Intel N5X device
Add N5X clock manager to socfpga_get_managers_addr function.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-08-25 12:54:37 +08:00
Adam Ford
221146c558 ARM: rmobile: beacon-renesom: Enable QSPI NOR Flash
There is a QSPI NOR flash part on the board.  Because this chip isn't
yet supported in Linux, but it is supported in U-Boot, and the
face that the RPC_SPI compatible names are different in U-Boot and
Linux, the device tree updates are confined to -u-boot.dtsi files.

In order to use the QSPI, TF-A must leave RPC unlocked by compiling
TF-A with RZG_RPC_HYPERFLASH_LOCKED=0.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Biju Bas <biju.das.jz@bp.renesas.com>
2021-08-24 20:03:09 +02:00
Tien Fong Chee
2fb2e04791 arm: socfpga: Add handoff data support for Intel N5X device
N5X support both HPS handoff data and DDR handoff data.
Existing HPS handoff functions are restructured to support both existing
devices and N5X device.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
2021-08-24 17:13:35 +08:00
Siew Chin Lim
0fbf31f966 arm: socfpga: Add base address for Intel N5X device
Reuse base_addr_soc64.h for Intel N5X device, the address is the
same as Agilex.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-08-24 15:14:23 +08:00
Siew Chin Lim
bdba67ba87 arm: socfpga: Changed base_addr_s10.h to base_addr_soc64.h
Rename to common file name to used by all SOC64 devices and change
"_S10_" to "_SOC64_" in base_addr_soc64.h.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
2021-08-24 15:11:34 +08:00