Convert CONFIG_SKIP_LOWLEVEL_INIT et al to Kconfig

This converts the following to Kconfig:
   CONFIG_SKIP_LOWLEVEL_INIT
   CONFIG_SKIP_LOWLEVEL_INIT_ONLY

In order to do this, we need to introduce SPL and TPL variants of these
options so that we can clearly disable these options only in SPL in some
cases, and both instances in other cases.

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2021-08-27 21:18:30 -04:00
parent ab92b38a01
commit a2ac2b964b
457 changed files with 512 additions and 310 deletions

16
README
View file

@ -2741,22 +2741,6 @@ Low Level (hardware related) configuration options:
This only takes effect if the memory commands are activated
globally (CONFIG_CMD_MEMORY).
- CONFIG_SKIP_LOWLEVEL_INIT
[ARM, NDS32, MIPS, RISC-V only] If this variable is defined, then certain
low level initializations (like setting up the memory
controller) are omitted and/or U-Boot does not
relocate itself into RAM.
Normally this variable MUST NOT be defined. The only
exception is when U-Boot is loaded (to RAM) by some
other boot loader or by a debugger which performs
these initializations itself.
- CONFIG_SKIP_LOWLEVEL_INIT_ONLY
[ARM926EJ-S only] This allows just the call to lowlevel_init()
to be skipped. The normal CP15 init (such as enabling the
instruction cache) is still performed.
- CONFIG_SPL_BUILD
Set when the currently-running compilation is for an artifact
that will end up in the SPL (as opposed to the TPL or U-Boot

View file

@ -351,6 +351,63 @@ config SYS_DISABLE_DCACHE_OPS
Note that, its up to the individual architectures to implement
this functionality.
config SKIP_LOWLEVEL_INIT
bool "Skip the calls to certain low level initialization functions"
depends on ARM || NDS32 || MIPS || RISCV
help
If enabled, then certain low level initializations (like setting up
the memory controller) are omitted and/or U-Boot does not relocate
itself into RAM.
Normally this variable MUST NOT be defined. The only exception is
when U-Boot is loaded (to RAM) by some other boot loader or by a
debugger which performs these initializations itself.
config SPL_SKIP_LOWLEVEL_INIT
bool "Skip the calls to certain low level initialization functions"
depends on SPL && (ARM || NDS32 || MIPS || RISCV)
help
If enabled, then certain low level initializations (like setting up
the memory controller) are omitted and/or U-Boot does not relocate
itself into RAM.
Normally this variable MUST NOT be defined. The only exception is
when U-Boot is loaded (to RAM) by some other boot loader or by a
debugger which performs these initializations itself.
config TPL_SKIP_LOWLEVEL_INIT
bool "Skip the calls to certain low level initialization functions"
depends on SPL && ARM
help
If enabled, then certain low level initializations (like setting up
the memory controller) are omitted and/or U-Boot does not relocate
itself into RAM.
Normally this variable MUST NOT be defined. The only exception is
when U-Boot is loaded (to RAM) by some other boot loader or by a
debugger which performs these initializations itself.
config SKIP_LOWLEVEL_INIT_ONLY
bool "Skip the call to lowlevel_init during early boot ONLY"
depends on ARM
help
This allows just the call to lowlevel_init() to be skipped. The
normal CP15 init (such as enabling the instruction cache) is still
performed.
config SPL_SKIP_LOWLEVEL_INIT_ONLY
bool "Skip the call to lowlevel_init during early boot ONLY"
depends on SPL && ARM
help
This allows just the call to lowlevel_init() to be skipped. The
normal CP15 init (such as enabling the instruction cache) is still
performed.
config TPL_SKIP_LOWLEVEL_INIT_ONLY
bool "Skip the call to lowlevel_init during early boot ONLY"
depends on TPL && ARM
help
This allows just the call to lowlevel_init() to be skipped. The
normal CP15 init (such as enabling the instruction cache) is still
performed.
source "arch/arc/Kconfig"
source "arch/arm/Kconfig"
source "arch/m68k/Kconfig"

View file

@ -39,7 +39,7 @@ reset:
msr cpsr,r0
/* the mask ROM code should have PLL and others stable */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
bl cpu_init_crit
#endif
@ -62,7 +62,7 @@ c_runtime_cpu_setup:
*
*************************************************************************
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
cpu_init_crit:
/*
* flush v4 I/D caches
@ -81,7 +81,7 @@ cpu_init_crit:
orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
mcr p15, 0, r0, c1, c0, 0
#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
/*
* Jump to board specific initialization... The Mask ROM will have already initialized
* basic memory. Go here to bump up clock rate and handle wake up conditions.
@ -91,4 +91,4 @@ cpu_init_crit:
mov lr, ip /* restore link */
#endif
mov pc, lr /* back to my caller */
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
#endif /* !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */

View file

@ -37,8 +37,8 @@ reset:
* we do sys-critical inits only at reboot,
* not when booting from ram!
*/
#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
!defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \
!CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
bl cpu_init_crit
#endif
@ -62,8 +62,8 @@ c_runtime_cpu_setup:
*************************************************************************
*/
#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
!defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \
!CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
cpu_init_crit:
mov ip, lr
@ -76,4 +76,4 @@ cpu_init_crit:
mov lr, ip
mov pc, lr
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */

View file

@ -53,7 +53,7 @@ copyex:
* we do sys-critical inits only at reboot,
* not when booting from ram!
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
bl cpu_init_crit
#endif
@ -78,7 +78,7 @@ c_runtime_cpu_setup:
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
cpu_init_crit:
/*
* flush v4 I/D caches
@ -97,7 +97,7 @@ cpu_init_crit:
orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
mcr p15, 0, r0, c1, c0, 0
#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
/*
* before relocating, we have to setup RAM timing
* because memory timing is board-dependend, you will
@ -109,4 +109,4 @@ cpu_init_crit:
mov lr, ip
#endif
mov pc, lr
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */

View file

@ -46,7 +46,7 @@ reset:
* we do sys-critical inits only at reboot,
* not when booting from ram!
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
bl cpu_init_crit
#endif
@ -69,7 +69,7 @@ c_runtime_cpu_setup:
*
*************************************************************************
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
cpu_init_crit:
/*
* flush D cache before disabling it
@ -100,7 +100,7 @@ flush_dcache:
#endif
mcr p15, 0, r0, c1, c0, 0
#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
/*
* Go setup Memory and board specific bits prior to relocation.
*/
@ -109,4 +109,4 @@ flush_dcache:
mov lr, r4 /* restore link */
#endif
mov pc, lr /* back to my caller */
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */

View file

@ -45,7 +45,7 @@ reset:
* we do sys-critical inits only at reboot,
* not when booting from ram!
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
bl cpu_init_crit
#endif
@ -70,7 +70,7 @@ c_runtime_cpu_setup:
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
cpu_init_crit:
/*
* flush v4 I/D caches
@ -89,7 +89,7 @@ cpu_init_crit:
orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
mcr p15, 0, r0, c1, c0, 0
#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
/*
* Go setup Memory and board specific bits prior to relocation.
*/

View file

@ -17,7 +17,7 @@ obj-$(CONFIG_EFI_LOADER) += sctlr.o
obj-$(CONFIG_ARMV7_NONSEC) += exception_level.o
endif
ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y)
ifneq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),y)
obj-y += lowlevel_init.o
endif

View file

@ -80,11 +80,11 @@ switch_to_hypervisor_ret:
#endif
/* the mask ROM code should have PLL and others stable */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
#ifdef CONFIG_CPU_V7A
bl cpu_init_cp15
#endif
#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
bl cpu_init_crit
#endif
#endif
@ -320,8 +320,8 @@ skip_errata_801819:
mov pc, r5 @ back to my caller
ENDPROC(cpu_init_cp15)
#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
!defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \
!CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
/*************************************************************************
*
* CPU_init_critical registers

View file

@ -5,6 +5,7 @@ config ARCH_LS1012A
select FSL_LAYERSCAPE
select FSL_LSCH2
select GICV2
select SKIP_LOWLEVEL_INIT
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR_BE
@ -62,6 +63,7 @@ config ARCH_LS1043A
select FSL_LSCH2
select GICV2
select HAS_FSL_XHCI_USB if USB_HOST
select SKIP_LOWLEVEL_INIT
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR
@ -96,6 +98,7 @@ config ARCH_LS1046A
select FSL_LSCH2
select GICV2
select HAS_FSL_XHCI_USB if USB_HOST
select SKIP_LOWLEVEL_INIT
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR
@ -134,6 +137,7 @@ config ARCH_LS1088A
select FSL_LAYERSCAPE
select FSL_LSCH3
select GICV3
select SKIP_LOWLEVEL_INIT
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR
@ -181,6 +185,7 @@ config ARCH_LS2080A
select FSL_LAYERSCAPE
select FSL_LSCH3
select GICV3
select SKIP_LOWLEVEL_INIT
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR
@ -296,6 +301,7 @@ config ARCH_LX2160A
config FSL_LSCH2
bool
select SKIP_LOWLEVEL_INIT
select SYS_FSL_HAS_CCI400
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_5

View file

@ -45,7 +45,7 @@ reset:
orr r0,r0,#0xd3
msr cpsr,r0
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
bl cpu_init_crit
#endif
@ -92,7 +92,7 @@ c_runtime_cpu_setup:
*
*************************************************************************
*/
#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X)
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) || defined(CONFIG_CPU_PXA25X)
cpu_init_crit:
/*
* flush v4 I/D caches
@ -111,7 +111,7 @@ cpu_init_crit:
mcr p15, 0, r0, c1, c0, 0
mov pc, lr /* back to my caller */
#endif /* !CONFIG_SKIP_LOWLEVEL_INIT || CONFIG_CPU_PXA25X */
#endif /* !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) || CONFIG_CPU_PXA25X */
/*
* Enable MMU to use DCache as DRAM.

View file

@ -39,7 +39,7 @@ reset:
* we do sys-critical inits only at reboot,
* not when booting from ram!
*/
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
bl cpu_init_crit
#endif
@ -95,7 +95,7 @@ cpu_init_crit:
ldr r1, cpuspeed
str r1, [r0, #PPCR]
#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
/*
* before relocating, we have to setup RAM timing
* because memory timing is board-dependend, you will

View file

@ -6,7 +6,7 @@
#ifndef __ARCH_ARM_MACH_CHILISOM_SOM_H__
#define __ARCH_ARM_MACH_CHILISOM_SOM_H__
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
void chilisom_enable_pin_mux(void);
void chilisom_spl_board_init(void);
#endif

View file

@ -10,7 +10,7 @@
#include <config.h>
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
#include <asm/arch/hardware.h>
#include <asm/arch/at91_mc.h>
@ -148,4 +148,4 @@ SMRDATA1:
.word CONFIG_SYS_SDRAM_VAL
SMRDATA1E:
/* SMRDATA1 is 176 bytes long */
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */

View file

@ -224,7 +224,7 @@ const struct rproc_att hostmap[] = {
};
#endif
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
/* enable all periherial can be accessed in nosec mode */
static void init_csu(void)
{

View file

@ -59,7 +59,7 @@ static inline unsigned long long us_to_tick(unsigned long long usec)
return usec;
}
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
int timer_init(void)
{
struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR;

View file

@ -27,10 +27,6 @@
#define CONFIG_SYS_L2_PL310
#ifdef CONFIG_SPL_BUILD
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
#endif
/*
* By default the generated mvebu kwbimage.cfg is used
* If for some board, different configuration file need to be used,

View file

@ -120,6 +120,7 @@ config AM33XX
select SPECIFY_CONSOLE_INDEX
imply NAND_OMAP_ELM
imply NAND_OMAP_GPMC
imply SKIP_LOWLEVEL_INIT
imply SPL_NAND_AM33XX_BCH
imply SPL_NAND_SUPPORT
imply SYS_I2C_OMAP24XX

View file

@ -13,7 +13,7 @@ endif
obj-$(CONFIG_TI816X) += clock_ti816x.o
obj-y += sys_info.o
obj-y += ddr.o
ifeq ($(CONFIG_TI816X)$(CONFIG_SKIP_LOWLEVEL_INIT),)
ifeq ($(CONFIG_TI816X)$(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),)
obj-y += emif4.o
endif
obj-$(CONFIG_TI816X) += ti816x_emif4.o

View file

@ -65,7 +65,7 @@ DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
sdram_init();
#endif
@ -351,7 +351,7 @@ int arch_misc_init(void)
#endif /* CONFIG_USB_MUSB_* && CONFIG_AM335X_USB* && !CONFIG_DM_USB */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC) || \
(defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_RTC_DDR_SUPPORT))
@ -599,7 +599,7 @@ void board_init_f(ulong dummy)
int arch_cpu_init_dm(void)
{
hw_data_init();
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
early_system_init();
#endif
return 0;

View file

@ -22,7 +22,7 @@
#include <power/tps65217.h>
#include <spl.h>
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
@ -182,4 +182,4 @@ void sdram_init(void)
&ddr3_chilisom_emif_reg_data, 0);
}
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */

View file

@ -76,8 +76,8 @@ void early_system_init(void)
hw_data_init();
}
#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
!defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \
!CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
/******************************************************************************
* Routine: secure_unlock

View file

@ -170,8 +170,8 @@ pll_div_val5:
go_to_speed_end:
#endif
#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) && \
!defined(CONFIG_SKIP_LOWLEVEL_INIT_ONLY)
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) && \
!CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
ENTRY(lowlevel_init)
ldr sp, SRAM_STACK
str ip, [sp] /* stash ip register */

View file

@ -11,7 +11,7 @@ obj-y = cpu.o
obj-y += dram.o
obj-y += timer.o
ifndef CONFIG_SKIP_LOWLEVEL_INIT
ifndef CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT
obj-y += lowlevel_init.o
endif

View file

@ -100,6 +100,7 @@ config ROCKCHIP_RK3288
bool "Support Rockchip RK3288"
select CPU_V7A
select OF_BOARD_SETUP
select SKIP_LOWLEVEL_INIT_ONLY
select SUPPORT_SPL
select SPL
select SUPPORT_TPL

View file

@ -72,6 +72,7 @@ config TEGRA_ARMV7_COMMON
select CPU_V7A
select SPL
select SPL_BOARD_INIT if SPL
select SPL_SKIP_LOWLEVEL_INIT_ONLY if SPL
select SUPPORT_SPL
select TEGRA_CLKRST
select TEGRA_COMMON

View file

@ -233,7 +233,7 @@ wr_done:
# endif
#endif
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
# ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
/* Initialize any external memory */
PTR_LA t9, lowlevel_init
@ -254,7 +254,7 @@ wr_done:
nop
#endif
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
# ifndef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
/* Initialize any external memory */
PTR_LA t9, lowlevel_init

View file

@ -28,7 +28,7 @@
.set noreorder
LEAF(mips_sram_init)
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
/* Setup CPU PLL */
li t0, DELAY_USEC(1000000)
li t1, KSEG1ADDR(SYSCTL_BASE + SYSCTL_ROM_STATUS_REG)
@ -116,7 +116,7 @@ _cpu_pll_done:
sub a1, CONFIG_SYS_DCACHE_LINE_SIZE
bnez a1, 3b
nop
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
jr ra
nop

View file

@ -94,7 +94,7 @@ mem_init:
move $lp, $r11
ret
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
.globl lowlevel_init
lowlevel_init:
move $r10, $lp
@ -144,4 +144,4 @@ enable_fpu:
ret
#endif
#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */
#endif /* #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */

View file

@ -164,7 +164,7 @@ sdram_b0_cr:
ret
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
.globl lowlevel_init
lowlevel_init:
@ -314,4 +314,4 @@ show_led:
li $r8, (CONFIG_DEBUG_LED)
swi $r7, [$r8]
ret
#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */
#endif /* #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */

View file

@ -174,7 +174,7 @@ set_ivb:
jal mem_init
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
jal lowlevel_init
/*
* gp = ~VMA for burn mode

View file

@ -5,7 +5,7 @@
# Copyright (C) 2018 Robert Bosch Power Tools GmbH
#
ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),)
obj-y := mux.o
endif

View file

@ -40,7 +40,7 @@
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
static const struct ddr_data ddr3_data = {

View file

@ -6,7 +6,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),)
obj-y := mux.o
endif

View file

@ -162,7 +162,7 @@ static void set_mpu_and_core_voltage(void)
}
}
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
static const struct ddr_data ddr2_data = {
.datardsratio0 = MT47H128M16RT25E_RD_DQS,
.datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
@ -235,7 +235,7 @@ void sdram_init(void)
config_ddr(266, &ioregs, &ddr2_data,
&ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
}
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
#ifdef CONFIG_DEBUG_UART
void board_debug_uart_init(void)

View file

@ -113,6 +113,5 @@ Start Address End Address Description Size
LS1021a rev1.0 Soc specific Options/Settings
--------------------------------------------
If the LS1021a Soc is rev1.0, you need modify the configure file.
Add the following define in include/configs/ls1021aqds.h:
#define CONFIG_SKIP_LOWLEVEL_INIT
If the LS1021a Soc is rev1.0, you need modify the configuration and enable
CONFIG_SPL_SKIP_LOWLEVEL_INIT in menuconfig or similar.

View file

@ -110,6 +110,5 @@ Start Address End Address Description Size
LS1021a rev1.0 Soc specific Options/Settings
--------------------------------------------
If the LS1021a Soc is rev1.0, you need modify the configure file.
Add the following define in include/configs/ls1021atwr.h:
#define CONFIG_SKIP_LOWLEVEL_INIT
If the LS1021a Soc is rev1.0, you need modify the configuration and enable
CONFIG_SPL_SKIP_LOWLEVEL_INIT in menuconfig or similar.

View file

@ -30,7 +30,7 @@ DECLARE_GLOBAL_DATA_PTR;
static __maybe_unused struct ctrl_dev *cdev =
(struct ctrl_dev *)CTRL_DEVICE_BASE;
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
static struct module_pin_mux uart0_pin_mux[] = {
{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
@ -69,9 +69,7 @@ static void enable_board_pin_mux(void)
configure_module_pin_mux(rmii1_pin_mux);
configure_module_pin_mux(mmc0_pin_mux);
}
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
void set_uart_mux_conf(void)
{
configure_module_pin_mux(uart0_pin_mux);
@ -86,7 +84,7 @@ void am33xx_spl_board_init(void)
{
chilisom_spl_board_init();
}
#endif
#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
/*
* Basic board specific setup. Pinmux has been handled already.

View file

@ -66,7 +66,7 @@ int board_early_init_f(void)
void __iomem *rst_regs = map_physmem(AR71XX_RESET_BASE,
AR71XX_RESET_SIZE, MAP_NOCACHE);
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
/* CPU:775, DDR:650, AHB:258 */
qca956x_pll_init();
qca956x_ddr_init();

View file

@ -4,7 +4,7 @@
#
# Copyright (C) 2015 Toby Churchill Ltd - http://www.toby-churchill.com/
ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),)
obj-y := mux.o
endif

View file

@ -40,7 +40,7 @@ DECLARE_GLOBAL_DATA_PTR;
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
static const struct ddr_data ddr3_sl50_data = {
.datardsratio0 = MT41K256M16HA125E_RD_DQS,

View file

@ -4,7 +4,7 @@
#
# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),)
obj-y := mux.o
endif

View file

@ -95,7 +95,7 @@ struct serial_device *default_serial_console(void)
}
#endif
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
static const struct ddr_data ddr2_data = {
.datardsratio0 = MT47H128M16RT25E_RD_DQS,
.datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,

View file

@ -4,7 +4,7 @@
#
# Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),)
obj-y := mux.o
endif

View file

@ -56,7 +56,7 @@ void do_board_detect(void)
}
#endif
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
const struct dpll_params dpll_mpu[NUM_CRYSTAL_FREQ][NUM_OPPS] = {
{ /* 19.2 MHz */

View file

@ -71,7 +71,7 @@ int board_early_init_f(void)
wdr4300_pinmux_config();
#endif
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
ar934x_pll_init(560, 480, 240);
ar934x_ddr_init(560, 480, 240);
#endif

View file

@ -4,7 +4,7 @@
#
# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),)
obj-y := mux.o
endif

View file

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y

View file

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_KIRKWOOD=y

View file

@ -1,4 +1,5 @@
CONFIG_NDS32=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_TEXT_BASE=0x4A000000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000

View file

@ -1,4 +1,5 @@
CONFIG_NDS32=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_TEXT_BASE=0x11000000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000

View file

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_COMMON_CMD_OPTIONS=y

View file

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_COMMON_CMD_OPTIONS=y

View file

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_ISW_ENTRY_ADDR=0x40300350

View file

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_SECURE_DEVICE=y

View file

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_K3=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y

View file

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_K3=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y

View file

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_K3=y
CONFIG_TI_SECURE_DEVICE=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y

View file

@ -1,4 +1,6 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_EXYNOS=y
CONFIG_SYS_TEXT_BASE=0x43E00000

View file

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_TARGET_ASPENITE=y
CONFIG_SYS_TEXT_BASE=0x600000

View file

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000

View file

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000

View file

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000

View file

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
CONFIG_TARGET_AT91SAM9261EK=y

View file

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
CONFIG_TARGET_AT91SAM9261EK=y

View file

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
CONFIG_TARGET_AT91SAM9261EK=y

View file

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21F00000

View file

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21F00000

View file

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21F00000

View file

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21F00000

View file

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
CONFIG_TARGET_AT91SAM9261EK=y

View file

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
CONFIG_TARGET_AT91SAM9261EK=y

View file

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000
CONFIG_TARGET_AT91SAM9261EK=y

View file

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000

View file

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000

View file

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000

View file

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000

View file

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000

View file

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x73f00000
CONFIG_TARGET_AT91SAM9M10G45EK=y

View file

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x73f00000
CONFIG_TARGET_AT91SAM9M10G45EK=y

View file

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_TARGET_AT91SAM9N12EK=y

View file

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_TARGET_AT91SAM9N12EK=y

View file

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_TARGET_AT91SAM9N12EK=y

View file

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21F00000

View file

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21F00000

View file

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21F00000

View file

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_TARGET_AT91SAM9X5EK=y

View file

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_TARGET_AT91SAM9X5EK=y

View file

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_TARGET_AT91SAM9X5EK=y

View file

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x26f00000
CONFIG_TARGET_AT91SAM9X5EK=y

View file

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000

View file

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000

View file

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_ARCH_AT91=y
CONFIG_SYS_TEXT_BASE=0x21f00000

View file

@ -1,4 +1,6 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y
CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y
CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_SYS_THUMB_BUILD=y

View file

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_BCMSTB=y
CONFIG_SYS_TEXT_BASE=0x10100000
CONFIG_TARGET_BCM7260=y

View file

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_BCMSTB=y
CONFIG_SYS_TEXT_BASE=0x80100000
CONFIG_TARGET_BCM7445=y

View file

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
# CONFIG_ARM64_SUPPORT_AARCH32 is not set
CONFIG_ARCH_BCM63158=y
CONFIG_SYS_TEXT_BASE=0x10000000

View file

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_BCM68360=y
CONFIG_SYS_TEXT_BASE=0x10000000
CONFIG_SYS_MALLOC_F_LEN=0x8000

View file

@ -1,4 +1,5 @@
CONFIG_MIPS=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_SYS_TEXT_BASE=0x80010000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
@ -6,6 +7,8 @@ CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="brcm,bcm968380gerg"
CONFIG_ARCH_BMIPS=y
CONFIG_SOC_BMIPS_BCM6838=y
CONFIG_MIPS_CACHE_SETUP=y
CONFIG_MIPS_CACHE_DISABLE=y
# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set
# CONFIG_MIPS_BOOT_ENV_LEGACY is not set
CONFIG_MIPS_BOOT_FDT=y

View file

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_BCM6858=y
CONFIG_SYS_TEXT_BASE=0x10000000
CONFIG_SYS_MALLOC_F_LEN=0x8000

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