Pali Rohár 3fc8b90d68 arm: mvebu: a38x: serdes: Don't set PCIe Common Clock Configuration ... Enabling Common Clock Configuration bit in PCIe Root Port Link Control Register should not be done unconditionally. It is enabled by operating system as part of ASPM. Also after enabling Common Clock Configuration it is required to do more work, like retraining link. Some cards may be broken due to this incomplete Common Clock Configuration and some cards are broken and do not support ASPM at all. Remove this incomplete code for Common Clock Configuration. It really should not be done in SerDes code as it is not related to SerDes, but to PCIe subsystem. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>		2021-10-08 08:33:52 +02:00
..
arc	WS cleanup: remove SPACE(s) followed by TAB	2021-09-30 09:08:16 -04:00
arm	arm: mvebu: a38x: serdes: Don't set PCIe Common Clock Configuration	2021-10-08 08:33:52 +02:00
m68k	WS cleanup: remove SPACE(s) followed by TAB	2021-09-30 09:08:16 -04:00
microblaze	lmb: Switch to generic arch_lmb_reserve_generic()	2021-09-23 14:15:32 -04:00
mips	WS cleanup: remove SPACE(s) followed by TAB	2021-09-30 09:08:16 -04:00
nds32	WS cleanup: remove SPACE(s) followed by TAB	2021-09-30 09:08:16 -04:00
nios2	lmb: nios2: Add arch_lmb_reserve()	2021-09-23 14:15:32 -04:00
powerpc	Convert CONFIG_NAND_FSL_ELBC et al to Kconfig	2021-10-06 09:16:24 -04:00
riscv	riscv: ae350: enable Coherence Manager for ae350	2021-10-07 16:08:23 +08:00
sandbox	WS cleanup: remove SPACE(s) followed by TAB	2021-09-30 09:08:16 -04:00
sh	WS cleanup: remove trailing empty lines	2021-09-30 08:08:56 -04:00
x86	WS cleanup: remove SPACE(s) followed by TAB	2021-09-30 09:08:16 -04:00
xtensa	WS cleanup: remove SPACE(s) followed by TAB	2021-09-30 09:08:16 -04:00
.gitignore
Kconfig	Prepare v2021.10-rc4	2021-09-16 10:29:40 -04:00
u-boot-elf.lds	arch: Add explicit linker script for u-boot-elf	2020-04-03 11:52:55 -04:00