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https://github.com/AsahiLinux/u-boot
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arm: dts: Add base dtsi and devkit dts for Intel N5X device
Add device tree for N5X. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Ley Foon Tan <lftan.linux@gmail.com>
This commit is contained in:
Siew Chin Lim
Tien Fong Chee
parent
d1b2e4bd29
commit
8208e9a914
4 changed files with 377 additions and 0 deletions
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@ -400,6 +400,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \
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socfpga_cyclone5_socrates.dtb \
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socfpga_cyclone5_sr1500.dtb \
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socfpga_cyclone5_vining_fpga.dtb \
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socfpga_n5x_socdk.dtb \
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socfpga_stratix10_socdk.dtb
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dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \
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191
arch/arm/dts/socfpga_n5x-u-boot.dtsi
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191
arch/arm/dts/socfpga_n5x-u-boot.dtsi
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@ -0,0 +1,191 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* U-Boot additions
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*
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* Copyright (C) 2020-2021 Intel Corporation <www.intel.com>
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*/
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#include "socfpga_soc64_fit-u-boot.dtsi"
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#include <dt-bindings/clock/n5x-clock.h>
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/{
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memory {
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#address-cells = <2>;
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#size-cells = <2>;
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u-boot,dm-pre-reloc;
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};
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soc {
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u-boot,dm-pre-reloc;
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ccu: cache-controller@f7000000 {
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compatible = "arteris,ncore-ccu";
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reg = <0xf7000000 0x100900>;
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u-boot,dm-pre-reloc;
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};
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clocks {
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dram_eosc_clk: dram-eosc-clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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};
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};
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memclkmgr: mem-clock-controller@f8040000 {
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compatible = "intel,n5x-mem-clkmgr";
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reg = <0xf8040000 0x1000>;
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#clock-cells = <0>;
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clocks = <&dram_eosc_clk>, <&f2s_free_clk>;
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};
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};
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};
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&clkmgr {
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compatible = "intel,n5x-clkmgr";
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u-boot,dm-pre-reloc;
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};
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&gmac0 {
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clocks = <&clkmgr N5X_EMAC0_CLK>;
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};
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&gmac1 {
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altr,sysmgr-syscon = <&sysmgr 0x48 0>;
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clocks = <&clkmgr N5X_EMAC1_CLK>;
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};
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&gmac2 {
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altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
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clocks = <&clkmgr N5X_EMAC2_CLK>;
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};
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&i2c0 {
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clocks = <&clkmgr N5X_L4_SP_CLK>;
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reset-names = "i2c";
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};
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&i2c1 {
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clocks = <&clkmgr N5X_L4_SP_CLK>;
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reset-names = "i2c";
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};
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&i2c2 {
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clocks = <&clkmgr N5X_L4_SP_CLK>;
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reset-names = "i2c";
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};
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&i2c3 {
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clocks = <&clkmgr N5X_L4_SP_CLK>;
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reset-names = "i2c";
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};
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&i2c4 {
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clocks = <&clkmgr N5X_L4_SP_CLK>;
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reset-names = "i2c";
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};
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&memclkmgr {
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u-boot,dm-pre-reloc;
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};
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&mmc {
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clocks = <&clkmgr N5X_L4_MP_CLK>,
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<&clkmgr N5X_SDMMC_CLK>;
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resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>;
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};
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&pdma {
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clocks = <&clkmgr N5X_L4_MAIN_CLK>;
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};
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&porta {
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bank-name = "porta";
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};
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&portb {
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bank-name = "portb";
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};
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&qspi {
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u-boot,dm-pre-reloc;
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};
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&rst {
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compatible = "altr,rst-mgr";
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altr,modrst-offset = <0x20>;
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u-boot,dm-pre-reloc;
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};
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&sdr {
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compatible = "intel,sdr-ctl-n5x";
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resets = <&rst DDRSCH_RESET>;
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clocks = <&memclkmgr>;
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clock-names = "mem_clk";
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u-boot,dm-pre-reloc;
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};
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&spi0 {
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clocks = <&clkmgr N5X_L4_MAIN_CLK>;
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};
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&spi1 {
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clocks = <&clkmgr N5X_L4_MAIN_CLK>;
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};
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&sysmgr {
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compatible = "altr,sys-mgr", "syscon";
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u-boot,dm-pre-reloc;
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};
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&timer0 {
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clocks = <&clkmgr N5X_L4_SP_CLK>;
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};
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&timer1 {
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clocks = <&clkmgr N5X_L4_SP_CLK>;
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};
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&timer2 {
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clocks = <&clkmgr N5X_L4_SP_CLK>;
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};
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&timer3 {
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clocks = <&clkmgr N5X_L4_SP_CLK>;
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};
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&uart0 {
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clocks = <&clkmgr N5X_L4_SP_CLK>;
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u-boot,dm-pre-reloc;
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};
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&uart1 {
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clocks = <&clkmgr N5X_L4_SP_CLK>;
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};
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&usb0 {
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clocks = <&clkmgr N5X_USB_CLK>;
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disable-over-current;
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u-boot,dm-pre-reloc;
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};
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&usb1 {
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clocks = <&clkmgr N5X_USB_CLK>;
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u-boot,dm-pre-reloc;
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};
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&watchdog0 {
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clocks = <&clkmgr N5X_L4_SYS_FREE_CLK>;
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u-boot,dm-pre-reloc;
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};
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&watchdog1 {
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clocks = <&clkmgr N5X_L4_SYS_FREE_CLK>;
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};
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&watchdog2 {
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clocks = <&clkmgr N5X_L4_SYS_FREE_CLK>;
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};
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&watchdog3 {
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clocks = <&clkmgr N5X_L4_SYS_FREE_CLK>;
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};
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63
arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi
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63
arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi
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@ -0,0 +1,63 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* U-Boot additions
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*
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* Copyright (C) 2020-2021 Intel Corporation <www.intel.com>
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*/
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#include "socfpga_n5x-u-boot.dtsi"
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/{
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aliases {
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spi0 = &qspi;
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i2c0 = &i2c1;
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};
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memory {
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/*
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* Memory type: DDR4 (non-interleaving mode)
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* 16GB
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* <0 0x00000000 0 0x80000000>,
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* <4 0x80000000 3 0x80000000>;
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*
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* 8GB
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* <0 0x00000000 0 0x80000000>,
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* <2 0x80000000 1 0x80000000>;
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*
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* 4GB
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* <0 0x00000000 0 0x80000000>,
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* <1 0x80000000 0 0x80000000>;
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*
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* Memory type: LPDDR4 (non-interleaving mode)
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* Total memory size 3GB, usable = 2.5GB, 0.5GB trade off for secure
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* region.
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*/
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reg = <0 0x00000000 0 0x60000000>,
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<0x10 0x00100000 0 0x40000000>;
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};
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};
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&flash0 {
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compatible = "jedec,spi-nor";
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spi-tx-bus-width = <4>;
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spi-rx-bus-width = <4>;
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u-boot,dm-pre-reloc;
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};
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&i2c1 {
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status = "okay";
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};
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&mmc {
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drvsel = <3>;
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smplsel = <0>;
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u-boot,dm-pre-reloc;
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};
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&qspi {
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status = "okay";
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};
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&watchdog0 {
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u-boot,dm-pre-reloc;
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};
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122
arch/arm/dts/socfpga_n5x_socdk.dts
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122
arch/arm/dts/socfpga_n5x_socdk.dts
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@ -0,0 +1,122 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020-2021, Intel Corporation
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*/
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#include "socfpga_agilex.dtsi"
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/ {
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model = "eASIC N5X SoCDK";
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aliases {
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serial0 = &uart0;
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ethernet0 = &gmac0;
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ethernet1 = &gmac1;
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ethernet2 = &gmac2;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory {
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device_type = "memory";
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/* We expect the bootloader to fill in the reg */
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reg = <0 0 0 0>;
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};
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soc {
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clocks {
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osc1 {
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clock-frequency = <25000000>;
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};
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};
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};
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};
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&gmac0 {
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status = "okay";
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phy-mode = "rgmii";
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phy-handle = <&phy0>;
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max-frame-size = <9000>;
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mdio0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dwmac-mdio";
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phy0: ethernet-phy@0 {
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reg = <4>;
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txd0-skew-ps = <0>; /* -420ps */
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txd1-skew-ps = <0>; /* -420ps */
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txd2-skew-ps = <0>; /* -420ps */
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txd3-skew-ps = <0>; /* -420ps */
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rxd0-skew-ps = <420>; /* 0ps */
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rxd1-skew-ps = <420>; /* 0ps */
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rxd2-skew-ps = <420>; /* 0ps */
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rxd3-skew-ps = <420>; /* 0ps */
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txen-skew-ps = <0>; /* -420ps */
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txc-skew-ps = <900>; /* 0ps */
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rxdv-skew-ps = <420>; /* 0ps */
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rxc-skew-ps = <1680>; /* 780ps */
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};
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};
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};
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&gpio1 {
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status = "okay";
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};
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&mmc {
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status = "okay";
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cap-sd-highspeed;
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broken-cd;
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bus-width = <4>;
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};
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&qspi {
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status = "okay";
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flash0: flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "mt25qu02g";
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reg = <0>;
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spi-max-frequency = <100000000>;
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m25p,fast-read;
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cdns,page-size = <256>;
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cdns,block-size = <16>;
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cdns,read-delay = <3>;
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cdns,tshsl-ns = <50>;
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cdns,tsd2d-ns = <50>;
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cdns,tchsh-ns = <4>;
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cdns,tslch-ns = <4>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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qspi_boot: partition@0 {
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label = "Boot and fpga data";
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reg = <0x0 0x034B0000>;
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};
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qspi_rootfs: partition@34B0000 {
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label = "Root Filesystem - JFFS2";
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reg = <0x034B0000 0x0EB50000>;
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};
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};
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};
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};
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&uart0 {
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status = "okay";
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};
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&usb0 {
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status = "okay";
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};
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&usb1 {
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status = "okay";
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};
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