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u-boot-imx-20211020

Browse source 
-------------------
 
 First PR from u-boot-imx for 2022.01
 
 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/9535
 
 - new board: kontron-sl-mx8mm
 - imx8m:
 	- fix secure boot
 - imx ESDHC: fixes
 - i.MX53: Support thum2, bmode and fixes for Menlo board
 	  usbarmory switch to Ethernet driver model
 - imx6 :
 	- DDR calibration for Toradex boards
 - imx7:
 	- Fixes
 - Updated gateworks boards (ventana / venice)
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Merge tag 'u-boot-imx-20211020' of https://source.denx.de/u-boot/custodians/u-boot-imx

u-boot-imx-20211020
-------------------

First PR from u-boot-imx for 2022.01

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/9535

- new board: kontron-sl-mx8mm
- imx8m:
	- fix secure boot
- imx ESDHC: fixes
- i.MX53: Support thum2, bmode and fixes for Menlo board
	  usbarmory switch to Ethernet driver model
- imx6 :
	- DDR calibration for Toradex boards
- imx7:
	- Fixes
- Updated gateworks boards (ventana / venice)

# gpg verification failed.
This commit is contained in:
Tom Rini 2021-10-20 14:24:09 -04:00
commit 79b8849d4c
123 changed files with 6594 additions and 533 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
Makefile
View file

@ -1339,9 +1339,6 @@ $(U_BOOT_ITS): $(subst ",,$(CONFIG_SPL_FIT_SOURCE))
else
ifneq ($(CONFIG_USE_SPL_FIT_GENERATOR),)
U_BOOT_ITS := u-boot.its
ifeq ($(CONFIG_SPL_FIT_GENERATOR),"arch/arm/mach-imx/mkimage_fit_atf.sh")
U_BOOT_ITS_DEPS += u-boot-nodtb.bin
endif
ifeq ($(CONFIG_SPL_FIT_GENERATOR),"arch/arm/mach-rockchip/make_fit_atf.py")
U_BOOT_ITS_DEPS += u-boot
endif

8
arch/arm/dts/Makefile
View file

@ -822,7 +822,9 @@ dtb-$(CONFIG_MX6UL) += \
imx6ul-liteboard.dtb \
imx6ul-phytec-segin-ff-rdk-nand.dtb \
imx6ul-pico-hobbit.dtb \
imx6ul-pico-pi.dtb
imx6ul-pico-pi.dtb \
imx6ul-kontron-n631x-s.dtb \
imx6ull-kontron-n641x-s.dtb
dtb-$(CONFIG_MX6ULL) += \
imx6ull-14x14-evk.dtb \
@ -877,6 +879,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mm-evk.dtb \
imx8mm-icore-mx8mm-ctouch2.dtb \
imx8mm-icore-mx8mm-edimm2.2.dtb \
imx8mm-kontron-n801x-s.dtb \
imx8mm-kontron-n801x-s-lvds.dtb \
imx8mm-venice.dtb \
imx8mm-venice-gw71xx-0x.dtb \
imx8mm-venice-gw72xx-0x.dtb \
@ -1144,6 +1148,8 @@ dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb
dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE) += imx8mm-cl-iot-gate.dtb
dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE_OPTEE) += imx8mm-cl-iot-gate-optee.dtb
dtb-$(CONFIG_TARGET_EA_LPC3250DEVKITV2) += lpc3250-ea3250.dtb
targets += $(dtb-y)

2
arch/arm/dts/imx53-m53menlo-u-boot.dtsi
View file

@ -7,7 +7,7 @@
soc {
u-boot,dm-pre-reloc;
aips@50000000 {
bus@50000000 {
u-boot,dm-pre-reloc;
};
};

1
arch/arm/dts/imx53-usbarmory.dts
View file

@ -91,6 +91,7 @@
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1>;
broken-cd;
status = "okay";
};

4
arch/arm/dts/imx53.dtsi
View file

@ -222,7 +222,7 @@
clock-names = "core_clk", "mem_iface_clk";
};
aips@50000000 { /* AIPS1 */
bus@50000000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@ -654,7 +654,7 @@
};
};
aips@60000000 { /* AIPS2 */
bus@60000000 { /* AIPS2 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;

11
arch/arm/dts/imx6-apalis-u-boot.dtsi Normal file
View file

@ -0,0 +1,11 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* Copyright 2020 Foundries.IO
*/
#include "imx6qdl-u-boot.dtsi"
&wdog1 {
status = "okay";
u-boot,dm-spl;
};

4
arch/arm/dts/imx6dl.dtsi
View file

@ -84,7 +84,7 @@
clocks = <&clks IMX6QDL_CLK_OCRAM>;
};
aips1: aips-bus@2000000 {
aips1: bus@2000000 {
iomuxc: iomuxc@20e0000 {
compatible = "fsl,imx6dl-iomuxc";
};
@ -100,7 +100,7 @@
};
};
aips2: aips-bus@2100000 {
aips2: bus@2100000 {
i2c4: i2c@21f8000 {
#address-cells = <1>;
#size-cells = <0>;

2
arch/arm/dts/imx6q-display5-u-boot.dtsi
View file

@ -23,7 +23,7 @@
soc {
u-boot,dm-pre-reloc;
aips-bus@2100000 {
bus@2100000 {
u-boot,dm-pre-reloc;
};
};

2
arch/arm/dts/imx6q.dtsi
View file

@ -162,7 +162,7 @@
clocks = <&clks IMX6QDL_CLK_OCRAM>;
};
aips-bus@2000000 { /* AIPS1 */
bus@2000000 { /* AIPS1 */
spba-bus@2000000 {
ecspi5: spi@2018000 {
#address-cells = <1>;

11
arch/arm/dts/imx6qdl-gw53xx.dtsi
View file

@ -137,7 +137,8 @@
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
@ -550,6 +551,8 @@
&usbh1 {
vbus-supply = <&reg_usb_h1_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1>;
status = "okay";
};
@ -720,6 +723,12 @@
>;
};
pinctrl_usbh1: usbh1grp {
fsl,pins = <
MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059

11
arch/arm/dts/imx6qdl-gw54xx.dtsi
View file

@ -146,7 +146,8 @@
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
gpio = <&gpio1 16 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usb_otg_vbus: regulator@3 {
@ -620,6 +621,8 @@
&usbh1 {
vbus-supply = <&reg_usb_h1_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1>;
status = "okay";
};
@ -815,6 +818,12 @@
>;
};
pinctrl_usbh1: usbh1grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059

21
arch/arm/dts/imx6qdl-gw552x.dtsi
View file

@ -121,6 +121,15 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_usb_h1_vbus: regulator-usbh1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&gpmi {
@ -390,9 +399,13 @@
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
status = "okay"; };
status = "okay";
};
&usbh1 {
vbus-supply = <&reg_usb_h1_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1>;
status = "okay";
};
@ -507,6 +520,12 @@
>;
};
pinctrl_usbh1: usbh1grp {
fsl,pins = <
MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x13059

3
arch/arm/dts/imx6qdl-gw560x.dtsi
View file

@ -221,7 +221,8 @@
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {

11
arch/arm/dts/imx6qdl-gw5904.dtsi
View file

@ -176,7 +176,8 @@
regulator-name = "usb_h1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usb_otg_vbus: regulator-usb-otg-vbus {
@ -593,6 +594,8 @@
&usbh1 {
vbus-supply = <&reg_usb_h1_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
status = "okay";
};
@ -753,6 +756,12 @@
>;
};
pinctrl_usbh1: usbh1grp {
fsl,pins = <
MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059

11
arch/arm/dts/imx6qdl-gw5912.dtsi
View file

@ -120,7 +120,8 @@
regulator-name = "usb_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
gpio = <&gpio4 5 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
@ -380,6 +381,8 @@
&usbh1 {
vbus-supply = <&reg_usb_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1>;
status = "okay";
};
@ -560,6 +563,12 @@
>;
};
pinctrl_usbh1: usbh1grp {
fsl,pins = <
MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059

4
arch/arm/dts/imx6qdl-u-boot.dtsi
View file

@ -13,14 +13,14 @@
u-boot,dm-spl;
u-boot,dm-pre-reloc;
aips-bus@2000000 {
bus@2000000 {
u-boot,dm-spl;
spba-bus@2000000 {
u-boot,dm-spl;
};
};
aips-bus@2100000 {
bus@2100000 {
u-boot,dm-spl;
};
};

4
arch/arm/dts/imx6qdl.dtsi
View file

@ -283,7 +283,7 @@
status = "disabled";
};
aips-bus@2000000 { /* AIPS1 */
bus@2000000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@ -913,7 +913,7 @@
};
};
aips-bus@2100000 { /* AIPS2 */
bus@2100000 { /* AIPS2 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;

2
arch/arm/dts/imx6qp.dtsi
View file

@ -18,7 +18,7 @@
clocks = <&clks IMX6QDL_CLK_OCRAM>;
};
aips-bus@2100000 {
bus@2100000 {
pre1: pre@21c8000 {
compatible = "fsl,imx6qp-pre";
reg = <0x021c8000 0x1000>;

4
arch/arm/dts/imx6sl.dtsi
View file

@ -130,7 +130,7 @@
interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
};
aips1: aips-bus@02000000 {
aips1: bus@02000000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@ -751,7 +751,7 @@
};
};
aips2: aips-bus@02100000 {
aips2: bus@02100000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;

4
arch/arm/dts/imx6sll.dtsi
View file

@ -176,7 +176,7 @@
arm,data-latency = <4 2 3>;
};
aips1: aips-bus@02000000 {
aips1: bus@02000000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@ -682,7 +682,7 @@
};
};
aips2: aips-bus@02100000 {
aips2: bus@02100000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;

6
arch/arm/dts/imx6sx.dtsi
View file

@ -235,7 +235,7 @@
status = "disabled";
};
aips1: aips-bus@2000000 {
aips1: bus@2000000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@ -830,7 +830,7 @@
};
};
aips2: aips-bus@2100000 {
aips2: bus@2100000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@ -1188,7 +1188,7 @@
};
};
aips3: aips-bus@2200000 {
aips3: bus@2200000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;

7
arch/arm/dts/imx6ul-kontron-n631x-s-u-boot.dtsi Normal file
View file

@ -0,0 +1,7 @@
// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright (C) 2017 exceet electronics GmbH
* Copyright (C) 2018 Kontron Electronics GmbH
*/
#include "imx6ul-kontron-n6x1x-s-u-boot.dtsi"

17
arch/arm/dts/imx6ul-kontron-n631x-s.dts Normal file
View file

@ -0,0 +1,17 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017 exceet electronics GmbH
* Copyright (C) 2018 Kontron Electronics GmbH
* Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
*/
/dts-v1/;
#include "imx6ul-kontron-n631x-som.dtsi"
#include "imx6ul-kontron-n6x1x-s.dtsi"
/ {
model = "Kontron N631X S";
compatible = "kontron,imx6ul-n631x-s", "kontron,imx6ul-n631x-som",
"fsl,imx6ul";
};

14
arch/arm/dts/imx6ul-kontron-n631x-som.dtsi Normal file
View file

@ -0,0 +1,14 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017 exceet electronics GmbH
* Copyright (C) 2018 Kontron Electronics GmbH
* Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
*/
#include "imx6ul.dtsi"
#include "imx6ul-kontron-n6x1x-som-common.dtsi"
/ {
model = "Kontron N631X SOM";
compatible = "kontron,imx6ul-n631x-som", "fsl,imx6ul";
};

63
arch/arm/dts/imx6ul-kontron-n6x1x-s-u-boot.dtsi Normal file
View file

@ -0,0 +1,63 @@
// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright (C) 2017 exceet electronics GmbH
* Copyright (C) 2018 Kontron Electronics GmbH
*/
#if defined(CONFIG_FIT)
/ {
binman: binman {
filename = "flash.bin";
pad-byte = <0x00>;
spl: blob-ext@1 {
offset = <0x0>;
filename = "SPL";
};
uboot: blob-ext@2 {
offset = <0x11000>;
filename = "u-boot.img";
};
};
};
#endif /* CONFIG_FIT */
/*
* To make the PHYs work, we need to set the reset pin once. Afterwards
* in Linux we can't assign the shared reset GPIO to the PHYs, as this
* would cause Linux to reset both PHYs every time one of them gets
* reinitialized.
*
* Also we disable the second ethernet as it currently doesn't work with
* the devicetree setup in U-Boot.
*/
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio>;
phy-mode = "rmii";
phy-handle = <&ethphy1>;
phy-reset-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@1 {
reg = <1>;
micrel,led-mode = <0>;
clocks = <&clks IMX6UL_CLK_ENET_REF>;
clock-names = "rmii-ref";
};
};
};
&fec2 {
status = "disabled";
/delete-property/ phy-handle;
/delete-node/ mdio;
};

423
arch/arm/dts/imx6ul-kontron-n6x1x-s.dts Normal file
View file

@ -0,0 +1,423 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017 exceet electronics GmbH
* Copyright (C) 2018 Kontron Electronics GmbH
* Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "imx6ul-kontron-n6x1x-som.dtsi"
/ {
gpio-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led1 {
label = "debug-led1";
gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
default-state = "off";
linux,default-trigger = "heartbeat";
};
led2 {
label = "debug-led2";
gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led3 {
label = "debug-led3";
gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
default-state = "off";
};
};
pwm-beeper {
compatible = "pwm-beeper";
pwms = <&pwm8 0 5000>;
};
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_5v: regulator-5v {
compatible = "regulator-fixed";
regulator-name = "5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_vref_adc: regulator-vref-adc {
compatible = "regulator-fixed";
regulator-name = "vref-adc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&adc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc1>;
num-channels = <3>;
vref-supply = <&reg_vref_adc>;
status = "okay";
};
&can2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
status = "okay";
};
&ecspi1 {
cs-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
eeprom@0 {
compatible = "anvo,anv32e61w", "atmel,at25";
reg = <0>;
spi-max-frequency = <20000000>;
spi-cpha;
spi-cpol;
pagesize = <1>;
size = <8192>;
address-width = <16>;
};
};
&fec1 {
pinctrl-0 = <&pinctrl_enet1>;
/delete-node/ mdio;
};
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>;
phy-mode = "rmii";
phy-handle = <&ethphy2>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@1 {
reg = <1>;
micrel,led-mode = <0>;
clocks = <&clks IMX6UL_CLK_ENET_REF>;
clock-names = "rmii-ref";
};
ethphy2: ethernet-phy@2 {
reg = <2>;
micrel,led-mode = <0>;
clocks = <&clks IMX6UL_CLK_ENET2_REF>;
clock-names = "rmii-ref";
};
};
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
};
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
rtc@32 {
compatible = "epson,rx8900";
reg = <0x32>;
};
};
&pwm8 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm8>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
linux,rs485-enabled-at-boot-time;
rs485-rx-during-tx;
rs485-rts-active-low;
uart-has-rtscts;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
fsl,uart-has-rtscts;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
&usbotg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1>;
dr_mode = "otg";
srp-disable;
hnp-disable;
adp-disable;
over-current-active-low;
vbus-supply = <&reg_usb_otg1_vbus>;
status = "okay";
};
&usbotg2 {
dr_mode = "host";
disable-over-current;
vbus-supply = <&reg_5v>;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
keep-power-in-suspend;
wakeup-source;
vmmc-supply = <&reg_3v3>;
voltage-ranges = <3300 3300>;
bus-width = <4>;
no-1-8-v;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
non-removable;
keep-power-in-suspend;
wakeup-source;
vmmc-supply = <&reg_3v3>;
voltage-ranges = <3300 3300>;
bus-width = <4>;
no-1-8-v;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl-0 = <&pinctrl_reset_out &pinctrl_gpio>;
pinctrl_adc1: adc1grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0xb0
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x100b1
MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x100b1
MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x100b1
MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x100b1 /* ECSPI1-CS1 */
>;
};
pinctrl_enet2: enet2grp {
fsl,pins = <
MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b009
>;
};
pinctrl_enet2_mdio: enet2mdiogrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
>;
};
pinctrl_flexcan2: flexcan2grp{
fsl,pins = <
MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
>;
};
pinctrl_gpio: gpiogrp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* DOUT1 */
MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* DIN1 */
MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1b0b0 /* DOUT2 */
MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* DIN2 */
>;
};
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b0b0 /* LED H14 */
MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* LED H15 */
MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* LED H16 */
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0
MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001f8b0
MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001f8b0
>;
};
pinctrl_pwm8: pwm8grp {
fsl,pins = <
MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x110b0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x1b0b1
MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x1b0b1
MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x1b0b1
/*
* mux unused RTS to make sure it doesn't cause
* any interrupts when it is undefined
*/
MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x1b0b1
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1
MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1
MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1
MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1
MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1
>;
};
pinctrl_usbotg1: usbotg1 {
fsl,pins = <
MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x1b0b0
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x100b1 /* SD1_CD */
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x30b0
>;
};
};

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@ -0,0 +1,420 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017 exceet electronics GmbH
* Copyright (C) 2018 Kontron Electronics GmbH
* Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
*/
#include <dt-bindings/gpio/gpio.h>
/ {
gpio-leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led1 {
label = "debug-led1";
gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
default-state = "off";
linux,default-trigger = "heartbeat";
};
led2 {
label = "debug-led2";
gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
default-state = "off";
};
led3 {
label = "debug-led3";
gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
default-state = "off";
};
};
pwm-beeper {
compatible = "pwm-beeper";
pwms = <&pwm8 0 5000>;
};
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_5v: regulator-5v {
compatible = "regulator-fixed";
regulator-name = "5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_usb_otg1_vbus: regulator-usb-otg1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_otg1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_vref_adc: regulator-vref-adc {
compatible = "regulator-fixed";
regulator-name = "vref-adc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
&adc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc1>;
num-channels = <3>;
vref-supply = <&reg_vref_adc>;
status = "okay";
};
&can2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
status = "okay";
};
&ecspi1 {
cs-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
eeprom@0 {
compatible = "anvo,anv32e61w", "atmel,at25";
reg = <0>;
spi-max-frequency = <20000000>;
spi-cpha;
spi-cpol;
pagesize = <1>;
size = <8192>;
address-width = <16>;
};
};
&fec1 {
pinctrl-0 = <&pinctrl_enet1>;
/delete-node/ mdio;
};
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio>;
phy-mode = "rmii";
phy-handle = <&ethphy2>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@1 {
reg = <1>;
micrel,led-mode = <0>;
clocks = <&clks IMX6UL_CLK_ENET_REF>;
clock-names = "rmii-ref";
};
ethphy2: ethernet-phy@2 {
reg = <2>;
micrel,led-mode = <0>;
clocks = <&clks IMX6UL_CLK_ENET2_REF>;
clock-names = "rmii-ref";
};
};
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
};
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
rtc@32 {
compatible = "epson,rx8900";
reg = <0x32>;
};
};
&pwm8 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm8>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
linux,rs485-enabled-at-boot-time;
rs485-rx-during-tx;
rs485-rts-active-low;
uart-has-rtscts;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
fsl,uart-has-rtscts;
status = "okay";
};
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
&usbotg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1>;
dr_mode = "otg";
srp-disable;
hnp-disable;
adp-disable;
over-current-active-low;
vbus-supply = <&reg_usb_otg1_vbus>;
status = "okay";
};
&usbotg2 {
dr_mode = "host";
disable-over-current;
vbus-supply = <&reg_5v>;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
keep-power-in-suspend;
wakeup-source;
vmmc-supply = <&reg_3v3>;
voltage-ranges = <3300 3300>;
bus-width = <4>;
no-1-8-v;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
non-removable;
keep-power-in-suspend;
wakeup-source;
vmmc-supply = <&reg_3v3>;
voltage-ranges = <3300 3300>;
bus-width = <4>;
no-1-8-v;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl-0 = <&pinctrl_reset_out &pinctrl_gpio>;
pinctrl_adc1: adc1grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0xb0
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6UL_PAD_CSI_DATA07__ECSPI1_MISO 0x100b1
MX6UL_PAD_CSI_DATA06__ECSPI1_MOSI 0x100b1
MX6UL_PAD_CSI_DATA04__ECSPI1_SCLK 0x100b1
MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x100b1 /* ECSPI1-CS1 */
>;
};
pinctrl_enet2: enet2grp {
fsl,pins = <
MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b009
>;
};
pinctrl_enet2_mdio: enet2mdiogrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
>;
};
pinctrl_flexcan2: flexcan2grp{
fsl,pins = <
MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
>;
};
pinctrl_gpio: gpiogrp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* DOUT1 */
MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* DIN1 */
MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x1b0b0 /* DOUT2 */
MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* DIN2 */
>;
};
pinctrl_gpio_leds: gpioledsgrp {
fsl,pins = <
MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b0b0 /* LED H14 */
MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* LED H15 */
MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* LED H16 */
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0
MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX6UL_PAD_UART2_TX_DATA__I2C4_SCL 0x4001f8b0
MX6UL_PAD_UART2_RX_DATA__I2C4_SDA 0x4001f8b0
>;
};
pinctrl_pwm8: pwm8grp {
fsl,pins = <
MX6UL_PAD_CSI_HSYNC__PWM8_OUT 0x110b0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6UL_PAD_NAND_DATA04__UART2_DCE_TX 0x1b0b1
MX6UL_PAD_NAND_DATA05__UART2_DCE_RX 0x1b0b1
MX6UL_PAD_NAND_DATA06__UART2_DCE_CTS 0x1b0b1
/*
* mux unused RTS to make sure it doesn't cause
* any interrupts when it is undefined
*/
MX6UL_PAD_NAND_DATA07__UART2_DCE_RTS 0x1b0b1
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX 0x1b0b1
MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX 0x1b0b1
MX6UL_PAD_UART3_CTS_B__UART3_DCE_CTS 0x1b0b1
MX6UL_PAD_UART3_RTS_B__UART3_DCE_RTS 0x1b0b1
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX 0x1b0b1
MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX 0x1b0b1
>;
};
pinctrl_usbotg1: usbotg1 {
fsl,pins = <
MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0x1b0b0
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x100b1 /* SD1_CD */
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10059
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO09__WDOG1_WDOG_ANY 0x30b0
>;
};
};

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arch/arm/dts/imx6ul-kontron-n6x1x-som-common.dtsi Normal file
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@ -0,0 +1,124 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017 exceet electronics GmbH
* Copyright (C) 2018 Kontron Electronics GmbH
* Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
*/
#include <dt-bindings/gpio/gpio.h>
/ {
chosen {
stdout-path = &uart4;
};
memory@80000000 {
reg = <0x80000000 0x10000000>;
device_type = "memory";
};
};
&ecspi2 {
cs-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
status = "okay";
spi-flash@0 {
compatible = "mxicy,mx25v8035f", "jedec,spi-nor";
spi-max-frequency = <50000000>;
reg = <0>;
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio>;
phy-mode = "rmii";
phy-handle = <&ethphy1>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@1 {
reg = <1>;
micrel,led-mode = <0>;
clocks = <&clks IMX6UL_CLK_ENET_REF>;
clock-names = "rmii-ref";
};
};
};
&fec2 {
phy-mode = "rmii";
status = "disabled";
};
&qspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi>;
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-nand";
spi-max-frequency = <104000000>;
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
reg = <0>;
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reset_out>;
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x100b1
MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x100b1
MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x100b1
MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x100b1
>;
};
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b009
>;
};
pinctrl_enet1_mdio: enet1mdiogrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
>;
};
pinctrl_qspi: qspigrp {
fsl,pins = <
MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
>;
};
pinctrl_reset_out: rstoutgrp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0
>;
};
};

4
arch/arm/dts/imx6ul.dtsi
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@ -206,7 +206,7 @@
status = "disabled";
};
aips1: aips-bus@2000000 {
aips1: bus@2000000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@ -763,7 +763,7 @@
};
};
aips2: aips-bus@2100000 {
aips2: bus@2100000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;

7
arch/arm/dts/imx6ull-kontron-n641x-s-u-boot.dtsi Normal file
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@ -0,0 +1,7 @@
// SPDX-License-Identifier: GPL-2.0 OR MIT
/*
* Copyright (C) 2017 exceet electronics GmbH
* Copyright (C) 2018 Kontron Electronics GmbH
*/
#include "imx6ul-kontron-n6x1x-s-u-boot.dtsi"

16
arch/arm/dts/imx6ull-kontron-n641x-s.dts Normal file
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@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017 exceet electronics GmbH
* Copyright (C) 2019 Kontron Electronics GmbH
*/
/dts-v1/;
#include "imx6ull-kontron-n641x-som.dtsi"
#include "imx6ul-kontron-n6x1x-s.dtsi"
/ {
model = "Kontron N641X S";
compatible = "kontron,imx6ull-n641x-s", "kontron,imx6ull-n641x-som",
"fsl,imx6ull";
};

13
arch/arm/dts/imx6ull-kontron-n641x-som.dtsi Normal file
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@ -0,0 +1,13 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2017 exceet electronics GmbH
* Copyright (C) 2018 Kontron Electronics GmbH
*/
#include "imx6ull.dtsi"
#include "imx6ul-kontron-n6x1x-som-common.dtsi"
/ {
model = "Kontron N641X SOM";
compatible = "kontron,imx6ull-n641x-som", "fsl,imx6ull";
};

2
arch/arm/dts/imx6ull.dtsi
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@ -44,7 +44,7 @@
/ {
soc {
aips3: aips-bus@2200000 {
aips3: bus@2200000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;

6
arch/arm/dts/imx7s.dtsi
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@ -340,7 +340,7 @@
<0x31006000 0x2000>;
};
aips1: aips-bus@30000000 {
aips1: bus@30000000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@ -647,7 +647,7 @@
};
};
aips2: aips-bus@30400000 {
aips2: bus@30400000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@ -739,7 +739,7 @@
};
};
aips3: aips-bus@30800000 {
aips3: bus@30800000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;

255
arch/arm/dts/imx8mm-cl-iot-gate-optee-u-boot.dtsi Normal file
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@ -0,0 +1,255 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019 NXP
*/
/ {
binman: binman {
multiple-images;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
u-boot,dm-spl;
};
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
};
&{/soc@0} {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
};
&clk {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ assigned-clock-rates;
};
&osc_24m {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
&aips1 {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
&aips2 {
u-boot,dm-spl;
};
&aips3 {
u-boot,dm-spl;
};
&iomuxc {
u-boot,dm-spl;
};
&pinctrl_uart3 {
u-boot,dm-spl;
};
&pinctrl_usdhc2_gpio {
u-boot,dm-spl;
};
&pinctrl_usdhc2 {
u-boot,dm-spl;
};
&pinctrl_usdhc3 {
u-boot,dm-spl;
};
&gpio1 {
u-boot,dm-spl;
};
&gpio2 {
u-boot,dm-spl;
};
&gpio3 {
u-boot,dm-spl;
};
&gpio4 {
u-boot,dm-spl;
};
&gpio5 {
u-boot,dm-spl;
};
&uart3 {
u-boot,dm-spl;
};
&usdhc1 {
u-boot,dm-spl;
};
&usdhc2 {
u-boot,dm-spl;
};
&usdhc3 {
u-boot,dm-spl;
};
&i2c1 {
u-boot,dm-spl;
};
&i2c2 {
u-boot,dm-spl;
};
&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b} {
u-boot,dm-spl;
};
&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b/regulators} {
u-boot,dm-spl;
};
&pinctrl_i2c2 {
u-boot,dm-spl;
};
&pinctrl_pmic {
u-boot,dm-spl;
};
&fec1 {
phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
};
&wdog1 {
u-boot,dm-spl;
};
&binman {
u-boot-spl-ddr {
filename = "u-boot-spl-ddr.bin";
pad-byte = <0xff>;
align-size = <4>;
align = <4>;
u-boot-spl {
align-end = <4>;
};
blob_1: blob-ext@1 {
filename = "lpddr4_pmu_train_1d_imem.bin";
size = <0x8000>;
};
blob_2: blob-ext@2 {
filename = "lpddr4_pmu_train_1d_dmem.bin";
size = <0x4000>;
};
blob_3: blob-ext@3 {
filename = "lpddr4_pmu_train_2d_imem.bin";
size = <0x8000>;
};
blob_4: blob-ext@4 {
filename = "lpddr4_pmu_train_2d_dmem.bin";
size = <0x4000>;
};
};
flash {
mkimage {
args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x7e1000";
blob {
filename = "u-boot-spl-ddr.bin";
};
};
};
itb {
filename = "u-boot.itb";
fit {
description = "Configuration to load ATF before U-Boot";
#address-cells = <1>;
fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
images {
uboot {
description = "U-Boot (64-bit)";
type = "standalone";
arch = "arm64";
compression = "none";
load = <CONFIG_SYS_TEXT_BASE>;
uboot_blob: blob-ext {
filename = "u-boot-nodtb.bin";
};
};
atf {
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
compression = "none";
load = <0x920000>;
entry = <0x920000>;
atf_blob: blob-ext {
filename = "bl2.bin";
};
};
fip {
description = "Trusted Firmware FIP";
type = "firmware";
arch = "arm64";
compression = "none";
load = <0x40310000>;
fip_blob: blob-ext{
filename = "fip.bin";
};
};
fdt {
description = "NAME";
type = "flat_dt";
compression = "none";
uboot_fdt_blob: blob-ext {
filename = "u-boot.dtb";
};
};
};
configurations {
default = "conf";
conf {
description = "NAME";
firmware = "uboot";
loadables = "atf", "fip";
fdt = "fdt";
};
};
};
};
};

6
arch/arm/dts/imx8mm-cl-iot-gate-optee.dts Normal file
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@ -0,0 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2019 NXP
*/
#include "imx8mm-cl-iot-gate.dts"

14
arch/arm/dts/imx8mm-cl-iot-gate-u-boot.dtsi
View file

@ -217,18 +217,6 @@
};
};
fip {
description = "Trusted Firmware FIP";
type = "firmware";
arch = "arm64";
compression = "none";
load = <0x40310000>;
fip_blob: blob-ext{
filename = "fip.bin";
};
};
fdt {
description = "NAME";
type = "flat_dt";
@ -246,7 +234,7 @@
conf {
description = "NAME";
firmware = "uboot";
loadables = "atf", "fip";
loadables = "atf";
fdt = "fdt";
};
};

116
arch/arm/dts/imx8mm-kontron-n801x-s-lvds.dts Normal file
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@ -0,0 +1,116 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 Kontron Electronics GmbH
*/
#include "imx8mm-kontron-n801x-s.dts"
/ {
model = "Kontron i.MX8MM N801X S LVDS";
compatible = "kontron,imx8mm-n801x-s-lvds", "fsl,imx8mm";
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm1 0 50000>; /* period = 5000000 ns => f = 200 Hz */
power-supply = <&reg_vdd_24v>;
brightness-levels = <0 100>;
num-interpolated-steps = <100>;
default-brightness-level = <100>;
status = "okay";
};
reg_panel_pwr: regpanel-pwr {
compatible = "regulator-fixed";
regulator-name = "reg_panel_pwr";
regulator-always-on;
gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_panel_rst: regpanel-rst {
compatible = "regulator-fixed";
regulator-name = "reg_panel_rst";
regulator-always-on;
gpio = <&gpio3 20 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_panel_stby: regpanel-stby {
compatible = "regulator-fixed";
regulator-name = "reg_panel_stby";
regulator-always-on;
gpio = <&gpio3 21 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_panel_hinv: regpanel-hinv {
compatible = "regulator-fixed";
regulator-name = "reg_panel_hinv";
regulator-always-on;
gpio = <&gpio3 24 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_panel_vinv: regpanel-vinv {
compatible = "regulator-fixed";
regulator-name = "reg_panel_vinv";
gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_vdd_24v: regulator-24v {
compatible = "regulator-fixed";
regulator-name = "reg-vdd-24v";
regulator-min-microvolt = <24000000>;
regulator-max-microvolt = <24000000>;
regulator-boot-on;
regulator-always-on;
status = "okay";
};
};
&i2c2 {
status = "okay";
gt911@5d {
compatible = "goodix,gt928";
reg = <0x5d>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_touch>;
interrupt-parent = <&gpio3>;
interrupts = <22 8>;
reset-gpios = <&gpio3 23 0>;
irq-gpios = <&gpio3 22 0>;
};
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&iomuxc {
pinctrl_panel: panelgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x19 /* TFT-PWR - family */
MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19 /* RESET family */
MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19 /* STBY family */
MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x19 /* HINV panel */
MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19 /* VINV panel */
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x6
>;
};
pinctrl_touch: touchgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19 /* Touch Interrupt */
MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19 /* Touch Reset */
>;
};
};

274
arch/arm/dts/imx8mm-kontron-n801x-s-u-boot.dtsi Normal file
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@ -0,0 +1,274 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Kontron Electronics GmbH
*/
#include "imx8mm-u-boot.dtsi"
/ {
aliases {
usb0 = &usbotg1;
usb1 = &usbotg2;
};
binman: binman {
multiple-images;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
u-boot,dm-spl;
};
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
};
};
};
&fec1 {
phy-mode = "rgmii-rxid";
};
&i2c1 {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
&i2c2 {
status = "okay";
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
&pinctrl_ecspi1 {
u-boot,dm-spl;
};
&pinctrl_i2c1 {
u-boot,dm-spl;
};
&pinctrl_pmic {
u-boot,dm-spl;
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141
/* Disable Pullup for SD_VSEL */
MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x41
>;
};
&pinctrl_uart3 {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
&pinctrl_usdhc1 {
u-boot,dm-spl;
};
&pinctrl_usdhc1_100mhz {
u-boot,dm-spl;
};
&pinctrl_usdhc1_200mhz {
u-boot,dm-spl;
};
&pinctrl_usdhc2 {
u-boot,dm-spl;
};
&pca9450 {
u-boot,dm-spl;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@25/regulators} {
u-boot,dm-spl;
};
&ecspi1 {
u-boot,dm-spl;
};
&gpio1 {
u-boot,dm-spl;
};
&gpio2 {
u-boot,dm-spl;
};
&gpio3 {
u-boot,dm-spl;
};
&gpio4 {
u-boot,dm-spl;
};
&gpio5 {
u-boot,dm-spl;
};
&uart3 {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
&usdhc1 {
u-boot,dm-spl;
};
&usdhc2 {
u-boot,dm-spl;
};
&wdog1 {
u-boot,dm-spl;
};
&binman {
u-boot-spl-ddr {
filename = "u-boot-spl-ddr.bin";
pad-byte = <0xff>;
align-size = <4>;
align = <4>;
u-boot-spl {
align-end = <4>;
};
blob_1: blob-ext@1 {
filename = "lpddr4_pmu_train_1d_imem.bin";
size = <0x8000>;
};
blob_2: blob-ext@2 {
filename = "lpddr4_pmu_train_1d_dmem.bin";
size = <0x4000>;
};
blob_3: blob-ext@3 {
filename = "lpddr4_pmu_train_2d_imem.bin";
size = <0x8000>;
};
blob_4: blob-ext@4 {
filename = "lpddr4_pmu_train_2d_dmem.bin";
size = <0x4000>;
};
};
spl {
filename = "spl.bin";
mkimage {
args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x7e1000";
blob {
filename = "u-boot-spl-ddr.bin";
};
};
};
itb {
filename = "u-boot.itb";
fit {
description = "Configuration to load ATF before U-Boot";
#address-cells = <1>;
fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
images {
uboot {
description = "U-Boot (64-bit)";
type = "standalone";
arch = "arm64";
compression = "none";
load = <CONFIG_SYS_TEXT_BASE>;
uboot_blob: blob-ext {
filename = "u-boot-nodtb.bin";
};
};
atf {
description = "ARM Trusted Firmware";
type = "firmware";
arch = "arm64";
compression = "none";
load = <0x920000>;
entry = <0x920000>;
atf_blob: blob-ext {
filename = "bl31.bin";
};
};
fdt {
description = "NAME";
type = "flat_dt";
compression = "none";
uboot_fdt_blob: blob-ext {
filename = "u-boot.dtb";
};
};
};
configurations {
default = "conf";
conf {
description = "NAME";
firmware = "uboot";
loadables = "atf";
fdt = "fdt";
};
};
};
};
imx-boot {
filename = "flash.bin";
pad-byte = <0x00>;
spl: blob-ext@1 {
offset = <0x0>;
filename = "spl.bin";
};
uboot: blob-ext@2 {
offset = <0x57c00>;
filename = "u-boot.itb";
};
};
u-boot-update {
filename = "firmware-update.itb";
fit {
description = "Configuration for firmware update file";
images {
flash-bin {
description = "U-Boot flash image";
type = "firmware";
os = "u-boot";
arch = "arm";
compress = "none";
load = <0>; /* unused */
blob {
filename = "flash.bin";
};
};
};
};
};
};

388
arch/arm/dts/imx8mm-kontron-n801x-s.dts Normal file
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@ -0,0 +1,388 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2019 Kontron Electronics GmbH
*/
/dts-v1/;
#include "imx8mm-kontron-n801x-som.dtsi"
#include <dt-bindings/net/mscc-phy-vsc8531.h>
/ {
model = "Kontron i.MX8MM N801X S";
compatible = "kontron,imx8mm-n801x-s", "kontron,imx8mm-n801x-som", "fsl,imx8mm";
aliases {
ethernet1 = &usbnet;
};
/* fixed crystal dedicated to mcp2515 */
osc_can: clock-osc-can {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <16000000>;
clock-output-names = "osc-can";
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_led>;
led1 {
label = "led1";
gpios = <&gpio4 17 GPIO_ACTIVE_LOW>;
linux,default-trigger = "heartbeat";
};
led2 {
label = "led2";
gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
};
led3 {
label = "led3";
gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
};
led4 {
label = "led4";
gpios = <&gpio4 8 GPIO_ACTIVE_LOW>;
};
led5 {
label = "led5";
gpios = <&gpio4 9 GPIO_ACTIVE_LOW>;
};
led6 {
label = "led6";
gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
};
};
pwm-beeper {
compatible = "pwm-beeper";
pwms = <&pwm2 0 5000 0>;
};
reg_rst_eth2: regulator-rst-eth2 {
compatible = "regulator-fixed";
regulator-name = "rst-usb-eth2";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_eth2>;
gpio = <&gpio3 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
reg_vdd_5v: regulator-5v {
compatible = "regulator-fixed";
regulator-name = "vdd-5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
};
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
status = "okay";
can0: can@0 {
compatible = "microchip,mcp2515";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can>;
clocks = <&osc_can>;
interrupt-parent = <&gpio4>;
interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
spi-max-frequency = <10000000>;
vdd-supply = <&reg_vdd_3v3>;
xceiver-supply = <&reg_vdd_5v>;
};
};
&ecspi3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>;
status = "okay";
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-connection-type = "rgmii-rxid";
phy-handle = <&ethphy>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy: ethernet-phy@0 {
compatible = "ethernet-phy-id0007.0570";
reg = <0>;
reset-assert-us = <100>;
reset-deassert-us = <100>;
reset-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>;
vsc8531,led-0-mode = <VSC8531_LINK_100_1000_ACTIVITY>;
vsc8531,led-1-mode = <VSC8531_LINK_ACTIVITY>;
vsc8531,led-0-combine-disable;
};
};
};
&gpio4 {
dsi_mux_sel: dsi_mux_sel {
gpio-hog;
gpios = <14 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "dsi-mux-sel";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dsi_sel>;
};
dsi_mux_oe {
gpio-hog;
gpios = <15 GPIO_ACTIVE_LOW>;
output-high;
line-name = "dsi-mux-oe";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dsi_oe>;
};
};
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
rtc@32 {
compatible = "epson,rx8900";
reg = <0x32>;
};
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
uart-has-rtscts;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
linux,rs485-enabled-at-boot-time;
uart-has-rtscts;
status = "okay";
};
&usbotg1 {
dr_mode = "otg";
over-current-active-low;
status = "okay";
};
&usbotg2 {
dr_mode = "host";
disable-over-current;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
usb1@1 {
compatible = "usb424,9514";
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
usbnet: usbether@1 {
compatible = "usb424,ec00";
reg = <1>;
local-mac-address = [ 00 00 00 00 00 00 ];
};
};
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
vmmc-supply = <&reg_vdd_3v3>;
vqmmc-supply = <&reg_nvcc_sd>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio>;
pinctrl_can: cangrp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19
>;
};
pinctrl_dsi_sel: dsiselgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x19
>;
};
pinctrl_dsi_oe: dsioegrp {
fsl,pins = <
MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x19
>;
};
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x19
>;
};
pinctrl_ecspi3: ecspi3grp {
fsl,pins = <
MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x82
MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x82
MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x82
MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x19
>;
};
pinctrl_enet: enetgrp {
fsl,pins = <
MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19 /* PHY RST */
MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x19 /* ETH IRQ */
>;
};
pinctrl_gpio_led: gpioledgrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x19
MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x19
MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x19
MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x19
MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19
MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19
>;
};
pinctrl_gpio: gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19
MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19
MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19
MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x19
MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19
MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x19
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x140
MX8MM_IOMUXC_SAI2_RXFS_UART1_DCE_TX 0x140
MX8MM_IOMUXC_SAI2_RXD0_UART1_DCE_RTS_B 0x140
MX8MM_IOMUXC_SAI2_TXFS_UART1_DCE_CTS_B 0x140
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140
MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140
MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140
MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140
>;
};
pinctrl_usb_eth2: usbeth2grp {
fsl,pins = <
MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x19
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019
>;
};
};

299
arch/arm/dts/imx8mm-kontron-n801x-som.dtsi Normal file
View file

@ -0,0 +1,299 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2019 Kontron Electronics GmbH
*/
#include "imx8mm.dtsi"
/ {
model = "Kontron i.MX8MM N801X SoM";
compatible = "kontron,imx8mm-n801x-som", "fsl,imx8mm";
memory@40000000 {
device_type = "memory";
/*
* There are multiple SoM flavors with different DDR sizes.
* The smallest is 1GB. For larger sizes the bootloader will
* update the reg property.
*/
reg = <0x0 0x40000000 0 0x80000000>;
};
chosen {
stdout-path = &uart3;
};
};
&A53_0 {
cpu-supply = <&reg_vdd_arm>;
};
&A53_1 {
cpu-supply = <&reg_vdd_arm>;
};
&A53_2 {
cpu-supply = <&reg_vdd_arm>;
};
&A53_3 {
cpu-supply = <&reg_vdd_arm>;
};
&ddrc {
operating-points-v2 = <&ddrc_opp_table>;
ddrc_opp_table: opp-table {
compatible = "operating-points-v2";
opp-25M {
opp-hz = /bits/ 64 <25000000>;
};
opp-100M {
opp-hz = /bits/ 64 <100000000>;
};
opp-750M {
opp-hz = /bits/ 64 <750000000>;
};
};
};
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
status = "okay";
spi-flash@0 {
compatible = "mxicy,mx25r1635f", "jedec,spi-nor";
spi-max-frequency = <80000000>;
reg = <0>;
};
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pca9450: pmic@25 {
compatible = "nxp,pca9450a";
reg = <0x25>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio1>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
regulators {
reg_vdd_soc: BUCK1 {
regulator-name = "buck1";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <850000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
nxp,dvs-run-voltage = <850000>;
nxp,dvs-standby-voltage = <800000>;
};
reg_vdd_arm: BUCK2 {
regulator-name = "buck2";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <950000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
nxp,dvs-run-voltage = <950000>;
nxp,dvs-standby-voltage = <850000>;
};
reg_vdd_dram: BUCK3 {
regulator-name = "buck3";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <950000>;
regulator-boot-on;
regulator-always-on;
};
reg_vdd_3v3: BUCK4 {
regulator-name = "buck4";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
reg_vdd_1v8: BUCK5 {
regulator-name = "buck5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_nvcc_dram: BUCK6 {
regulator-name = "buck6";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-boot-on;
regulator-always-on;
};
reg_nvcc_snvs: LDO1 {
regulator-name = "ldo1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_vdd_snvs: LDO2 {
regulator-name = "ldo2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
regulator-boot-on;
regulator-always-on;
};
reg_vdda: LDO3 {
regulator-name = "ldo3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_vdd_phy: LDO4 {
regulator-name = "ldo4";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
regulator-always-on;
};
reg_nvcc_sd: LDO5 {
regulator-name = "ldo5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
};
};
};
&uart3 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
vmmc-supply = <&reg_vdd_3v3>;
vqmmc-supply = <&reg_vdd_1v8>;
bus-width = <8>;
non-removable;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x19
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141
MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x141
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0
MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0
MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0
MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0
MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4
MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4
MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4
MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4
MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6
MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6
MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6
MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6
MX8MM_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0x019
MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>;
};
};

62
arch/arm/dts/imx8mm-venice-gw700x-u-boot.dtsi
View file

@ -3,59 +3,7 @@
* Copyright 2021 Gateworks Corporation
*/
#include "imx8mm-u-boot.dtsi"
&gpio1 {
u-boot,dm-spl;
};
&gpio2 {
u-boot,dm-spl;
};
&gpio3 {
u-boot,dm-spl;
};
&gpio4 {
u-boot,dm-spl;
};
&gpio5 {
u-boot,dm-spl;
};
&uart2 {
u-boot,dm-spl;
};
&pinctrl_uart2 {
u-boot,dm-spl;
};
&usdhc3 {
u-boot,dm-spl;
};
&pinctrl_usdhc3 {
u-boot,dm-spl;
};
&i2c1 {
u-boot,dm-spl;
};
&pinctrl_i2c1 {
u-boot,dm-spl;
};
&i2c2 {
u-boot,dm-spl;
};
&pinctrl_i2c2 {
u-boot,dm-spl;
};
#include "imx8mm-venice-u-boot.dtsi"
&fec1 {
phy-reset-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
@ -63,6 +11,10 @@
phy-reset-post-delay = <1>;
};
&pinctrl_fec1 {
u-boot,dm-spl;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@69} {
u-boot,dm-spl;
};
@ -70,3 +22,7 @@
&{/soc@0/bus@30800000/i2c@30a20000/pmic@69/regulators} {
u-boot,dm-spl;
};
&pinctrl_pmic {
u-boot,dm-spl;
};

56
arch/arm/dts/imx8mm-venice-gw700x.dtsi
View file

@ -282,65 +282,83 @@
reg = <0x69>;
regulators {
/* vdd_0p95: DRAM/GPU/VPU */
buck1 {
regulator-name = "vdd_0p95";
regulator-min-microvolt = <805000>;
regulator-name = "buck1";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1000000>;
regulator-max-microamp = <2500000>;
regulator-min-microamp = <3800000>;
regulator-max-microamp = <6800000>;
regulator-boot-on;
regulator-always-on;
};
/* vdd_soc */
buck2 {
regulator-name = "vdd_soc";
regulator-min-microvolt = <805000>;
regulator-name = "buck2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <900000>;
regulator-max-microamp = <1000000>;
regulator-min-microamp = <2200000>;
regulator-max-microamp = <5200000>;
regulator-boot-on;
regulator-always-on;
};
/* vdd_arm */
buck3_reg: buck3 {
regulator-name = "vdd_arm";
regulator-min-microvolt = <805000>;
regulator-name = "buck3";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1000000>;
regulator-max-microamp = <2200000>;
regulator-boot-on;
regulator-min-microamp = <3800000>;
regulator-max-microamp = <6800000>;
regulator-always-on;
};
/* vdd_1p8 */
buck4 {
regulator-name = "vdd_1p8";
regulator-name = "buck4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-max-microamp = <500000>;
regulator-min-microamp = <2200000>;
regulator-max-microamp = <5200000>;
regulator-boot-on;
regulator-always-on;
};
/* nvcc_snvs_1p8 */
ldo1 {
regulator-name = "nvcc_snvs_1p8";
regulator-name = "ldo1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-max-microamp = <300000>;
regulator-boot-on;
regulator-always-on;
};
/* vdd_snvs_0p8 */
ldo2 {
regulator-name = "vdd_snvs_0p8";
regulator-name = "ldo2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
regulator-boot-on;
regulator-always-on;
};
/* vdd_0p9 */
ldo3 {
regulator-name = "vdd_0p95";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
regulator-name = "ldo3";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
regulator-always-on;
};
/* vdd_1p8 */
ldo4 {
regulator-name = "vdd_1p8";
regulator-name = "ldo4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
};
};

66
arch/arm/dts/imx8mm-venice-gw7901-u-boot.dtsi
View file

@ -3,67 +3,7 @@
* Copyright 2020 Gateworks Corporation
*/
#include "imx8mm-u-boot.dtsi"
&gpio1 {
u-boot,dm-spl;
};
&gpio2 {
u-boot,dm-spl;
};
&gpio3 {
u-boot,dm-spl;
};
&gpio4 {
u-boot,dm-spl;
};
&gpio5 {
u-boot,dm-spl;
};
&uart2 {
u-boot,dm-spl;
};
&pinctrl_uart2 {
u-boot,dm-spl;
};
&usdhc2 {
u-boot,dm-spl;
};
&pinctrl_usdhc2 {
u-boot,dm-spl;
};
&usdhc3 {
u-boot,dm-spl;
};
&pinctrl_usdhc3 {
u-boot,dm-spl;
};
&i2c1 {
u-boot,dm-spl;
};
&pinctrl_i2c1 {
u-boot,dm-spl;
};
&i2c2 {
u-boot,dm-spl;
};
&pinctrl_i2c2 {
u-boot,dm-spl;
};
#include "imx8mm-venice-u-boot.dtsi"
&fec1 {
phy-reset-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
@ -71,6 +11,10 @@
phy-reset-post-delay = <1>;
};
&pinctrl_fec1 {
u-boot,dm-spl;
};
&{/soc@0/bus@30800000/i2c@30a30000/pmic@4b} {
u-boot,dm-spl;
};

12
arch/arm/dts/imx8mm-venice-gw7901.dts
View file

@ -1041,15 +1041,3 @@
>;
};
};
&cpu_alert0 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
&cpu_crit0 {
temperature = <105000>;
hysteresis = <2000>;
type = "critical";
};

54
arch/arm/dts/imx8mm-venice-gw7902-u-boot.dtsi
View file

@ -3,59 +3,7 @@
* Copyright 2021 Gateworks Corporation
*/
#include "imx8mm-u-boot.dtsi"
&gpio1 {
u-boot,dm-spl;
};
&gpio2 {
u-boot,dm-spl;
};
&gpio3 {
u-boot,dm-spl;
};
&gpio4 {
u-boot,dm-spl;
};
&gpio5 {
u-boot,dm-spl;
};
&uart2 {
u-boot,dm-spl;
};
&pinctrl_uart2 {
u-boot,dm-spl;
};
&usdhc3 {
u-boot,dm-spl;
};
&pinctrl_usdhc3 {
u-boot,dm-spl;
};
&i2c1 {
u-boot,dm-spl;
};
&pinctrl_i2c1 {
u-boot,dm-spl;
};
&i2c2 {
u-boot,dm-spl;
};
&pinctrl_i2c2 {
u-boot,dm-spl;
};
#include "imx8mm-venice-u-boot.dtsi"
&fec1 {
phy-reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;

12
arch/arm/dts/imx8mm-venice-gw7902.dts
View file

@ -913,15 +913,3 @@
>;
};
};
&cpu_alert0 {
temperature = <95000>;
hysteresis = <2000>;
type = "passive";
};
&cpu_crit0 {
temperature = <105000>;
hysteresis = <2000>;
type = "critical";
};

2
arch/arm/dts/imx8mm-verdin.dts
View file

@ -160,7 +160,7 @@
&fec1 {
fsl,magic-packet;
phy-handle = <&ethphy0>;
phy-mode = "rgmii";
phy-mode = "rgmii-id";
phy-supply = <&reg_ethphy>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_fec1>;

19
arch/arm/dts/imx8mp-u-boot.dtsi
View file

@ -79,7 +79,9 @@
};
};
flash {
spl {
filename = "spl.bin";
mkimage {
args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x920000";
@ -146,4 +148,19 @@
};
};
};
imx-boot {
filename = "flash.bin";
pad-byte = <0x00>;
spl: blob-ext@1 {
filename = "spl.bin";
offset = <0x0>;
};
uboot: blob-ext@2 {
filename = "u-boot.itb";
offset = <0x58000>;
};
};
};

4
arch/arm/dts/vf.dtsi
View file

@ -34,7 +34,7 @@
compatible = "simple-bus";
ranges;
aips0: aips-bus@40000000 {
aips0: bus@40000000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
@ -158,7 +158,7 @@
};
};
aips1: aips-bus@40080000 {
aips1: bus@40080000 {
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;

21
arch/arm/include/asm/mach-imx/iomux-v3.h
View file

@ -87,15 +87,6 @@ typedef u64 iomux_v3_cfg_t;
#define MUX_MODE_LPSR ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \
MUX_MODE_SHIFT)
#ifdef CONFIG_IMX8M
#define PAD_CTL_DSE0 (0x0 << 0)
#define PAD_CTL_DSE1 (0x1 << 0)
#define PAD_CTL_DSE2 (0x2 << 0)
#define PAD_CTL_DSE3 (0x3 << 0)
#define PAD_CTL_DSE4 (0x4 << 0)
#define PAD_CTL_DSE5 (0x5 << 0)
#define PAD_CTL_DSE6 (0x6 << 0)
#define PAD_CTL_DSE7 (0x7 << 0)
#define PAD_CTL_FSEL0 (0x0 << 3)
#define PAD_CTL_FSEL1 (0x1 << 3)
#define PAD_CTL_FSEL2 (0x2 << 3)
@ -105,8 +96,20 @@ typedef u64 iomux_v3_cfg_t;
#define PAD_CTL_PUE (0x1 << 6)
#define PAD_CTL_HYS (0x1 << 7)
#if defined(CONFIG_IMX8MM) || defined(CONFIG_IMX8MN) || defined(CONFIG_IMX8MP)
#define PAD_CTL_DSE1 (0x0 << 1)
#define PAD_CTL_DSE2 (0x2 << 1)
#define PAD_CTL_DSE4 (0x1 << 1)
#define PAD_CTL_DSE6 (0x3 << 1)
#define PAD_CTL_PE (0x1 << 8)
#else
#define PAD_CTL_DSE0 (0x0 << 0)
#define PAD_CTL_DSE1 (0x1 << 0)
#define PAD_CTL_DSE2 (0x2 << 0)
#define PAD_CTL_DSE3 (0x3 << 0)
#define PAD_CTL_DSE4 (0x4 << 0)
#define PAD_CTL_DSE5 (0x5 << 0)
#define PAD_CTL_DSE6 (0x6 << 0)
#define PAD_CTL_DSE7 (0x7 << 0)
#define PAD_CTL_LVTTL (0x1 << 8)
#endif

2
arch/arm/mach-imx/Kconfig
View file

@ -48,7 +48,7 @@ config USE_IMXIMG_PLUGIN
config IMX_HAB
bool "Support i.MX HAB features"
depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX5 || ARCH_IMX8M
depends on ARCH_MX7 || ARCH_MX6 || ARCH_MX5 || ARCH_IMX8M || ARCH_MX7ULP
select FSL_CAAM if HAS_CAAM
imply CMD_DEKBLOB if HAS_CAAM
help

13
arch/arm/mach-imx/Makefile
View file

@ -114,8 +114,7 @@ endif
DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o u-boot-dtb.cfgout $(srctree)/$(IMX_CONFIG); if [ -f u-boot-dtb.cfgout ]; then $(CNTR_DEPFILES) u-boot-dtb.cfgout; echo $$?; fi)
else ifeq ($(CONFIG_ARCH_IMX8M), y)
IMAGE_TYPE := imx8mimage
IMX8M_DEPFILES := $(srctree)/tools/imx8m_image.sh
DEPFILE_EXISTS := $(shell $(CPP) $(cpp_flags) -x c -o spl/u-boot-spl.cfgout $(srctree)/$(IMX_CONFIG);if [ -f spl/u-boot-spl.cfgout ]; then $(IMX8M_DEPFILES) spl/u-boot-spl.cfgout 0; echo $$?; fi)
DEPFILE_EXISTS := 0
else
IMAGE_TYPE := imximage
DEPFILE_EXISTS := 0
@ -150,16 +149,18 @@ endif
ifdef CONFIG_ARM64
ifeq ($(CONFIG_ARCH_IMX8M), y)
SPL:
SPL: spl/u-boot-spl.bin spl/u-boot-spl.cfgout FORCE
MKIMAGEFLAGS_flash.bin = -n spl/u-boot-spl.cfgout \
-T $(IMAGE_TYPE) -e $(CONFIG_SPL_TEXT_BASE)
flash.bin: MKIMAGEOUTPUT = flash.log
spl/u-boot-spl.cfgout: $(IMX_CONFIG) FORCE
$(Q)mkdir -p $(dir $@)
$(call if_changed_dep,cpp_cfg)
spl/u-boot-spl-ddr.bin: spl/u-boot-spl.bin spl/u-boot-spl.cfgout FORCE
ifeq ($(DEPFILE_EXISTS),0)
$(IMX8M_DEPFILES) spl/u-boot-spl.cfgout 1
endif
flash.bin: spl/u-boot-spl-ddr.bin u-boot.itb FORCE
$(call if_changed,mkimage)

15
arch/arm/mach-imx/imx8m/Kconfig
View file

@ -75,6 +75,13 @@ config TARGET_IMX8MM_VENICE
select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_KONTRON_MX8MM
bool "Kontron Electronics N80xx"
select BINMAN
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_IMX8MN_EVK
bool "imx8mn LPDDR4 EVK board"
select BINMAN
@ -138,6 +145,13 @@ config TARGET_IMX8MM_CL_IOT_GATE
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_IMX8MM_CL_IOT_GATE_OPTEE
bool "CompuLab iot-gate-imx8 with optee support"
select BINMAN
select IMX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
endchoice
source "board/beacon/imx8mm/Kconfig"
@ -150,6 +164,7 @@ source "board/freescale/imx8mn_evk/Kconfig"
source "board/freescale/imx8mp_evk/Kconfig"
source "board/gateworks/venice/Kconfig"
source "board/google/imx8mq_phanbell/Kconfig"
source "board/kontron/sl-mx8mm/Kconfig"
source "board/phytec/phycore_imx8mm/Kconfig"
source "board/phytec/phycore_imx8mp/Kconfig"
source "board/ronetix/imx8mq-cm/Kconfig"

16
arch/arm/mach-imx/imx8m/soc.c
View file

@ -298,16 +298,26 @@ phys_size_t get_effective_memsize(void)
ulong board_get_usable_ram_top(ulong total_size)
{
ulong top_addr = PHYS_SDRAM + gd->ram_size;
/*
* Some IPs have their accessible address space restricted by
* the interconnect. Let's make sure U-Boot only ever uses the
* space below the 4G address boundary (which is 3GiB big),
* even when the effective available memory is bigger.
*/
if (PHYS_SDRAM + gd->ram_size > 0x80000000)
return 0x80000000;
if (top_addr > 0x80000000)
top_addr = 0x80000000;
return PHYS_SDRAM + gd->ram_size;
/*
* rom_pointer[0] stores the TEE memory start address.
* rom_pointer[1] stores the size TEE uses.
* We need to reserve the memory region for TEE.
*/
if (rom_pointer[0] && rom_pointer[1] && top_addr > rom_pointer[0])
top_addr = rom_pointer[0];
return top_addr;
}
static u32 get_cpu_variant_type(u32 type)

143
arch/arm/mach-imx/mkimage_fit_atf.sh
View file

@ -1,143 +0,0 @@
#!/bin/sh
# SPDX-License-Identifier: GPL-2.0+
#
# script to generate FIT image source for i.MX8MQ boards with
# ARM Trusted Firmware and multiple device trees (given on the command line)
#
# usage: $0 <dt_name> [<dt_name> [<dt_name] ...]
[ -z "$BL31" ] && BL31="bl31.bin"
[ -z "$TEE_LOAD_ADDR" ] && TEE_LOAD_ADDR="0xfe000000"
[ -z "$ATF_LOAD_ADDR" ] && ATF_LOAD_ADDR="0x00910000"
[ -z "$BL33_LOAD_ADDR" ] && BL33_LOAD_ADDR="0x40200000"
if [ ! -f $BL31 ]; then
echo "ERROR: BL31 file $BL31 NOT found" >&2
exit 0
else
echo "$BL31 size: " >&2
stat -c %s $BL31 >&2
fi
BL32="tee.bin"
if [ ! -f $BL32 ]; then
BL32=/dev/null
else
echo "Building with TEE support, make sure your $BL31 is compiled with spd. If you do not want tee, please delete $BL31" >&2
echo "$BL32 size: " >&2
stat -c %s $BL32 >&2
fi
BL33="u-boot-nodtb.bin"
if [ ! -f $BL33 ]; then
echo "ERROR: $BL33 file NOT found" >&2
exit 0
else
echo "u-boot-nodtb.bin size: " >&2
stat -c %s u-boot-nodtb.bin >&2
fi
for dtname in $*
do
echo "$dtname size: " >&2
stat -c %s $dtname >&2
done
cat << __HEADER_EOF
/dts-v1/;
/ {
description = "Configuration to load ATF before U-Boot";
images {
uboot@1 {
description = "U-Boot (64-bit)";
os = "u-boot";
data = /incbin/("$BL33");
type = "standalone";
arch = "arm64";
compression = "none";
load = <$BL33_LOAD_ADDR>;
};
__HEADER_EOF
cnt=1
for dtname in $*
do
cat << __FDT_IMAGE_EOF
fdt@$cnt {
description = "$(basename $dtname .dtb)";
data = /incbin/("$dtname");
type = "flat_dt";
compression = "none";
};
__FDT_IMAGE_EOF
cnt=$((cnt+1))
done
cat << __HEADER_EOF
atf@1 {
description = "ARM Trusted Firmware";
os = "arm-trusted-firmware";
data = /incbin/("$BL31");
type = "firmware";
arch = "arm64";
compression = "none";
load = <$ATF_LOAD_ADDR>;
entry = <$ATF_LOAD_ADDR>;
};
__HEADER_EOF
if [ -f $BL32 ]; then
cat << __HEADER_EOF
tee@1 {
description = "TEE firmware";
data = /incbin/("$BL32");
type = "firmware";
arch = "arm64";
compression = "none";
load = <$TEE_LOAD_ADDR>;
entry = <$TEE_LOAD_ADDR>;
};
__HEADER_EOF
fi
cat << __CONF_HEADER_EOF
};
configurations {
default = "config@1";
__CONF_HEADER_EOF
cnt=1
for dtname in $*
do
if [ -f $BL32 ]; then
cat << __CONF_SECTION_EOF
config@$cnt {
description = "$(basename $dtname .dtb)";
firmware = "uboot@1";
loadables = "atf@1", "tee@1";
fdt = "fdt@$cnt";
};
__CONF_SECTION_EOF
else
cat << __CONF_SECTION1_EOF
config@$cnt {
description = "$(basename $dtname .dtb)";
firmware = "uboot@1";
loadables = "atf@1";
fdt = "fdt@$cnt";
};
__CONF_SECTION1_EOF
fi
cnt=$((cnt+1))
done
cat << __ITS_EOF
};
};
__ITS_EOF

10
arch/arm/mach-imx/mx6/Kconfig
View file

@ -230,6 +230,15 @@ config TARGET_GW_VENTANA
imply CMD_SATA
imply CMD_SPL
config TARGET_KONTRON_MX6UL
bool "Kontron Electronics SL/BL i.MX6UL/ULL (N63xx/N64xx)"
depends on MX6UL
select BINMAN
select DM
select DM_THERMAL
select SUPPORT_SPL
imply CMD_DM
config TARGET_KOSAGI_NOVENA
bool "Kosagi Novena"
select BOARD_LATE_INIT
@ -668,6 +677,7 @@ source "board/grinn/liteboard/Kconfig"
source "board/phytec/pcm058/Kconfig"
source "board/phytec/pcl063/Kconfig"
source "board/gateworks/gw_ventana/Kconfig"
source "board/kontron/sl-mx6ul/Kconfig"
source "board/kosagi/novena/Kconfig"
source "board/softing/vining_2000/Kconfig"
source "board/liebherr/display5/Kconfig"

31
arch/arm/mach-imx/mx7ulp/soc.c
View file

@ -93,14 +93,31 @@ int board_postclk_init(void)
static void disable_wdog(u32 wdog_base)
{
writel(UNLOCK_WORD0, (wdog_base + 0x04));
writel(UNLOCK_WORD1, (wdog_base + 0x04));
writel(0x0, (wdog_base + 0x0C)); /* Set WIN to 0 */
writel(0x400, (wdog_base + 0x08)); /* Set timeout to default 0x400 */
writel(0x120, (wdog_base + 0x00)); /* Disable it and set update */
u32 val_cs = readl(wdog_base + 0x00);
writel(REFRESH_WORD0, (wdog_base + 0x04)); /* Refresh the CNT */
writel(REFRESH_WORD1, (wdog_base + 0x04));
if (!(val_cs & 0x80))
return;
dmb();
__raw_writel(REFRESH_WORD0, (wdog_base + 0x04)); /* Refresh the CNT */
__raw_writel(REFRESH_WORD1, (wdog_base + 0x04));
dmb();
if (!(val_cs & 800)) {
dmb();
__raw_writel(UNLOCK_WORD0, (wdog_base + 0x04));
__raw_writel(UNLOCK_WORD1, (wdog_base + 0x04));
dmb();
while (!(readl(wdog_base + 0x00) & 0x800));
}
dmb();
__raw_writel(0x0, wdog_base + 0x0C); /* Set WIN to 0 */
__raw_writel(0x400, wdog_base + 0x08); /* Set timeout to default 0x400 */
__raw_writel(0x120, wdog_base + 0x00); /* Disable it and set update */
dmb();
while (!(readl(wdog_base + 0x00) & 0x400));
}
void init_wdog(void)

47
arch/arm/mach-imx/spl.c
View file

@ -334,6 +334,20 @@ void board_spl_fit_post_load(const void *fit)
}
#endif
void *board_spl_fit_buffer_addr(ulong fit_size, int sectors, int bl_len)
{
int align_len = ARCH_DMA_MINALIGN - 1;
/* Some devices like SDP, NOR, NAND, SPI are using bl_len =1, so their fit address
* is different with SD/MMC, this cause mismatch with signed address. Thus, adjust
* the bl_len to align with SD/MMC.
*/
if (bl_len < 512)
bl_len = 512;
return (void *)((CONFIG_SYS_TEXT_BASE - fit_size - bl_len -
align_len) & ~align_len);
}
#endif
#if defined(CONFIG_MX6) && defined(CONFIG_SPL_OS_BOOT)
@ -345,3 +359,36 @@ int dram_init_banksize(void)
return 0;
}
#endif
/*
* read the address where the IVT header must sit
* from IVT image header, loaded from SPL into
* an malloced buffer and copy the IVT header
* to this address
*/
void *spl_load_simple_fit_fix_load(const void *fit)
{
struct ivt *ivt;
unsigned long new;
unsigned long offset;
unsigned long size;
u8 *tmp = (u8 *)fit;
offset = ALIGN(fdt_totalsize(fit), 0x1000);
size = ALIGN(fdt_totalsize(fit), 4);
size = board_spl_fit_size_align(size);
tmp += offset;
ivt = (struct ivt *)tmp;
if (ivt->hdr.magic != IVT_HEADER_MAGIC) {
debug("no IVT header found\n");
return (void *)fit;
}
debug("%s: ivt: %p offset: %lx size: %lx\n", __func__, ivt, offset, size);
debug("%s: ivt self: %x\n", __func__, ivt->self);
new = ivt->self;
new -= offset;
debug("%s: new %lx\n", __func__, new);
memcpy((void *)new, fit, size);
return (void *)new;
}

2
board/compulab/imx8mm-cl-iot-gate/Kconfig
View file

@ -1,4 +1,4 @@
if TARGET_IMX8MM_CL_IOT_GATE
if TARGET_IMX8MM_CL_IOT_GATE || TARGET_IMX8MM_CL_IOT_GATE_OPTEE
config SYS_BOARD
default "imx8mm-cl-iot-gate"

1
board/compulab/imx8mm-cl-iot-gate/MAINTAINERS
View file

@ -4,3 +4,4 @@ S: Maintained
F: board/compulab/imx8mm-cl-iot-gate/
F: include/configs/imx8mm-cl-iot-gate.h
F: configs/imx8mm-cl-iot-gate_defconfig
F: configs/imx8mm-cl-iot-gate-optee_defconfig

25
board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c
View file

@ -6,6 +6,7 @@
#include <common.h>
#include <env.h>
#include <hang.h>
#include <init.h>
#include <miiphy.h>
#include <netdev.h>
@ -14,8 +15,32 @@
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
#include "ddr/ddr.h"
DECLARE_GLOBAL_DATA_PTR;
int board_phys_sdram_size(phys_size_t *size)
{
struct lpddr4_tcm_desc *lpddr4_tcm_desc =
(struct lpddr4_tcm_desc *)TCM_DATA_CFG;
switch (lpddr4_tcm_desc->size) {
case 4096:
case 2048:
case 1024:
*size = (1L << 20) * lpddr4_tcm_desc->size;
break;
default:
printf("%s: DRAM size %uM is not supported\n",
__func__,
lpddr4_tcm_desc->size);
hang();
break;
};
return 0;
}
static int setup_fec(void)
{
if (IS_ENABLED(CONFIG_FEC_MXC)) {

2
board/freescale/imx8mp_evk/imximage-8mp-lpddr4.cfg
View file

@ -7,4 +7,4 @@
ROM_VERSION v2
BOOT_FROM sd
LOADER mkimage.flash.mkimage 0x920000
LOADER u-boot-spl-ddr.bin 0x920000

102
board/gateworks/gw_ventana/gw_ventana.c
View file

@ -39,41 +39,6 @@ DECLARE_GLOBAL_DATA_PTR;
struct ventana_board_info ventana_info;
static int board_type;
#ifdef CONFIG_USB_EHCI_MX6
/* toggle USB_HUB_RST# for boards that have it; it is not defined in dt */
int board_ehci_hcd_init(int port)
{
int gpio;
/* USB HUB is always on P1 */
if (port == 0)
return 0;
/* Reset USB HUB */
switch (board_type) {
case GW53xx:
case GW552x:
case GW5906:
gpio = (IMX_GPIO_NR(1, 9));
break;
case GW54proto:
case GW54xx:
gpio = (IMX_GPIO_NR(1, 16));
break;
default:
return 0;
}
/* request and toggle hub rst */
gpio_request(gpio, "usb_hub_rst#");
gpio_direction_output(gpio, 0);
mdelay(2);
gpio_set_value(gpio, 1);
return 0;
}
#endif /* CONFIG_USB_EHCI_MX6 */
/* configure eth0 PHY board-specific LED behavior */
int board_phy_config(struct phy_device *phydev)
{
@ -158,25 +123,54 @@ static void enable_hdmi(struct display_info_t const *dev)
imx_enable_hdmi_phy();
}
static int detect_i2c(struct display_info_t const *dev)
static int detect_lvds(struct display_info_t const *dev)
{
/* only the following boards support LVDS connectors */
switch (board_type) {
case GW52xx:
case GW53xx:
case GW54xx:
case GW560x:
case GW5905:
case GW5909:
break;
default:
return 0;
}
return i2c_set_bus_num(dev->bus) == 0 &&
i2c_probe(dev->addr) == 0;
}
static void enable_lvds(struct display_info_t const *dev)
{
struct iomuxc *iomux = (struct iomuxc *)
IOMUXC_BASE_ADDR;
struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
u32 reg = readl(&iomux->gpr[2]);
reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
writel(reg, &iomux->gpr[2]);
/* Enable Backlight */
gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio");
gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
/* Configure GPIO */
switch (board_type) {
case GW52xx:
case GW53xx:
case GW54xx:
if (!strncmp(dev->mode.name, "Hannstar", 8)) {
SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
gpio_request(IMX_GPIO_NR(1, 10), "cabc");
gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
} else if (!strncmp(dev->mode.name, "DLC", 3)) {
SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
gpio_request(IMX_GPIO_NR(1, 10), "touch_rst#");
gpio_direction_output(IMX_GPIO_NR(1, 10), 1);
}
break;
default:
break;
}
/* Configure backlight */
gpio_request(IMX_GPIO_NR(1, 18), "bklt_en");
SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
@ -208,7 +202,7 @@ struct display_info_t const displays[] = {{
.bus = 2,
.addr = 0x4,
.pixfmt = IPU_PIX_FMT_LVDS666,
.detect = detect_i2c,
.detect = detect_lvds,
.enable = enable_lvds,
.mode = {
.name = "Hannstar-XGA",
@ -228,7 +222,7 @@ struct display_info_t const displays[] = {{
/* DLC700JMG-T-4 */
.bus = 2,
.addr = 0x38,
.detect = NULL,
.detect = detect_lvds,
.enable = enable_lvds,
.pixfmt = IPU_PIX_FMT_LVDS666,
.mode = {
@ -247,9 +241,9 @@ struct display_info_t const displays[] = {{
.vmode = FB_VMODE_NONINTERLACED
} }, {
/* DLC0700XDP21LF-C-1 */
.bus = 0,
.addr = 0,
.detect = NULL,
.bus = 2,
.addr = 0x38,
.detect = detect_lvds,
.enable = enable_lvds,
.pixfmt = IPU_PIX_FMT_LVDS666,
.mode = {
@ -270,7 +264,7 @@ struct display_info_t const displays[] = {{
/* DLC800FIG-T-3 */
.bus = 2,
.addr = 0x14,
.detect = NULL,
.detect = detect_lvds,
.enable = enable_lvds,
.pixfmt = IPU_PIX_FMT_LVDS666,
.mode = {
@ -290,7 +284,7 @@ struct display_info_t const displays[] = {{
} }, {
.bus = 2,
.addr = 0x5d,
.detect = detect_i2c,
.detect = detect_lvds,
.enable = enable_lvds,
.pixfmt = IPU_PIX_FMT_LVDS666,
.mode = {
@ -358,10 +352,6 @@ static void setup_display(void)
| (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
writel(reg, &iomux->gpr[3]);
/* LVDS Backlight GPIO on LVDS connector - output low */
SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
}
#endif /* CONFIG_VIDEO_IPUV3 */
@ -1047,6 +1037,14 @@ int ft_board_setup(void *blob, struct bd_info *bd)
ft_board_pci_fixup(blob, bd);
#endif
/*
* remove reset gpio control as we configure the PHY registers
* for internal delay, LED config, and clock config in the bootloader
*/
i = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-fec");
if (i)
fdt_delprop(blob, i, "phy-reset-gpios");
/*
* Peripheral Config:
* remove nodes by alias path if EEPROM config tells us the

3
board/gateworks/venice/gsc.c
View file

@ -527,6 +527,9 @@ static int gsc_info(int verbose)
printf("%d\n", buf[0] | buf[1] << 8 | buf[2] << 16 | buf[3] << 24);
}
/* Display hwmon */
gsc_hwmon();
return 0;
}

21
board/gateworks/venice/imx8mm_venice.c
View file

@ -114,7 +114,8 @@ int board_late_init(void)
led_default_state();
/* Set board serial/model */
env_set_ulong("serial#", gsc_get_serial());
if (!env_get("serial#"))
env_set_ulong("serial#", gsc_get_serial());
env_set("model", gsc_get_model());
/* Set fdt_file vars */
@ -155,8 +156,26 @@ int board_mmc_get_env_dev(int devno)
int ft_board_setup(void *blob, struct bd_info *bd)
{
int off;
/* set board model dt prop */
fdt_setprop_string(blob, 0, "board", gsc_get_model());
/* update temp thresholds */
off = fdt_path_offset(blob, "/thermal-zones/cpu-thermal/trips");
if (off >= 0) {
int minc, maxc, prop;
get_cpu_temp_grade(&minc, &maxc);
fdt_for_each_subnode(prop, blob, off) {
const char *type = fdt_getprop(blob, prop, "type", NULL);
if (type && (!strcmp("critical", type)))
fdt_setprop_u32(blob, prop, "temperature", maxc * 1000);
else if (type && (!strcmp("passive", type)))
fdt_setprop_u32(blob, prop, "temperature", (maxc - 10) * 1000);
}
}
return 0;
}

15
board/kontron/sl-mx6ul/Kconfig Normal file
View file

@ -0,0 +1,15 @@
if TARGET_KONTRON_MX6UL
config SYS_BOARD
string
default "sl-mx6ul"
config SYS_VENDOR
string
default "kontron"
config SYS_CONFIG_NAME
string
default "kontron-sl-mx6ul"
endif

9
board/kontron/sl-mx6ul/MAINTAINERS Normal file
View file

@ -0,0 +1,9 @@
Kontron SL/BL i.MX6UL/ULL Boards (N63xx/N64xx)
M: Frieder Schrempf <frieder.schrempf@kontron.de>
S: Maintained
F: arch/arm/dts/imx6ul-kontron-n6*
F: arch/arm/dts/imx6ull-kontron-n6*
F: board/kontron/sl-mx6ul
F: configs/kontron-sl-mx6ul_defconfig
F: doc/board/kontron/sl-mx6ul.rst
F: include/configs/kontron-sl-mx6ul.h

8
board/kontron/sl-mx6ul/Makefile Normal file
View file

@ -0,0 +1,8 @@
# SPDX-License-Identifier: GPL-2.0+
# (C) Copyright 2018 Kontron Electronics GmbH
ifdef CONFIG_SPL_BUILD
obj-y := spl.o
else
obj-y := sl-mx6ul.o
endif

85
board/kontron/sl-mx6ul/sl-mx6ul.c Normal file
View file

@ -0,0 +1,85 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Kontron Electronics GmbH
*/
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/global_data.h>
#include <fdt_support.h>
#include <phy.h>
DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
gd->ram_size = imx_ddr_size();
return 0;
}
int ft_board_setup(void *blob, struct bd_info *bd)
{
/*
* Overwrite the memory size in the devicetree that is
* passed to the kernel with the actual size detected.
*/
return fdt_fixup_memory(blob, PHYS_SDRAM, gd->ram_size);
}
static int setup_fec(void)
{
struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
int ret;
/*
* Use 50M anatop loopback REF_CLK1 for ENET1,
* clear gpr1[13], set gpr1[17].
*/
clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
/*
* Use 50M anatop loopback REF_CLK2 for ENET2,
* clear gpr1[14], set gpr1[18].
*/
clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
ret = enable_fec_anatop_clock(0, ENET_50MHZ);
if (ret)
return ret;
ret = enable_fec_anatop_clock(1, ENET_50MHZ);
if (ret)
return ret;
return 0;
}
int board_phy_config(struct phy_device *phydev)
{
phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
int board_early_init_f(void)
{
enable_qspi_clk(0);
return 0;
}
int board_init(void)
{
/* Address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
setup_fec();
return 0;
}

377
board/kontron/sl-mx6ul/spl.c Normal file
View file

@ -0,0 +1,377 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Kontron Electronics GmbH
*/
#include <asm/arch/clock.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/mach-imx/iomux-v3.h>
#include <fsl_esdhc_imx.h>
#include <init.h>
#include <linux/delay.h>
#include <linux/sizes.h>
#include <linux/errno.h>
#include <mmc.h>
DECLARE_GLOBAL_DATA_PTR;
enum {
BOARD_TYPE_KTN_N631X = 1,
BOARD_TYPE_KTN_N641X,
BOARD_TYPE_MAX
};
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define USDHC_CD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
#include <spl.h>
#include <asm/arch/mx6-ddr.h>
static iomux_v3_cfg_t const usdhc1_pads[] = {
MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
/* CD */
MX6_PAD_UART1_RTS_B__GPIO1_IO19 | MUX_PAD_CTRL(USDHC_CD_PAD_CTRL),
};
#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 19)
static iomux_v3_cfg_t const usdhc2_pads[] = {
MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
/* RST */
MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
#define USDHC2_PWR_GPIO IMX_GPIO_NR(4, 10)
static struct fsl_esdhc_cfg usdhc_cfg[2] = {
{USDHC1_BASE_ADDR, 0, 4},
{USDHC2_BASE_ADDR, 0, 4},
};
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
switch (cfg->esdhc_base) {
case USDHC1_BASE_ADDR:
ret = !gpio_get_value(USDHC1_CD_GPIO);
break;
case USDHC2_BASE_ADDR:
// This SDHC interface does not use a CD pin
ret = 1;
break;
}
return ret;
}
int board_mmc_init(struct bd_info *bis)
{
int i, ret;
/*
* According to the board_mmc_init() the following map is done:
* (U-boot device node) (Physical Port)
* mmc0 USDHC1
* mmc1 USDHC2
*/
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
gpio_direction_input(USDHC1_CD_GPIO);
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
break;
case 1:
imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
gpio_direction_output(USDHC2_PWR_GPIO, 0);
udelay(500);
gpio_direction_output(USDHC2_PWR_GPIO, 1);
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
break;
default:
printf("Warning: you configured more USDHC controllers (%d) than supported by the board\n",
i + 1);
return -EINVAL;
}
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
if (ret) {
printf("Warning: failed to initialize mmc dev %d\n", i);
return ret;
}
}
return 0;
}
iomux_v3_cfg_t const ecspi2_pads[] = {
MX6_PAD_CSI_DATA00__ECSPI2_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_CSI_DATA02__ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_CSI_DATA03__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_CSI_DATA01__GPIO4_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
int board_spi_cs_gpio(unsigned int bus, unsigned int cs)
{
return (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS)
? (IMX_GPIO_NR(4, 22)) : -1;
}
static void setup_spi(void)
{
gpio_request(IMX_GPIO_NR(4, 22), "spi2_cs0");
gpio_direction_output(IMX_GPIO_NR(4, 22), 1);
imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads));
enable_spi_clk(true, 1);
}
static iomux_v3_cfg_t const uart4_pads[] = {
MX6_PAD_UART4_TX_DATA__UART4_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_UART4_RX_DATA__UART4_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
}
// DDR 256MB (Hynix H5TQ2G63DFR)
static struct mx6_ddr3_cfg mem_256M_ddr = {
.mem_speed = 800,
.density = 2,
.width = 16,
.banks = 8,
.rowaddr = 14,
.coladdr = 10,
.pagesz = 2,
.trcd = 1350,
.trcmin = 4950,
.trasmin = 3600,
};
static struct mx6_mmdc_calibration mx6_mmcd_256M_calib = {
.p0_mpwldectrl0 = 0x00000000,
.p0_mpdgctrl0 = 0x01340134,
.p0_mprddlctl = 0x40405052,
.p0_mpwrdlctl = 0x40404E48,
};
// DDR 512MB (Hynix H5TQ4G63DFR)
static struct mx6_ddr3_cfg mem_512M_ddr = {
.mem_speed = 800,
.density = 4,
.width = 16,
.banks = 8,
.rowaddr = 15,
.coladdr = 10,
.pagesz = 2,
.trcd = 1350,
.trcmin = 4950,
.trasmin = 3600,
};
static struct mx6_mmdc_calibration mx6_mmcd_512M_calib = {
.p0_mpwldectrl0 = 0x00000000,
.p0_mpdgctrl0 = 0X01440144,
.p0_mprddlctl = 0x40405454,
.p0_mpwrdlctl = 0x40404E4C,
};
// Common DDR parameters (256MB and 512MB)
static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
.grp_addds = 0x00000028,
.grp_ddrmode_ctl = 0x00020000,
.grp_b0ds = 0x00000028,
.grp_ctlds = 0x00000028,
.grp_b1ds = 0x00000028,
.grp_ddrpke = 0x00000000,
.grp_ddrmode = 0x00020000,
.grp_ddr_type = 0x000c0000,
};
static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
.dram_dqm0 = 0x00000028,
.dram_dqm1 = 0x00000028,
.dram_ras = 0x00000028,
.dram_cas = 0x00000028,
.dram_odt0 = 0x00000028,
.dram_odt1 = 0x00000028,
.dram_sdba2 = 0x00000000,
.dram_sdclk_0 = 0x00000028,
.dram_sdqs0 = 0x00000028,
.dram_sdqs1 = 0x00000028,
.dram_reset = 0x00000028,
};
struct mx6_ddr_sysinfo ddr_sysinfo = {
.dsize = 0,
.cs_density = 20,
.ncs = 1,
.cs1_mirror = 0,
.rtt_wr = 2,
.rtt_nom = 1, /* RTT_Nom = RZQ/2 */
.walat = 1, /* Write additional latency */
.ralat = 5, /* Read additional latency */
.mif3_mode = 3, /* Command prediction working mode */
.bi_on = 1, /* Bank interleaving enabled */
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
.ddr_type = DDR_TYPE_DDR3,
.refsel = 0, /* Refresh cycles at 64KHz */
.refr = 1, /* 2 refresh commands per refresh cycle */
};
static void ccgr_init(void)
{
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
writel(0xFFFFFFFF, &ccm->CCGR0);
writel(0xFFFFFFFF, &ccm->CCGR1);
writel(0xFFFFFFFF, &ccm->CCGR2);
writel(0xFFFFFFFF, &ccm->CCGR3);
writel(0xFFFFFFFF, &ccm->CCGR4);
writel(0xFFFFFFFF, &ccm->CCGR5);
writel(0xFFFFFFFF, &ccm->CCGR6);
writel(0xFFFFFFFF, &ccm->CCGR7);
}
static void spl_dram_init(void)
{
unsigned int size;
// DDR RAM connection is always 16 bit wide. Init IOs.
mx6ul_dram_iocfg(16, &mx6_ddr_ioregs, &mx6_grp_ioregs);
// Try to detect the 512MB RAM chip first.
mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_512M_calib, &mem_512M_ddr);
// Get the available RAM size
size = get_ram_size((void *)PHYS_SDRAM, SZ_512M);
gd->ram_size = size;
if (size == SZ_512M) {
// 512MB RAM was detected
return;
} else if (size == SZ_256M) {
// 256MB RAM was detected, use correct config and calibration
mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_256M_calib, &mem_256M_ddr);
} else {
printf("Invalid DDR RAM size detected: %x\n", size);
}
}
static int do_board_detect(void)
{
if (is_mx6ul())
gd->board_type = BOARD_TYPE_KTN_N631X;
else if (is_mx6ull())
gd->board_type = BOARD_TYPE_KTN_N641X;
printf("Kontron SL i.MX6UL%s (N6%s1x) module, %lu MB RAM detected\n",
is_mx6ull() ? "L" : "", is_mx6ull() ? "4" : "3", gd->ram_size / SZ_1M);
return 0;
}
void board_init_f(ulong dummy)
{
ccgr_init();
/* setup AIPS and disable watchdog */
arch_cpu_init();
/* iomux and setup of UART and SPI */
board_early_init_f();
/* setup GP timer */
timer_init();
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
/* DDR initialization */
spl_dram_init();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
/* Detect the board type */
do_board_detect();
/* load/boot image from boot device */
board_init_r(NULL, 0);
}
void board_boot_order(u32 *spl_boot_list)
{
u32 bootdev = spl_boot_device();
/*
* The default boot fuse settings use the SD card (MMC1) as primary
* boot device, but allow SPI NOR as a fallback boot device.
* We can't detect the fallback case and spl_boot_device() will return
* BOOT_DEVICE_MMC1 despite the actual boot device being SPI NOR.
* Therefore we try to load U-Boot proper vom SPI NOR after loading
* from MMC has failed.
*/
spl_boot_list[0] = bootdev;
switch (bootdev) {
case BOOT_DEVICE_MMC1:
case BOOT_DEVICE_MMC2:
spl_boot_list[1] = BOOT_DEVICE_SPI;
break;
}
}
int board_early_init_f(void)
{
setup_iomux_uart();
setup_spi();
return 0;
}
int board_fit_config_name_match(const char *name)
{
if (gd->board_type == BOARD_TYPE_KTN_N631X && is_mx6ul() &&
!strcmp(name, "imx6ul-kontron-n631x-s"))
return 0;
if (gd->board_type == BOARD_TYPE_KTN_N641X && is_mx6ull() &&
!strcmp(name, "imx6ull-kontron-n641x-s"))
return 0;
return -1;
}

15
board/kontron/sl-mx8mm/Kconfig Normal file
View file

@ -0,0 +1,15 @@
if TARGET_KONTRON_MX8MM
config SYS_BOARD
string
default "sl-mx8mm"
config SYS_VENDOR
string
default "kontron"
config SYS_CONFIG_NAME
string
default "kontron-sl-mx8mm"
endif

8
board/kontron/sl-mx8mm/MAINTAINERS Normal file
View file

@ -0,0 +1,8 @@
Kontron SL/BL i.MX8M Mini Boards (N801x)
M: Frieder Schrempf <frieder.schrempf@kontron.de>
S: Maintained
F: arch/arm/dts/imx8mm-kontron-n801x-*
F: board/kontron/sl-mx8mm
F: configs/kontron-sl-mx8mm_defconfig
F: doc/board/kontron/sl-mx8mm.rst
F: include/configs/kontron-sl-mx8mm.h

9
board/kontron/sl-mx8mm/Makefile Normal file
View file

@ -0,0 +1,9 @@
# SPDX-License-Identifier: GPL-2.0+
# (C) Copyright 2019 Kontron Electronics GmbH
obj-y := sl-mx8mm.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o
endif

9
board/kontron/sl-mx8mm/imximage.cfg Normal file
View file

@ -0,0 +1,9 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Kontron Electronics GmbH
*/
#define __ASSEMBLY__
BOOT_FROM sd
LOADER u-boot-spl-ddr.bin 0x7E1000

1844
board/kontron/sl-mx8mm/lpddr4_timing.c Normal file
View file

File diff suppressed because it is too large Load diff

99
board/kontron/sl-mx8mm/sl-mx8mm.c Normal file
View file

@ -0,0 +1,99 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Kontron Electronics GmbH
*/
#include <asm/arch/imx-regs.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <fdt_support.h>
#include <linux/errno.h>
#include <net.h>
DECLARE_GLOBAL_DATA_PTR;
int board_phys_sdram_size(phys_size_t *size)
{
u32 ddr_size = readl(M4_BOOTROM_BASE_ADDR);
if (ddr_size == 4) {
*size = 0x100000000;
} else if (ddr_size == 3) {
*size = 0xc0000000;
} else if (ddr_size == 2) {
*size = 0x80000000;
} else if (ddr_size == 1) {
*size = 0x40000000;
} else {
printf("Unknown DDR type!!!\n");
*size = 0x40000000;
}
return 0;
}
/*
* If the SoM is mounted on a baseboard with a USB ethernet controller,
* there might be an additional MAC address programmed to the MAC OTP fuses.
* Although the i.MX8MM has only one MAC, the MAC0, MAC1 and MAC2 registers
* in the OTP fuses can still be used to store two separate addresses.
* Try to read the secondary address from MAC1 and MAC2 and adjust the
* devicetree so Linux can pick up the MAC address.
*/
int fdt_set_usb_eth_addr(void *blob)
{
u32 value = readl(OCOTP_BASE_ADDR + 0x660);
unsigned char mac[6];
int node, ret;
mac[0] = value >> 24;
mac[1] = value >> 16;
mac[2] = value >> 8;
mac[3] = value;
value = readl(OCOTP_BASE_ADDR + 0x650);
mac[4] = value >> 24;
mac[5] = value >> 16;
node = fdt_path_offset(blob, fdt_get_alias(blob, "ethernet1"));
if (node < 0) {
/*
* There is no node for the USB ethernet in the devicetree. Just skip.
*/
return 0;
}
if (is_zero_ethaddr(mac)) {
printf("\nNo MAC address for USB ethernet set in OTP fuses!\n");
return 0;
}
if (!is_valid_ethaddr(mac)) {
printf("\nInvalid MAC address for USB ethernet set in OTP fuses!\n");
return -EINVAL;
}
ret = fdt_setprop(blob, node, "local-mac-address", &mac, 6);
if (ret)
ret = fdt_setprop(blob, node, "mac-address", &mac, 6);
if (ret)
printf("\nMissing mac-address or local-mac-address property in dt, skip setting MAC address for USB ethernet\n");
return 0;
}
int ft_board_setup(void *blob, struct bd_info *bd)
{
int ret = fdt_set_usb_eth_addr(blob);
if (ret)
return ret;
return fdt_fixup_memory(blob, PHYS_SDRAM, gd->ram_size);
}
int board_init(void)
{
return 0;
}

321
board/kontron/sl-mx8mm/spl.c Normal file
View file

@ -0,0 +1,321 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Kontron Electronics GmbH
*/
#include <asm/arch/imx8mm_pins.h>
#include <asm/arch/clock.h>
#include <asm/arch/ddr.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/iomux-v3.h>
#include <dm/uclass.h>
#include <hang.h>
#include <i2c.h>
#include <init.h>
#include <linux/errno.h>
#include <linux/delay.h>
#include <power/pca9450.h>
#include <power/pmic.h>
#include <spl.h>
DECLARE_GLOBAL_DATA_PTR;
enum {
BOARD_TYPE_KTN_N801X,
BOARD_TYPE_KTN_N801X_LVDS,
BOARD_TYPE_MAX
};
#define GPIO_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
#define TOUCH_RESET_GPIO IMX_GPIO_NR(3, 23)
static iomux_v3_cfg_t const i2c1_pads[] = {
IMX8MM_PAD_I2C1_SCL_I2C1_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL) | MUX_MODE_SION,
IMX8MM_PAD_I2C1_SDA_I2C1_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL) | MUX_MODE_SION
};
static iomux_v3_cfg_t const i2c2_pads[] = {
IMX8MM_PAD_I2C2_SCL_I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL) | MUX_MODE_SION,
IMX8MM_PAD_I2C2_SDA_I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL) | MUX_MODE_SION
};
static iomux_v3_cfg_t const touch_gpio[] = {
IMX8MM_PAD_SAI5_RXD2_GPIO3_IO23 | MUX_PAD_CTRL(GPIO_PAD_CTRL)
};
static iomux_v3_cfg_t const uart_pads[] = {
IMX8MM_PAD_UART3_RXD_UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
IMX8MM_PAD_UART3_TXD_UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static iomux_v3_cfg_t const wdog_pads[] = {
IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
int spl_board_boot_device(enum boot_device boot_dev_spl)
{
switch (boot_dev_spl) {
case USB_BOOT:
return BOOT_DEVICE_BOARD;
case SPI_NOR_BOOT:
return BOOT_DEVICE_SPI;
case SD1_BOOT:
case MMC1_BOOT:
return BOOT_DEVICE_MMC1;
case SD2_BOOT:
case MMC2_BOOT:
return BOOT_DEVICE_MMC2;
default:
return BOOT_DEVICE_NONE;
}
}
bool check_ram_available(long size)
{
long sz = get_ram_size((long *)PHYS_SDRAM, size);
if (sz == size)
return true;
return false;
}
static void spl_dram_init(void)
{
u32 size = 0;
/*
* Try the default DDR settings in lpddr4_timing.c to
* comply with the Micron 4GB DDR.
*/
if (!ddr_init(&dram_timing) && check_ram_available(SZ_4G)) {
size = 4;
} else {
/*
* Overwrite some values to comply with the Micron 1GB/2GB DDRs.
*/
dram_timing.ddrc_cfg[2].val = 0xa1080020;
dram_timing.ddrc_cfg[37].val = 0x1f;
dram_timing.fsp_msg[0].fsp_cfg[9].val = 0x110;
dram_timing.fsp_msg[0].fsp_cfg[21].val = 0x1;
dram_timing.fsp_msg[1].fsp_cfg[10].val = 0x110;
dram_timing.fsp_msg[1].fsp_cfg[22].val = 0x1;
dram_timing.fsp_msg[2].fsp_cfg[10].val = 0x110;
dram_timing.fsp_msg[2].fsp_cfg[22].val = 0x1;
dram_timing.fsp_msg[3].fsp_cfg[10].val = 0x110;
dram_timing.fsp_msg[3].fsp_cfg[22].val = 0x1;
if (!ddr_init(&dram_timing)) {
if (check_ram_available(SZ_2G))
size = 2;
else if (check_ram_available(SZ_1G))
size = 1;
}
}
if (size == 0) {
printf("Failed to initialize DDR RAM!\n");
size = 1;
}
printf("Kontron SL i.MX8MM (N801X) module, %u GB RAM detected\n", size);
writel(size, M4_BOOTROM_BASE_ADDR);
}
static void touch_reset(void)
{
/*
* Toggle the reset of the touch panel.
*/
imx_iomux_v3_setup_multiple_pads(touch_gpio, ARRAY_SIZE(touch_gpio));
gpio_request(TOUCH_RESET_GPIO, "touch_reset");
gpio_direction_output(TOUCH_RESET_GPIO, 0);
mdelay(20);
gpio_direction_output(TOUCH_RESET_GPIO, 1);
mdelay(20);
}
static int i2c_detect(u8 bus, u16 addr)
{
struct udevice *udev;
int ret;
/*
* Try to probe the touch controller to check if an LVDS panel is
* connected.
*/
ret = i2c_get_chip_for_busnum(bus, addr, 0, &udev);
if (ret == 0)
return 0;
return 1;
}
int do_board_detect(void)
{
bool lvds = false;
/*
* Check the I2C touch controller to detect a LVDS panel.
*/
imx_iomux_v3_setup_multiple_pads(i2c2_pads, ARRAY_SIZE(i2c2_pads));
touch_reset();
if (i2c_detect(1, 0x5d) == 0) {
printf("Touch controller detected, assuming LVDS panel...\n");
lvds = true;
}
/*
* Check the I2C PMIC to detect the deprecated SoM with DA9063.
*/
imx_iomux_v3_setup_multiple_pads(i2c1_pads, ARRAY_SIZE(i2c1_pads));
if (i2c_detect(0, 0x58) == 0) {
printf("### ATTENTION: DEPRECATED SOM REVISION (N8010 Rev0) DETECTED! ###\n");
printf("### THIS HW IS NOT SUPPRTED AND BOOTING WILL PROBABLY FAIL ###\n");
printf("### PLEASE UPGRADE TO LATEST MODULE ###\n");
}
if (lvds)
gd->board_type = BOARD_TYPE_KTN_N801X_LVDS;
else
gd->board_type = BOARD_TYPE_KTN_N801X;
return 0;
}
int board_fit_config_name_match(const char *name)
{
if (gd->board_type == BOARD_TYPE_KTN_N801X_LVDS && is_imx8mm() &&
!strncmp(name, "imx8mm-kontron-n801x-s-lvds", 27))
return 0;
if (gd->board_type == BOARD_TYPE_KTN_N801X && is_imx8mm() &&
!strncmp(name, "imx8mm-kontron-n801x-s", 22))
return 0;
return -1;
}
void spl_board_init(void)
{
struct udevice *dev;
int ret;
puts("Normal Boot\n");
ret = uclass_get_device_by_name(UCLASS_CLK,
"clock-controller@30380000",
&dev);
if (ret < 0)
printf("Failed to find clock node. Check device tree\n");
}
int board_early_init_f(void)
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
set_wdog_reset(wdog);
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
return 0;
}
static int power_init_board(void)
{
struct udevice *dev;
int ret = pmic_get("pmic@25", &dev);
if (ret == -ENODEV)
puts("No pmic found\n");
if (ret)
return ret;
/* BUCKxOUT_DVS0/1 control BUCK123 output, clear PRESET_EN */
pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
/* increase VDD_DRAM to 0.95V for 1.5GHz DDR */
pmic_reg_write(dev, PCA9450_BUCK3OUT_DVS0, 0x1c);
/* set VDD_SNVS_0V8 from default 0.85V to 0.8V */
pmic_reg_write(dev, PCA9450_LDO2CTRL, 0xC0);
/* set WDOG_B_CFG to cold reset */
pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);
return 0;
}
void board_init_f(ulong dummy)
{
int ret;
arch_cpu_init();
init_uart_clk(2);
board_early_init_f();
timer_init();
preloader_console_init();
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
ret = spl_init();
if (ret) {
debug("spl_init() failed: %d\n", ret);
hang();
}
enable_tzc380();
/* PMIC initialization */
power_init_board();
/* DDR initialization */
spl_dram_init();
/* Detect the board type */
do_board_detect();
board_init_r(NULL, 0);
}
void board_boot_order(u32 *spl_boot_list)
{
u32 bootdev = spl_boot_device();
/*
* The default boot fuse settings use the SD card (MMC2) as primary
* boot device, but allow SPI NOR as a fallback boot device.
* We can't detect the fallback case and spl_boot_device() will return
* BOOT_DEVICE_MMC2 despite the actual boot device being SPI NOR.
* Therefore we try to load U-Boot proper vom SPI NOR after loading
* from MMC has failed.
*/
spl_boot_list[0] = bootdev;
switch (bootdev) {
case BOOT_DEVICE_MMC1:
case BOOT_DEVICE_MMC2:
spl_boot_list[1] = BOOT_DEVICE_SPI;
break;
}
}

5
board/menlo/m53menlo/m53menlo.c
View file

@ -17,6 +17,7 @@
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/iomux-mx53.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/mx5_video.h>
#include <asm/mach-imx/video.h>
#include <asm/gpio.h>
@ -334,6 +335,10 @@ int splash_screen_prepare(void)
int board_late_init(void)
{
#ifdef CONFIG_CMD_BMODE
add_board_boot_modes(NULL);
#endif
#if defined(CONFIG_VIDEO_IPUV3)
struct udevice *dev;
int xpos, ypos, ret;

2
board/phytec/phycore_imx8mp/imximage-8mp-sd.cfg
View file

@ -7,4 +7,4 @@
ROM_VERSION v2
BOOT_FROM sd
LOADER mkimage.flash.mkimage 0x920000
LOADER u-boot-spl-ddr.bin 0x920000

19
board/toradex/apalis_imx6/apalis_imx6.c
View file

@ -1076,6 +1076,24 @@ static void ddr_init(int *table, int size)
writel(table[2 * i + 1], table[2 * i]);
}
/* Perform DDR DRAM calibration */
static void spl_dram_perform_cal(void)
{
#ifdef CONFIG_MX6_DDRCAL
int err;
struct mx6_ddr_sysinfo ddr_sysinfo = {
.dsize = 2,
};
err = mmdc_do_write_level_calibration(&ddr_sysinfo);
if (err)
printf("error %d from write level calibration\n", err);
err = mmdc_do_dqs_calibration(&ddr_sysinfo);
if (err)
printf("error %d from dqs calibration\n", err);
#endif
}
static void spl_dram_init(void)
{
int minc, maxc;
@ -1094,6 +1112,7 @@ static void spl_dram_init(void)
break;
};
udelay(100);
spl_dram_perform_cal();
}
void board_init_f(ulong dummy)

22
board/toradex/colibri_imx6/colibri_imx6.c
View file

@ -997,9 +997,28 @@ static void ddr_init(int *table, int size)
writel(table[2 * i + 1], table[2 * i]);
}
/* Perform DDR DRAM calibration */
static void spl_dram_perform_cal(u8 dsize)
{
#ifdef CONFIG_MX6_DDRCAL
int err;
struct mx6_ddr_sysinfo ddr_sysinfo = {
.dsize = dsize,
};
err = mmdc_do_write_level_calibration(&ddr_sysinfo);
if (err)
printf("error %d from write level calibration\n", err);
err = mmdc_do_dqs_calibration(&ddr_sysinfo);
if (err)
printf("error %d from dqs calibration\n", err);
#endif
}
static void spl_dram_init(void)
{
int minc, maxc;
u8 dsize = 2;
switch (get_cpu_temp_grade(&minc, &maxc)) {
case TEMP_COMMERCIAL:
@ -1009,6 +1028,7 @@ static void spl_dram_init(void)
ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
} else {
puts("Commercial temperature grade DDR3 timings, 32bit bus width.\n");
dsize = 1;
ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
}
break;
@ -1020,11 +1040,13 @@ static void spl_dram_init(void)
ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
} else {
puts("Industrial temperature grade DDR3 timings, 32bit bus width.\n");
dsize = 1;
ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
}
break;
};
udelay(100);
spl_dram_perform_cal(dsize);
}
static iomux_v3_cfg_t const gpio_reset_pad[] = {

18
common/spl/spl_fit.c
View file

@ -538,6 +538,11 @@ static void *spl_get_fit_load_buffer(size_t size)
return buf;
}
__weak void *board_spl_fit_buffer_addr(ulong fit_size, int sectors, int bl_len)
{
return spl_get_fit_load_buffer(sectors * bl_len);
}
/*
* Weak default function to allow customizing SPL fit loading for load-only
* use cases by allowing to skip the parsing/processing of the FIT contents
@ -548,6 +553,15 @@ __weak bool spl_load_simple_fit_skip_processing(void)
return false;
}
/*
* Weak default function to allow fixes after fit header
* is loaded.
*/
__weak void *spl_load_simple_fit_fix_load(const void *fit)
{
return (void *)fit;
}
static void warn_deprecated(const char *msg)
{
printf("DEPRECATED: %s\n", msg);
@ -631,7 +645,7 @@ static int spl_simple_fit_read(struct spl_fit_info *ctx,
* For FIT with external data, data is not loaded in this step.
*/
sectors = get_aligned_image_size(info, size, 0);
buf = spl_get_fit_load_buffer(sectors * info->bl_len);
buf = board_spl_fit_buffer_addr(size, sectors, info->bl_len);
count = info->read(info, sector, sectors, buf);
ctx->fit = buf;
@ -685,6 +699,8 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,
if (spl_load_simple_fit_skip_processing())
return 0;
ctx.fit = spl_load_simple_fit_fix_load(ctx.fit);
ret = spl_simple_fit_parse(&ctx);
if (ret < 0)
return ret;

1
configs/apalis_imx6_defconfig
View file

@ -10,6 +10,7 @@ CONFIG_SYS_MEMTEST_END=0x10010000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFDE00
CONFIG_MX6Q=y
CONFIG_MX6_DDRCAL=y
CONFIG_TARGET_APALIS_IMX6=y
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y

1
configs/colibri_imx6_defconfig
View file

@ -10,6 +10,7 @@ CONFIG_SYS_MEMTEST_END=0x10010000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFFFFDE00
CONFIG_MX6DL=y
CONFIG_MX6_DDRCAL=y
CONFIG_TARGET_COLIBRI_IMX6=y
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y

15
configs/gwventana_emmc_defconfig
View file

@ -44,7 +44,6 @@ CONFIG_SPL_DMA=y
CONFIG_SPL_I2C=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_POWER=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Ventana > "
CONFIG_CMD_BOOTZ=y
@ -54,12 +53,15 @@ CONFIG_CMD_UNZIP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_WDT=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
@ -113,12 +115,19 @@ CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_MXC_SPI=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_DM_THERMAL=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y
CONFIG_USB_ETHER_LAN75XX=y
CONFIG_USB_ETHER_LAN78XX=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Gateworks"
@ -137,4 +146,8 @@ CONFIG_DM_VIDEO=y
CONFIG_SYS_WHITE_ON_BLACK=y
# CONFIG_PANEL is not set
CONFIG_VIDEO_IPUV3=y
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_WATCHDOG_TIMEOUT_MSECS=60000
CONFIG_IMX_WATCHDOG=y
CONFIG_FDT_FIXUP_PARTITIONS=y

15
configs/gwventana_gw5904_defconfig
View file

@ -44,7 +44,6 @@ CONFIG_SPL_DMA=y
CONFIG_SPL_I2C=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_POWER=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Ventana > "
CONFIG_CMD_BOOTZ=y
@ -54,12 +53,15 @@ CONFIG_CMD_UNZIP=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_PART=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_WDT=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
@ -117,12 +119,19 @@ CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_MXC_SPI=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_DM_THERMAL=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y
CONFIG_USB_ETHER_LAN75XX=y
CONFIG_USB_ETHER_LAN78XX=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Gateworks"
@ -141,4 +150,8 @@ CONFIG_DM_VIDEO=y
CONFIG_SYS_WHITE_ON_BLACK=y
# CONFIG_PANEL is not set
CONFIG_VIDEO_IPUV3=y
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_WATCHDOG_TIMEOUT_MSECS=60000
CONFIG_IMX_WATCHDOG=y
CONFIG_FDT_FIXUP_PARTITIONS=y

15
configs/gwventana_nand_defconfig
View file

@ -45,7 +45,6 @@ CONFIG_SPL_I2C=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_POWER=y
CONFIG_SPL_WATCHDOG=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="Ventana > "
CONFIG_CMD_BOOTZ=y
@ -57,12 +56,15 @@ CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_PART=y
CONFIG_CMD_PCI=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_WDT=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_BMP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y
CONFIG_CMD_EXT2=y
@ -121,12 +123,19 @@ CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_MXC_SPI=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_DM_THERMAL=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y
CONFIG_USB_ETHER_LAN75XX=y
CONFIG_USB_ETHER_LAN78XX=y
CONFIG_USB_ETHER_MCS7830=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_USB_ETHER_SMSC95XX=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Gateworks"
@ -145,4 +154,8 @@ CONFIG_DM_VIDEO=y
CONFIG_SYS_WHITE_ON_BLACK=y
# CONFIG_PANEL is not set
CONFIG_VIDEO_IPUV3=y
CONFIG_SPLASH_SCREEN=y
CONFIG_SPLASH_SCREEN_ALIGN=y
CONFIG_WATCHDOG_TIMEOUT_MSECS=60000
CONFIG_IMX_WATCHDOG=y
CONFIG_FDT_FIXUP_PARTITIONS=y

148
configs/imx8mm-cl-iot-gate-optee_defconfig Normal file
View file

@ -0,0 +1,148 @@
CONFIG_ARM=y
CONFIG_SPL_SYS_ICACHE_OFF=y
CONFIG_SPL_SYS_DCACHE_OFF=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x4400
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mm-cl-iot-gate-optee"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_TARGET_IMX8MM_CL_IOT_GATE_OPTEE=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_IMX_CONFIG="board/compulab/imx8mm-cl-iot-gate/imximage-8mm-lpddr4.cfg"
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_PROMPT="u-boot=> "
CONFIG_CMD_BOOTEFI_SELFTEST=y
CONFIG_CMD_NVEDIT_EFI=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_SHA1SUM=y
CONFIG_CMD_BIND=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_SNTP=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_RTC=y
CONFIG_CMD_TIME=y
CONFIG_CMD_GETTIME=y
CONFIG_CMD_TIMER=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_TPM=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_MMC_ENV_DEV=2
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_CLK_COMPOSITE_CCF=y
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_SPL_CLK_IMX8MM=y
CONFIG_CLK_IMX8MM=y
CONFIG_DFU_TFTP=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_UDP_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x44000000
CONFIG_FASTBOOT_BUF_SIZE=0x5000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=2
CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
CONFIG_DM_KEYBOARD=y
CONFIG_SUPPORT_EMMC_RPMB=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC_IMX=y
CONFIG_DM_SPI_FLASH=y
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PCI_ENDPOINT=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
CONFIG_POWER_DOMAIN=y
CONFIG_IMX8M_POWER_DOMAIN=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_BD71837=y
CONFIG_SPL_DM_PMIC_BD71837=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_BD71837=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_DM_RTC=y
CONFIG_RTC_ABX80X=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_PSCI=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_TEE=y
CONFIG_OPTEE=y
CONFIG_DM_THERMAL=y
CONFIG_TPM2_TIS_SPI=y
CONFIG_TPM2_FTPM_TEE=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_GENERIC=y
CONFIG_USB_HOST_ETHER=y
CONFIG_USB_ETHER_ASIX88179=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_SDP_LOADADDR=0x40400000
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_IMX_WATCHDOG=y
CONFIG_SPL_TINY_MEMSET=y
CONFIG_TPM=y
CONFIG_LZO=y
CONFIG_BZIP2=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_EFI_SET_TIME=y
CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
CONFIG_EFI_CAPSULE_ON_DISK=y
CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y
CONFIG_EFI_SECURE_BOOT=y

109
configs/kontron-sl-mx6ul_defconfig Normal file
View file

@ -0,0 +1,109 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x87800000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x90000000
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0xF0000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_MX6UL=y
CONFIG_TARGET_KONTRON_MX6UL=y
CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ul-kontron-n631x-s"
CONFIG_SPL_TEXT_BASE=0x00908000
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SPL=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_IMX_CONFIG="arch/arm/mach-imx/spl_sd.cfg"
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
CONFIG_BOARD_TYPES=y
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_RAW_IMAGE_SUPPORT=y
CONFIG_SPL_LEGACY_IMAGE_SUPPORT=y
CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8A
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x11400
CONFIG_SPL_USB_HOST=y
CONFIG_SPL_USB_GADGET=y
CONFIG_SPL_USB_SDP_SUPPORT=y
CONFIG_SPL_WATCHDOG=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
CONFIG_CMD_SF_TEST=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_SDP=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FS_UUID=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nor0=spi1.0,spi-nand0=spi4.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=spi1.0:128k(spl),832k(u-boot),64k(env);spi4.0:-(UBI)"
CONFIG_CMD_UBI=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIST="imx6ul-kontron-n631x-s imx6ull-kontron-n641x-s"
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USE_ENV_SPI_BUS=y
CONFIG_ENV_SPI_BUS=2
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_ENV=y
CONFIG_DM_I2C=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_SPI_NAND=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_BUS=1
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=10000000
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_DM_ETH=y
CONFIG_DM_ETH_PHY=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_CONS_INDEX=4
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_FSL_QSPI=y
CONFIG_MXC_SPI=y
CONFIG_IMX_THERMAL=y
CONFIG_USB=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_FDT_FIXUP_PARTITIONS=y

142
configs/kontron-sl-mx8mm_defconfig Normal file
View file

@ -0,0 +1,142 @@
CONFIG_ARM=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_SYS_MALLOC_F_LEN=0x10000
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0x1f0000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_SYS_MALLOC_LEN=0x4000000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mm-kontron-n801x-s"
CONFIG_SPL_TEXT_BASE=0x7E1000
CONFIG_TARGET_KONTRON_MX8MM=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_BOOTCOUNT_BOOTLIMIT=3
CONFIG_SPL=y
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI_SUPPORT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_BOARD_SETUP=y
CONFIG_IMX_CONFIG="board/kontron/sl-mx8mm/imximage.cfg"
CONFIG_BOARD_TYPES=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
# CONFIG_SPL_FIT_IMAGE_TINY is not set
CONFIG_SPL_I2C=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_POWER=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x58000
CONFIG_SPL_WATCHDOG=y
CONFIG_SPL_ATF=y
CONFIG_CMD_NVEDIT_EFI=y
# CONFIG_CMD_LZMADEC is not set
# CONFIG_CMD_UNZIP is not set
CONFIG_CMD_CLK=y
CONFIG_CMD_DFU=y
CONFIG_CMD_FUSE=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_WDT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EFIDEBUG=y
CONFIG_CMD_RTC=y
CONFIG_CMD_TIME=y
CONFIG_CMD_PMIC=y
CONFIG_CMD_REGULATOR=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIST="imx8mm-kontron-n801x-s imx8mm-kontron-n801x-s-lvds"
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_USE_ENV_SPI_BUS=y
CONFIG_ENV_SPI_BUS=0
CONFIG_USE_ENV_SPI_MAX_HZ=y
CONFIG_ENV_SPI_MAX_HZ=80000000
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_ENV=y
CONFIG_SPL_CLK_COMPOSITE_CCF=y
CONFIG_CLK_COMPOSITE_CCF=y
CONFIG_SPL_CLK_IMX8MM=y
CONFIG_CLK_IMX8MM=y
CONFIG_DFU_SF=y
CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_ESDHC_IMX=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=80000000
CONFIG_SPI_FLASH_MACRONIX=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_SPI_FLASH_MTD=y
CONFIG_PHYLIB=y
CONFIG_PHY_MSCC=y
CONFIG_DM_ETH=y
CONFIG_DM_ETH_PHY=y
CONFIG_PHY_GIGE=y
CONFIG_FEC_MXC=y
CONFIG_RGMII=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
CONFIG_POWER_DOMAIN=y
CONFIG_IMX8M_POWER_DOMAIN=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_PCA9450=y
CONFIG_SPL_DM_PMIC_PCA9450=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_RTC=y
CONFIG_RTC_RV8803=y
CONFIG_CONS_INDEX=2
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_MXC_SPI=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_PSCI=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_DM_THERMAL=y
CONFIG_IMX_TMU=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
# CONFIG_WATCHDOG_AUTOSTART is not set
CONFIG_IMX_WATCHDOG=y
# CONFIG_HEXDUMP is not set
CONFIG_EFI_SET_TIME=y
CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
CONFIG_EFI_CAPSULE_ON_DISK=y
CONFIG_EFI_IGNORE_OSINDICATIONS=y
CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y

2
configs/m53menlo_defconfig
View file

@ -1,4 +1,5 @@
CONFIG_ARM=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_MX5=y
CONFIG_SYS_TEXT_BASE=0x71000000
CONFIG_SPL_GPIO=y
@ -22,7 +23,6 @@ CONFIG_SYS_BOOTCOUNT_ADDR=0x53FA401C
CONFIG_SPL=y
CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
CONFIG_ENV_OFFSET_REDUND=0x180000
# CONFIG_CMD_BMODE is not set
CONFIG_SYS_LOAD_ADDR=0x70800000
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y

2
configs/mx7ulp_com_defconfig
View file

@ -9,6 +9,8 @@ CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7ulp-com"
CONFIG_LDO_ENABLED_MODE=y
CONFIG_TARGET_MX7ULP_COM=y
CONFIG_USE_BOOTCOMMAND=y
CONFIG_BOOTCOMMAND="if run loadimage; then run mmcboot; fi"
CONFIG_SYS_LOAD_ADDR=0x60800000
CONFIG_DEFAULT_FDT_FILE="imx7ulp-com"
CONFIG_BOARD_EARLY_INIT_F=y

5
configs/smegw01_defconfig
View file

@ -4,15 +4,17 @@ CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0xa0000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xC0000
CONFIG_ENV_OFFSET=0x100000
CONFIG_SYS_MALLOC_LEN=0x2300000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx7d-smegw01"
CONFIG_TARGET_SMEGW01=y
CONFIG_ENV_OFFSET_REDUND=0x110000
CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
# CONFIG_ARMV7_VIRT is not set
CONFIG_IMX_RDC=y
CONFIG_IMX_BOOTAUX=y
CONFIG_IMX_HAB=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_HUSH_PARSER=y
@ -35,6 +37,7 @@ CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_OF_CONTROL=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_BOUNCE_BUFFER=y

1
configs/usbarmory_defconfig
View file

@ -39,3 +39,4 @@ CONFIG_DM_REGULATOR_GPIO=y
CONFIG_MXC_UART=y
CONFIG_USB=y
CONFIG_USB_EHCI_MX5=y
CONFIG_DM_ETH=y

2
doc/board/kontron/index.rst
View file

@ -7,3 +7,5 @@ Kontron
:maxdepth: 2
sl28
sl-mx6ul
sl-mx8mm

43
doc/board/kontron/sl-mx6ul.rst Normal file
View file

@ -0,0 +1,43 @@
.. SPDX-License-Identifier: GPL-2.0+
Kontron Electronics SL i.MX6UL/ULL SoM
======================================
The Kontron SoM-Line i.MX6UL/ULL (N6x1x) by Kontron Electronics GmbH is a SoM module
with either an i.MX6UL or i.MX6ULL SoC, 256/512 MB DDR3 RAM, SPI NOR, SPI NAND and Ethernet PHY.
The matching evaluation boards (Board-Line) have two Ethernet ports, USB 2.0,
RGB, SD card, CAN, RS485, RS232 and much more.
Quick Start
-----------
- Build U-Boot
- Boot
Build U-Boot
^^^^^^^^^^^^
.. code-block:: bash
$ make kontron-sl-mx6ul_defconfig
$ make
Burn the flash.bin to SD card at an offset of 1 KiB:
.. code-block:: bash
$ dd if=flash.bin of=/dev/sd[x] bs=1K seek=1 conv=notrunc
Boot
^^^^
Put the SD card in the slot on the board and apply power.
Further Information
-------------------
The bootloader configuration is setup to be used with kernel FIT images. Legacy
images might not be working out of the box.
Please see https://docs.kontron-electronics.de for further vendor documentation.

85
doc/board/kontron/sl-mx8mm.rst Normal file
View file

@ -0,0 +1,85 @@
.. SPDX-License-Identifier: GPL-2.0+
Kontron Electronics SL i.MX8MM SoM
==================================
The Kontron SoM-Line i.MX8MM (N801x) by Kontron Electronics GmbH is a SoM module
with an i.MX8M-Mini SoC, 1/2/4 GB LPDDR4 RAM, SPI NOR, eMMC and PMIC.
The matching evaluation boards (Board-Line) have two Ethernet ports, USB 2.0,
HDMI/LVDS, SD card, CAN, RS485, RS232 and much more.
Quick Start
-----------
- Get and Build the Trusted Firmware-A (TF-A)
- Get the DDR firmware
- Build U-Boot
- Boot
Get and Build the Trusted Firmware-A (TF-A)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Note: builddir is U-Boot build directory (source directory for in-tree builds)
There are two sources for the TF-A. Mainline and NXP. Get the one you prefer
(support and features might differ).
**NXP's imx-atf**
1. Get TF-A from: https://source.codeaurora.org/external/imx/imx-atf, branch: imx_5.4.70_2.3.0
2. Apply the patch to select the correct UART for the console, otherwise the TF-A will lock up during boot.
3. Build
.. code-block:: bash
$ make PLAT=imx8mm bl31
$ cp build/imx8mm/release/bl31.bin $(builddir)
**Mainline TF-A**
1. Get TF-A from: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/, tag: v2.4
2. Build
.. code-block:: bash
$ make PLAT=imx8mm CROSS_COMPILE=aarch64-linux-gnu- IMX_BOOT_UART_BASE="0x30880000" bl31
$ cp build/imx8mm/release/bl31.bin $(builddir)
Get the DDR firmware
^^^^^^^^^^^^^^^^^^^^
.. code-block:: bash
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.9.bin
$ chmod +x firmware-imx-8.9.bin
$ ./firmware-imx-8.9.bin
$ cp firmware-imx-8.9/firmware/ddr/synopsys/lpddr4*.bin $(builddir)
Build U-Boot
^^^^^^^^^^^^
.. code-block:: bash
$ make kontron-sl-mx8mm_defconfig
$ export ATF_LOAD_ADDR=0x920000
$ make
Burn the flash.bin to SD card at an offset of 33 KiB:
.. code-block:: bash
$ dd if=flash.bin of=/dev/sd[x] bs=1K seek=33 conv=notrunc
Boot
^^^^
Put the SD card in the slot on the board and apply power.
Further Information
-------------------
The bootloader configuration is setup to be used with kernel FIT images. Legacy
images might not be working out of the box.
Please see https://docs.kontron-electronics.de for further vendor documentation.

1
doc/board/nxp/imx8mp_evk.rst
View file

@ -52,7 +52,6 @@ Burn the flash.bin to the MicroSD card at offset 32KB:
.. code-block:: bash
$sudo dd if=build/flash.bin of=/dev/sd[x] bs=1K seek=32 conv=notrunc; sync
$sudo dd if=build/u-boot.itb of=/dev/sd[x] bs=1K seek=384 conv=notrunc; sync
Boot
----

9
drivers/misc/Kconfig
View file

@ -233,6 +233,15 @@ config MXC_OCOTP
Programmable memory pages that are stored on the some
Freescale i.MX processors.
config SPL_MXC_OCOTP
bool "Enable MXC OCOTP driver in SPL"
depends on SPL && (ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610)
default y
help
If you say Y here, you will get support for the One Time
Programmable memory pages, that are stored on some
Freescale i.MX processors, in SPL.
config NUVOTON_NCT6102D
bool "Enable Nuvoton NCT6102D Super I/O driver"
help

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