mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-28 23:51:33 +00:00
Convert CONFIG_SYS_NAND_BAD_BLOCK_POS to Kconfig
This converts the following to Kconfig: CONFIG_SYS_NAND_BAD_BLOCK_POS In order to do this, introduce a choice for HAS_LARGE/SMALL_BADBLOCK_POS as those are the only valid values. Use LARGE as the default as no in-tree boards use SMALL, but it is possible. Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
parent
606c377849
commit
9d9f59dd0a
39 changed files with 21 additions and 40 deletions
|
@ -38,10 +38,8 @@
|
|||
#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
|
||||
48, 49, 50, 51, 52, 53, 54, 55, \
|
||||
56, 57, 58, 59, 60, 61, 62, 63, }
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
|
||||
#elif (CONFIG_SYS_NAND_PAGE_SIZE == NAND_SMALL_BLOCK_PAGE_SIZE)
|
||||
#define CONFIG_SYS_NAND_ECCPOS { 10, 11, 12, 13, 14, 15, }
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
|
||||
#else
|
||||
#error "CONFIG_SYS_NAND_PAGE_SIZE set to an invalid value"
|
||||
#endif
|
||||
|
|
|
@ -425,6 +425,27 @@ config SYS_NAND_MAX_CHIPS
|
|||
|
||||
if SPL
|
||||
|
||||
choice
|
||||
prompt "NAND bad block marker/indicator positon in the OOB"
|
||||
depends on SPL_NAND_AM33XX_BCH || SPL_NAND_DENALI || SPL_NAND_SIMPLE || \
|
||||
SPL_NAND_SUPPORT && (NAND_ATMEL || NAND_MXC)
|
||||
default HAS_NAND_LARGE_BADBLOCK_POS
|
||||
help
|
||||
In the OOB, which position contains the badblock information.
|
||||
|
||||
config HAS_NAND_LARGE_BADBLOCK_POS
|
||||
bool "Set the bad block marker/indicator to the 'large' position"
|
||||
|
||||
config HAS_NAND_SMALL_BADBLOCK_POS
|
||||
bool "Set the bad block marker/indicator to the 'small' position"
|
||||
|
||||
endchoice
|
||||
|
||||
config SYS_NAND_BAD_BLOCK_POS
|
||||
int
|
||||
default 0 if HAS_NAND_LARGE_BADBLOCK_POS
|
||||
default 5 if HAS_NAND_SMALL_BADBLOCK_POS
|
||||
|
||||
config SYS_NAND_U_BOOT_LOCATIONS
|
||||
bool "Define U-boot binaries locations in NAND"
|
||||
help
|
||||
|
|
|
@ -182,7 +182,6 @@
|
|||
/* NAND: device related configs */
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
/* NAND: driver related configs */
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
|
||||
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
|
||||
10, 11, 12, 13, 14, 15, 16, 17, \
|
||||
18, 19, 20, 21, 22, 23, 24, 25, \
|
||||
|
|
|
@ -137,8 +137,6 @@
|
|||
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH16_CODE_HW
|
||||
#define MTDIDS_DEFAULT "nand0=nand.0"
|
||||
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
|
||||
|
||||
#endif /* CONFIG_MTD_RAW_NAND */
|
||||
|
||||
#define CONFIG_AM335X_USB0
|
||||
|
|
|
@ -107,7 +107,6 @@
|
|||
|
||||
/* NAND config */
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
|
||||
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
|
||||
10, 11, 12, 13, 14, 15, 16, 17, \
|
||||
18, 19, 20, 21, 22, 23, 24, 25, \
|
||||
|
|
|
@ -20,7 +20,6 @@
|
|||
/* Board NAND Info. */
|
||||
#ifdef CONFIG_MTD_RAW_NAND
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
|
||||
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, 10, \
|
||||
11, 12, 13, 14, 16, 17, 18, 19, 20, \
|
||||
21, 22, 23, 24, 25, 26, 27, 28, 30, \
|
||||
|
|
|
@ -161,7 +161,6 @@
|
|||
/* NAND: driver related configs */
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH16_CODE_HW
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
|
||||
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
|
||||
10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \
|
||||
20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \
|
||||
|
|
|
@ -97,7 +97,6 @@
|
|||
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
|
||||
#define CONFIG_SYS_NAND_ECCSIZE 256
|
||||
#define CONFIG_SYS_NAND_ECCBYTES 3
|
||||
#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
|
||||
|
|
|
@ -116,6 +116,5 @@
|
|||
#endif
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
|
||||
|
||||
#endif
|
||||
|
|
|
@ -99,6 +99,5 @@
|
|||
#endif
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
|
||||
|
||||
#endif
|
||||
|
|
|
@ -210,7 +210,6 @@
|
|||
|
||||
#ifdef CONFIG_MTD_RAW_NAND
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
|
||||
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
|
||||
10, 11, 12, 13, 14, 15, 16, 17, \
|
||||
18, 19, 20, 21, 22, 23, 24, 25, \
|
||||
|
|
|
@ -147,7 +147,6 @@ NANDTGTS \
|
|||
/* don't change OMAP_ELM, ECCSCHEME. ROM code only supports this */
|
||||
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
|
||||
#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, \
|
||||
10, 11, 12, 13, 14, 15, 16, 17, \
|
||||
18, 19, 20, 21, 22, 23, 24, 25, \
|
||||
|
|
|
@ -125,7 +125,6 @@
|
|||
/* NAND: device related configs */
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
/* NAND: driver related configs */
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
|
||||
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
|
||||
10, 11, 12, 13, 14, 15, 16, 17, \
|
||||
18, 19, 20, 21, 22, 23, 24, 25, \
|
||||
|
|
|
@ -86,7 +86,6 @@
|
|||
|
||||
/* NAND support */
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
|
||||
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
|
||||
10, 11, 12, 13, 14, 15, 16, 17, \
|
||||
18, 19, 20, 21, 22, 23, 24, 25, \
|
||||
|
|
|
@ -24,7 +24,6 @@
|
|||
/* NAND support */
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
|
||||
#define CONFIG_SYS_NAND_ECCSIZE 512
|
||||
#define CONFIG_SYS_NAND_ECCBYTES 14
|
||||
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
|
||||
|
|
|
@ -99,7 +99,6 @@
|
|||
#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
|
||||
#define CONFIG_SYS_NAND_ECCSIZE 256
|
||||
#define CONFIG_SYS_NAND_ECCBYTES 3
|
||||
#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
|
||||
|
|
|
@ -135,7 +135,6 @@
|
|||
39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \
|
||||
49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \
|
||||
59, 60, 61, 62, 63 }
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
|
||||
#define CONFIG_SYS_NAND_ECCSIZE 512
|
||||
#define CONFIG_SYS_NAND_ECCBYTES 10
|
||||
|
||||
|
|
|
@ -134,7 +134,6 @@
|
|||
|
||||
/* NAND boot config */
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
|
||||
#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
|
||||
10, 11, 12, 13}
|
||||
|
||||
|
|
|
@ -84,7 +84,6 @@
|
|||
/* NAND: driver related configs */
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
|
||||
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
|
||||
10, 11, 12, 13, 14, 15, 16, 17, \
|
||||
18, 19, 20, 21, 22, 23, 24, 25, \
|
||||
|
|
|
@ -61,7 +61,6 @@
|
|||
#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
|
||||
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
|
||||
|
||||
#define CONFIG_SPL_PAD_TO CONFIG_SYS_NAND_U_BOOT_OFFS
|
||||
#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO
|
||||
|
|
|
@ -141,7 +141,6 @@
|
|||
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
|
||||
#define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024)
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
|
||||
|
||||
/*
|
||||
* Extra Environments
|
||||
|
|
|
@ -23,7 +23,6 @@
|
|||
#define CONFIG_SYS_FLASH_BASE NAND_BASE
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
|
||||
#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
|
||||
10, 11, 12, 13}
|
||||
#define CONFIG_SYS_NAND_ECCSIZE 512
|
||||
|
|
|
@ -28,7 +28,6 @@
|
|||
#define CONFIG_SYS_FLASH_BASE NAND_BASE
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
|
||||
#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
|
||||
10, 11, 12, 13}
|
||||
#define CONFIG_SYS_NAND_ECCSIZE 512
|
||||
|
|
|
@ -76,7 +76,6 @@
|
|||
|
||||
/* NAND config */
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
|
||||
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
|
||||
10, 11, 12, 13, 14, 15, 16, 17, \
|
||||
18, 19, 20, 21, 22, 23, 24, 25, \
|
||||
|
|
|
@ -19,7 +19,6 @@
|
|||
#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
|
||||
/* NAND devices */
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
|
||||
#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \
|
||||
13, 14, 16, 17, 18, 19, 20, 21, 22, \
|
||||
23, 24, 25, 26, 27, 28, 30, 31, 32, \
|
||||
|
|
|
@ -135,7 +135,6 @@
|
|||
22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
|
||||
38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
|
||||
54, 55, 56, 57, 58, 59, 60, 61, 62, 63 }
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
|
||||
#define CONFIG_SYS_NAND_ECCSIZE 512
|
||||
#define CONFIG_SYS_NAND_ECCBYTES 10
|
||||
#endif
|
||||
|
|
|
@ -87,7 +87,6 @@
|
|||
/* NAND: device related configs */
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
/* NAND: driver related configs */
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
|
||||
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
|
||||
10, 11, 12, 13, 14, 15, 16, 17, \
|
||||
18, 19, 20, 21, 22, 23, 24, 25, \
|
||||
|
|
|
@ -87,7 +87,6 @@
|
|||
#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
|
||||
#define CONFIG_SYS_NAND_ECCSIZE 256
|
||||
#define CONFIG_SYS_NAND_ECCBYTES 3
|
||||
#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
|
||||
|
|
|
@ -71,7 +71,6 @@
|
|||
#endif
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
|
||||
|
||||
/* Falcon boot support on raw MMC */
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x100 /* 128 KiB */
|
||||
|
|
|
@ -83,6 +83,5 @@
|
|||
#endif
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
|
||||
|
||||
#endif
|
||||
|
|
|
@ -47,6 +47,5 @@
|
|||
#endif
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
|
||||
|
||||
#endif
|
||||
|
|
|
@ -47,6 +47,5 @@
|
|||
#endif
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
|
||||
|
||||
#endif
|
||||
|
|
|
@ -74,7 +74,6 @@
|
|||
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
|
||||
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
|
||||
10, 11, 12, 13, 14, 15, 16, 17, \
|
||||
18, 19, 20, 21, 22, 23, 24, 25, \
|
||||
|
|
|
@ -169,7 +169,6 @@
|
|||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
|
||||
#define CONFIG_SYS_NAND_SIZE (SZ_256M)
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
|
||||
#define CONFIG_SYS_NAND_ECCSIZE 256
|
||||
#define CONFIG_SYS_NAND_ECCBYTES 3
|
||||
#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
|
||||
|
|
|
@ -123,7 +123,6 @@
|
|||
* NAND Support
|
||||
*/
|
||||
#ifdef CONFIG_NAND_DENALI
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
#define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS
|
||||
|
|
|
@ -127,7 +127,6 @@
|
|||
|
||||
/* NAND boot config */
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
|
||||
#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\
|
||||
48, 49, 50, 51, 52, 53, 54, 55,\
|
||||
56, 57, 58, 59, 60, 61, 62, 63}
|
||||
|
|
|
@ -171,7 +171,6 @@
|
|||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
|
||||
#define CONFIG_SYS_NAND_SIZE (256 * SZ_1M)
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
|
||||
#define CONFIG_SYS_NAND_ECCSIZE 256
|
||||
#define CONFIG_SYS_NAND_ECCBYTES 3
|
||||
#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
|
||||
|
|
|
@ -59,7 +59,6 @@
|
|||
/* NAND: device related configs */
|
||||
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
|
||||
/* NAND: driver related configs */
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
|
||||
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
|
||||
10, 11, 12, 13, 14, 15, 16, 17, \
|
||||
18, 19, 20, 21, 22, 23, 24, 25, \
|
||||
|
|
|
@ -57,7 +57,6 @@
|
|||
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
#define CONFIG_SYS_NAND_REGS_BASE 0x68100000
|
||||
#define CONFIG_SYS_NAND_DATA_BASE 0x68000000
|
||||
#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
|
||||
|
||||
/*
|
||||
* Network Configuration
|
||||
|
|
Loading…
Reference in a new issue