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clk: ast2600: Add YCLK control for HACE

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Add YCLK enable for HACE, the HW hash engine of
ASPEED AST2600 SoCs.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
This commit is contained in:
Joel Stanley 2021-10-27 14:17:26 +08:00 • committed by Tom Rini
parent 3d99be97f1
commit 4080714f5e
2 changed files with 25 additions and 2 deletions
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5
arch/arm/include/asm/arch-aspeed/scu_ast2600.h
View file

@ -10,8 +10,9 @@
#define SCU_CLKGATE1_EMMC BIT(27)
#define SCU_CLKGATE1_MAC2 BIT(21)
#define SCU_CLKGATE1_MAC1 BIT(20)
#define SCU_CLKGATE1_USB_HUB BIT(14)
#define SCU_CLKGATE1_USB_HOST2 BIT(7)
#define SCU_CLKGATE1_USB_HUB BIT(14)
#define SCU_CLKGATE1_HACE BIT(13)
#define SCU_CLKGATE1_USB_HOST2 BIT(7)
#define SCU_CLKGATE2_FSI BIT(30)
#define SCU_CLKGATE2_MAC4 BIT(21)

22
drivers/clk/aspeed/clk_ast2600.c
View file

@ -1013,6 +1013,25 @@ static ulong ast2600_enable_usbbhclk(struct ast2600_scu *scu)
return 0;
}
static ulong ast2600_enable_haceclk(struct ast2600_scu *scu)
{
uint32_t reset_bit;
uint32_t clkgate_bit;
reset_bit = BIT(ASPEED_RESET_HACE);
clkgate_bit = SCU_CLKGATE1_HACE;
/*
* we don't do reset assertion here as HACE
* shares the same reset control with ACRY
*/
writel(clkgate_bit, &scu->clkgate_clr1);
mdelay(20);
writel(reset_bit, &scu->modrst_clr1);
return 0;
}
static int ast2600_clk_enable(struct clk *clk)
{
struct ast2600_clk_priv *priv = dev_get_priv(clk->dev);
@ -1051,6 +1070,9 @@ static int ast2600_clk_enable(struct clk *clk)
case ASPEED_CLK_GATE_USBPORT2CLK:
ast2600_enable_usbbhclk(priv->scu);
break;
case ASPEED_CLK_GATE_YCLK:
ast2600_enable_haceclk(priv->scu);
break;
default:
pr_err("can't enable clk\n");
return -ENOENT;