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global: Remove dead code that starts with CONFIG_[0-9A]

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This removes a number of spots of dead code based on symbols that start
with CONFIG_[0-9] or CONFIG_A.

Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2021-08-19 15:02:35 -04:00
parent b21f965bb0
commit d1240b6ab2
14 changed files with 3 additions and 253 deletions
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144
arch/powerpc/cpu/mpc83xx/pcie.c
View file

@ -34,148 +34,6 @@ static struct {
#endif
};
#ifdef CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES
/* private structure for mpc83xx pcie hose */
static struct mpc83xx_pcie_priv {
u8 index;
} pcie_priv[PCIE_MAX_BUSES] = {
{
/* pcie controller 1 */
.index = 0,
},
{
/* pcie controller 2 */
.index = 1,
},
};
static int mpc83xx_pcie_remap_cfg(struct pci_controller *hose, pci_dev_t dev)
{
int bus = PCI_BUS(dev) - hose->first_busno;
immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
struct mpc83xx_pcie_priv *pcie_priv = hose->priv_data;
pex83xx_t *pex = &immr->pciexp[pcie_priv->index];
struct pex_outbound_window *out_win = &pex->bridge.pex_outbound_win[0];
u8 devfn = PCI_DEV(dev) << 3 | PCI_FUNC(dev);
u32 dev_base = bus << 24 | devfn << 16;
if (hose->indirect_type == INDIRECT_TYPE_NO_PCIE_LINK)
return -1;
/*
* Workaround for the HW bug: for Type 0 configure transactions the
* PCI-E controller does not check the device number bits and just
* assumes that the device number bits are 0.
*/
if (devfn & 0xf8)
return -1;
out_le32(&out_win->tarl, dev_base);
return 0;
}
#define cfg_read(val, addr, type, op) \
do { *val = op((type)(addr)); } while (0)
#define cfg_write(val, addr, type, op) \
do { op((type *)(addr), (val)); } while (0)
#define cfg_read_err(val) do { *val = -1; } while (0)
#define cfg_write_err(val) do { } while (0)
#define PCIE_OP(rw, size, type, op) \
static int pcie_##rw##_config_##size(struct pci_controller *hose, \
pci_dev_t dev, int offset, \
type val) \
{ \
int ret; \
\
ret = mpc83xx_pcie_remap_cfg(hose, dev); \
if (ret) { \
cfg_##rw##_err(val); \
return ret; \
} \
cfg_##rw(val, (void *)hose->cfg_addr + offset, type, op); \
return 0; \
}
PCIE_OP(read, byte, u8 *, in_8)
PCIE_OP(read, word, u16 *, in_le16)
PCIE_OP(read, dword, u32 *, in_le32)
PCIE_OP(write, byte, u8, out_8)
PCIE_OP(write, word, u16, out_le16)
PCIE_OP(write, dword, u32, out_le32)
static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg,
u8 link)
{
extern void disable_addr_trans(void); /* start.S */
static struct pci_controller pcie_hose[PCIE_MAX_BUSES];
struct pci_controller *hose = &pcie_hose[bus];
int i;
/*
* There are no spare BATs to remap all PCI-E windows for U-Boot, so
* disable translations. In general, this is not great solution, and
* that's why we don't register PCI-E hoses by default.
*/
disable_addr_trans();
for (i = 0; i < 2; i++, reg++) {
if (reg->size == 0)
break;
hose->regions[i] = *reg;
hose->region_count++;
}
i = hose->region_count++;
hose->regions[i].bus_start = 0;
hose->regions[i].phys_start = 0;
hose->regions[i].size = gd->ram_size;
hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY;
i = hose->region_count++;
hose->regions[i].bus_start = CONFIG_SYS_IMMR;
hose->regions[i].phys_start = CONFIG_SYS_IMMR;
hose->regions[i].size = 0x100000;
hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY;
hose->first_busno = pci_last_busno() + 1;
hose->last_busno = 0xff;
hose->cfg_addr = (unsigned int *)mpc83xx_pcie_cfg_space[bus].base;
hose->priv_data = &pcie_priv[bus];
pci_set_ops(hose,
pcie_read_config_byte,
pcie_read_config_word,
pcie_read_config_dword,
pcie_write_config_byte,
pcie_write_config_word,
pcie_write_config_dword);
if (!link)
hose->indirect_type = INDIRECT_TYPE_NO_PCIE_LINK;
pci_register_hose(hose);
#ifdef CONFIG_PCI_SCAN_SHOW
printf("PCI: Bus Dev VenId DevId Class Int\n");
#endif
/*
* Hose scan.
*/
hose->last_busno = pci_hose_scan(hose);
}
#else
static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg,
u8 link) {}
#endif /* CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES */
int get_pcie_clk(int index)
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
@ -340,8 +198,6 @@ static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg)
printf("link\n");
else
printf("No link\n");
mpc83xx_pcie_register_hose(bus, reg, reg16 >= PCI_LTSSM_L0);
}
/*

4
arch/powerpc/include/asm/processor.h
View file

@ -46,11 +46,7 @@
#define MSR_RI (1<<1) /* Recoverable Exception */
#define MSR_LE (1<<0) /* Little Endian */
#ifdef CONFIG_APUS_FAST_EXCEPT
#define MSR_ MSR_ME|MSR_IP|MSR_RI
#else
#define MSR_ MSR_ME|MSR_RI
#endif
#ifndef CONFIG_E500
#define MSR_KERNEL MSR_|MSR_IR|MSR_DR
#else

2
board/freescale/mpc8349emds/mpc8349emds.c
View file

@ -50,8 +50,6 @@ int board_early_init_f (void)
return 0;
}
#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
int dram_init(void)
{
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;

13
drivers/net/smc91111.h
View file

@ -251,18 +251,14 @@ struct smc91111_priv{
* We have only 16 Bit PCMCIA access on Socket 0
*/
#ifdef CONFIG_ADNPESC1
#define SMC_inw(a,r) (*((volatile word *)((a)->iobase+((r)<<1))))
#elif CONFIG_ARM64
#if CONFIG_ARM64
#define SMC_inw(a, r) (*((volatile word*)((a)->iobase+((dword)(r)))))
#else
#define SMC_inw(a, r) (*((volatile word*)((a)->iobase+(r))))
#endif
#define SMC_inb(a,r) (((r)&1) ? SMC_inw((a),(r)&~1)>>8 : SMC_inw((a),(r)&0xFF))
#ifdef CONFIG_ADNPESC1
#define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+((r)<<1))) = d)
#elif CONFIG_ARM64
#if CONFIG_ARM64
#define SMC_outw(a, d, r) \
(*((volatile word*)((a)->iobase+((dword)(r)))) = d)
#else
@ -439,11 +435,6 @@ struct smc91111_priv{
#define RPC_LED_RX (0x07) /* LED = RX packet occurred */
#if defined(CONFIG_DK1C20) || defined(CONFIG_DK1S10)
/* buggy schematic: LEDa -> yellow, LEDb --> green */
#define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \
| (RPC_LED_TX_RX << RPC_LSXA_SHFT) \
| (RPC_LED_100_10 << RPC_LSXB_SHFT) )
#elif defined(CONFIG_ADNPESC1)
/* SSV ADNP/ESC1 has only one LED: LEDa -> Rx/Tx indicator */
#define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \
| (RPC_LED_TX_RX << RPC_LSXA_SHFT) \
| (RPC_LED_100_10 << RPC_LSXB_SHFT) )

68
drivers/video/pxa_lcd.c
View file

@ -199,72 +199,6 @@ vidinfo_t panel_info = {
/*----------------------------------------------------------------------*/
#ifdef CONFIG_ACX517AKN
# define LCD_BPP LCD_COLOR8
/* you have to set lccr0 and lccr3 (including pcd) */
# define REG_LCCR0 0x003008f9
# define REG_LCCR3 0x03700006
vidinfo_t panel_info = {
.vl_col = 320,
.vl_row = 320,
.vl_width = 320,
.vl_height = 320,
.vl_clkp = CONFIG_SYS_HIGH,
.vl_oep = CONFIG_SYS_LOW,
.vl_hsp = CONFIG_SYS_LOW,
.vl_vsp = CONFIG_SYS_LOW,
.vl_dp = CONFIG_SYS_HIGH,
.vl_bpix = LCD_BPP,
.vl_lbw = 0,
.vl_splt = 1,
.vl_clor = 1,
.vl_tft = 1,
.vl_hpw = 0x04,
.vl_blw = 0x1c,
.vl_elw = 0x08,
.vl_vpw = 0x01,
.vl_bfw = 0x07,
.vl_efw = 0x08,
};
#endif /* CONFIG_ACX517AKN */
#ifdef CONFIG_ACX544AKN
# define LCD_BPP LCD_COLOR16
/* you have to set lccr0 and lccr3 (including pcd) */
# define REG_LCCR0 0x003008f9
# define REG_LCCR3 0x04700007 /* 16bpp */
vidinfo_t panel_info = {
.vl_col = 320,
.vl_row = 320,
.vl_width = 320,
.vl_height = 320,
.vl_clkp = CONFIG_SYS_LOW,
.vl_oep = CONFIG_SYS_LOW,
.vl_hsp = CONFIG_SYS_LOW,
.vl_vsp = CONFIG_SYS_LOW,
.vl_dp = CONFIG_SYS_LOW,
.vl_bpix = LCD_BPP,
.vl_lbw = 0,
.vl_splt = 0,
.vl_clor = 1,
.vl_tft = 1,
.vl_hpw = 0x05,
.vl_blw = 0x13,
.vl_elw = 0x08,
.vl_vpw = 0x02,
.vl_bfw = 0x07,
.vl_efw = 0x05,
};
#endif /* CONFIG_ACX544AKN */
/*----------------------------------------------------------------------*/
#ifdef CONFIG_LQ038J7DH53
# define LCD_BPP LCD_COLOR8
@ -295,7 +229,7 @@ vidinfo_t panel_info = {
.vl_bfw = 0x04,
.vl_efw = 0x01,
};
#endif /* CONFIG_ACX517AKN */
#endif /* CONFIG_LQ038J7DH53 */
/*----------------------------------------------------------------------*/

3
include/configs/MPC8349EMDS.h
View file

@ -210,9 +210,6 @@
#if defined(CONFIG_PCI)
#define CONFIG_83XX_PCI_STREAMING
#if !defined(CONFIG_PCI_PNP)
#define PCI_ENET0_IOADDR 0xFIXME
#define PCI_ENET0_MEMADDR 0xFIXME

3
include/configs/MPC8349EMDS_SDRAM.h
View file

@ -265,9 +265,6 @@
#if defined(CONFIG_PCI)
#define CONFIG_83XX_PCI_STREAMING
#if !defined(CONFIG_PCI_PNP)
#define PCI_ENET0_IOADDR 0xFIXME
#define PCI_ENET0_MEMADDR 0xFIXME

1
include/configs/aspenite.h
View file

@ -14,7 +14,6 @@
*/
#define CONFIG_SHEEVA_88SV331xV5 1 /* CPU Core subversion */
#define CONFIG_ARMADA100 1 /* SOC Family Name */
#define CONFIG_ARMADA168 1 /* SOC Used on this Board */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
/*

1
include/configs/km/km-mpc8309.h
View file

@ -8,7 +8,6 @@
/*
* System Clock Setup
*/
#define CONFIG_83XX_CLKIN 66000000
#define CONFIG_SYS_CLK_FREQ 66000000
#define CONFIG_83XX_PCICLK 66000000

1
include/configs/km/km-mpc832x.h
View file

@ -6,7 +6,6 @@
/*
* System Clock Setup
*/
#define CONFIG_83XX_CLKIN 66000000
#define CONFIG_SYS_CLK_FREQ 66000000
#define CONFIG_83XX_PCICLK 66000000

1
include/configs/kmcoge5ne.h
View file

@ -27,7 +27,6 @@
/*
* System Clock Setup
*/
#define CONFIG_83XX_CLKIN 66000000
#define CONFIG_SYS_CLK_FREQ 66000000
#define CONFIG_83XX_PCICLK 66000000

10
include/configs/sniper.h
View file

@ -11,16 +11,6 @@
#include <asm/arch/cpu.h>
#include <asm/arch/omap.h>
/*
* CPU
*/
#define CONFIG_ARM_ARCH_CP15_ERRATA
/*
* Board
*/
/*
* Clocks
*/

2
include/configs/total_compute.h
View file

@ -34,9 +34,7 @@
#define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_ARM_PL180_MMCI_BASE 0x001c050000
#define CONFIG_SYS_MMC_MAX_BLK_COUNT 127
#define CONFIG_ARM_PL180_MMCI_CLOCK_FREQ 12000000
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootm_size=0x20000000\0" \

3
include/configs/vexpress_common.h
View file

@ -56,7 +56,6 @@
/* Common peripherals relative to CS7. */
#define V2M_AACI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(4))
#define V2M_MMCI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(5))
#define V2M_KMI0 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(6))
#define V2M_KMI1 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(7))
@ -135,9 +134,7 @@
#define CONFIG_SYS_SERIAL0 V2M_UART0
#define CONFIG_SYS_SERIAL1 V2M_UART1
#define CONFIG_ARM_PL180_MMCI_BASE V2M_MMCI
#define CONFIG_SYS_MMC_MAX_BLK_COUNT 127
#define CONFIG_ARM_PL180_MMCI_CLOCK_FREQ 6250000
/* BOOTP options */
#define CONFIG_BOOTP_BOOTFILESIZE