mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-28 15:41:40 +00:00
- device-tree sync-up with Linux for ls1028a - fixes/update in fsl-ddr driver, fsl-validate, lx2162a, fsl-mc, spintable code, configs, qspi node, pci - enable EFI_SET_TIME support in sl28 - powerpc: Drop -mstring
This commit is contained in:
commit
1e72ad6b38
197 changed files with 2423 additions and 1023 deletions
|
@ -10,7 +10,7 @@ config ARCH_LS1012A
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select SYS_HAS_SERDES
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select SYS_FSL_DDR_BE
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select SYS_FSL_MMDC
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select SYS_FSL_ERRATUM_A010315
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select SYS_FSL_ERRATUM_A010315 if PCIE_LAYERSCAPE
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select SYS_FSL_ERRATUM_A009798
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select SYS_FSL_ERRATUM_A008997
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select SYS_FSL_ERRATUM_A009007
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@ -77,7 +77,7 @@ config ARCH_LS1043A
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select SYS_FSL_ERRATUM_A009663 if !TFABOOT
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select SYS_FSL_ERRATUM_A009798
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select SYS_FSL_ERRATUM_A009942 if !TFABOOT
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select SYS_FSL_ERRATUM_A010315
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select SYS_FSL_ERRATUM_A010315 if PCIE_LAYERSCAPE
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select SYS_FSL_ERRATUM_A010539
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select SYS_FSL_HAS_DDR3
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select SYS_FSL_HAS_DDR4
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@ -427,7 +427,7 @@ static void fdt_disable_multimedia(void *blob, unsigned int svr)
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fdt_status_disabled(blob, off);
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/* Disable GPU node */
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off = fdt_node_offset_by_compatible(blob, -1, "fsl,ls1028a-gpu");
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off = fdt_node_offset_by_compatible(blob, -1, "vivante,gc");
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if (off != -FDT_ERR_NOTFOUND)
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fdt_status_disabled(blob, off);
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}
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@ -18,7 +18,7 @@ struct icid_id_table icid_tbl[] = {
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SET_SATA_ICID(1, "fsl,ls1028a-ahci", FSL_SATA1_STREAM_ID),
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SET_EDMA_ICID(FSL_EDMA_STREAM_ID),
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SET_QDMA_ICID("fsl,ls1028a-qdma", FSL_DMA_STREAM_ID),
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SET_GPU_ICID("fsl,ls1028a-gpu", FSL_GPU_STREAM_ID),
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SET_GPU_ICID("vivante,gc", FSL_GPU_STREAM_ID),
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SET_DISPLAY_ICID(FSL_DISPLAY_STREAM_ID),
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#ifdef CONFIG_FSL_CAAM
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SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID),
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@ -14,11 +14,12 @@
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#include <asm/system.h>
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#include <asm/arch/mp.h>
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#include <asm/arch/soc.h>
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#include <linux/compat.h>
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#include <linux/delay.h>
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#include <linux/psci.h>
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#include <malloc.h>
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#include "cpu.h"
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#include <asm/arch-fsl-layerscape/soc.h>
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#include <efi_loader.h>
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DECLARE_GLOBAL_DATA_PTR;
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@ -83,8 +84,7 @@ int fsl_layerscape_wake_seconday_cores(void)
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int i, timeout = 10;
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u64 *table;
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#ifdef CONFIG_EFI_LOADER
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u64 reloc_addr = U32_MAX;
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efi_status_t ret;
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void *reloc_addr;
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#endif
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#ifdef COUNTER_FREQUENCY_REAL
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@ -102,27 +102,26 @@ int fsl_layerscape_wake_seconday_cores(void)
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* Keep this after the __real_cntfrq update, so we have it when we
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* copy the complete section here.
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*/
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ret = efi_allocate_pages(EFI_ALLOCATE_MAX_ADDRESS,
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EFI_RESERVED_MEMORY_TYPE,
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efi_size_in_pages(secondary_boot_code_size),
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&reloc_addr);
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if (ret == EFI_SUCCESS) {
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debug("Relocating spin table from %llx to %llx (size %lx)\n",
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(u64)secondary_boot_code_start, reloc_addr,
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reloc_addr = memalign(PAGE_SIZE,
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round_up(secondary_boot_code_size, PAGE_SIZE));
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if (reloc_addr) {
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debug("Relocating spin table from %p to %p (size %lx)\n",
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secondary_boot_code_start, reloc_addr,
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secondary_boot_code_size);
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memcpy((void *)reloc_addr, secondary_boot_code_start,
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memcpy(reloc_addr, secondary_boot_code_start,
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secondary_boot_code_size);
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flush_dcache_range(reloc_addr,
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reloc_addr + secondary_boot_code_size);
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flush_dcache_range((unsigned long)reloc_addr,
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(unsigned long)reloc_addr +
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secondary_boot_code_size);
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/* set new entry point for secondary cores */
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secondary_boot_addr += (void *)reloc_addr -
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secondary_boot_addr += reloc_addr -
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secondary_boot_code_start;
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flush_dcache_range((unsigned long)&secondary_boot_addr,
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(unsigned long)&secondary_boot_addr + 8);
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/* this will be used to reserve the memory */
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secondary_boot_code_start = (void *)reloc_addr;
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secondary_boot_code_start = reloc_addr;
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}
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#endif
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@ -929,25 +929,23 @@ __weak int fsl_board_late_init(void)
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#define DWC3_GSBUSCFG0_CACHETYPE(n) (((n) & 0xffff) \
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<< DWC3_GSBUSCFG0_CACHETYPE_SHIFT)
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void enable_dwc3_snooping(void)
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static void enable_dwc3_snooping(void)
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{
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int ret;
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u32 val;
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struct udevice *bus;
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struct uclass *uc;
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static const char * const compatibles[] = {
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"fsl,layerscape-dwc3",
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"fsl,ls1028a-dwc3",
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};
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fdt_addr_t dwc3_base;
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ofnode node;
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u32 val;
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int i;
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ret = uclass_get(UCLASS_USB, &uc);
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if (ret)
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return;
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uclass_foreach_dev(bus, uc) {
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if (!strcmp(bus->driver->of_match->compatible, "fsl,layerscape-dwc3")) {
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dwc3_base = devfdt_get_addr(bus);
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if (dwc3_base == FDT_ADDR_T_NONE) {
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dev_err(bus, "dwc3 regs missing\n");
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for (i = 0; i < ARRAY_SIZE(compatibles); i++) {
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ofnode_for_each_compatible_node(node, compatibles[i]) {
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dwc3_base = ofnode_get_addr(node);
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if (dwc3_base == FDT_ADDR_T_NONE)
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continue;
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}
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val = in_le32(dwc3_base + DWC3_GSBUSCFG0);
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val &= ~DWC3_GSBUSCFG0_CACHETYPE(~0);
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val |= DWC3_GSBUSCFG0_CACHETYPE(0x2222);
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@ -49,7 +49,7 @@
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interrupts = <0 64 0x4>;
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clock-names = "dspi";
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clocks = <&clockgen 4 0>;
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num-cs = <6>;
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spi-num-chipselects = <6>;
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big-endian;
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status = "disabled";
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};
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@ -157,7 +157,7 @@
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compatible = "fsl,ls1012a-ahci";
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reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
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0x0 0x20140520 0x0 0x4>; /* ecc sata addr */
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reg-names = "sata-base", "ecc-addr";
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reg-names = "ahci", "sata-ecc";
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interrupts = <0 69 4>;
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clocks = <&clockgen 4 0>;
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status = "disabled";
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@ -4,17 +4,20 @@
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/ {
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aliases {
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mmc0 = &esdhc1;
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mmc1 = &esdhc0;
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i2c0 = &i2c0;
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i2c1 = &i2c3;
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i2c2 = &i2c4;
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rtc0 = &rtc;
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ethernet2 = &enetc2;
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ethernet3 = &enetc6;
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ethernet2 = &enetc_port2;
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ethernet3 = &enetc_port3;
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};
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binman: binman {
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multiple-images;
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};
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};
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&binman {
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u_boot_rom: u-boot-rom {
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filename = "u-boot.rom";
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pad-byte = <0xff>;
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@ -133,6 +136,31 @@
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};
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};
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&binman {
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u-boot-update {
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filename = "u-boot.update";
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fit {
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description = "FIT update image";
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images {
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u-boot-bin {
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description = "U-Boot";
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type = "firmware";
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os = "u-boot";
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arch = "arm";
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compression = "none";
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load = <0>; /* unused */
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blob {
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filename = "u-boot.rom";
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};
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};
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};
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};
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};
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};
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#ifdef CONFIG_SL28_ENABLE_SER0_CONSOLE
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/ {
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chosen {
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@ -142,7 +170,7 @@
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#endif
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#ifdef CONFIG_SL28_SPL_LOADS_ATF_BL31
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&binman {
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&u_boot_rom {
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fit {
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images {
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bl31 {
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@ -191,7 +219,7 @@
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#endif
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#ifdef CONFIG_SL28_SPL_LOADS_OPTEE_BL32
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&binman {
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&u_boot_rom {
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fit {
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images {
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bl32 {
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@ -234,11 +262,6 @@
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};
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#endif
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&i2c0 {
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rtc: rtc@32 {
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};
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};
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&fspi {
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u-boot,dm-pre-reloc;
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flash@0 {
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@ -250,7 +273,7 @@
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u-boot,dm-pre-reloc;
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};
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&esdhc0 {
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&esdhc {
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u-boot,dm-pre-reloc;
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};
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@ -262,7 +285,28 @@
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u-boot,dm-pre-reloc;
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};
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&serial0 {
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&duart0 {
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u-boot,dm-pre-reloc;
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};
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/*
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* u-boot will enable the device in the linux device tree in place. Because
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* we are using the linux device tree, we have to enable the PCI controller
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* ourselves.
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*/
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&pcie1 {
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status = "okay";
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};
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&pcie2 {
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status = "okay";
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};
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&sata {
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status = "okay";
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};
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&soc {
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u-boot,dm-pre-reloc;
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};
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|
|
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@ -3,6 +3,6 @@
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/ {
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aliases {
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ethernet0 = &enetc1;
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ethernet0 = &enetc_port1;
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};
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};
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|
|
|
@ -8,7 +8,7 @@
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* None of the four SerDes lanes are used by the module, instead they are
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* all led out to the carrier for customer use.
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*
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* Copyright (C) 2020 Michael Walle <michael@walle.cc>
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* Copyright (C) 2021 Michael Walle <michael@walle.cc>
|
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*
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*/
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|
@ -21,28 +21,17 @@
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compatible = "kontron,sl28-var1", "kontron,sl28", "fsl,ls1028a";
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};
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|
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&enetc0 {
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status = "disabled";
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/delete-property/ phy-handle;
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};
|
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&enetc_mdio_pf3 {
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/* Delete unused phy node */
|
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/delete-node/ ethernet-phy@5;
|
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|
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&enetc1 {
|
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phy-handle = <&phy0>;
|
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phy-mode = "rgmii-id";
|
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status = "okay";
|
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};
|
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|
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/delete-node/ &phy0;
|
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&mdio0 {
|
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phy0: ethernet-phy@4 {
|
||||
reg = <0x4>;
|
||||
eee-broken-1000t;
|
||||
eee-broken-100tx;
|
||||
|
||||
qca,clk-out-frequency = <125000000>;
|
||||
qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
|
||||
qca,keep-pll-enabled;
|
||||
|
||||
vddio-supply = <&vddio>;
|
||||
|
||||
vddio: vddio-regulator {
|
||||
|
@ -56,3 +45,15 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
&enetc_port0 {
|
||||
status = "disabled";
|
||||
/* Delete the phy-handle to the old phy0 label */
|
||||
/delete-property/ phy-handle;
|
||||
};
|
||||
|
||||
&enetc_port1 {
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
status = "okay";
|
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};
|
||||
|
|
|
@ -7,3 +7,11 @@
|
|||
ethernet1 = &mscc_felix_port1;
|
||||
};
|
||||
};
|
||||
|
||||
&mscc_felix_port0 {
|
||||
label = "gbe0";
|
||||
};
|
||||
|
||||
&mscc_felix_port1 {
|
||||
label = "gbe1";
|
||||
};
|
||||
|
|
|
@ -2,10 +2,10 @@
|
|||
/*
|
||||
* Device Tree file for the Kontron SMARC-sAL28 board.
|
||||
*
|
||||
* This is for the network variant 2 which has no ethernet support in the
|
||||
* bootloader.
|
||||
* This is for the network variant 2 which has two ethernet ports. These
|
||||
* ports are connected to the internal switch.
|
||||
*
|
||||
* Copyright (C) 2020 Michael Walle <michael@walle.cc>
|
||||
* Copyright (C) 2021 Michael Walle <michael@walle.cc>
|
||||
*
|
||||
*/
|
||||
|
||||
|
@ -17,12 +17,25 @@
|
|||
compatible = "kontron,sl28-var2", "kontron,sl28", "fsl,ls1028a";
|
||||
};
|
||||
|
||||
&enetc0 {
|
||||
&enetc_mdio_pf3 {
|
||||
phy1: ethernet-phy@4 {
|
||||
reg = <0x4>;
|
||||
eee-broken-1000t;
|
||||
eee-broken-100tx;
|
||||
};
|
||||
};
|
||||
|
||||
&enetc_port0 {
|
||||
status = "disabled";
|
||||
/*
|
||||
* In the base device tree the PHY at address 5 was assigned for
|
||||
* this port. On this module this PHY is connected to a switch
|
||||
* port instead. Therefore, delete the phy-handle property here.
|
||||
*/
|
||||
/delete-property/ phy-handle;
|
||||
};
|
||||
|
||||
&enetc2 {
|
||||
&enetc_port2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
@ -31,35 +44,22 @@
|
|||
};
|
||||
|
||||
&mscc_felix_port0 {
|
||||
label = "gbe0";
|
||||
label = "swp0";
|
||||
managed = "in-band-status";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "sgmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mscc_felix_port1 {
|
||||
label = "gbe1";
|
||||
label = "swp1";
|
||||
managed = "in-band-status";
|
||||
phy-handle = <&phy1>;
|
||||
phy-mode = "sgmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mscc_felix_port4 {
|
||||
ethernet = <&enetc2>;
|
||||
ethernet = <&enetc_port2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/delete-node/ &phy0;
|
||||
&mdio0 {
|
||||
phy0: ethernet-phy@5 {
|
||||
reg = <0x5>;
|
||||
eee-broken-1000t;
|
||||
eee-broken-100tx;
|
||||
};
|
||||
|
||||
phy1: ethernet-phy@4 {
|
||||
reg = <0x4>;
|
||||
eee-broken-1000t;
|
||||
eee-broken-100tx;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -3,6 +3,6 @@
|
|||
|
||||
/ {
|
||||
aliases {
|
||||
ethernet0 = &enetc0;
|
||||
ethernet0 = &enetc_port0;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -3,7 +3,7 @@
|
|||
|
||||
/ {
|
||||
aliases {
|
||||
ethernet0 = &enetc0;
|
||||
ethernet1 = &enetc1;
|
||||
ethernet0 = &enetc_port0;
|
||||
ethernet1 = &enetc_port1;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -5,7 +5,7 @@
|
|||
* This is for the network variant 4 which has two ethernet ports. It
|
||||
* extends the base and provides one more port connected via RGMII.
|
||||
*
|
||||
* Copyright (C) 2019 Michael Walle <michael@walle.cc>
|
||||
* Copyright (C) 2021 Michael Walle <michael@walle.cc>
|
||||
*
|
||||
*/
|
||||
|
||||
|
@ -18,22 +18,14 @@
|
|||
compatible = "kontron,sl28-var4", "kontron,sl28", "fsl,ls1028a";
|
||||
};
|
||||
|
||||
&enetc1 {
|
||||
phy-handle = <&phy1>;
|
||||
phy-mode = "rgmii-id";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdio0 {
|
||||
&enetc_mdio_pf3 {
|
||||
phy1: ethernet-phy@4 {
|
||||
reg = <0x4>;
|
||||
eee-broken-1000t;
|
||||
eee-broken-100tx;
|
||||
|
||||
qca,clk-out-frequency = <125000000>;
|
||||
qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
|
||||
qca,keep-pll-enabled;
|
||||
|
||||
vddio-supply = <&vddio>;
|
||||
|
||||
vddio: vddio-regulator {
|
||||
|
@ -47,3 +39,9 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
&enetc_port1 {
|
||||
phy-handle = <&phy1>;
|
||||
phy-mode = "rgmii-id";
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
@ -2,23 +2,61 @@
|
|||
/*
|
||||
* Device Tree file for the Kontron SMARC-sAL28 board.
|
||||
*
|
||||
* Copyright (C) 2019 Michael Walle <michael@walle.cc>
|
||||
* Copyright (C) 2021 Michael Walle <michael@walle.cc>
|
||||
*
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "fsl-ls1028a.dtsi"
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
model = "Kontron SMARC-sAL28";
|
||||
compatible = "kontron,sl28", "fsl,ls1028a";
|
||||
|
||||
aliases {
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
crypto = &crypto;
|
||||
serial0 = &duart0;
|
||||
serial1 = &duart1;
|
||||
serial2 = &lpuart1;
|
||||
spi0 = &fspi;
|
||||
spi1 = &dspi2;
|
||||
mmc0 = &esdhc1;
|
||||
mmc1 = &esdhc;
|
||||
rtc0 = &rtc;
|
||||
rtc1 = &ftm_alarm0;
|
||||
};
|
||||
|
||||
buttons0 {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
power-button {
|
||||
interrupts-extended = <&sl28cpld_intc
|
||||
4 IRQ_TYPE_EDGE_BOTH>;
|
||||
linux,code = <KEY_POWER>;
|
||||
label = "Power";
|
||||
};
|
||||
|
||||
sleep-button {
|
||||
interrupts-extended = <&sl28cpld_intc
|
||||
5 IRQ_TYPE_EDGE_BOTH>;
|
||||
linux,code = <KEY_SLEEP>;
|
||||
label = "Sleep";
|
||||
};
|
||||
};
|
||||
|
||||
buttons1 {
|
||||
compatible = "gpio-keys-polled";
|
||||
poll-interval = <200>;
|
||||
|
||||
lid-switch {
|
||||
linux,input-type = <EV_SW>;
|
||||
linux,code = <SW_LID>;
|
||||
gpios = <&sl28cpld_gpio3 4 GPIO_ACTIVE_LOW>;
|
||||
label = "Lid";
|
||||
};
|
||||
};
|
||||
|
||||
chosen {
|
||||
|
@ -26,25 +64,38 @@
|
|||
};
|
||||
};
|
||||
|
||||
&can0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dspi2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&enetc0 {
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "sgmii";
|
||||
&duart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&enetc2 {
|
||||
status = "disabled";
|
||||
&duart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&enetc6 {
|
||||
status = "disabled";
|
||||
&enetc_mdio_pf3 {
|
||||
phy0: ethernet-phy@5 {
|
||||
reg = <0x5>;
|
||||
eee-broken-1000t;
|
||||
eee-broken-100tx;
|
||||
};
|
||||
};
|
||||
|
||||
&esdhc0 {
|
||||
&enetc_port0 {
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "sgmii";
|
||||
managed = "in-band-status";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&esdhc {
|
||||
sd-uhs-sdr104;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-sdr25;
|
||||
|
@ -63,8 +114,6 @@
|
|||
status = "okay";
|
||||
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "jedec,spi-nor";
|
||||
m25p,fast-read;
|
||||
spi-max-frequency = <133000000>;
|
||||
|
@ -72,17 +121,167 @@
|
|||
/* The following setting enables 1-1-2 (CMD-ADDR-DATA) mode */
|
||||
spi-rx-bus-width = <2>; /* 2 SPI Rx lines */
|
||||
spi-tx-bus-width = <1>; /* 1 SPI Tx line */
|
||||
|
||||
partitions {
|
||||
compatible = "fixed-partitions";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
reg = <0x000000 0x010000>;
|
||||
label = "rcw";
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@10000 {
|
||||
reg = <0x010000 0x1d0000>;
|
||||
label = "failsafe bootloader";
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@200000 {
|
||||
reg = <0x200000 0x010000>;
|
||||
label = "configuration store";
|
||||
};
|
||||
|
||||
partition@210000 {
|
||||
reg = <0x210000 0x1d0000>;
|
||||
label = "bootloader";
|
||||
};
|
||||
|
||||
partition@3e0000 {
|
||||
reg = <0x3e0000 0x020000>;
|
||||
label = "bootloader environment";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
gpio-line-names =
|
||||
"", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "TDO", "TCK",
|
||||
"", "", "", "", "", "", "", "";
|
||||
};
|
||||
|
||||
&gpio2 {
|
||||
gpio-line-names =
|
||||
"", "", "", "", "", "", "TMS", "TDI",
|
||||
"", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "",
|
||||
"", "", "", "", "", "", "", "";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
|
||||
rtc@32 {
|
||||
rtc: rtc@32 {
|
||||
compatible = "microcrystal,rv8803";
|
||||
reg = <0x32>;
|
||||
};
|
||||
|
||||
sl28cpld@4a {
|
||||
compatible = "kontron,sl28cpld";
|
||||
reg = <0x4a>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
watchdog@4 {
|
||||
compatible = "kontron,sl28cpld-wdt";
|
||||
reg = <0x4>;
|
||||
kontron,assert-wdt-timeout-pin;
|
||||
};
|
||||
|
||||
hwmon@b {
|
||||
compatible = "kontron,sl28cpld-fan";
|
||||
reg = <0xb>;
|
||||
};
|
||||
|
||||
sl28cpld_pwm0: pwm@c {
|
||||
compatible = "kontron,sl28cpld-pwm";
|
||||
reg = <0xc>;
|
||||
#pwm-cells = <2>;
|
||||
};
|
||||
|
||||
sl28cpld_pwm1: pwm@e {
|
||||
compatible = "kontron,sl28cpld-pwm";
|
||||
reg = <0xe>;
|
||||
#pwm-cells = <2>;
|
||||
};
|
||||
|
||||
sl28cpld_gpio0: gpio@10 {
|
||||
compatible = "kontron,sl28cpld-gpio";
|
||||
reg = <0x10>;
|
||||
interrupts-extended = <&gpio2 6
|
||||
IRQ_TYPE_EDGE_FALLING>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-line-names =
|
||||
"GPIO0_CAM0_PWR_N", "GPIO1_CAM1_PWR_N",
|
||||
"GPIO2_CAM0_RST_N", "GPIO3_CAM1_RST_N",
|
||||
"GPIO4_HDA_RST_N", "GPIO5_PWM_OUT",
|
||||
"GPIO6_TACHIN", "GPIO7";
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
sl28cpld_gpio1: gpio@15 {
|
||||
compatible = "kontron,sl28cpld-gpio";
|
||||
reg = <0x15>;
|
||||
interrupts-extended = <&gpio2 6
|
||||
IRQ_TYPE_EDGE_FALLING>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-line-names =
|
||||
"GPIO8", "GPIO9", "GPIO10", "GPIO11",
|
||||
"", "", "", "";
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
sl28cpld_gpio2: gpio@1a {
|
||||
compatible = "kontron,sl28cpld-gpo";
|
||||
reg = <0x1a>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-line-names =
|
||||
"LCD0 voltage enable",
|
||||
"LCD0 backlight enable",
|
||||
"eMMC reset", "LVDS bridge reset",
|
||||
"LVDS bridge power-down",
|
||||
"SDIO power enable",
|
||||
"", "";
|
||||
};
|
||||
|
||||
sl28cpld_gpio3: gpio@1b {
|
||||
compatible = "kontron,sl28cpld-gpi";
|
||||
reg = <0x1b>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-line-names =
|
||||
"Power button", "Force recovery", "Sleep",
|
||||
"Battery low", "Lid state", "Charging",
|
||||
"Charger present", "";
|
||||
};
|
||||
|
||||
sl28cpld_intc: interrupt-controller@1c {
|
||||
compatible = "kontron,sl28cpld-intc";
|
||||
reg = <0x1c>;
|
||||
interrupts-extended = <&gpio2 6
|
||||
IRQ_TYPE_EDGE_FALLING>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "atmel,24c32";
|
||||
reg = <0x50>;
|
||||
|
@ -107,32 +306,3 @@
|
|||
&lpuart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdio0 {
|
||||
status = "okay";
|
||||
phy0: ethernet-phy@5 {
|
||||
reg = <0x5>;
|
||||
eee-broken-1000t;
|
||||
eee-broken-100tx;
|
||||
};
|
||||
};
|
||||
|
||||
&sata {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&serial0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&serial1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
@ -13,8 +13,8 @@
|
|||
#include "fsl-sch-30842.dtsi"
|
||||
};
|
||||
|
||||
&enetc0 {
|
||||
&enetc_port0 {
|
||||
status = "okay";
|
||||
phy-mode = "usxgmii";
|
||||
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
|
||||
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
|
||||
};
|
||||
|
|
|
@ -12,8 +12,8 @@
|
|||
#include "fsl-sch-30842.dtsi"
|
||||
};
|
||||
|
||||
&enetc0 {
|
||||
&enetc_port0 {
|
||||
status = "okay";
|
||||
phy-mode = "2500base-x";
|
||||
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
|
||||
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
|
||||
};
|
||||
|
|
|
@ -20,7 +20,7 @@
|
|||
#include "fsl-sch-30841.dtsi"
|
||||
};
|
||||
|
||||
&enetc2 {
|
||||
&enetc_port2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
@ -31,28 +31,28 @@
|
|||
&mscc_felix_port0 {
|
||||
status = "okay";
|
||||
phy-mode = "2500base-x";
|
||||
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@00}>;
|
||||
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@00}>;
|
||||
};
|
||||
|
||||
&mscc_felix_port1 {
|
||||
status = "okay";
|
||||
phy-mode = "2500base-x";
|
||||
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@01}>;
|
||||
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@01}>;
|
||||
};
|
||||
|
||||
&mscc_felix_port2 {
|
||||
status = "okay";
|
||||
phy-mode = "2500base-x";
|
||||
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
|
||||
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
|
||||
};
|
||||
|
||||
&mscc_felix_port3 {
|
||||
status = "okay";
|
||||
phy-mode = "2500base-x";
|
||||
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>;
|
||||
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>;
|
||||
};
|
||||
|
||||
&mscc_felix_port4 {
|
||||
ethernet = <&enetc2>;
|
||||
ethernet = <&enetc_port2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
@ -9,7 +9,7 @@
|
|||
#include "fsl-sch-30841.dtsi"
|
||||
};
|
||||
|
||||
&enetc2 {
|
||||
&enetc_port2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
@ -20,16 +20,16 @@
|
|||
&mscc_felix_port0 {
|
||||
status = "okay";
|
||||
phy-mode = "2500base-x";
|
||||
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
|
||||
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
|
||||
};
|
||||
|
||||
&mscc_felix_port3 {
|
||||
status = "okay";
|
||||
phy-mode = "2500base-x";
|
||||
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>;
|
||||
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>;
|
||||
};
|
||||
|
||||
&mscc_felix_port4 {
|
||||
ethernet = <&enetc2>;
|
||||
ethernet = <&enetc_port2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
@ -12,8 +12,8 @@
|
|||
#include "fsl-sch-24801.dtsi"
|
||||
};
|
||||
|
||||
&enetc0 {
|
||||
&enetc_port0 {
|
||||
status = "okay";
|
||||
phy-mode = "sgmii";
|
||||
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>;
|
||||
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>;
|
||||
};
|
||||
|
|
|
@ -34,7 +34,7 @@
|
|||
#include "fsl-sch-24801.dtsi"
|
||||
};
|
||||
|
||||
&enetc2 {
|
||||
&enetc_port2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
@ -45,28 +45,28 @@
|
|||
&mscc_felix_port0 {
|
||||
status = "okay";
|
||||
phy-mode = "sgmii";
|
||||
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>;
|
||||
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>;
|
||||
};
|
||||
|
||||
&mscc_felix_port1 {
|
||||
status = "okay";
|
||||
phy-mode = "sgmii";
|
||||
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@1c}>;
|
||||
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@1c}>;
|
||||
};
|
||||
|
||||
&mscc_felix_port2 {
|
||||
status = "okay";
|
||||
phy-mode = "sgmii";
|
||||
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1e}>;
|
||||
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1e}>;
|
||||
};
|
||||
|
||||
&mscc_felix_port3 {
|
||||
status = "okay";
|
||||
phy-mode = "sgmii";
|
||||
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1f}>;
|
||||
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1f}>;
|
||||
};
|
||||
|
||||
&mscc_felix_port4 {
|
||||
ethernet = <&enetc2>;
|
||||
ethernet = <&enetc_port2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
@ -19,7 +19,7 @@
|
|||
#include "fsl-sch-24801.dtsi"
|
||||
};
|
||||
|
||||
&enetc2 {
|
||||
&enetc_port2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
@ -30,28 +30,28 @@
|
|||
&mscc_felix_port0 {
|
||||
status = "okay";
|
||||
phy-mode = "sgmii";
|
||||
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>;
|
||||
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>;
|
||||
};
|
||||
|
||||
&mscc_felix_port1 {
|
||||
status = "okay";
|
||||
phy-mode = "sgmii";
|
||||
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1d}>;
|
||||
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1d}>;
|
||||
};
|
||||
|
||||
&mscc_felix_port2 {
|
||||
status = "okay";
|
||||
phy-mode = "sgmii";
|
||||
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1e}>;
|
||||
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1e}>;
|
||||
};
|
||||
|
||||
&mscc_felix_port3 {
|
||||
status = "okay";
|
||||
phy-mode = "sgmii";
|
||||
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1f}>;
|
||||
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1f}>;
|
||||
};
|
||||
|
||||
&mscc_felix_port4 {
|
||||
ethernet = <&enetc2>;
|
||||
ethernet = <&enetc_port2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
@ -10,6 +10,6 @@
|
|||
|
||||
/ {
|
||||
chosen {
|
||||
stdout-path = &serial0;
|
||||
stdout-path = &duart0;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -19,7 +19,7 @@
|
|||
#include "fsl-sch-30841.dtsi"
|
||||
};
|
||||
|
||||
&enetc2 {
|
||||
&enetc_port2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
@ -30,28 +30,28 @@
|
|||
&mscc_felix_port0 {
|
||||
status = "okay";
|
||||
phy-mode = "usxgmii";
|
||||
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@00}>;
|
||||
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@00}>;
|
||||
};
|
||||
|
||||
&mscc_felix_port1 {
|
||||
status = "okay";
|
||||
phy-mode = "usxgmii";
|
||||
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@01}>;
|
||||
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@01}>;
|
||||
};
|
||||
|
||||
&mscc_felix_port2 {
|
||||
status = "okay";
|
||||
phy-mode = "usxgmii";
|
||||
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@02}>;
|
||||
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@02}>;
|
||||
};
|
||||
|
||||
&mscc_felix_port3 {
|
||||
status = "okay";
|
||||
phy-mode = "usxgmii";
|
||||
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@03}>;
|
||||
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@03}>;
|
||||
};
|
||||
|
||||
&mscc_felix_port4 {
|
||||
ethernet = <&enetc2>;
|
||||
ethernet = <&enetc_port2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
@ -13,7 +13,7 @@
|
|||
#include "fsl-sch-28021.dtsi"
|
||||
};
|
||||
|
||||
&enetc2 {
|
||||
&enetc_port2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
@ -24,28 +24,28 @@
|
|||
&mscc_felix_port0 {
|
||||
status = "okay";
|
||||
phy-mode = "qsgmii";
|
||||
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@08}>;
|
||||
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@08}>;
|
||||
};
|
||||
|
||||
&mscc_felix_port1 {
|
||||
status = "okay";
|
||||
phy-mode = "qsgmii";
|
||||
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@09}>;
|
||||
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@09}>;
|
||||
};
|
||||
|
||||
&mscc_felix_port2 {
|
||||
status = "okay";
|
||||
phy-mode = "qsgmii";
|
||||
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0a}>;
|
||||
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0a}>;
|
||||
};
|
||||
|
||||
&mscc_felix_port3 {
|
||||
status = "okay";
|
||||
phy-mode = "qsgmii";
|
||||
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0b}>;
|
||||
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0b}>;
|
||||
};
|
||||
|
||||
&mscc_felix_port4 {
|
||||
ethernet = <&enetc2>;
|
||||
ethernet = <&enetc_port2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
@ -9,7 +9,7 @@
|
|||
#include "fsl-sch-30842.dtsi"
|
||||
};
|
||||
|
||||
&enetc2 {
|
||||
&enetc_port2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
@ -20,10 +20,10 @@
|
|||
&mscc_felix_port1 {
|
||||
status = "okay";
|
||||
phy-mode = "2500base-x";
|
||||
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@02}>;
|
||||
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@02}>;
|
||||
};
|
||||
|
||||
&mscc_felix_port4 {
|
||||
ethernet = <&enetc2>;
|
||||
ethernet = <&enetc_port2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
@ -9,7 +9,7 @@
|
|||
#include "fsl-sch-30842.dtsi"
|
||||
};
|
||||
|
||||
&enetc2 {
|
||||
&enetc_port2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
@ -20,10 +20,10 @@
|
|||
&mscc_felix_port2 {
|
||||
status = "okay";
|
||||
phy-mode = "2500base-x";
|
||||
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@60/phy@02}>;
|
||||
phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@60/phy@02}>;
|
||||
};
|
||||
|
||||
&mscc_felix_port4 {
|
||||
ethernet = <&enetc2>;
|
||||
ethernet = <&enetc_port2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
@ -105,7 +105,7 @@
|
|||
};
|
||||
};
|
||||
|
||||
&esdhc0 {
|
||||
&esdhc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
@ -130,7 +130,6 @@
|
|||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
fpga@66 {
|
||||
#address-cells = <1>;
|
||||
|
@ -145,7 +144,7 @@
|
|||
reg = <0x54>;
|
||||
#mux-control-cells = <1>;
|
||||
mux-reg-masks = <0x54 0xf0>;
|
||||
mdio-parent-bus = <&mdio0>;
|
||||
mdio-parent-bus = <&enetc_mdio_pf3>;
|
||||
|
||||
/* on-board MDIO with a single RGMII PHY */
|
||||
mdio@00 {
|
||||
|
@ -233,11 +232,23 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&serial0 {
|
||||
&duart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&serial1 {
|
||||
&duart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
@ -245,17 +256,13 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&enetc1 {
|
||||
&enetc_port1 {
|
||||
status = "okay";
|
||||
phy-mode = "rgmii-id";
|
||||
phy-handle = <&qds_phy0>;
|
||||
};
|
||||
|
||||
&mdio0 {
|
||||
&enetc_mdio_pf3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
|
|
@ -15,8 +15,8 @@
|
|||
compatible = "fsl,ls1028a-rdb", "fsl,ls1028a";
|
||||
aliases {
|
||||
spi0 = &fspi;
|
||||
ethernet0 = &enetc0;
|
||||
ethernet1 = &enetc2;
|
||||
ethernet0 = &enetc_port0;
|
||||
ethernet1 = &enetc_port2;
|
||||
ethernet2 = &mscc_felix_port0;
|
||||
ethernet3 = &mscc_felix_port1;
|
||||
ethernet4 = &mscc_felix_port2;
|
||||
|
@ -36,7 +36,7 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&esdhc0 {
|
||||
&esdhc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
@ -61,7 +61,6 @@
|
|||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
u-boot,dm-pre-reloc;
|
||||
|
||||
i2c-mux@77 {
|
||||
|
||||
|
@ -115,11 +114,23 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&serial0 {
|
||||
&duart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&serial1 {
|
||||
&duart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pcie2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
@ -127,17 +138,13 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&enetc0 {
|
||||
&enetc_port0 {
|
||||
status = "okay";
|
||||
phy-mode = "sgmii";
|
||||
phy-handle = <&rdb_phy0>;
|
||||
};
|
||||
|
||||
&enetc2 {
|
||||
&enetc_port2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
@ -174,11 +181,11 @@
|
|||
};
|
||||
|
||||
&mscc_felix_port4 {
|
||||
ethernet = <&enetc2>;
|
||||
ethernet = <&enetc_port2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mdio0 {
|
||||
&enetc_mdio_pf3 {
|
||||
status = "okay";
|
||||
rdb_phy0: phy@2 {
|
||||
reg = <2>;
|
||||
|
|
File diff suppressed because it is too large
Load diff
|
@ -53,7 +53,7 @@
|
|||
interrupts = <0 64 0x4>;
|
||||
clock-names = "dspi";
|
||||
clocks = <&clockgen 4 0>;
|
||||
num-cs = <6>;
|
||||
spi-num-chipselects = <6>;
|
||||
big-endian;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -66,7 +66,7 @@
|
|||
interrupts = <0 65 0x4>;
|
||||
clock-names = "dspi";
|
||||
clocks = <&clockgen 4 0>;
|
||||
num-cs = <6>;
|
||||
spi-num-chipselects = <6>;
|
||||
big-endian;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -331,7 +331,7 @@
|
|||
compatible = "fsl,ls1043a-ahci";
|
||||
reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
|
||||
0x0 0x20140520 0x0 0x4>; /* ecc sata addr*/
|
||||
reg-names = "sata-base", "ecc-addr";
|
||||
reg-names = "ahci", "sata-ecc";
|
||||
interrupts = <0 69 4>;
|
||||
clocks = <&clockgen 4 0>;
|
||||
status = "disabled";
|
||||
|
|
|
@ -52,7 +52,7 @@
|
|||
interrupts = <0 64 0x4>;
|
||||
clock-names = "dspi";
|
||||
clocks = <&clockgen 4 0>;
|
||||
num-cs = <6>;
|
||||
spi-num-chipselects = <6>;
|
||||
big-endian;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -65,7 +65,7 @@
|
|||
interrupts = <0 65 0x4>;
|
||||
clock-names = "dspi";
|
||||
clocks = <&clockgen 4 0>;
|
||||
num-cs = <6>;
|
||||
spi-num-chipselects = <6>;
|
||||
big-endian;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -367,7 +367,7 @@
|
|||
compatible = "fsl,ls1046a-ahci";
|
||||
reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
|
||||
0x0 0x20140520 0x0 0x4>; /* ecc sata addr*/
|
||||
reg-names = "sata-base", "ecc-addr";
|
||||
reg-names = "ahci", "sata-ecc";
|
||||
interrupts = <0 69 4>;
|
||||
clocks = <&clockgen 4 1>;
|
||||
status = "disabled";
|
||||
|
|
|
@ -89,7 +89,7 @@
|
|||
#size-cells = <0>;
|
||||
reg = <0x0 0x2100000 0x0 0x10000>;
|
||||
interrupts = <0 26 0x4>; /* Level high type */
|
||||
num-cs = <6>;
|
||||
spi-num-chipselects = <6>;
|
||||
};
|
||||
|
||||
qspi: quadspi@1550000 {
|
||||
|
@ -99,7 +99,7 @@
|
|||
reg = <0x0 0x20c0000 0x0 0x10000>,
|
||||
<0x0 0x20000000 0x0 0x10000000>;
|
||||
reg-names = "QuadSPI", "QuadSPI-memory";
|
||||
num-cs = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
esdhc: esdhc@2140000 {
|
||||
|
@ -226,7 +226,7 @@
|
|||
compatible = "fsl,ls1088a-ahci";
|
||||
reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
|
||||
0x7 0x100520 0x0 0x4>; /* ecc sata addr*/
|
||||
reg-names = "sata-base", "ecc-addr";
|
||||
reg-names = "ahci", "sata-ecc";
|
||||
interrupts = <0 133 4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
@ -93,7 +93,7 @@
|
|||
#size-cells = <0>;
|
||||
reg = <0x0 0x2100000 0x0 0x10000>;
|
||||
interrupts = <0 26 0x4>; /* Level high type */
|
||||
num-cs = <6>;
|
||||
spi-num-chipselects = <6>;
|
||||
};
|
||||
|
||||
qspi: quadspi@1550000 {
|
||||
|
|
|
@ -172,7 +172,7 @@
|
|||
#size-cells = <0>;
|
||||
reg = <0x0 0x2100000 0x0 0x10000>;
|
||||
interrupts = <0 26 0x4>; /* Level high type */
|
||||
num-cs = <6>;
|
||||
spi-num-chipselects = <6>;
|
||||
};
|
||||
|
||||
dspi1: dspi@2110000 {
|
||||
|
@ -181,7 +181,7 @@
|
|||
#size-cells = <0>;
|
||||
reg = <0x0 0x2110000 0x0 0x10000>;
|
||||
interrupts = <0 26 0x4>; /* Level high type */
|
||||
num-cs = <6>;
|
||||
spi-num-chipselects = <6>;
|
||||
};
|
||||
|
||||
dspi2: dspi@2120000 {
|
||||
|
@ -190,7 +190,7 @@
|
|||
#size-cells = <0>;
|
||||
reg = <0x0 0x2120000 0x0 0x10000>;
|
||||
interrupts = <0 241 0x4>; /* Level high type */
|
||||
num-cs = <6>;
|
||||
spi-num-chipselects = <6>;
|
||||
};
|
||||
|
||||
gpio0: gpio@2300000 {
|
||||
|
|
|
@ -1087,7 +1087,7 @@
|
|||
};
|
||||
|
||||
watchdog0: watchdog@e8a06000 {
|
||||
compatible = "arm,sp805-wdt", "arm,primecell";
|
||||
compatible = "arm,sp805", "arm,primecell";
|
||||
reg = <0x0 0xe8a06000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&crg_ctrl HI3660_OSC32K>;
|
||||
|
@ -1095,7 +1095,7 @@
|
|||
};
|
||||
|
||||
watchdog1: watchdog@e8a07000 {
|
||||
compatible = "arm,sp805-wdt", "arm,primecell";
|
||||
compatible = "arm,sp805", "arm,primecell";
|
||||
reg = <0x0 0xe8a07000 0x0 0x1000>;
|
||||
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&crg_ctrl HI3660_OSC32K>;
|
||||
|
|
|
@ -190,7 +190,7 @@
|
|||
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "dspi";
|
||||
clocks = <&platform_clk 1>;
|
||||
num-cs = <6>;
|
||||
spi-num-chipselects = <6>;
|
||||
big-endian;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -203,7 +203,7 @@
|
|||
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "dspi";
|
||||
clocks = <&platform_clk 1>;
|
||||
num-cs = <6>;
|
||||
spi-num-chipselects = <6>;
|
||||
big-endian;
|
||||
status = "disabled";
|
||||
};
|
||||
|
@ -469,7 +469,7 @@
|
|||
sata: sata@3200000 {
|
||||
compatible = "fsl,ls1021a-ahci";
|
||||
reg = <0x3200000 0x10000 0x20220520 0x4>;
|
||||
reg-names = "sata-base", "ecc-addr";
|
||||
reg-names = "ahci", "sata-ecc";
|
||||
interrupts = <0 101 4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
|
|
@ -70,7 +70,7 @@
|
|||
#size-cells = <0>;
|
||||
compatible = "fsl,vf610-dspi";
|
||||
reg = <0x4002c000 0x1000>;
|
||||
num-cs = <5>;
|
||||
spi-num-chipselects = <5>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
@ -79,7 +79,7 @@
|
|||
#size-cells = <0>;
|
||||
compatible = "fsl,vf610-dspi";
|
||||
reg = <0x4002d000 0x1000>;
|
||||
num-cs = <5>;
|
||||
spi-num-chipselects = <5>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
|
@ -3,4 +3,4 @@
|
|||
# (C) Copyright 2000-2010
|
||||
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
|
||||
PLATFORM_CPPFLAGS += -mstring -mcpu=860 -msoft-float
|
||||
PLATFORM_CPPFLAGS += -mcpu=860 -msoft-float
|
||||
|
|
|
@ -499,12 +499,8 @@ static int calc_img_key_hash(struct fsl_secboot_img_priv *img)
|
|||
return ret;
|
||||
|
||||
ret = algo->hash_init(algo, &ctx);
|
||||
if (ret) {
|
||||
if (ctx)
|
||||
free(ctx);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Update hash for ESBC key */
|
||||
#ifdef CONFIG_KEY_REVOCATION
|
||||
if (check_srk(img)) {
|
||||
|
@ -519,15 +515,12 @@ static int calc_img_key_hash(struct fsl_secboot_img_priv *img)
|
|||
img->img_key, img->key_len, 1);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Copy hash at destination buffer */
|
||||
ret = algo->hash_finish(algo, ctx, hash_val, algo->digest_size);
|
||||
if (ret) {
|
||||
if (ctx)
|
||||
free(ctx);
|
||||
free(ctx);
|
||||
return ret;
|
||||
}
|
||||
|
||||
for (i = 0; i < SHA256_BYTES; i++)
|
||||
img->img_key_hash[i] = hash_val[i];
|
||||
|
||||
|
@ -554,18 +547,14 @@ static int calc_esbchdr_esbc_hash(struct fsl_secboot_img_priv *img)
|
|||
|
||||
ret = algo->hash_init(algo, &ctx);
|
||||
/* Copy hash at destination buffer */
|
||||
if (ret) {
|
||||
free(ctx);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Update hash for CSF Header */
|
||||
ret = algo->hash_update(algo, ctx,
|
||||
(u8 *)&img->hdr, sizeof(struct fsl_secboot_img_hdr), 0);
|
||||
if (ret) {
|
||||
free(ctx);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Update the hash with that of srk table if srk flag is 1
|
||||
* If IE Table is selected, key is not added in the hash
|
||||
|
@ -592,22 +581,17 @@ static int calc_esbchdr_esbc_hash(struct fsl_secboot_img_priv *img)
|
|||
key_hash = 1;
|
||||
}
|
||||
#endif
|
||||
if (ret) {
|
||||
free(ctx);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
if (!key_hash) {
|
||||
free(ctx);
|
||||
return ERROR_KEY_TABLE_NOT_FOUND;
|
||||
}
|
||||
|
||||
/* Update hash for actual Image */
|
||||
ret = algo->hash_update(algo, ctx,
|
||||
(u8 *)(*(img->img_addr_ptr)), img->img_size, 1);
|
||||
if (ret) {
|
||||
free(ctx);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Copy hash at destination buffer */
|
||||
ret = algo->hash_finish(algo, ctx, hash_val, algo->digest_size);
|
||||
|
|
|
@ -825,10 +825,18 @@ int ft_board_setup(void *blob, struct bd_info *bd)
|
|||
u64 mc_memory_base = 0;
|
||||
u64 mc_memory_size = 0;
|
||||
u16 total_memory_banks;
|
||||
int err;
|
||||
#if CONFIG_IS_ENABLED(TARGET_LX2160ARDB)
|
||||
u8 board_rev;
|
||||
#endif
|
||||
|
||||
err = fdt_increase_size(blob, 512);
|
||||
if (err) {
|
||||
printf("%s fdt_increase_size: err=%s\n", __func__,
|
||||
fdt_strerror(err));
|
||||
return err;
|
||||
}
|
||||
|
||||
ft_cpu_setup(blob, bd);
|
||||
|
||||
fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
|
||||
|
|
|
@ -1,6 +1,7 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
* Copyright 2021 NXP
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
|
@ -83,6 +84,7 @@ found:
|
|||
/* optimize cpo for erratum A-009942 */
|
||||
popts->cpo_sample = 0x59;
|
||||
#else
|
||||
popts->cpo_sample = 0x54;
|
||||
popts->half_strength_driver_enable = 0;
|
||||
#endif
|
||||
/*
|
||||
|
|
|
@ -1,6 +1,7 @@
|
|||
Kontron SMARC-sAL28 board
|
||||
M: Michael Walle <michael@walle.cc>
|
||||
S: Maintained
|
||||
F: arch/arm/dts/fsl-ls1028a.dtsi
|
||||
F: arch/arm/dts/fsl-ls1028a-kontron-sl28-*
|
||||
F: board/kontron/sl28/
|
||||
F: configs/kontron_sl28_defconfig
|
||||
|
|
|
@ -62,6 +62,7 @@ CONFIG_DM_MDIO=y
|
|||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_FMAN_ENET=y
|
||||
CONFIG_SYS_FMAN_FW_ADDR=0x100000
|
||||
CONFIG_MII=y
|
||||
CONFIG_PCIE_FSL=y
|
||||
CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
|
||||
|
|
|
@ -61,6 +61,7 @@ CONFIG_DM_MDIO=y
|
|||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_FMAN_ENET=y
|
||||
CONFIG_SYS_FMAN_FW_ADDR=0xD2000
|
||||
CONFIG_MII=y
|
||||
CONFIG_PCIE_FSL=y
|
||||
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
|
||||
|
|
|
@ -62,6 +62,7 @@ CONFIG_DM_MDIO=y
|
|||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_FMAN_ENET=y
|
||||
CONFIG_SYS_FMAN_FW_ADDR=0x110000
|
||||
CONFIG_MII=y
|
||||
CONFIG_PCIE_FSL=y
|
||||
CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
|
||||
|
|
|
@ -57,6 +57,7 @@ CONFIG_DM_MDIO=y
|
|||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_FMAN_ENET=y
|
||||
CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000
|
||||
CONFIG_MII=y
|
||||
CONFIG_PCIE_FSL=y
|
||||
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
|
||||
|
|
|
@ -60,6 +60,7 @@ CONFIG_PHY_VITESSE=y
|
|||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_FMAN_ENET=y
|
||||
CONFIG_SYS_FMAN_FW_ADDR=0x100000
|
||||
CONFIG_MII=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_FSL=y
|
||||
|
|
|
@ -59,6 +59,7 @@ CONFIG_PHY_VITESSE=y
|
|||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_FMAN_ENET=y
|
||||
CONFIG_SYS_FMAN_FW_ADDR=0xD2000
|
||||
CONFIG_MII=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_FSL=y
|
||||
|
|
|
@ -60,6 +60,7 @@ CONFIG_PHY_VITESSE=y
|
|||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_FMAN_ENET=y
|
||||
CONFIG_SYS_FMAN_FW_ADDR=0x110000
|
||||
CONFIG_MII=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_FSL=y
|
||||
|
|
|
@ -55,6 +55,7 @@ CONFIG_PHY_VITESSE=y
|
|||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_FMAN_ENET=y
|
||||
CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000
|
||||
CONFIG_MII=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_FSL=y
|
||||
|
|
|
@ -58,6 +58,7 @@ CONFIG_PHY_VITESSE=y
|
|||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_FMAN_ENET=y
|
||||
CONFIG_SYS_FMAN_FW_ADDR=0xD2000
|
||||
CONFIG_MII=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_FSL=y
|
||||
|
|
|
@ -59,6 +59,7 @@ CONFIG_PHY_VITESSE=y
|
|||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_FMAN_ENET=y
|
||||
CONFIG_SYS_FMAN_FW_ADDR=0x110000
|
||||
CONFIG_MII=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_FSL=y
|
||||
|
|
|
@ -54,6 +54,7 @@ CONFIG_PHY_VITESSE=y
|
|||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_FMAN_ENET=y
|
||||
CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000
|
||||
CONFIG_MII=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_FSL=y
|
||||
|
|
|
@ -61,6 +61,7 @@ CONFIG_PHY_VITESSE=y
|
|||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_FMAN_ENET=y
|
||||
CONFIG_SYS_FMAN_FW_ADDR=0x100000
|
||||
CONFIG_MII=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_FSL=y
|
||||
|
|
|
@ -59,6 +59,7 @@ CONFIG_PHY_VITESSE=y
|
|||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_FMAN_ENET=y
|
||||
CONFIG_SYS_FMAN_FW_ADDR=0xD2000
|
||||
CONFIG_MII=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_FSL=y
|
||||
|
|
|
@ -60,6 +60,7 @@ CONFIG_PHY_VITESSE=y
|
|||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_FMAN_ENET=y
|
||||
CONFIG_SYS_FMAN_FW_ADDR=0x110000
|
||||
CONFIG_MII=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_FSL=y
|
||||
|
|
|
@ -55,6 +55,7 @@ CONFIG_PHY_VITESSE=y
|
|||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_FMAN_ENET=y
|
||||
CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000
|
||||
CONFIG_MII=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_FSL=y
|
||||
|
|
|
@ -92,6 +92,8 @@ CONFIG_DM_ETH=y
|
|||
CONFIG_DM_MDIO=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_FMAN_ENET=y
|
||||
ONFIG_SYS_FMAN_FW_ADDR=0x180000
|
||||
CONFIG_SYS_QE_FW_ADDR=0x200000
|
||||
CONFIG_MII=y
|
||||
CONFIG_PCIE_FSL=y
|
||||
CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
|
||||
|
|
|
@ -88,6 +88,8 @@ CONFIG_DM_ETH=y
|
|||
CONFIG_DM_MDIO=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_FMAN_ENET=y
|
||||
CONFIG_SYS_FMAN_FW_ADDR=0x104000
|
||||
CONFIG_SYS_QE_FW_ADDR=0x124000
|
||||
CONFIG_MII=y
|
||||
CONFIG_PCIE_FSL=y
|
||||
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
|
||||
|
|
|
@ -90,6 +90,8 @@ CONFIG_DM_ETH=y
|
|||
CONFIG_DM_MDIO=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_FMAN_ENET=y
|
||||
CONFIG_SYS_FMAN_FW_ADDR=0x110000
|
||||
CONFIG_SYS_QE_FW_ADDR=0x130000
|
||||
CONFIG_MII=y
|
||||
CONFIG_PCIE_FSL=y
|
||||
CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
|
||||
|
|
|
@ -73,6 +73,8 @@ CONFIG_DM_ETH=y
|
|||
CONFIG_DM_MDIO=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_FMAN_ENET=y
|
||||
CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000
|
||||
CONFIG_SYS_QE_FW_ADDR=0xEFE00000
|
||||
CONFIG_MII=y
|
||||
CONFIG_PCIE_FSL=y
|
||||
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
|
||||
|
|
|
@ -87,6 +87,8 @@ CONFIG_DM_MDIO=y
|
|||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_FMAN_ENET=y
|
||||
CONFIG_SYS_FMAN_FW_ADDR=0x280000
|
||||
CONFIG_SYS_QE_FW_ADDR=0x380000
|
||||
CONFIG_MII=y
|
||||
CONFIG_PCIE_FSL=y
|
||||
CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
|
||||
|
|
|
@ -83,6 +83,8 @@ CONFIG_DM_MDIO=y
|
|||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_FMAN_ENET=y
|
||||
CONFIG_SYS_FMAN_FW_ADDR=0x10400
|
||||
ONFIG_SYS_QE_FW_ADDR=0x124000
|
||||
CONFIG_MII=y
|
||||
CONFIG_PCIE_FSL=y
|
||||
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
|
||||
|
|
|
@ -85,6 +85,8 @@ CONFIG_DM_MDIO=y
|
|||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_FMAN_ENET=y
|
||||
CONFIG_SYS_FMAN_FW_ADDR=0x110000
|
||||
CONFIG_SYS_QE_FW_ADDR=0x130000
|
||||
CONFIG_MII=y
|
||||
CONFIG_PCIE_FSL=y
|
||||
CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
|
||||
|
|
|
@ -68,6 +68,8 @@ CONFIG_DM_MDIO=y
|
|||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_FMAN_ENET=y
|
||||
CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000
|
||||
CONFIG_SYS_QE_FW_ADDR=0xEFF10000
|
||||
CONFIG_MII=y
|
||||
CONFIG_PCIE_FSL=y
|
||||
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
|
||||
|
|
|
@ -86,6 +86,7 @@ CONFIG_PHY_TERANETICS=y
|
|||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_FMAN_ENET=y
|
||||
CONFIG_SYS_FMAN_FW_ADDR=0x160000
|
||||
CONFIG_MII=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_FSL=y
|
||||
|
|
|
@ -82,6 +82,7 @@ CONFIG_PHY_TERANETICS=y
|
|||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_FMAN_ENET=y
|
||||
CONFIG_SYS_FMAN_FW_ADDR=0x104000
|
||||
CONFIG_MII=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_FSL=y
|
||||
|
|
|
@ -66,6 +66,7 @@ CONFIG_PHY_TERANETICS=y
|
|||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_FMAN_ENET=y
|
||||
CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000
|
||||
CONFIG_MII=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_FSL=y
|
||||
|
|
|
@ -84,6 +84,7 @@ CONFIG_PHY_TERANETICS=y
|
|||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_FMAN_ENET=y
|
||||
CONFIG_SYS_FMAN_FW_ADDR=0x110000
|
||||
CONFIG_MII=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_FSL=y
|
||||
|
|
|
@ -59,6 +59,7 @@ CONFIG_PHY_TERANETICS=y
|
|||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_FMAN_ENET=y
|
||||
CONFIG_SYS_FMAN_FW_ADDR=0xFFE00000
|
||||
CONFIG_MII=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_FSL=y
|
||||
|
|
|
@ -67,6 +67,7 @@ CONFIG_PHY_TERANETICS=y
|
|||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_FMAN_ENET=y
|
||||
CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000
|
||||
CONFIG_MII=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_FSL=y
|
||||
|
|
|
@ -93,6 +93,7 @@ CONFIG_DM_ETH=y
|
|||
CONFIG_DM_MDIO=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_FMAN_ENET=y
|
||||
CONFIG_SYS_FMAN_FW_ADDR=0x180000
|
||||
CONFIG_MII=y
|
||||
CONFIG_PCIE_FSL=y
|
||||
CONFIG_SYS_QE_FMAN_FW_IN_NAND=y
|
||||
|
|
|
@ -89,6 +89,7 @@ CONFIG_DM_ETH=y
|
|||
CONFIG_DM_MDIO=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_FMAN_ENET=y
|
||||
CONFIG_SYS_FMAN_FW_ADDR=0x104000
|
||||
CONFIG_MII=y
|
||||
CONFIG_PCIE_FSL=y
|
||||
CONFIG_SYS_QE_FMAN_FW_IN_MMC=y
|
||||
|
|
|
@ -91,6 +91,7 @@ CONFIG_DM_ETH=y
|
|||
CONFIG_DM_MDIO=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_FMAN_ENET=y
|
||||
CONFIG_SYS_FMAN_FW_ADDR=0x110000
|
||||
CONFIG_MII=y
|
||||
CONFIG_PCIE_FSL=y
|
||||
CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y
|
||||
|
|
|
@ -73,6 +73,7 @@ CONFIG_DM_ETH=y
|
|||
CONFIG_DM_MDIO=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_FMAN_ENET=y
|
||||
ONFIG_SYS_FMAN_FW_ADDR=0xEFF00000
|
||||
CONFIG_MII=y
|
||||
CONFIG_PCIE_FSL=y
|
||||
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
|
||||
|
|
|
@ -94,6 +94,7 @@ CONFIG_DM_ETH=y
|
|||
CONFIG_DM_MDIO=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_FMAN_ENET=y
|
||||
CONFIG_SYS_FMAN_FW_ADDR=0x180000
|
||||
CONFIG_MII=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_FSL=y
|
||||
|
|
|
@ -90,6 +90,7 @@ CONFIG_DM_ETH=y
|
|||
CONFIG_DM_MDIO=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_FMAN_ENET=y
|
||||
CONFIG_SYS_FMAN_FW_ADDR=0x104000
|
||||
CONFIG_MII=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_FSL=y
|
||||
|
|
|
@ -92,6 +92,7 @@ CONFIG_DM_ETH=y
|
|||
CONFIG_DM_MDIO=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_FMAN_ENET=y
|
||||
CONFIG_SYS_FMAN_FW_ADDR=0x110000
|
||||
CONFIG_MII=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_FSL=y
|
||||
|
|
|
@ -74,6 +74,7 @@ CONFIG_DM_ETH=y
|
|||
CONFIG_DM_MDIO=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_FMAN_ENET=y
|
||||
CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000
|
||||
CONFIG_MII=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_FSL=y
|
||||
|
|
|
@ -76,6 +76,7 @@ CONFIG_DM_MDIO=y
|
|||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_FMAN_ENET=y
|
||||
CONFIG_SYS_FMAN_FW_ADDR=0x104000
|
||||
CONFIG_MII=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_FSL=y
|
||||
|
|
|
@ -61,6 +61,7 @@ CONFIG_DM_MDIO=y
|
|||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_FMAN_ENET=y
|
||||
CONFIG_SYS_FMAN_FW_ADDR=0xEFF00000
|
||||
CONFIG_MII=y
|
||||
CONFIG_DM_PCI_COMPAT=y
|
||||
CONFIG_PCIE_FSL=y
|
||||
|
|
|
@ -69,6 +69,8 @@ CONFIG_DM_ETH=y
|
|||
CONFIG_DM_MDIO=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_FMAN_ENET=y
|
||||
CONFIG_SYS_FMAN_FW_ADDR=0xE8020000
|
||||
CONFIG_SYS_QE_FW_ADDR=0xE8040000
|
||||
CONFIG_RGMII=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_PCI_REGION_MULTI_ENTRY=y
|
||||
|
|
|
@ -179,5 +179,6 @@ CONFIG_QE_UEC=y
|
|||
# CONFIG_PINCTRL_FULL is not set
|
||||
CONFIG_QE=y
|
||||
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
|
||||
CONFIG_SYS_QE_FW_ADDR=0xF00C0000
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_BCH=y
|
||||
|
|
|
@ -39,12 +39,14 @@ CONFIG_SYS_SPI_U_BOOT_OFFS=0x230000
|
|||
CONFIG_CMD_ASKENV=y
|
||||
CONFIG_CMD_GREPENV=y
|
||||
CONFIG_CMD_NVEDIT_EFI=y
|
||||
CONFIG_CMD_DFU=y
|
||||
CONFIG_CMD_DM=y
|
||||
CONFIG_CMD_GPT=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_PCI=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_USB_MASS_STORAGE=y
|
||||
CONFIG_CMD_CACHE=y
|
||||
CONFIG_CMD_EFIDEBUG=y
|
||||
CONFIG_CMD_RNG=y
|
||||
|
@ -64,6 +66,8 @@ CONFIG_FSL_CAAM=y
|
|||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_DDR_ECC=y
|
||||
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
|
||||
CONFIG_DFU_MMC=y
|
||||
CONFIG_DFU_SF=y
|
||||
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
|
||||
CONFIG_I2C_MUX=y
|
||||
CONFIG_MMC_HS400_SUPPORT=y
|
||||
|
@ -78,6 +82,7 @@ CONFIG_PHY_FIXED=y
|
|||
CONFIG_DM_DSA=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_FSL_ENETC=y
|
||||
CONFIG_MSCC_FELIX_SWITCH=y
|
||||
CONFIG_NVME=y
|
||||
CONFIG_PCIE_ECAM_GENERIC=y
|
||||
|
@ -90,7 +95,17 @@ CONFIG_FSL_DSPI=y
|
|||
CONFIG_NXP_FSPI=y
|
||||
CONFIG_USB=y
|
||||
# CONFIG_SPL_DM_USB is not set
|
||||
CONFIG_DM_USB_GADGET=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
# CONFIG_USB_XHCI_FSL is not set
|
||||
CONFIG_USB_DWC3=y
|
||||
CONFIG_USB_DWC3_LAYERSCAPE=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_DOWNLOAD=y
|
||||
CONFIG_OF_LIBFDT_ASSUME_MASK=0x0
|
||||
CONFIG_OF_LIBFDT_OVERLAY=y
|
||||
CONFIG_EFI_SET_TIME=y
|
||||
CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y
|
||||
CONFIG_EFI_CAPSULE_ON_DISK=y
|
||||
CONFIG_EFI_IGNORE_OSINDICATIONS=y
|
||||
CONFIG_EFI_CAPSULE_FIRMWARE_FIT=y
|
||||
|
|
|
@ -63,3 +63,4 @@ CONFIG_FSL_QSPI=y
|
|||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_SYS_QE_FW_ADDR=0xf40000
|
||||
|
|
|
@ -79,3 +79,4 @@ CONFIG_FSL_QSPI=y
|
|||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_SYS_QE_FW_ADDR=0xf40000
|
||||
|
|
|
@ -84,3 +84,4 @@ CONFIG_USB=y
|
|||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_SYS_QE_FW_ADDR=0x60940000
|
||||
|
|
|
@ -84,3 +84,4 @@ CONFIG_USB=y
|
|||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_SYS_QE_FW_ADDR=0x60940000
|
||||
|
|
|
@ -105,3 +105,4 @@ CONFIG_USB=y
|
|||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_SYS_QE_FW_ADDR=0x60940000
|
||||
|
|
|
@ -83,3 +83,4 @@ CONFIG_USB_XHCI_DWC3=y
|
|||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_RSA=y
|
||||
CONFIG_SPL_RSA=y
|
||||
CONFIG_SYS_QE_FW_ADDR=0x60940000
|
||||
|
|
|
@ -85,3 +85,4 @@ CONFIG_USB=y
|
|||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_SYS_QE_FW_ADDR=0x60940000
|
||||
|
|
|
@ -85,3 +85,4 @@ CONFIG_USB=y
|
|||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_SYS_QE_FW_ADDR=0x60940000
|
||||
|
|
|
@ -80,3 +80,4 @@ CONFIG_USB=y
|
|||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_SYS_QE_FW_ADDR=0x940000
|
||||
|
|
|
@ -102,3 +102,4 @@ CONFIG_USB=y
|
|||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_SYS_QE_FW_ADDR=0x940000
|
||||
|
|
|
@ -97,3 +97,4 @@ CONFIG_USB=y
|
|||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_SYS_QE_FW_ADDR=0x940000
|
||||
|
|
|
@ -70,3 +70,4 @@ CONFIG_USB_XHCI_HCD=y
|
|||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_RSA=y
|
||||
CONFIG_SPL_RSA=y
|
||||
CONFIG_SYS_QE_FW_ADDR=0x60940000
|
||||
|
|
|
@ -72,3 +72,4 @@ CONFIG_SYS_NS16550=y
|
|||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_SYS_QE_FW_ADDR=0x60940000
|
||||
|
|
|
@ -73,3 +73,4 @@ CONFIG_FSL_LPUART=y
|
|||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_SYS_QE_FW_ADDR=0x60940000
|
||||
|
|
|
@ -74,3 +74,4 @@ CONFIG_FSL_QSPI=y
|
|||
CONFIG_USB=y
|
||||
CONFIG_USB_XHCI_HCD=y
|
||||
CONFIG_USB_XHCI_DWC3=y
|
||||
CONFIG_SYS_QE_FW_ADDR=0x940000
|
||||
|
|
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue