mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 07:04:28 +00:00
Convert CONFIG_NAND_FSL_ELBC et al to Kconfig
This converts the following to Kconfig: CONFIG_NAND_FSL_ELBC CONFIG_NAND_FSL_IFC Note that a number of PowerPC platforms had previously enabled CONFIG_NAND_FSL_ELBC without CONFIG_MTD_RAW_NAND, and now they no longer enable the option, reducing the size of a few functions. Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
parent
b2e25afabd
commit
53f06134ed
108 changed files with 96 additions and 38 deletions
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@ -167,7 +167,6 @@
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#define CONFIG_SYS_FSL_DSP_M2_RAM_ADDR 0xb0000000
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#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
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#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
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#define CONFIG_NAND_FSL_IFC
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#define CONFIG_ESDHC_HC_BLK_ADDR
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#elif defined(CONFIG_ARCH_BSC9132)
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@ -179,7 +178,6 @@
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#define CONFIG_SYS_FSL_DSP_M3_RAM_ADDR 0xc0000000
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#define CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT 0xff600000
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#define CONFIG_SYS_FSL_IFC_BANK_COUNT 3
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#define CONFIG_NAND_FSL_IFC
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#define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
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#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
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#define CONFIG_ESDHC_HC_BLK_ADDR
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@ -68,6 +68,7 @@ CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x4000
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SF_DEFAULT_MODE=0
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@ -67,6 +67,7 @@ CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x4000
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SF_DEFAULT_MODE=0
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@ -70,6 +70,7 @@ CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x80000
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_DM_SPI_FLASH=y
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@ -69,6 +69,7 @@ CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x80000
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_DM_SPI_FLASH=y
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@ -68,6 +68,7 @@ CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_ELBC=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x4000
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SF_DEFAULT_MODE=0
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@ -67,6 +67,7 @@ CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_ELBC=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x4000
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SF_DEFAULT_MODE=0
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@ -71,6 +71,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_FLASH_CFI_MTD=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_ELBC=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SF_DEFAULT_MODE=0
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@ -73,6 +73,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_FLASH_CFI_MTD=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_ELBC=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x4000
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SF_DEFAULT_MODE=0
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@ -72,6 +72,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_FLASH_CFI_MTD=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_ELBC=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x4000
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SF_DEFAULT_MODE=0
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@ -49,6 +49,7 @@ CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_ELBC=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SF_DEFAULT_MODE=0
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CONFIG_SF_DEFAULT_SPEED=10000000
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@ -49,6 +49,7 @@ CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_ELBC=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SF_DEFAULT_MODE=0
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CONFIG_SF_DEFAULT_SPEED=10000000
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@ -50,6 +50,7 @@ CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_ELBC=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SF_DEFAULT_MODE=0
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CONFIG_SF_DEFAULT_SPEED=10000000
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@ -80,6 +80,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_FLASH_CFI_MTD=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x80000
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_DM_SPI_FLASH=y
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@ -74,6 +74,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_FLASH_CFI_MTD=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x80000
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_DM_SPI_FLASH=y
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@ -72,6 +72,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_FLASH_CFI_MTD=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_DM_SPI_FLASH=y
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@ -78,6 +78,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_FLASH_CFI_MTD=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x80000
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_DM_SPI_FLASH=y
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@ -79,6 +79,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_FLASH_CFI_MTD=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x80000
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_DM_SPI_FLASH=y
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@ -170,6 +170,7 @@ CONFIG_FLASH_CFI_MTD=y
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CONFIG_SYS_FLASH_PROTECTION=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_ELBC=y
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CONFIG_PHY_ATHEROS=y
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CONFIG_PHY_BROADCOM=y
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CONFIG_PHY_DAVICOM=y
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@ -59,6 +59,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_FLASH_CFI_MTD=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_PHYLIB=y
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CONFIG_PHYLIB_10G=y
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@ -65,6 +65,7 @@ CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_PHY_REALTEK=y
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CONFIG_PHY_GIGE=y
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@ -66,6 +66,7 @@ CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_PHY_REALTEK=y
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CONFIG_PHY_GIGE=y
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@ -86,6 +86,7 @@ CONFIG_MTD_NOR_FLASH=y
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CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_PHY_REALTEK=y
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@ -64,6 +64,7 @@ CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_PHY_REALTEK=y
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CONFIG_PHY_GIGE=y
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@ -66,6 +66,7 @@ CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_PHY_REALTEK=y
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CONFIG_PHY_GIGE=y
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@ -67,6 +67,7 @@ CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_PHY_REALTEK=y
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CONFIG_PHY_GIGE=y
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@ -85,6 +85,7 @@ CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_PHY_REALTEK=y
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CONFIG_PHY_GIGE=y
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@ -60,6 +60,7 @@ CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SF_DEFAULT_BUS=1
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CONFIG_PHYLIB=y
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@ -61,6 +61,7 @@ CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SF_DEFAULT_BUS=1
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CONFIG_PHYLIB=y
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@ -79,6 +79,7 @@ CONFIG_MTD_NOR_FLASH=y
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CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SF_DEFAULT_BUS=1
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@ -61,6 +61,7 @@ CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SF_DEFAULT_BUS=1
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CONFIG_PHYLIB=y
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@ -80,6 +80,7 @@ CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SF_DEFAULT_BUS=1
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CONFIG_PHYLIB=y
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@ -60,6 +60,7 @@ CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SF_DEFAULT_BUS=1
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# CONFIG_SPI_FLASH_BAR is not set
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@ -70,6 +70,7 @@ CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SF_DEFAULT_BUS=1
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# CONFIG_SPI_FLASH_BAR is not set
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@ -47,6 +47,7 @@ CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SF_DEFAULT_BUS=1
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CONFIG_PHYLIB=y
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@ -50,6 +50,7 @@ CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SF_DEFAULT_BUS=1
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CONFIG_PHYLIB=y
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@ -61,6 +61,7 @@ CONFIG_MTD_NOR_FLASH=y
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CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SF_DEFAULT_BUS=1
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@ -69,6 +69,7 @@ CONFIG_MTD_NOR_FLASH=y
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CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SF_DEFAULT_BUS=1
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@ -64,6 +64,7 @@ CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SF_DEFAULT_BUS=1
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CONFIG_PHYLIB=y
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@ -69,6 +69,7 @@ CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SF_DEFAULT_BUS=1
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CONFIG_PHYLIB=y
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@ -49,6 +49,7 @@ CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SF_DEFAULT_BUS=1
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CONFIG_PHYLIB=y
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@ -55,6 +55,7 @@ CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_MTD_RAW_NAND=y
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CONFIG_NAND_FSL_IFC=y
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CONFIG_SYS_NAND_ONFI_DETECTION=y
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CONFIG_SF_DEFAULT_BUS=1
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CONFIG_PHYLIB=y
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||||
|
|
|
@ -41,6 +41,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x52
|
|||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_FSL_IFC=y
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
# CONFIG_SPI_FLASH_BAR is not set
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
|
|
|
@ -47,6 +47,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x52
|
|||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_FSL_IFC=y
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
# CONFIG_SPI_FLASH_BAR is not set
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
|
|
|
@ -57,6 +57,7 @@ CONFIG_FLASH_CFI_DRIVER=y
|
|||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_FSL_IFC=y
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
CONFIG_SF_DEFAULT_BUS=1
|
||||
CONFIG_PHYLIB=y
|
||||
|
|
|
@ -60,6 +60,7 @@ CONFIG_FLASH_CFI_DRIVER=y
|
|||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_FSL_IFC=y
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
CONFIG_SF_DEFAULT_BUS=1
|
||||
CONFIG_PHYLIB=y
|
||||
|
|
|
@ -61,6 +61,7 @@ CONFIG_FLASH_CFI_DRIVER=y
|
|||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_FSL_IFC=y
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
CONFIG_SF_DEFAULT_BUS=1
|
||||
CONFIG_PHYLIB=y
|
||||
|
|
|
@ -71,6 +71,7 @@ CONFIG_MTD_NOR_FLASH=y
|
|||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_NAND_FSL_IFC=y
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
CONFIG_SF_DEFAULT_BUS=1
|
||||
CONFIG_PHYLIB=y
|
||||
|
|
|
@ -80,6 +80,7 @@ CONFIG_FLASH_CFI_DRIVER=y
|
|||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_FSL_IFC=y
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
CONFIG_SF_DEFAULT_BUS=1
|
||||
CONFIG_PHYLIB=y
|
||||
|
|
|
@ -60,6 +60,7 @@ CONFIG_FLASH_CFI_DRIVER=y
|
|||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_FSL_IFC=y
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
CONFIG_SF_DEFAULT_BUS=1
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
|
|
|
@ -69,6 +69,7 @@ CONFIG_FLASH_CFI_DRIVER=y
|
|||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_FSL_IFC=y
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
CONFIG_SF_DEFAULT_BUS=1
|
||||
# CONFIG_SPI_FLASH_BAR is not set
|
||||
|
|
|
@ -69,6 +69,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x53
|
|||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_FSL_IFC=y
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
# CONFIG_SPI_FLASH_BAR is not set
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
|
|
|
@ -50,6 +50,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x53
|
|||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_FSL_IFC=y
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
# CONFIG_SPI_FLASH_BAR is not set
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
|
|
|
@ -54,6 +54,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x53
|
|||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_FSL_IFC=y
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
# CONFIG_SPI_FLASH_BAR is not set
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
|
|
|
@ -73,6 +73,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x53
|
|||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_FSL_IFC=y
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
# CONFIG_SPI_FLASH_BAR is not set
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
|
|
|
@ -66,6 +66,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x53
|
|||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_FSL_IFC=y
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
# CONFIG_SPI_FLASH_BAR is not set
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
|
|
|
@ -67,6 +67,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x53
|
|||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_FSL_IFC=y
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
# CONFIG_SPI_FLASH_BAR is not set
|
||||
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
|
||||
|
|
|
@ -47,6 +47,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x53
|
|||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_FSL_IFC=y
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
# CONFIG_SPI_FLASH_BAR is not set
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
|
|
|
@ -53,6 +53,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x53
|
|||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_FSL_IFC=y
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
# CONFIG_SPI_FLASH_BAR is not set
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
|
|
|
@ -58,6 +58,7 @@ CONFIG_FLASH_CFI_DRIVER=y
|
|||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_FSL_IFC=y
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_PHYLIB=y
|
||||
|
|
|
@ -51,6 +51,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x57
|
|||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_FSL_IFC=y
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
# CONFIG_SPI_FLASH_BAR is not set
|
||||
|
|
|
@ -54,6 +54,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x57
|
|||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_FSL_IFC=y
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
# CONFIG_SPI_FLASH_BAR is not set
|
||||
|
|
|
@ -69,6 +69,7 @@ CONFIG_FLASH_CFI_DRIVER=y
|
|||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_FSL_IFC=y
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHYLIB_10G=y
|
||||
|
|
|
@ -64,6 +64,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x57
|
|||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_FSL_IFC=y
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
# CONFIG_SPI_FLASH_BAR is not set
|
||||
|
|
|
@ -70,6 +70,7 @@ CONFIG_FLASH_CFI_DRIVER=y
|
|||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_FSL_IFC=y
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
# CONFIG_SPI_FLASH_BAR is not set
|
||||
|
|
|
@ -55,6 +55,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x57
|
|||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_FSL_IFC=y
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
# CONFIG_SPI_FLASH_BAR is not set
|
||||
|
|
|
@ -58,6 +58,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x57
|
|||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_FSL_IFC=y
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
# CONFIG_SPI_FLASH_BAR is not set
|
||||
|
|
|
@ -68,6 +68,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x57
|
|||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_FSL_IFC=y
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
# CONFIG_SPI_FLASH_BAR is not set
|
||||
|
|
|
@ -68,6 +68,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x57
|
|||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_FSL_IFC=y
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
# CONFIG_SPI_FLASH_BAR is not set
|
||||
|
|
|
@ -56,6 +56,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x57
|
|||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_FSL_IFC=y
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
# CONFIG_SPI_FLASH_BAR is not set
|
||||
|
|
|
@ -62,6 +62,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x57
|
|||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_FSL_IFC=y
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
# CONFIG_SPI_FLASH_BAR is not set
|
||||
|
|
|
@ -51,6 +51,7 @@ CONFIG_FLASH_CFI_DRIVER=y
|
|||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_FSL_IFC=y
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_PHYLIB=y
|
||||
|
|
|
@ -54,6 +54,7 @@ CONFIG_FLASH_CFI_DRIVER=y
|
|||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_FSL_IFC=y
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_PHYLIB=y
|
||||
|
|
|
@ -61,6 +61,7 @@ CONFIG_SYS_I2C_EARLY_INIT=y
|
|||
CONFIG_SYS_I2C_EEPROM_ADDR=0x57
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_NAND_FSL_IFC=y
|
||||
CONFIG_SYS_NAND_BLOCK_SIZE=0x20000
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
|
|
|
@ -52,6 +52,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x57
|
|||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_FSL_IFC=y
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
# CONFIG_SPI_FLASH_BAR is not set
|
||||
|
|
|
@ -58,6 +58,7 @@ CONFIG_SYS_I2C_EEPROM_ADDR=0x57
|
|||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_FSL_IFC=y
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
# CONFIG_SPI_FLASH_BAR is not set
|
||||
|
|
|
@ -51,6 +51,7 @@ CONFIG_FLASH_CFI_DRIVER=y
|
|||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_FSL_IFC=y
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_PHYLIB=y
|
||||
|
|
|
@ -54,6 +54,7 @@ CONFIG_FLASH_CFI_DRIVER=y
|
|||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_FSL_IFC=y
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_PHYLIB=y
|
||||
|
|
|
@ -63,6 +63,7 @@ CONFIG_MTD_NOR_FLASH=y
|
|||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_NAND_FSL_IFC=y
|
||||
CONFIG_SYS_NAND_BLOCK_SIZE=0x80000
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
CONFIG_PHYLIB=y
|
||||
|
|
|
@ -67,6 +67,7 @@ CONFIG_FLASH_CFI_DRIVER=y
|
|||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_FSL_IFC=y
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
CONFIG_PHYLIB=y
|
||||
|
|
|
@ -58,6 +58,7 @@ CONFIG_FLASH_CFI_DRIVER=y
|
|||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_FSL_IFC=y
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
# CONFIG_SPI_FLASH_BAR is not set
|
||||
|
|
|
@ -65,6 +65,7 @@ CONFIG_FLASH_CFI_DRIVER=y
|
|||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_FSL_IFC=y
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
CONFIG_DM_SPI_FLASH=y
|
||||
# CONFIG_SPI_FLASH_BAR is not set
|
||||
|
|
|
@ -62,6 +62,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
|||
CONFIG_FLASH_CFI_MTD=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_FSL_IFC=y
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_FIXED=y
|
||||
|
|
|
@ -62,6 +62,7 @@ CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
|||
CONFIG_FLASH_CFI_MTD=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_NAND_FSL_IFC=y
|
||||
CONFIG_SYS_NAND_ONFI_DETECTION=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_FIXED=y
|
||||
|
|
|
@ -126,6 +126,17 @@ config NAND_DENALI_DT
|
|||
Enable the driver for NAND flash on platforms using a Denali NAND
|
||||
controller as a DT device.
|
||||
|
||||
config NAND_FSL_ELBC
|
||||
bool "Support Freescale Enhanced Local Bus Controller FCM NAND driver"
|
||||
depends on FSL_ELBC
|
||||
help
|
||||
Enable the Freescale Enhanced Local Bus Controller FCM NAND driver.
|
||||
|
||||
config NAND_FSL_IFC
|
||||
bool "Support Freescale Integrated Flash Controller NAND driver"
|
||||
help
|
||||
Enable the Freescale Integrated Flash Controller NAND driver.
|
||||
|
||||
config NAND_LPC32XX_MLC
|
||||
bool "Support LPC32XX_MLC controller"
|
||||
help
|
||||
|
|
|
@ -14,7 +14,6 @@
|
|||
#include <linux/stringify.h>
|
||||
|
||||
#include <asm/config_mpc85xx.h>
|
||||
#define CONFIG_NAND_FSL_IFC
|
||||
|
||||
#ifdef CONFIG_SDCARD
|
||||
#define CONFIG_SPL_FLUSH_IMAGE
|
||||
|
|
|
@ -159,7 +159,6 @@ unsigned long get_board_sys_clk(unsigned long dummy);
|
|||
#define CONFIG_SYS_RAMBOOT
|
||||
#endif
|
||||
|
||||
#define CONFIG_NAND_FSL_ELBC
|
||||
/* Nand Flash */
|
||||
#ifdef CONFIG_NAND_FSL_ELBC
|
||||
#define CONFIG_SYS_NAND_BASE 0xffa00000
|
||||
|
|
|
@ -9,7 +9,6 @@
|
|||
*/
|
||||
#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
|
||||
|
||||
#define CONFIG_NAND_FSL_ELBC
|
||||
#define CONFIG_FSL_SATA_V2
|
||||
#define CONFIG_PCIE3
|
||||
#define CONFIG_PCIE4
|
||||
|
|
|
@ -9,7 +9,6 @@
|
|||
*/
|
||||
#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */
|
||||
|
||||
#define CONFIG_NAND_FSL_ELBC
|
||||
#define CONFIG_PCIE3
|
||||
#define CONFIG_FSL_SATA_V2
|
||||
#define CONFIG_SYS_FSL_RAID_ENGINE
|
||||
|
|
|
@ -242,7 +242,6 @@ unsigned long get_board_sys_clk(void);
|
|||
#endif
|
||||
|
||||
/* NAND Flash on IFC */
|
||||
#define CONFIG_NAND_FSL_IFC
|
||||
#define CONFIG_SYS_NAND_BASE 0xff800000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
|
||||
|
|
|
@ -236,7 +236,6 @@
|
|||
#define CONFIG_SYS_CS2_FTIM3 0x0
|
||||
|
||||
/* NAND Flash on IFC */
|
||||
#define CONFIG_NAND_FSL_IFC
|
||||
#define CONFIG_SYS_NAND_BASE 0xff800000
|
||||
#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
|
||||
|
||||
|
|
|
@ -214,7 +214,6 @@ unsigned long get_board_sys_clk(void);
|
|||
#define CONFIG_SYS_CS3_FTIM3 0x0
|
||||
|
||||
/* NAND Flash on IFC */
|
||||
#define CONFIG_NAND_FSL_IFC
|
||||
#define CONFIG_SYS_NAND_BASE 0xff800000
|
||||
#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
|
||||
|
||||
|
|
|
@ -188,7 +188,6 @@ unsigned long get_board_sys_clk(void);
|
|||
#define CONFIG_SYS_CS2_FTIM3 0x0
|
||||
|
||||
/* NAND Flash on IFC */
|
||||
#define CONFIG_NAND_FSL_IFC
|
||||
#define CONFIG_SYS_NAND_BASE 0xff800000
|
||||
#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
|
||||
|
||||
|
|
|
@ -284,7 +284,6 @@ unsigned long get_board_sys_clk(void);
|
|||
+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
|
||||
|
||||
/* NAND Flash on IFC */
|
||||
#define CONFIG_NAND_FSL_IFC
|
||||
#define CONFIG_SYS_NAND_MAX_ECCPOS 256
|
||||
#define CONFIG_SYS_NAND_MAX_OOBFREE 2
|
||||
#define CONFIG_SYS_NAND_BASE 0xff800000
|
||||
|
|
|
@ -129,7 +129,6 @@
|
|||
*/
|
||||
#define CONFIG_SYS_NAND_BASE 0xE1000000
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_NAND_FSL_ELBC
|
||||
#define NAND_CACHE_PAGES 64
|
||||
|
||||
|
||||
|
|
|
@ -94,7 +94,6 @@
|
|||
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
|
||||
|
||||
/* NAND Flash Definitions */
|
||||
#define CONFIG_NAND_FSL_IFC
|
||||
#define CONFIG_SYS_NAND_BASE 0x68000000
|
||||
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
|
||||
|
||||
|
|
|
@ -256,7 +256,6 @@
|
|||
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
|
||||
|
||||
/* NAND Flash on IFC CS1*/
|
||||
#define CONFIG_NAND_FSL_IFC
|
||||
#define CONFIG_SYS_NAND_BASE 0xfa000000
|
||||
#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
|
||||
|
||||
|
|
|
@ -125,7 +125,6 @@ unsigned long get_board_sys_clk(void);
|
|||
/*
|
||||
* NAND Flash Definitions
|
||||
*/
|
||||
#define CONFIG_NAND_FSL_IFC
|
||||
|
||||
#define CONFIG_SYS_NAND_BASE 0x7e800000
|
||||
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
|
||||
|
|
|
@ -111,7 +111,6 @@ unsigned long get_board_sys_clk(void);
|
|||
/*
|
||||
* NAND Flash Definitions
|
||||
*/
|
||||
#define CONFIG_NAND_FSL_IFC
|
||||
|
||||
#define CONFIG_SYS_NAND_BASE 0x7e800000
|
||||
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
|
||||
|
|
|
@ -72,9 +72,6 @@
|
|||
/*
|
||||
* NAND Flash Definitions
|
||||
*/
|
||||
#ifndef SPL_NO_IFC
|
||||
#define CONFIG_NAND_FSL_IFC
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_NAND_BASE 0x7e800000
|
||||
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
|
||||
|
|
Some files were not shown because too many files have changed in this diff Show more
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Reference in a new issue