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clk: ast2600: Add RSACLK control for ACRY

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Add RSACLK enable for ACRY, the HW RSA/ECC crypto engine
of ASPEED AST2600 SoCs.

Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
This commit is contained in:
Chia-Wei Wang 2021-10-27 14:17:29 +08:00 committed by Tom Rini
parent a2f16d0073
commit af6451187c
2 changed files with 25 additions and 0 deletions
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1
arch/arm/include/asm/arch-aspeed/scu_ast2600.h
View file

@ -8,6 +8,7 @@
#define SCU_UNLOCK_KEY 0x1688a8a8
#define SCU_CLKGATE1_EMMC BIT(27)
#define SCU_CLKGATE1_ACRY BIT(24)
#define SCU_CLKGATE1_MAC2 BIT(21)
#define SCU_CLKGATE1_MAC1 BIT(20)
#define SCU_CLKGATE1_USB_HUB BIT(14)

24
drivers/clk/aspeed/clk_ast2600.c
View file

@ -1018,6 +1018,7 @@ static ulong ast2600_enable_haceclk(struct ast2600_scu *scu)
uint32_t reset_bit;
uint32_t clkgate_bit;
/* share the same reset control bit with ACRY */
reset_bit = BIT(ASPEED_RESET_HACE);
clkgate_bit = SCU_CLKGATE1_HACE;
@ -1032,6 +1033,26 @@ static ulong ast2600_enable_haceclk(struct ast2600_scu *scu)
return 0;
}
static ulong ast2600_enable_rsaclk(struct ast2600_scu *scu)
{
uint32_t reset_bit;
uint32_t clkgate_bit;
/* same reset control bit with HACE */
reset_bit = BIT(ASPEED_RESET_HACE);
clkgate_bit = SCU_CLKGATE1_ACRY;
/*
* we don't do reset assertion here as HACE
* shares the same reset control with ACRY
*/
writel(clkgate_bit, &scu->clkgate_clr1);
mdelay(20);
writel(reset_bit, &scu->modrst_clr1);
return 0;
}
static int ast2600_clk_enable(struct clk *clk)
{
struct ast2600_clk_priv *priv = dev_get_priv(clk->dev);
@ -1073,6 +1094,9 @@ static int ast2600_clk_enable(struct clk *clk)
case ASPEED_CLK_GATE_YCLK:
ast2600_enable_haceclk(priv->scu);
break;
case ASPEED_CLK_GATE_RSACLK:
ast2600_enable_rsaclk(priv->scu);
break;
default:
pr_err("can't enable clk\n");
return -ENOENT;