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https://github.com/AsahiLinux/u-boot
synced 2024-11-10 15:14:43 +00:00
Convert CONFIG_TPL_TEXT_BASE to Kconfig
This converts the following to Kconfig: CONFIG_TPL_TEXT_BASE Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
parent
ed35de6170
commit
1b46518736
17 changed files with 13 additions and 23 deletions
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@ -8,7 +8,6 @@ config ROCKCHIP_PX30
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select SPL
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select TPL
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select TPL_TINY_FRAMEWORK if TPL
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select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
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select TPL_NEEDS_SEPARATE_STACK if TPL
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imply SPL_SEPARATE_BSS
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select SPL_SERIAL
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@ -80,7 +79,6 @@ config ROCKCHIP_RK322X
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select TPL
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select TPL_DM
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select TPL_OF_LIBFDT
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select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
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select TPL_NEEDS_SEPARATE_STACK if TPL
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select SPL_DRIVERS_MISC
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imply ROCKCHIP_COMMON_BOARD
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@ -112,7 +110,6 @@ config ROCKCHIP_RK3288
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imply TPL_DRIVERS_MISC
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imply TPL_LIBCOMMON_SUPPORT
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imply TPL_LIBGENERIC_SUPPORT
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imply TPL_NEEDS_SEPARATE_TEXT_BASE
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imply TPL_NEEDS_SEPARATE_STACK
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imply TPL_OF_CONTROL
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imply TPL_OF_PLATDATA
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@ -160,7 +157,6 @@ config ROCKCHIP_RK3328
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select SPL
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select SUPPORT_TPL
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select TPL
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select TPL_NEEDS_SEPARATE_TEXT_BASE if TPL
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select TPL_NEEDS_SEPARATE_STACK if TPL
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imply ROCKCHIP_COMMON_BOARD
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imply ROCKCHIP_SDRAM_COMMON
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@ -183,7 +179,6 @@ config ROCKCHIP_RK3368
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select ARM64
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select SUPPORT_SPL
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select SUPPORT_TPL
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select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL
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select TPL_NEEDS_SEPARATE_STACK if TPL
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imply ROCKCHIP_COMMON_BOARD
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imply SPL_ROCKCHIP_COMMON_BOARD
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@ -216,7 +211,6 @@ config ROCKCHIP_RK3399
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select SPL_RAM if SPL
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select SPL_REGMAP if SPL
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select SPL_SYSCON if SPL
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select TPL_NEEDS_SEPARATE_TEXT_BASE if TPL
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select TPL_NEEDS_SEPARATE_STACK if TPL
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select SPL_SEPARATE_BSS
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select SPL_SERIAL
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@ -1351,14 +1351,6 @@ config TPL_LDSCRIPT
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May be left empty to trigger the Makefile infrastructure to
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fall back to the linker-script used for the SPL stage.
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config TPL_NEEDS_SEPARATE_TEXT_BASE
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bool "TPL needs a separate text-base"
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depends on TPL
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help
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Enable, if the TPL stage should not inherit its text-base
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from the SPL stage. When enabled, a base address for the
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.text sections of the TPL stage has to be set below.
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config TPL_NEEDS_SEPARATE_STACK
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bool "TPL needs a separate initial stack-pointer"
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depends on TPL
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@ -1380,7 +1372,6 @@ config TPL_POWER
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config TPL_TEXT_BASE
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hex "Base address for the .text section of the TPL stage"
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depends on TPL_NEEDS_SEPARATE_TEXT_BASE
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help
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The base address for the .text section of the TPL stage.
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@ -6,6 +6,7 @@ CONFIG_ENV_OFFSET=0x100000
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CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b"
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CONFIG_SPL_TEXT_BASE=0xFF800000
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CONFIG_SPL_SERIAL=y
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CONFIG_TPL_TEXT_BASE=0xD0001000
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CONFIG_TPL_LIBCOMMON_SUPPORT=y
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CONFIG_TPL_LIBGENERIC_SUPPORT=y
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CONFIG_SPL_DRIVERS_MISC=y
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@ -6,6 +6,7 @@ CONFIG_ENV_OFFSET=0x100000
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CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa"
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CONFIG_SPL_TEXT_BASE=0xFF800000
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CONFIG_SPL_SERIAL=y
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CONFIG_TPL_TEXT_BASE=0xD0001000
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CONFIG_TPL_LIBCOMMON_SUPPORT=y
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CONFIG_TPL_LIBGENERIC_SUPPORT=y
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CONFIG_SPL_DRIVERS_MISC=y
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@ -6,6 +6,7 @@ CONFIG_ENV_OFFSET=0x100000
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CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b"
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CONFIG_SPL_TEXT_BASE=0xFF800000
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CONFIG_SPL_SERIAL=y
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CONFIG_TPL_TEXT_BASE=0xD0001000
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CONFIG_TPL_LIBCOMMON_SUPPORT=y
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CONFIG_TPL_LIBGENERIC_SUPPORT=y
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CONFIG_SPL_DRIVERS_MISC=y
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@ -6,6 +6,7 @@ CONFIG_ENV_OFFSET=0x100000
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CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb"
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CONFIG_SPL_TEXT_BASE=0xFF800000
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CONFIG_SPL_SERIAL=y
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CONFIG_TPL_TEXT_BASE=0xD0001000
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CONFIG_TPL_LIBCOMMON_SUPPORT=y
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CONFIG_TPL_LIBGENERIC_SUPPORT=y
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CONFIG_SPL_DRIVERS_MISC=y
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@ -6,6 +6,7 @@ CONFIG_ENV_OFFSET=0x100000
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CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b"
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CONFIG_SPL_TEXT_BASE=0xFF800000
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CONFIG_SPL_SERIAL=y
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CONFIG_TPL_TEXT_BASE=0xF8F81000
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CONFIG_TPL_LIBCOMMON_SUPPORT=y
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CONFIG_TPL_LIBGENERIC_SUPPORT=y
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CONFIG_SPL=y
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@ -6,6 +6,7 @@ CONFIG_ENV_OFFSET=0x100000
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CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc"
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CONFIG_SPL_TEXT_BASE=0xFF800000
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CONFIG_SPL_SERIAL=y
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CONFIG_TPL_TEXT_BASE=0xF8F81000
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CONFIG_TPL_LIBCOMMON_SUPPORT=y
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CONFIG_TPL_LIBGENERIC_SUPPORT=y
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CONFIG_SPL=y
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@ -6,6 +6,7 @@ CONFIG_ENV_OFFSET=0x100000
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CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd"
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CONFIG_SPL_TEXT_BASE=0xFF800000
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CONFIG_SPL_SERIAL=y
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CONFIG_TPL_TEXT_BASE=0xF8F81000
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CONFIG_TPL_LIBCOMMON_SUPPORT=y
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CONFIG_TPL_LIBGENERIC_SUPPORT=y
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CONFIG_SPL=y
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@ -6,6 +6,7 @@ CONFIG_ENV_OFFSET=0x100000
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CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b"
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CONFIG_SPL_TEXT_BASE=0xFF800000
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CONFIG_SPL_SERIAL=y
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CONFIG_TPL_TEXT_BASE=0xF8F81000
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CONFIG_TPL_LIBCOMMON_SUPPORT=y
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CONFIG_TPL_LIBGENERIC_SUPPORT=y
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CONFIG_SPL=y
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@ -6,6 +6,7 @@ CONFIG_ENV_OFFSET=0x100000
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CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc"
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CONFIG_SPL_TEXT_BASE=0xFF800000
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CONFIG_SPL_SERIAL=y
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CONFIG_TPL_TEXT_BASE=0xF8F81000
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CONFIG_TPL_LIBCOMMON_SUPPORT=y
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CONFIG_TPL_LIBGENERIC_SUPPORT=y
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CONFIG_SPL=y
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@ -6,6 +6,7 @@ CONFIG_MAX_CPUS=8
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CONFIG_SPL_DM_SPI=y
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CONFIG_DEFAULT_DEVICE_TREE="chromebook_coral"
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CONFIG_SPL_TEXT_BASE=0xfef10000
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CONFIG_TPL_TEXT_BASE=0xffff8000
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CONFIG_SPL_SYS_MALLOC_F_LEN=0xf000
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CONFIG_BOOTSTAGE_STASH_ADDR=0xfef00000
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CONFIG_DEBUG_UART_BOARD_INIT=y
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@ -8,6 +8,7 @@ CONFIG_ENV_SECT_SIZE=0x1000
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CONFIG_SPL_DM_SPI=y
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CONFIG_DEFAULT_DEVICE_TREE="chromebook_samus"
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CONFIG_SPL_TEXT_BASE=0xffe70000
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CONFIG_TPL_TEXT_BASE=0xfffd8000
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CONFIG_DEBUG_UART_BOARD_INIT=y
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CONFIG_DEBUG_UART_BASE=0x3f8
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CONFIG_DEBUG_UART_CLOCK=1843200
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@ -70,7 +70,6 @@
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#define CONFIG_SPL_NAND_INIT
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#define CONFIG_SPL_COMMON_INIT_DDR
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#define CONFIG_SPL_MAX_SIZE (128 << 10)
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#define CONFIG_TPL_TEXT_BASE 0xD0001000
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#define CONFIG_SYS_MPC85XX_NO_RESETVEC
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#define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10)
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#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
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@ -102,7 +101,7 @@
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#endif
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#ifdef CONFIG_TPL_BUILD
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#define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE
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#define CONFIG_SYS_MONITOR_BASE 0xD0001000
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#elif defined(CONFIG_SPL_BUILD)
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
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#else
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@ -18,8 +18,6 @@
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"stdout=vidconsole,serial\0" \
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"stderr=vidconsole,serial\0"
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#define CONFIG_TPL_TEXT_BASE 0xffff8000
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#define CONFIG_SYS_NS16550_MEM32
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#undef CONFIG_SYS_NS16550_PORT_MAPPED
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@ -23,6 +23,4 @@
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"stdout=vidconsole,serial\0" \
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"stderr=vidconsole,serial\0"
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#define CONFIG_TPL_TEXT_BASE 0xfffd8000
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#endif /* __CONFIG_H */
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@ -102,7 +102,6 @@
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#define CONFIG_SPL_NAND_INIT
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#define CONFIG_SPL_COMMON_INIT_DDR
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#define CONFIG_SPL_MAX_SIZE (128 << 10)
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#define CONFIG_TPL_TEXT_BASE 0xf8f81000
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#define CONFIG_SYS_MPC85XX_NO_RESETVEC
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#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
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#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
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@ -130,7 +129,7 @@
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#ifndef CONFIG_SYS_MONITOR_BASE
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#ifdef CONFIG_TPL_BUILD
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#define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE
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#define CONFIG_SYS_MONITOR_BASE 0xf8f81000
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#elif defined(CONFIG_SPL_BUILD)
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
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#else
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