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SoC: qcom: add support for SDM845
Hi-end qualcomm chip, introduced in late 2017. Mostly used in flagship phones and tablets of 2018. Features: - arm64 arch - total of 8 Kryo 385 Gold / Silver cores - Hexagon 685 DSP - Adreno 630 GPU Tested only as second-stage bootloader. Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com> Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Tom Rini <trini@konsulko.com> Cc: Stephan Gerhold <stephan@gerhold.net>
This commit is contained in:
Dzmitry Sankouski
Tom Rini
parent
90496afc27
commit
4cbc16ceb2
7 changed files with 312 additions and 0 deletions
116
arch/arm/dts/sdm845.dtsi
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116
arch/arm/dts/sdm845.dtsi
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@ -0,0 +1,116 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Qualcomm SDM845 chip device tree source
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*
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* (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
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*
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*/
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/dts-v1/;
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#include "skeleton64.dtsi"
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/ {
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soc: soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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gcc: clock-controller@100000 {
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u-boot,dm-pre-reloc;
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compatible = "qcom,gcc-sdm845";
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reg = <0x100000 0x1f0000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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gpio_north: gpio_north@3900000 {
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u-boot,dm-pre-reloc;
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#gpio-cells = <2>;
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compatible = "qcom,sdm845-pinctrl";
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reg = <0x3900000 0x400000>;
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gpio-count = <150>;
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gpio-controller;
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gpio-ranges = <&gpio_north 0 0 150>;
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gpio-bank-name = "soc_north.";
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};
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tlmm_north: pinctrl_north@3900000 {
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u-boot,dm-pre-reloc;
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compatible = "qcom,tlmm-sdm845";
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reg = <0x3900000 0x400000>;
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gpio-count = <150>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&tlmm_north 0 0 150>;
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/* DEBUG UART */
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qup_uart9: qup-uart9-default {
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pinmux {
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pins = "GPIO_4", "GPIO_5";
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function = "qup9";
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};
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};
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};
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debug_uart: serial@a84000 {
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compatible = "qcom,msm-geni-uart";
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reg = <0xa84000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk";
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clocks = <&gcc 0x58>;
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pinctrl-names = "default";
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pinctrl-0 = <&qup_uart9>;
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qcom,wrapper-core = <0x8a>;
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status = "disabled";
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};
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spmi@c440000 {
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compatible = "qcom,spmi-pmic-arb";
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reg = <0xc440000 0x1100>,
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<0xc600000 0x2000000>,
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<0xe600000 0x100000>;
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reg-names = "cnfg", "core", "obsrvr";
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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qcom,revid@100 {
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compatible = "qcom,qpnp-revid";
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reg = <0x100 0x100>;
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};
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pmic0: pm8998@0 {
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compatible = "qcom,spmi-pmic";
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reg = <0x0 0x1>;
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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pm8998_pon: pm8998_pon@800 {
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compatible = "qcom,pm8998-pwrkey";
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reg = <0x800 0x100>;
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#gpio-cells = <2>;
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gpio-controller;
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gpio-bank-name = "pm8998_key.";
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};
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pm8998_gpios: pm8998_gpios@c000 {
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compatible = "qcom,pm8998-gpio";
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reg = <0xc000 0x1a00>;
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gpio-controller;
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gpio-count = <21>;
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#gpio-cells = <2>;
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gpio-bank-name = "pm8998.";
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};
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};
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pmic1: pm8998@1 {
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compatible = "qcom,spmi-pmic";
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reg = <0x1 0x0>;
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#address-cells = <0x2>;
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#size-cells = <0x0>;
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};
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};
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};
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};
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@ -9,6 +9,10 @@ config SYS_MALLOC_F_LEN
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config SPL_SYS_MALLOC_F_LEN
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default 0x2000
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config SDM845
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bool "Qualcomm Snapdragon 845 SoC"
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default n
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choice
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prompt "Snapdragon board select"
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@ -2,6 +2,9 @@
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#
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# (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
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obj-$(CONFIG_SDM845) += clock-sdm845.o
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obj-$(CONFIG_SDM845) += sysmap-sdm845.o
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obj-$(CONFIG_SDM845) += init_sdm845.o
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obj-$(CONFIG_TARGET_DRAGONBOARD820C) += clock-apq8096.o
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obj-$(CONFIG_TARGET_DRAGONBOARD820C) += sysmap-apq8096.o
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obj-$(CONFIG_TARGET_DRAGONBOARD410C) += clock-apq8016.o
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@ -12,3 +15,4 @@ obj-y += dram.o
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obj-y += pinctrl-snapdragon.o
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obj-y += pinctrl-apq8016.o
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obj-y += pinctrl-apq8096.o
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obj-$(CONFIG_SDM845) += pinctrl-sdm845.o
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42
arch/arm/mach-snapdragon/include/mach/sysmap-sdm845.h
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42
arch/arm/mach-snapdragon/include/mach/sysmap-sdm845.h
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@ -0,0 +1,42 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Qualcomm SDM845 sysmap
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*
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* (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
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*/
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#ifndef _MACH_SYSMAP_SDM845_H
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#define _MACH_SYSMAP_SDM845_H
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#define TLMM_BASE_ADDR (0x1010000)
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/* Strength (sdc1) */
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#define SDC1_HDRV_PULL_CTL_REG (TLMM_BASE_ADDR + 0x0012D000)
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/* Clocks: (from CLK_CTL_BASE) */
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#define GPLL0_STATUS (0x0000)
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#define APCS_GPLL_ENA_VOTE (0x52000)
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#define APCS_CLOCK_BRANCH_ENA_VOTE (0x52004)
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#define SDCC2_BCR (0x14000) /* block reset */
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#define SDCC2_APPS_CBCR (0x14004) /* branch control */
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#define SDCC2_AHB_CBCR (0x14008)
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#define SDCC2_CMD_RCGR (0x1400c)
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#define SDCC2_CFG_RCGR (0x14010)
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#define SDCC2_M (0x14014)
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#define SDCC2_N (0x14018)
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#define SDCC2_D (0x1401C)
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#define RCG2_CFG_REG 0x4
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#define M_REG 0x8
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#define N_REG 0xc
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#define D_REG 0x10
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#define SE9_AHB_CBCR (0x25004)
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#define SE9_UART_APPS_CBCR (0x29004)
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#define SE9_UART_APPS_CMD_RCGR (0x18148)
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#define SE9_UART_APPS_CFG_RCGR (0x1814C)
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#define SE9_UART_APPS_M (0x18150)
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#define SE9_UART_APPS_N (0x18154)
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#define SE9_UART_APPS_D (0x18158)
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#endif
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82
arch/arm/mach-snapdragon/init_sdm845.c
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82
arch/arm/mach-snapdragon/init_sdm845.c
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@ -0,0 +1,82 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Common init part for boards based on SDM845
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*
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* (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
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*/
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#include <init.h>
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#include <env.h>
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#include <common.h>
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#include <asm/system.h>
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#include <asm/gpio.h>
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#include <dm.h>
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DECLARE_GLOBAL_DATA_PTR;
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int dram_init(void)
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{
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return fdtdec_setup_mem_size_base();
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}
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void reset_cpu(void)
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{
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psci_system_reset();
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}
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__weak int board_init(void)
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{
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return 0;
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}
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/* Check for vol- and power buttons */
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__weak int misc_init_r(void)
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{
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struct udevice *pon;
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struct gpio_desc resin;
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int node, ret;
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ret = uclass_get_device_by_name(UCLASS_GPIO, "pm8998_pon@800", &pon);
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if (ret < 0) {
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printf("Failed to find PMIC pon node. Check device tree\n");
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return 0;
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}
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node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(pon),
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"key_vol_down");
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if (node < 0) {
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printf("Failed to find key_vol_down node. Check device tree\n");
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return 0;
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}
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if (gpio_request_by_name_nodev(offset_to_ofnode(node), "gpios", 0,
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&resin, 0)) {
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printf("Failed to request key_vol_down button.\n");
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return 0;
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}
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if (dm_gpio_get_value(&resin)) {
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env_set("key_vol_down", "1");
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printf("Volume down button pressed\n");
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} else {
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env_set("key_vol_down", "0");
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}
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node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(pon),
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"key_power");
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if (node < 0) {
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printf("Failed to find key_power node. Check device tree\n");
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return 0;
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}
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if (gpio_request_by_name_nodev(offset_to_ofnode(node), "gpios", 0,
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&resin, 0)) {
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printf("Failed to request key_power button.\n");
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return 0;
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}
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if (dm_gpio_get_value(&resin)) {
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env_set("key_power", "1");
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printf("Power button pressed\n");
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} else {
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env_set("key_power", "0");
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}
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return 0;
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}
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31
arch/arm/mach-snapdragon/sysmap-sdm845.c
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31
arch/arm/mach-snapdragon/sysmap-sdm845.c
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@ -0,0 +1,31 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Qualcomm SDM845 memory map
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*
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* (C) Copyright 2021 Dzmitry Sankouski <dsankousk@gmail.com>
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*/
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#include <common.h>
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#include <asm/armv8/mmu.h>
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static struct mm_region sdm845_mem_map[] = {
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{
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.virt = 0x0UL, /* Peripheral block */
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.phys = 0x0UL, /* Peripheral block */
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.size = 0x10000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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.virt = 0x80000000UL, /* DDR */
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.phys = 0x80000000UL, /* DDR */
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.size = 0x200000000UL, /* 8GiB - maximum allowed memory */
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = sdm845_mem_map;
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33
include/configs/sdm845.h
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33
include/configs/sdm845.h
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Configuration file for boards, based on Qualcomm SDM845 chip
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*
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* (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
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*/
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#ifndef __CONFIGS_SDM845_H
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#define __CONFIGS_SDM845_H
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#include <linux/sizes.h>
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#include <asm/arch/sysmap-sdm845.h>
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#define CONFIG_SYS_LOAD_ADDR 0x80000000
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#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 }
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/* Generic Timer Definitions */
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#define COUNTER_FREQUENCY 19000000
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#define EXTRA_ENV_SETTINGS \
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"loadaddr=0x80000000\0"
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_8M)
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#define CONFIG_SYS_BOOTM_LEN SZ_64M
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/* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 512
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#define CONFIG_SYS_MAXARGS 64
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#endif
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