Move CONFIG_SYS_TEXT_BASE to Kconfig, and add default values in board
Kconfig files matching what was present in their config headers. This
will make it cleaner to conditionalise the value for Malta based on 32
vs 64 bit builds.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
The address of the UART differs based upon the system controller because
it's actually within the I/O port region, which is in a different
location for each system controller. Rather than handling this as 2
UARTs with the correct one selected at runtime, use I/O port accessors
for the UART such that access to it gets translated into the I/O port
region automatically.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Recently a set of CONFIG_CMD_FOO defines was moved from being defined
in config_distro_defaults to Kconfig, and added to all sunxi defconfigs
to compensate.
Instead of explictly selecting these in all sunxi defconfigs,
simply always select these for sunxi boards. This makes the defconfigs
simpler and ensures a consistent set of available commands across all
sunxi boards.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The ARM Trusted Firmware (ATF) code now lives in SRAM on the Pine64/A64,
so we can claim the whole of DRAM for OS use.
This reverts commit 3ffe39ed2b.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The A80 uses the AXP809 as its primary PMIC.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The AXP818 has a switchable output, SW. This is commonly used for
controlling power to the LCD backlight.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The newer chips use a newer display pipeline, which is not supported.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
A83T, H3, and A64 have a dedicated pin for card detect on the PF
pingroup. This is used in all designs. Set it as the default.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
In most other places, we sort SoC descriptions by family (sunXi) first,
then by the chip name (A20).
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The user should always select an SoC variant to support. Not choosing
one doesn't make sense for a bootloader.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Now that we are using driver model, we can drop the weak functions and LCD
init in the board file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Update several boards to use driver model for video. This involves changes
to the EDP and FIMD (frame buffer) drivers. Existing PWM, simple-panel and
pwm-backlight drivers are used. These work without additional configuration
since they use the device tree settings in the same way as Linux.
Boards converted are:
- snow
- spring
- peach-pit
- peach-pi
All have been tested. Not converted:
- MIPI display driver
- s5pc210_universal
- smdk5420
- smdk5250
- trats
- trats2
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This function controls enabling the EDP PHY. Rename it and drop the existing
weak functions, which are confusing.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Some boards have the LCD enabled but I cannot test operation for the driver
model conversion. Disable the LCD on these to avoid build errors.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This file currently requires LCD support. Adjust it so that it can still be
built without LCD support (even thought it won't work fully).
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Espresso7420 is a development/evaluation board for Exynos7420 SoC. It
includes multiple onboard compoments (EMMC/Codec) and various
interconnects (USB/HDMI).
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Disable the non-existent ethernet ports on T4240RDB:FM1_DTSEC5,
FM1_DTSEC6, FM2_DTSEC5 and FM2_DTSEC6.
Signed-off-by: Ying Zhang <ying.zhang22455@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <york.sun@nxp.com>
NAND+MMC env support costs 12KB in the SPL which is fairly expensive just
for the ability to specify whether or not to boot to uboot or directly
to linux. The Ventana boards have plenty of EEPROM storage so we will use
a byte there to signify if we should boot to the bootloader or to the OS.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Extending Kconfig for adding new platform is a lot of work
for nothing. Setting SYS_CONFIG_NAME directly in Kconfig and
remove all dependencies on TARGET_ZYNQ_* options including SPL.
As a side-effect it also remove custom init folder for ps7_init_gpl.*
files. Folder is chosen based on device-tree file.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Support RAM and MMC boot mode in SPL also with SPL_FIT images.
In MMC boot mode two boot options are available:
1) Boot flow with ATF(EL3) and full U-Boot(EL2):
aarch64-linux-gnu-objcopy -O binary bl31.elf bl31.bin
mkimage -A arm64 -O linux -T kernel -C none -a 0xfffe5000 -e 0xfffe5000
-d bl31.bin atf.ub
cp spl/boot.bin <sdcard fat partition>
cp atf.ub <sdcard fat partition>
cp u-boot.bin <sdcard fat partition>
2) Boot flow with full U-Boot(EL3):
cp spl/boot.bin <sdcard>
cp u-boot*.img <sdcard>
3) emmc boot mode
dd if=/dev/zero of=sd.img bs=1024 count=1024
parted sd.img mktable msdos
parted sd.img mkpart p fat32 0% 100%
kpartx -a sd.img
mkfs.vfat /dev/mapper/loop0p1
mount /dev/mapper/loop0p1 /mnt/
cp spl/boot.bin /mnt
cp u-boot.img /mnt
cp u-boot.bin /mnt
cp atf.ub /mnt
umount /dev/mapper/loop0p1
kpartx -d sd.img
cp sd.img /tftpboot/
and program it via u-boot
tftpb 10000 sd.img
mmcinfo
mmc write 10000 0 $filesize
mmc rescan
mmc part
ls mmc 0
psu_init() function contains low level SoC setup generated for every HW
design by Xilinx design tools. xil_io.h is only supporting file to fix
all dependencies from tools. The same solution was used on Xilinx Zynq.
The patch also change CONFIG_SYS_INIT_SP_ADDR to the end of OCM which
stays at the same location all the time.
Bootrom expects starting address to be at 0xfffc0000 that's why this
address is SPL_TEXT_BASE.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add support for on board eeprom with programmed MAC for using in u-boot
to have uniq address for every board.
Most of the time uniq MAC address is on a label on the board.
If address is not programmed use these command to program it.
On zcu102:
ZynqMP> mm.b 0
00000000: 00 ? 00
00000001: a0 ? 0a
00000002: 35 ? 35
00000003: 02 ? 02
00000004: 00 ? ef
00000005: 00 ? 67
00000006: 00 ? q
i2c dev 5
i2c write 0 54 20 6
i2c md 54 20
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Change the clock source of the SDHCI's generated clock from PLLA to
UPLL clock to align to Linux driver.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
Fix the missing pin config of the SDMMC0 interface.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
The board supports following features:
- Boot media support: NAND Flash/SPI Flash
- Support ethernet
- Support USB mass storage
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
Override the default product name U-Boot reports in the SMBIOS
table, to be compatible with the Intel provided UEFI BIOS, as
Linux kernel drivers (drivers/mfd/intel_quark_i2c_gpio.c and
drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c) make use of
it to do different board level configuration.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Let git ignore dsdt.aml, dsdt.asl.tmp and dsdt.c files.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Enable ACPI table generation by creating a DSDT table for all baytrail
boards: conga-qeval20-qa3-e3845, bayleybay and minnowmax.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
We always build for a mips32 or higher ISA, so this ".set mips32"
directive is redundant. Once MIPSr6 support is added it will become
harmful since some instruction encodings change & this directive will
cause the older encodings to be incorrectly emitted instead of the
appropriate ones for the build.
In preparation for supporting MIPSr6, remove this redundant directive.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Add support for the TPLink WDR4300 router, which is based on the
AR9344 MIPS 74Kc CPU and has 128 MiB of RAM. The USB is supported
on this system as well.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Wills Wang <wills.wang@live.com>
This patch add board-level code and base DT for AP143.
Signed-off-by: Wills Wang <wills.wang@live.com>
[updated defconfig, enabled CONFIG_USE_PRIVATE_LIBGCC=y]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
This patch add board-level code and base DT for AP121.
Signed-off-by: Wills Wang <wills.wang@live.com>
[updated defconfig, enabled CONFIG_USE_PRIVATE_LIBGCC=y]
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Add layout definitions and implement functions for field printing/updating,
layout detection, layout assignment, and layout parsing.
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Tom Rini <trini@konsulko.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
To use AQR105 PHY's interrupt, we need to invert the IRQ pin polarity
by setting relative bit in SCFG_INTPCR register, because AQR105
interrupt is low active but GIC accepts high active.
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Some SOCs, specifically the ones in the C29x familiy can have
multiple security engines. This patch adds a system configuration
define which indicates the maximum number of SEC engines that
can be found on a SoC.
Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Using u16 for cfg_rcw_src and u8 for sd1refclk_sel is enough.
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
gd->env_addr will be initialized in env_init() in
common/env_nowhere.c if CONFIG_ENV_IS_NOWHERE is defined.
So no need to do it again.
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The current 'cpld reset' will just write global_rst register
but couldn't switch to NOR boot if the board's switches are
for NAND/SD boot. So need to write rcw source registers for
NOR boot as well.
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Mix usage of uint32_t and u32 fixed in favor of u32.
Signed-off-by: Vincent Siles <vincent.siles@provenrun.com>
Reviewed-by: York Sun <york.sun@nxp.com>
On the LS102x boards, in order to initialize the ICID values of
masters, the dev_stream_id array holds absolute offsets from the
base of SCFG.
In ls102xa_config_ssmu_stream_id, the base pointer is cast to
uint32_t * before adding the offset, leading to an invalid address.
Casting it to void * solves the issue.
Signed-off-by: Vincent Siles <vincent.siles@provenrun.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Update MAINTAINERS file for ls2080aqds and ls2080ardb platforms.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Optimize DDR timing for good margins to support new Transcend
and Apacer DDR4 UDIMM besides current Micron UDIMM.
Verified 1333MT/s, 1600MT/s, 1866MT/s, 2133MT/s rate with
following UDIMM on LS2080ARDB.
- Micron UDIMM: MTA18ASF1G72AZ-2G1A1Z
- Apacer UDIMM: 78.C1GM4.AF10B
- Transcend UDIMM: TS1GLH72V1H
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Barrier transactions from CCI400 need to be disabled till
the DDR is configured, otherwise it may lead to system hang.
The patch adds workaround to fix the erratum.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This option currently enables both the command and the SCSI functionality.
Rename the existing option to CONFIG_SCSI since most of the code relates
to the feature.
Signed-off-by: Simon Glass <sjg@chromium.org>
While the driver-model block device support is in progress, it is useful to
build sandbox both with and without CONFIG_BLK. Add a separate board for
the latter.
Signed-off-by: Simon Glass <sjg@chromium.org>
This imports v11 of "Jetson TK1 Development Platform Pin Mux" from
https://developer.nvidia.com/embedded/downloads.
The new version defines the mux option for the MIPI pad ctrl selection.
The OWR pin no longer has an entry in the configuration table because
the only mux option it support is OWR, that feature isn't supported, and
hence can't conflict with any other pin. This pin can only usefully be
used as a GPIO.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
ABB should be initialized for all required domains voltage domain
for DRA7: IVA, GPU, EVE in addition to the existing MPU domain. If
we do not do this, kernel configuring just the frequency using the
default boot loader configured voltage can fail on many corner lot
units and has been hard to debug. This specifically is a concern with
DRA7 generation of SoCs since other than VDD_MPU, all other domains
are only permitted to setup the voltages to required OPP only at boot.
Reported-by: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
ABB TX_DONE mask will vary depending on ABB module. For example,
3630 never had ABB on IVA domain, while OMAP5 does use ABB on MM domain,
DRA7 has it on all domains with the exception of CORE, RTC.
Hence, move the txdone mask definition over to structure describing
voltage domain.
Signed-off-by: Nishanth Menon <nm@ti.com>
This patch updates and simplifies the hikey README. The old
instructions were hard to follow, and convoluted.
This patch also updates the link to the mcuimage.bin which was outdated.
Using an outdated mcuimage.bin results in the additional a53 cores
not coming online when the kernel issues PSCI requests to
arm trusted firmware (ATF).
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
The memory node gets automatically generated by U-Boot
in arch_fixup_fdt(), before passing control to the kernel
using U-Boots representation of the dram banks.
However the upstream kernel uses the memory node to carve-out
regions of RAM for various purposes. To make this work without
changing arch_fixup_fdt() which will effect many platforms
we replicate the upstream memory node layout using the dram
banks.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Currently only the serial pl01x driver is using DT,
and the other drivers still use platform data but
as more DT lands in the upstream kernel the aim is
to migrate the other drivers over to DT as well to
have a fully DT configured hikey u-boot.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
This patch adds myself as maintainer for the hikey
U-Boot port.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Add support for Technexion's PICO-IMX6UL-EMMC board.
For information about this board, please visit:
http://www.technexion.com/products/pico/pico-som/pico-imx6-emmc
Signed-off-by: Richard Hu <richard.hu@technexion.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
On a reset/reboot, the display power needs to be off for atleast 500ms
before turning it back on. So add a delay to the boot process to meet
the display timing requirement.
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Cc: Stefano Babic <sbabic@denx.de>
To generate accurate pixel clocks required by the displays we need to
set the ldb_di_clk source on bx50v3 to PLL3 and b850v3 to PLL5. Since
PLL5 is disabled on reset, we need to enable PLL5.
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Cc: Stefano Babic <sbabic@denx.de>
B450v3/B650v3 uses single channel LVDS and does not support HDMI.
B850v3 uses dual channel LVDS and supports HDMI. Hence split the display
setup into two different functions.
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Cc: Stefano Babic <sbabic@denx.de>
Certain pins are not used on the i.MX6, and should have a neutral
pad configuration in order to reduce electrical interference on
the board. This commit defines these pins with a default value
rather than relying on the system defaults.
Signed-off-by: Justin Waters <justin.waters@timesys.com>
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Cc: Stefano Babic <sbabic@denx.de>
Apparently, all "dave"-related vendor content was removed in commit
5344cc1a82fcc2817d4671696b3939b0dfa4323e; remove remaining directory
board/dave/, which consists solely of board/dave/common/flash.c.
Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
Not all Keystone2 devices has AEMIF NAND controller. So adding Kconfig
entry for CONFIG_TI_AEMIF and enabling it in respective defconfigs on
platforms with AEMIF controller.
Reported-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The AM572x-IDK board (Industrial Dev Kit) is a board based on TI's AM5728x
SOC which has a dual core 1.5GHz A15 processor. This board is a development
platform for the Industrial market with:
- 2GB of DDR3L
- Dual 1Gbps Ethernet
- HDMI,
- PRU-ICSS
- uSD
- 16GB eMMC
- CAN
- RS-485
- PCIe
- USB3.0
- Video Input Port
- Industrial IO port and expansion connector
The link to the data sheet and TRM can be found here:
http://www.ti.com/product/AM5728
NOTE: DT support is still pending upstream kernel acceptance but we
should be able to get the base system support with this patch.
Signed-off-by: Schuyler Patton <spatton@ti.com>
Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Update EMIF data based on recommendations from the now standard TI
EMIF tool version 1.1.1 based on 256MBx16 DDR3L Kingston D2516EC4BXGGB
data sheet
Update T_RRD from 5 to 6 based on AM57xx TRM -
Minimum number of DDR cycles from activate to ativate for a different
bank, minus 1.
Update T_CKESR from 4 to 3 based on AM57xx TRM - Minimum number of DDR
clocks cycles for which SDRAM must remain in self refresh, minus 1.
Signed-off-by: Schuyler Patton <spatton@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
- Move the CONS_INDEX selection out of CONFIG_SYS_EXTRA_OPTIONS and
into Kconfig proper.
- Edit the relevant am57x configs to remove the now unneeded
CONFIG_SYS_EXTRA_OPTIONS.
Signed-off-by: Daniel Allred <d-allred@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Update dm test command with pytest instead of ./test/dm/test-dm.sh
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Jagan Teki <jteki@openedev.com>
Including netdev.h is causing compilation warning:
+ int fecmxc_register_mii_postcall(struct eth_device *dev, int
(*cb)(int));
+ ^
w+In file included from ../board/xilinx/zynqmp/zynqmp.c:9:0:
w+../include/netdev.h:204:41: warning: ‘struct eth_device’ declared
inside parameter list [enabled by default]
w+../include/netdev.h:204:41: warning: its scope is only this definition
or declaration, which is probably not what you want [enabled by default]
This patch removes it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Define u64 types to be usable on 32bit system because of 64bit address
and size cells and 32bit shifts in the code.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This line is not needed, as the board supports DT based probing. And
here the "Model:" is already printed:
Model: Marvell Armada XP theadorable
Board: theadorable
One line for the board name is enough.
Signed-off-by: Stefan Roese <sr@denx.de>
Sometimes the PCIe link for the PEX-switch will not come-up. In this case,
the board is not in a usable state. This patch makes sure that in this
case a soft-reset is issued. If this soft-reset does not result in the
PEX-switch being detected after some soft-reset cycles, an I2C message
is sent to the uC to issue a complete power-cycle of the board.
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds an USB power toggle for theadorable. Additionally, the
USB PHY RX Channel Control 0 Register is changed to fix some issues
noticed while accessing some specific USB sticks.
Signed-off-by: Stefan Roese <sr@denx.de>
The Orange Pi One SBC, is a stripped down version of the popular
Orange Pi PC. The one is a H3 based SBC, with 512M of RAM,
micro-sd slot, 1 host usb, 1 otg usb, hdmi and 100Mbit ethernet.
The dts is identical to the dts submitted to the upstream kernel.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Some boards have on board usb devices which need longer than the USB
spec's 1 second to connect from board powerup. Add a config option which
when non 0 adds an extra delay before the first usb bus scan.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Now that rpi_*defconfig and Kconfig (rather than the config header file)
provide the identity of the build, we don't need to separate config
headers and board directories for each RPi variant. Set CONFIG_SYS_BOARD
and CONFIG_SYS_CONFIG_NAME so that we can get rid of the duplication. This
requires a tiny number of extra ifdefs in the config header.
The only disadvantage of this approach is that the $board/$board_name
environment variables aren't as descriptive as they used to be. This isn't
really an issue because those only exist to allow scripts to create DTB
filenames at runtime. However, the RPi board code already sets $fdtfile to
something more accurate based on FW-reported board ID anyway.
While at it, unify some Kconfig select options, and add a MAINTAINERS
entry for bcm283x too.
Partially-suggested-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
init_sata() is done as part of scsi_init() in
arch/arm/cpu/armv7/omap-common/sata.c so no need to duplicate
it here.
This seems to fix SATA problems in the kernel when CONFIG_TI_PIPE3 is
configured as loadable module.
Cc: Cooper Jr., Franklin <fcooper@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
On all Pis so far, the VC FW provides a short stub to set up the ARM CPU
before entering the kernel (a/k/a U-Boot for us). This feature is not
currently supported by the VC FW when booting in 64-bit mode. However,
this feature will likely appear in the near future, and this U-Boot port
assumes that such a feature is in place. Without that feature, or a
temporary workaround described below, U-Boot will not boot.
Once the VC FW does provide the ARM stub, u-boot.bin built for rpi_3 can
be used drectly as kernel7.img, in the same way as any other RPi port. The
following config.txt is required:
# Fix mini UART input frequency, and setup/enable up the UART.
# Without this option, U-Boot will not boot, even if you don't care
# about the serial console. This option will always be required for
# all RPi3 use-cases, unless the PL011 UART is used, which is not
# yet supported by rpi_3* builds of U-Boot.
enable_uart=1
# Boot in AArch64 (64-bit) mode.
# It is possible that a future VC FW will remove the need for this
# option, instead auto-setting 32-/64-bit mode based on the "kernel"
# filename present on the SD card.
arm_control=0x200
Prior to the VC FW providing the ARM boot stub, you can use the following
steps to build an equivalent stub into the U-Boot binary:
git clone https://github.com/swarren/rpi-3-aarch64-demo.git \
../rpi-3-aarch64-demo
(cd ../rpi-3-aarch64-demo && ./build.sh)
Build U-Boot for rpi_3 in the usual way
cat ../rpi-3-aarch64-demo/armstub64.bin u-boot.bin > u-boot.bin.stubbed
Use u-boot.bin.stubbed as kernel7.img on the Pi SD card.
In this case, the following additional entries are required in config.txt:
# Tell the FW to load the kernel image at address 0, the reset vector.
kernel_old=1
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
The currently present DRAM timings generated from GHRD 14.0 did
not work on SoCkit rev. D because they were too tight. Load the
DRAM timings from GHRD 13.0 which are more relaxed and work with
SoCkit rev. D.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Chin Liang See <clsee@altera.com>
LS2080A is the primary SoC, and LS2085A is a personality with AIOP
and DPAA DDR. The RDB and QDS boards support both personality. By
detecting the SVR at runtime, a single image per board can support
both SoCs. It gives users flexibility to swtich SoC without the need
to reprogram the board.
Signed-off-by: York Sun <york.sun@nxp.com>
CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
When setting fixed-link property to DTS, the values should be converted
with using cpu_to_fdt32 so that to have correct value on little endian
Soc.
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Read information about memory from DT. This patch simplify life with
synchronization between DT and board files.
dram_init() only needs maximum RAM size below 4GB that's why please sort
banks in memory node.
dram_init_banksize() copies memory setup to bi_dram[].
This will avoid reading information from DT twice.
Memory test start/end were changed to DDR location to let memtest still
compiled.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
There is incorrect setting for USB which didn't work with origin
ps7_init_gpl.X files.
Use default setting for Digilent Zybo projects with HDMI in PL.
Signed-off-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Provide board specific option how to read MAC address from ROM.
Do it in generic way to be reusable by differnet boards.
If this is not enough board specific functions can be created.
Signed-off-by: Joe Hershberger <joe.hershberger@gmail.com> # driver part
Signed-off-by: Michal Simek <monstr@monstr.eu>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch adds basic support for the Marvell A375 eval board. Tested
are the following interfaces:
- I2C
- SPI
- SPI NOR
- Ethernet (mvpp2), port 0 & 1
Currently the A375 SerDes and DDR3 init code is not intergrated. So
the SPL U-Boot is not fully functional.
Right now, this A375 mainline U-Boot can only be used by chainloading
it via the original Marvell U-Boot. This can be done via this
command:
=> tftpboot 00800000 a375/u-boot-dtb.bin;go 00800000
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Having had a similar board and memory part under logic analyzer, a
tINIT3 violation was measured. The fix was involved keeping tXPR and
SDE_to_RST at the power-on defaults and setting RST_to_CKE the JEDEC
value for LPDDR2. There was also a tIH-CA violation and this was
resolved by writing the default value in rather than what the script
here uses.
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Having had a similar board and memory part under logic analyzer, a
tINIT3 violation was measured. The fix was involved keeping tXPR and
SDE_to_RST at the power-on defaults and setting RST_to_CKE the JEDEC
value for LPDDR2.
Cc: Jason Liu <jason.hui.liu@nxp.com>
Cc: Ye Li <ye.li@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
enable_lvds() function only set bits IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT and
IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT, but these bits were already set
previously inside setup_display().
We can safely remove enable_lvds() then.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
This commit add support for 96Boards Dragonboard410C.
It is board based on APQ8016 Qualcomm SoC, complying with
96boards specification.
Features (present out of the box):
- 4x Cortex A53 (ARMv8)
- 2x USB Host port
- 1x USB Device port
- 4x LEDs
- 1x HDMI connector
- 1x uSD connector
- 3x buttons (Power, Vol+, Vol-/Reset)
- WIFI, Bluetooth with integrated antenna
- 8GiB eMMC
U-Boot boots chained with fastboot in 64-bit mode.
For detailed build instructions see readme.txt in board directory.
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Tested-by: Simon Glass <sjg@chromium.org>
Most of ehci-fsl header describe USB controller
designed by Chipidea and used by various SoC vendors.
This patch renames it to a generic header: ehci-ci.h
Contents of file are not changed (so it contains several
references to freescale SoCs).
Signed-off-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Acked-by: Marek Vasut <marex@denx.de>
Tested-by: Simon Glass <sjg@chromium.org>
Enable the TI DP83867 Giga bit phy on the
dra7 rev c board. The rx and tx internal
delays are need for this board so the usage
of RGMII_ID is required.
Signed-off-by: Dan Murphy <dmurphy@ti.com>
Acked-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This moves the sniper board from the lge to lg, in order to match the devicetree
vendor prefix already defined in the kernel.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
With the previous implementation, rebooting without registering a recognized
reboot mode would end up with U-Boot checking for a valid power-on reason, which
might result in the device turning off (e.g. with no USB cable attached and no
buttons pressed).
Since this approach is not viable (breaks reboot in most cases), the validity of
the reboot reason is checked (in turn, by checking that a warm reset happened,
as there is no magic) to detect a reboot and the 'o' char is recognized to
indicate that power-off is required. Still, that might be overridden by the
detection of usual power-on reasons, on purpose.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
With the previous implementation, rebooting without registering a recognized
reboot mode (despite registering the magic) would end up with U-Boot checking
for a valid power-on reason, which might result in the device turning off (e.g.
with no USB cable attached and no buttons pressed).
This was designed to catch reboots that are actually intended to be power-off,
something that old Android kernels do, instead of properly turning the device
off using the TWL4030.
However, since this approach is not viable (breaks reboot in most cases), the
validity of the reboot mode magic is checked to detect a reboot and the 'o' char
is recognized to indicate that power-off is required. Still, that might be
overridden by the detection of usual power-on reasons, on purpose.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
The Raspberry Pi 3 contains a BCM2837 SoC. The BCM2837 is a BCM2836 with
the CPU complex swapped out for a quad-core ARMv8. This can operate in 32-
or 64-bit mode. 32-bit mode is the current default selected by the
VideoCore firmware on the Raspberry Pi 3. This patch adds a 32-bit port of
U-Boot for the Raspberry Pi 3.
>From U-Boot's perspective, the only delta between the RPi 2 and RPi 3 is a
change in usage of the SoC UARTs. On all previous Pis, the PL011 was the
only UART in use. The Raspberry Pi 3 adds a Bluetooth module which uses a
UART to connect to the SoC. By default, the PL011 is used for this purpose
since it has larger FIFOs than the other "mini" UART. However, this can
be configured via the VideoCore firmware's config.txt file. This patch
hard-codes use of the mini UART in the RPi 3 port. If your system uses the
PL011 UART for the console even on the RPi 3, please use the RPi 2 U-Boot
port instead. A future change might determine which UART to use at
run-time, thus allowing the RPi 2 and RPi 3 (32-bit) ports to be squashed
together.
The mini UART has some limitations. One externally visible issue in the
BCM2837 integration is that the UART divides the SoC's "core clock" to
generate the baud rate. The core clock is typically variable, and under
control of the VideoCore firmware for thermal management reasons. If the
VC FW does modify the core clock rate, UART communication will be
corrupted since the baud rate will vary from the expected value. This was
not an issue for the PL011 UART, since it is fed by a fixed 3MHz clock. To
work around this, the VideoCore firmware can be told not to modify the SoC
core clock. However, the only way this can happen and be thermally safe is
to limit the core clock to a low/minimum frequency. This leaves
performance on the table for use-cases that don't care about a UART
console. Consequently, use of the mini UART console must be explicitly
requested by entering the following line into config.txt:
enable_uart=1
A recent version of the VC firmware is required to ensure that the mini
UART is fully and correctly initialized by the VC FW; at least
firmware.git 046effa13ebc "firmware: arm_loader: emmc clock depends on
core clock See: https://github.com/raspberrypi/firmware/issues/572".
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
This allows U-Boot to known the name of the board.
The existing rpi_2_defconfig can operate correctly on the Raspberry Pi 3
in 32-bit mode /if/ you have configured the firmware to use the PL011 UART
as the console UART (the default is the mini UART). This requires two
things:
a) config.txt should contain dtoverlay=pi3-miniuart-bt
b) You should run the following to tell the VC FW to process DT when
booting, and copy u-boot.bin.img (rather than u-boot.bin) to the SD card
as the kernel image:
path/to/kernel/scripts/mkknlimg --dtok u-boot.bin u-boot.bin.img
This works as of firmware.git commit 046effa13ebc "firmware: arm_loader:
emmc clock depends on core clock See:
https://github.com/raspberrypi/firmware/issues/572".
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
To simplify support for new SoCs, just use a constant filename
for the unknown case. In practice this case shouldn't be hit anyway, so
the filename isn't relevant, and certainly doesn't need to differentiate
between SoCs. If a user has an as-yet-unknown board, they can override
this value in the environment anyway.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
On the A64 we usually boot with ATF running in EL3. ATF as it is available
today resides in the first 16MB of RAM. So we should make sure we reserve
that space in our memory maps.
Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The Pine64+ is a system based on the Allwinner A64 SoC. It is capable of
running AArch64 code and thus is the first of its kind for the sunxi target.
This patch adds a defconfig and device tree chunks for it.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
[agraf: Change patch description]
Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The Allwinner A64 SoC is used in the Pine64. This patch adds
all bits necessary to compile U-Boot for it running in AArch64
mode.
Unfortunately SPL is not ready yet due to legal problems, so
we need to boot using the binary boot0 for now.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
[agraf: remove SPL code, move to AArch64]
Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The FLDOs on AXP818 PMIC normally provide power to CPUS and USB HSIC PHY
on the A83T/H8.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This patch enable VID support for ls2080ardb platform.
It uses the common VID driver.
Signed-off-by: Rai Harninder <harninder.rai@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Use a pointer to pass image address to fsl_secboot_validate(),
instead of using environmental variable "img_addr".
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
In case of fatal failure during secure boot execution (e.g. header
not found), reset is asserted to stop execution. If the RESET_REQ
is not tied to HRESET, this allows the execution to continue.
Add esbh_halt() after the reset to make sure execution stops.
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Sec_init has been called at the beginning to initialize SEC Block
(CAAM) which is used by secure boot validation later for both ls2080a
qds and rdb. 64-bit address in ESBC Header has been enabled. Secure
boot defconfigs are created for boards (NOR boot).
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
For secure boot, a header is used to identify key table, signature
and image address. A new header structure is added for lsch3.
Currently key extension (IE) feature is not supported. Single key
feature is not supported. Keys must be in table format. Hence, SRK
(key table) must be present. Max key number has increase from 4 to
8. The 8th key is irrevocable. A new barker Code is used.
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The MAC addresses for the PRU Ethernet ports will be available in the
board EEPROM as an address range. Populate those MAC addresses (if valid)
into the u-boot environment so that they can be passed on to the
device tree during fdt_fixup_ethernet().
Signed-off-by: Roger Quadros <rogerq@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Currently, CONFIG_BCM2835 is defined for all BCM283x builds and _BCM2836
is defined when building for that SoC. That means there isn't a single
define that means "exactly BCM2835". This will complicate future patches
where BCM2835-vs-anything-else needs to be determined simply.
Modify the code to define one or the other of CONFIG_BCM2835/BCM2836 so
future patches are simpler.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Add the pinmux data for rev C evm. This is different from previous
revisions of the platform thanks to the deltas introduced both from
silicon side and from SoC side.
Based on J6EcoES2_EVM_Base_Config-20160309b and PCT-DRA72x-v1.3.0.7 for
SR2.0 silicon.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
DDR configuration has changes from SR1.1 based Rev-A/B version of evm
to the SR2.0 based Rev C of the EVM. Rev C evm now uses the higher
density MT41K512M8RH-125-AAT:E (IT) which is of size 2GB.
Update the DDR configuration based on data from EMIF configuration
tool 1.1.1. NOTE: we use eeprom information (ram_size) to update the
configuration.
Tested-by: Vishal Mahaveer <vishalm@ti.com>
Signed-off-by: Ravi Babu <ravibabu@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This patch add support for the CCV xPress board which is equipped
with the i.MX6UL. And provides the following interfaces:
- 128MiB DDR
- UART
- I2C
- eMMC (with booting)
- Ethernet
- USB
This patch adds two build targets. One with and one without SPL. The
non-SPL version is used for loading U-Boot via USB (imx_usb_loader).
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
VESA 1024x768 results in much more accurate timings.
Based on the patch from Soeren Moch for the tbs2910 board.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
The fsl-mc node has been moved under /soc, so update
the path references accordingly. Backwards compatibility
is retained for /fsl-mc.
Delete backwards compatibility for the completely obsolete
/fsl,dprc@0.
Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
It has been superseded in kwbimage.cfg in favor of an SPL in commit
9e30b31d20 (arm: mvebu: db-88f6820: Add
SPL support with DDR init code). Found via code review.
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch adds support for Altera StratixV bitstream programming. 2 FPGAs
are connected to the SPI busses. This patch uses board specific write
code to program the bitstream via SPI direct write mode.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Signed-off-by: Stefan Roese <sr@denx.de>
Always select OF_BOARD_SETUP on sunxi, rather then having it in almost
all our defconfigs. This also fixes it missing from some recently
added defconfigs.
This commit also modifies our ft_board_setup() to not cause warnings
when CONFIG_VIDEO_DT_SIMPLEFB is not set, since we will now always
build it.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
There are 2 reasons for doing this:
1) The main reason for doing this is to move it outside of
board/sunxi/ahci.c, so that it can be used on boards which use
a usb<->sata chip too;
2) While doing this I realized that doing it from board_init also meant
doing it much earlier. Some printf get_timer(0) calls show that the
time between board_init() and scsi_init() is more then 600 ms,
so we can drop the mdelay(500)
While at it also drop the printf("SUNXI SCSI INIT\n") AHCI init is
noisy enough by itself.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
cpu_eth_init is no longer called for dm enabled eth drivers, this
was causing the sunxi gmac eth controller to no longer work in u-boot.
This commit fixes this by calling the clock, reset and pinmux setup
function from s_init() and enabling the phy power pin (if any) from
board_init().
The enabling of phy power cannot be done from s_init because it uses dm
and dm is not ready yet at this point.
Note that the mdelay is dropped as the phy gets enabled much earlier
now, so it is no longer needed.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Tested-by: Karsten Merker <merker@debian.org>
Tested-by: Michael Haas <haas@computerlinguist.org>
The H3 has USB0 - USB3, add support for having a USB vbus pin for USB3.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The Orange Pi 2 is a SBC based on the Allwinner H3 SoC with a uSD slot,
4 USB ports connected via a USB-2 hub, a 10/100M ethernet port using the
SoC's integrated PHY, Wifi via a RTL8189ETV sdio wifi chip, USB OTG, HDMI,
a TRRS headphone jack for stereo out and composite out, a microphone,
an IR receiver, a CSI connector, 2 LEDs, a 3 pin UART header
and a 40-pin GPIO header.
The added dts file is identical to the one submitted to the upstream
kernel.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The Dserve DSRV9703C is a 9.7" A10 tablet with a 1024x768 ips LCD,
1G RAM, 4GB flash, a Focaltech FT5406EE8 touchscreen and rtl8188ctv wifi.
The dts file is identical to the one submitted to the upstream kernel.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The yones toptech bs1078-v2 is a 10.1" tablet without any clear markings on
the outside, but 'YONESTOPTECH-BS1078' written on the PCB silkscreen.
It features a 16:9 1024:600 LCD, A31s SoC, 1GB RAM, 8G NAND, silead gsl3675
touchscreen and a RTL8723AS wifi chip:
https://linux-sunxi.org/Yones_Toptech_BS1078_V2
Signed-off-by: Peter Korsgaard <peter@korsgaard.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The Sinlinx A31s SDK is a A31s based module/baseboard development kit.
The core module has the SoC, PMIC, DRAM, eMMC and supporting components.
There are also pads for UART0, JTAG and I2S.
The baseboard has 100 Mbps Ethernet, 5x USB 2.0 host ports via a USB 2.0
hub chip, MMC, HDMI, SPDIF, CIR, audio jacks, 2 tablet-like volume
buttons, RS232 style UART and USB OTG (though VBUS is not connected).
Various headers are available for other addon modules, such as SDIO
WiFi, LCD display, camera sensor, UARTs, I2C, SPI and GPIOs.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Add defconfig for the multi board device based on the
Allwinner A20 SoC. It contains the A20 Itead Core module and a
base board for the external interfaces.
The core module comes with 4GB NAND and 1GB DDR RAM.
The base board to which the core board is connected provides
3 USB 2.0 Host ports, 1 USB 2.0 OTG, 1 uSD slot, 10/100 Ethernet
port, HDMI, IR receiver, SPDIF and a 32-pin GPIO header. This
header expands the features of core board by exposing the VGA pins,
audio In/Out pins, SATA, SPI, I2C, UARTS, USB-OTG and power..
Signed-off-by: Marcus Cooper <codekipper@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Cubietruck Plus is a A83T/H8 based development board. The board has
standard DDR3 SDRAM, AXP818 PMIC/codec, SD/MMC, eMMC, USB 2.0 host
via HSIC USB Hub, USB OTG, SATA via USB bridge, gigabit ethernet,
WiFi, headphone out / mic in, and various GPIO headers.
The board also has an EEPROM on i2c0 which holds the MAC address.
DLDO3 and DLDO4 provide power to the EMAC pins and PHY. Pin PA20
is connected to the reset control of the PHY. EMAC is not actually
supported yet.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The Polaroid MID2809PXE4 is a 9" tablet which is clearly marked
Polaroid MID2809PXE4 on the back. It features a 9" 16:9 800x480 LCD,
A23 Soc, 1GB RAM, 8GB NAND, gsl3670 touchscreen and esp8089 wifi.
The dts file is identical to the one submitted to the upstream kernel.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The Difrnce dit4350 tablet is a tiny tablet with a 4.3" 16:9 480x272 LCD,
A13 SoC, 512M RAM, 4G NAND, solomon systech ssd2532qn6 touchscreen at
i2c1 address 0x48, Memsic MXC622X accelerometer at i2c1 address 0x15 and
rtl8188etv wifi.
The dts file is identical to the one submitted to the upstream kernel.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The colorfly e708 q1 is a 7" tablet which is clearly marked as colorfly
e708 q1 on the back. It features a 9:16 800x1280 IPS LCD, A31s SoC,
1GB RAM, 8G NAND, ilitek 2139qt004 touchscreen on i2c-1 addr 0x41,
stk8313 accelerometer on i2c-2 addr 0x22 and a rtl8188etv wifi chip.
The added dts is identical to the dts submitted to the upstream kernel,
note this commit also syncs axp22x.dtsi and sun6i-a31.dtsi with the
upstream kernel as the added dts depends on these.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
For Raspberry Pi, we had the input clock rate to the pl011 fixed in
the rpi.c file, but it may be changed by firmware due to user changes
to config.txt. Since the firmware always sets up the uart (default
115200 output unless the user changes it), we can just skip our own
uart init to simplify the boot process and more reliably get serial
output.
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Tom Rini <trini@konsulko.com>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
After power cycle of a K2G EVM dhcp fails due to a auto-negotiation
timeout. This commit increases the timeout to fix the issue.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Return i2c mux to the default channel after accessing retimer.
Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
IR chip is on one of the channels on multiplexed I2C-bus.
Reset to default channel after accessing.
Signed-off-by: Wenbin Song <wenbin.song@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
As phy_connect and phy_config are being called from DPAA2 driver.
Remove calling of mentioned function from board file.
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
To use AQR405 PHY's interrupt, we need to invert the relative IRQ pins
polarity by setting IRQCR register, because AQR405 interrupt is low
active but GIC accepts high active.
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This patch adds support for the congatec conga-QA3/E3845-4G eMMC8 SoM,
installed on the congatec Qseven 2.0 evaluation carrier board
(conga-QEVAL).
Its port is very similar to the MinnowboardMAX port and also uses
the Intel FSP as described in doc/README.x86.
Currently supported are the following interfaces / devices:
- UART (via Winbond legacy SuperIO chip on carrier board)
- Ethernet (PCIe Intel I210 / E1000)
- SPI including SPI NOR as boot-device
- USB 2.0
- SATA via U-Boot SCSI IF
- eMMC
- Video (HDMI output @ 800x600)
- PCIe
Not supported yet is:
- I2C
- USB 3.0
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This adds basic support for chromebook_samus. This is the 2015 Pixel and
is based on an Intel broadwell platform.
Supported so far are:
- Serial
- SPI flash
- SDRAM init (with MRC cache)
- SATA
- Video (on the internal LCD panel)
- Keyboard
Various less-visible drivers are provided to make the above work (e.g. PCH,
power control and LPC).
The platform requires various binary blobs which are documented in the
README. The major missing feature is USB3 since the existing U-Boot support
does not work correctly with Intel XHCI controllers.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
We don't need this anymore - we can use device tree and the new pinconfig
driver instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Some of the LPC code is common to several Intel LPC devices. Move it into a
common location.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
When we switch to including all linker lists in SPL it is important to
not include commands as that may lead to link errors due to other things
we have already discarded. In this case as we don't have other common
code nor other Synology borads, move the cmd_syno.c file (which claims
to be ds414 specific anyways!) into the ds414 directory and only build
it for non-SPL builds.
Signed-off-by: Tom Rini <trini@konsulko.com>
When we switch to including all linker lists in SPL it is important
to not include commands as that may lead to link errors due to other
things we have already discarded. In this case change things so that we
only build the right objects for SPL or non-SPL
Cc: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
Signed-off-by: Tom Rini <trini@konsulko.com>
After booting has finished, EFI allows firmware to still interact with the OS
using the "runtime services". These callbacks live in a separate address space,
since they are available long after U-Boot has been overwritten by the OS.
This patch adds enough framework for arbitrary code inside of U-Boot to become
a runtime service with the right section attributes set. For now, we don't make
use of it yet though.
We could maybe in the future map U-boot environment variables to EFI variables
here.
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
The hikey runs with dcache disabled today. There really should be no reason
not to use caches on AArch64, so let's add MMU definitions and enable the
dcache.
Signed-off-by: Alexander Graf <agraf@suse.de>
There's no good excuse for running with caches disabled on AArch64,
so let's just move the vexpress64 target to enable the MMU and run
with caches on.
Signed-off-by: Alexander Graf <agraf@suse.de>
The MMU range table can vary depending on things we may only find
out at runtime. While the very simple ThunderX variant does not
change, other boards will, so move the definition from a static
entry in a header file to the board file.
Signed-off-by: Alexander Graf <agraf@suse.de>
Reboot mode garbage is found on cold reset and might be seen as valid on the
next warm reset, thus it has to be cleared on cold reset.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Some power on reasons are not desirable (e.g. too short press on the power
button), battery plug. Thus, power off the device when one of those occurs.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
This adds support for the omap4 reboot mode mechanism and exports the reboot
mode via an environment variable, that is used in the boot command to make it
possible to boot from the recovery partition or fastboot.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
This adds support for the MUSB USB dual-role controller in peripheral mode,
with configuration options for the fastboot USB gadget.
At this point, flashing the internal eMMC is support.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
The Amazon Kindle Fire (first generation) codename kc1 is a tablet that was
released by Amazon back in 2011.
It is using an OMAP4430 SoC GP version, which allows running U-Boot and the
U-Boot SPL from the ground up.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
There is no distinction between essential and non-essential mux configuration,
so it doesn't make sense to have an "essential" prefix.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Boards using the TWL6030 regulator may not all use the LDOs the same way.
Some might also not use MMC1 at all, so VMMC would't have to be enabled.
This delegates TWL6030 MMC power initializations to board-specific functions,
that may still call twl6030_power_mmc_init for the default behavior.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reboot mode garbage is found on cold reset and might be seen as valid on the
next warm reset, thus it has to be cleared on cold reset.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
There is no need to set the reboot mode to a particular value prior to reboot,
since valid values will have been caught and cleared earlier.
In addition, this breaks the reboot-bootloader fastboot call, by overriding the
required value for fastboot.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
This switches reboot mode handling to a string-based interface, that allows more
flexibility to set a common interface with the next generations of OMAP devices.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
All the mux configurations needs to be done as part of the IODelay
sequence to avoid glitch. Adding all the mux configuration, MANUAL/VIRTUAL
mode configuration as needed for DRA72-evm.
Also update the mux for SD card detect on DRA74-evm.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Updating the memory banks properly so that DT is populated accordingly.
And updating this only after DDR is properly detected by eeprom, so that
git bisect is still maintained.
Acked-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The REVH and later versions of DRA7-evm uses MICRON MT41K512M16HA-125 memory
chips which is of size 4GB(2GB on EMIF1 and 2GB on EMIF2). Add support for the
same.
Acked-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The newer versions of DRA7 boards has EEPROM populated with DDR
size specified in it. Moving DRA7 specific emif related settings
to board files so that emif settings can be identified based on EEPROM.
Acked-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
DRA7 EVM revH and later EVMs have EEPROM populated that can contain board
description information such as name, revision, DDR definition, etc. Adding
support for this EEPROM format.
Acked-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
There are certain EMIF timing failures seen on the some x15 boards. Updating
the EMIF settings to get rid of these timing failures.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
A few boards still use ns16550_platdata structures, but assume the structure
is going to be in a specific order. By explicitly naming each entry,
this should also help 'future-proof' in the event the structure changes.
Tested on the Logic PD Torpedo + Wireless.
I only changed a handful of devices that used the same syntax as the Logic
board. Appologies if I missed one or stepped on toes. Thanks to Derald Woods
and Alexander Graf.
Signed-off-by: Adam Ford <aford173@gmail.com>
V6: Add fix to arch/arm/cpu/armv7/am33xx/board.c
V5: Add fix to arch/arm/cpu/arm926ejs/lpc32xx/devices.c
V4: Fix subject heading
V3: Remove reg_offset out in all the structs. It was reverted out, and and if
it did exist, it would get initialized to 0 by default.
V2: I hastily copy-pasted the boards without looking at the UART number.
This addresses 3 boards that use UART3 and not UART1.
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Because KS2 u-boot works in 32 bit address space the existing ram_size
global data field cannot be used. The maximum, which the get_ram_size()
can detect is 2GB only. The ft_board_setup() needs the actual ddr3 size
to fix up dtb.
This commit introduces the ddr3_get_size() which uses SPD data to
calculate the ddr3 size. This function replaces the "ddr3_size"
environment variable, which was used to get the SODIMM size.
For platforms, which don't have SODIMM with SPD and ddr3 is populated to
a board a simple ddr3_get_size function that returns ddr3 size has to be
implemented. See hardware-k2l.h
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This commit replaces hard-coded EMIF and PHY DDR3 configurations for
predefined SODIMMs to a calculated configuration. The SODIMM parameters
are read from SODIMM's SPD and used to calculated the configuration.
The current commit supports calculation for DDR3 with 1600MHz and 1333MHz
only.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The maximum device and arm speeds can be determined by reading
EFUSE_BOOTROM register. As there is already a framework for reading this
register, adding support for all possible speeds on k2g devices.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Its not compulsory that speed definition should be same on EFUSE_BOOTROM
register for all keystone 2 devices. So, allow for board specific
speed definitions.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This is based on the davinci da850evm. It can boot from either the
on-board 16MB flash or from a microSD card. It also reads board
information from an I2C EEPROM.
The EV3 itself initally boots from write-protected EEPROM, so no
u-boot SPL is needed.
Signed-off-by: David Lechner <david@lechnology.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Current AM57xx evm supports both BeagleBoard-X15
(http://beagleboard.org/x15) and AM57xx EVM
(http://www.ti.com/tool/tmdxevm5728).
The AM572x EValuation Module(EVM) provides an affordable platform to
quickly start evaluation of Sitara. ARM Cortex-A15 AM57x Processors
(AM5728, AM5726, AM5718, AM5716) and accelerate development for HMI,
machine vision, networking, medical imaging and many other industrial
applications. This EVM is based on the same BeagleBoard-X15 Chassis
and adds mPCIe, mSATA, LCD, touchscreen, Camera, push button and TI's
wlink8 offering.
Since the EEPROM contents are compatible between the BeagleBoard-X15 and
the AM57xx-evm, we add support for the detection logic to enable
support for various user programmable scripting capability.
NOTE: U-boot configuration is currently a superset of AM57xx evm and
BeagleBoard-X15 and no additional configuration tweaking is needed.
This change also sets up the stage for future support of TI AM57xx EVMs
to the same base bootloader build.
Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Now that we have a generic TI eeprom logic which can be reused across
platforms, reuse the same.
This revision also includes fixes identified by Dave Gerlach
<d-gerlach@ti.com>
Cc: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Steven Kipisz <s-kipisz2@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Use the generic EEPROM detection logic instead of duplicating the AM
eeprom logic.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Steven Kipisz <s-kipisz2@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Several TI EVMs have EEPROM that can contain board description information
such as revision, DDR definition, serial number, etc. In just about all
cases, these EEPROM are on the I2C bus and provides us the opportunity
to centralize the generic operations involved.
The on-board EEPROM on the BeagleBone Black, BeagleBone, AM335x EVM,
AM43x GP EVM, AM57xx-evm, BeagleBoard-X15 share the same format.
However, DRA-7* EVMs, OMAP4SDP use a modified format.
We hence introduce logic which is generic between these platforms
without enforcing any specific format. This allows the boards to use the
relevant format for operations that they might choose.
This module will compile for all TI SoC based boards when
CONFIG_TI_I2C_BOARD_DETECT is enabled to have optimal build times for
platforms that require this support.
It is important to note that this logic is fundamental to the board
configuration process such as DDR configuration which is needed in
SPL, hence cannot be part of the standard u-boot driver model (which
is available later in the process). Hence, to aid efficiency, the
eeprom contents are copied over to SRAM scratchpad memory area at the
first invocation to retrieve data.
To prevent churn with cases such as DRA7, where eeprom format maybe
incompatible, we introduce a generic common format in eeprom which
is made available over accessor functions for usage.
Special handling for BBG1 EEPROM had to be introduced thanks to the
weird eeprom rev contents used.
The follow on patches introduce the use of this library for AM335x,
AM437x, and AM57xx.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
There are already two FIT options in Kconfig but the CONFIG options are
still in the header files. We need to do a proper move to fix this.
Move these options to Kconfig and tidy up board configuration:
CONFIG_FIT
CONFIG_OF_BOARD_SETUP
CONFIG_OF_SYSTEM_SETUP
CONFIG_FIT_SIGNATURE
CONFIG_FIT_BEST_MATCH
CONFIG_FIT_VERBOSE
CONFIG_OF_STDOUT_VIA_ALIAS
CONFIG_RSA
Unfortunately the first one is a little complicated. We need to make sure
this option is not enabled in SPL by this change. Also this option is
enabled automatically in the host builds by defining CONFIG_FIT in the
image.h file. To solve this, add a new IMAGE_USE_FIT #define which can
be used in files that are built on the host but must also build for U-Boot
and SPL.
Note: Masahiro's moveconfig.py script is amazing.
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Add microblaze change, various configs/ re-applies]
Signed-off-by: Tom Rini <trini@konsulko.com>
This is a device number, and we want to use 'dev' to mean a driver model
device. Rename the member.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Rename three partition functions so that they start with part_. This makes
it clear what they relate to.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Stephen Warren <swarren@nvidia.com>
Use 'struct' instead of a typdef. Also since 'struct block_dev_desc' is long
and causes 80-column violations, rename it to struct blk_desc.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
GPIO4_21 is the LAN8720 power pin, not the LAN8720 reset pin.
Fix that, so that we can have Ethernet functional again.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Add support for GE B450v3, B650v3 and B850v3 boards. The boards
are based on Advantech BA16 module which has a i.MX6D processor.
The boards support:
- FEC Ethernet
- USB Ports
- SDHC and MMC boot
- SPI NOR
- LVDS and HDMI display
Basic information about the module:
- Module manufacturer: Advantech
- CPU: Freescale ARM Cortex-A9 i.MX6D
- SPECS:
Up to 2GB Onboard DDR3 Memory;
Up to 16GB Onboard eMMC NAND Flash
Supports OpenGL ES 2.0 and OpenVG 1.1
HDMI, 24-bit LVDS
1x UART, 2x I2C, 8x GPIO,
4x Host USB 2.0 port, 1x USB OTG port,
1x micro SD (SDHC),1x SDIO, 1x SATA II,
1x 10/100/1000 Mbps Ethernet, 1x PCIe X1 Gen2
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Fix the BOOTCFG value for eMMC in the same way as commit
214c3f0f99
[imx: MX6DQ{P}/DL:SABRESD Fix bmode eMMC failure]
did for sabresd.
Signed-off-by: Soeren Moch <smoch@web.de>
This introduces some minor cleanups, regarding aspects such as board name, code
and headers organization as well as deprecated and missing config options.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
Gets propagated into the device tree and then into /proc/cpuinfo where
users often expect it.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
During boot, U-Boot raises the CPU frequency but the CORE and MPU regulators
are not updated. This is not a problem in cold boot since the default values
that the pmic outputs are correct, but if Linux were to switch the module to a
low power OPP, the new voltage values will be retained after a reboot and the
module will likely hang once U-Boot raises the CPU frequency back up.
Set both CORE and MPU regulators to to 1.1V on boot.
Cc: Tom Rini <trini@konsulko.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Reviewed-by: Tom Rini <trini@konsulko.com>
CM-T43 does not have a vtt regulator. Remove the function that's supposed
to enable it.
Cc: Tom Rini <trini@konsulko.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Reviewed-by: Tom Rini <trini@konsulko.com>
Set TPS65218 FSEAL bit to 1 so that RTC could be powered using on-board
3V battery. This is necessary so that time and date will survive reboots and
power offs.
Cc: Tom Rini <trini@konsulko.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Reviewed-by: Tom Rini <trini@konsulko.com>
Simplify the board file by splitting it to spl portion and u-boot portion.
Some unnecessary includes were identified and removed. No functional changes.
Cc: Tom Rini <trini@konsulko.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Reviewed-by: Tom Rini <trini@konsulko.com>
During very early prototype-phase we did boot the AM335x boards
initially from CPSW-EMAC.
Now we don't need this feature anymore.
So we drop it to save MLO-space and having therefore a more quickly
boot.
Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Reviewed-by: Tom Rini <trini@konsulko.com>
Logic PD makes four different system on modules. This patch will auto
detect the board type and identify the corresponding device tree image.
V2:
Added 'default:' case to switch statement
Since board_late_init() is defined as int, we now return 0
Signed-off-by: Derald Woods <woods.technical@gmail.com>
Signed-off-by: Adam Ford <aford173@gmail.com>
Compiling the mkorigenspl tool on darwin complains about undefined ulong. Fix
this by using the unified way.
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
This patch removes the gpio clock enable from gpio driver & move it in the
board code, making it possible to use the gpio driver with other socs.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
The initialization for smmu and stream id is moved into the common soc
code.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
QE-HDLC and USB multi-use the pins, modify the pin-muxing code
for them, when set "hwconfig=qe-hdlc" in uboot, assign the pins
to QE-HDLC, if not, assgin it to USB
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Pin-muxing code should be in config_board_mux, move USB muxing
config to config_board_mux.
Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
As the QE firmware struct is shared with Fman, move the header file
out of drivers/qe/.
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
As QSPI and IFC are pin-multiplexed on LS1021A, only IFC is supported
in SD boot now. For the customer's demand, QSPI needs to be supported
in SD boot too.
This patch adds QSPI or IFC support in SD boot according to the
corresponding defconfig. For detail, ls1021aqds_sdcard_ifc_defconfig
is used to support IFC in SD boot and ls1021aqds_sdcard_qspi_defconfig
is used to support QSPI in SD boot.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
SY8106A is a PMIC which is used on the Allwinner
H3 Orange Pi Pc and Plus board. The VOUT1_SEL register is
implemented to set the default V-CPU voltage to 1200 mV.
This driver is required to ensure the SY8106A V-CPU
voltage is set to 1200 mV after a software reset. On cold
boot the default SY8106A output voltage is selected to be
1200 mV by a pair of resistors on the Orange Pi PC and Plus.
Signed-off-by: Jelle van der Waa <jelle@vdwaa.nl>
Tested-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
OF_CONTROL is setup by default and memory reading is done via DT. Remove
all config files with memory references.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Specify max_bus_width directly in usdhc_cfg static definition instead
of tweaking it in the board_mmc_init() function.
Signed-off-by: Julien Corjon <corjon.j@ecagroup.com>
USDHC2 does not exist on mx6quq7 board, as USDHC4 was already been
declared this is probably a typo.
Signed-off-by: Julien Corjon <corjon.j@ecagroup.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
When running the 'ums' command we get:
=> ums 0 mmc 0
UMS: disk start sector: 0x0, count: 0xe18000
g_dnl_register: failed!, error: -22
ERROR: g_dnl_register failed
at common/cmd_usb_mass_storage.c:107/do_usb_mass_storage()
Fix this by initializing USB OTG1 port as USB device mode instead of host.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
This adds basic support to Intel Cougar Canyon 2 board, a board
based on Chief River platform with an Ivy Bridge processor and
a Panther Point chipset.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
The Versatile Industrial Communication platform is a community oriented
board from Landis + Gyr. It comes with:
- an RS-485 port
- 2 Ethernet ports
- a wireless M-BUS
- a 4G modem
- a 4MB SPI flash
- a 4GB eMMC
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
[rebase on current TOT]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Add support for DENX MA5D4 SoM and MA5D4EVK board, based on the
Atmel SAMA5D4 SoC. The SoM contains the SoC, eMMC, SPI NOR, SPI
CAN controllers and DRAM, the baseboard contains UART connectors,
ethernet port, microSD slot, LCD header, 2x CAN connector and a
lot of expansion headers.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Due to introducing the PMC_PLLICPR init function, use this
function to clean up the code.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Tested-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Due to introducing the new PLLB clock handle functions,
use these functions to clean up the PLLB enable code.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Tested-by: Heiko Schocher <hs@denx.de>
Due to introducing the new UTMI PLL clock handle functions,
use the functions to reduce the duplicated code.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Tested-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Due to introducing the new peripheral clock handle functions,
use these functions to reduce duplicated code.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Tested-by: Heiko Schocher <hs@denx.de>
[Rebased on current master, fixup for at91rm9200ek]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Move this driver over to use driver model. This involves rearranging the
code somewhat. The effect is that everything is run from the probe() method.
Boards which use this are fixed up, but only seaboard is tested.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This option refers only to the tegra20 video driver, so name it as such
to avoid confusion with tegra124.
Also move this option to Kconfig.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
Signed-off-by: Tom Warren <twarren@nvidia.com>
According to Data Manual(SPRS915P) of AM572x, TI QSPI controller on
DRA74 EVM(rev 1.1+) can support up to 64MHz in MODE-0, whereas MODE-3 is
limited to 48MHz. Hence, switch to MODE-0 for better throughput.
Also, add IODelay parameters for the same.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
I will take this over from Peter Barada, since I work with it daily
at Logic PD.
Signed-off-by: Adam Ford <aford173@gmail.com>
Acked-by: Peter Barada <peter.barada@logicpd.com>
There are various different boards with the same hardware sold as LG Optimus
Black, such as P970, P970g and KU5900. Since this port is functional for all
variants, it doesn't make sense to keep references to P970.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
Let's set "ethaddr" when we get the ethernet address too, so that
fdt_fixup_ethernet() sets the address in the device tree and the Linux
driver can pick it up.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
remove board_eth_init when CONFIG_DM_ETH is defined
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Android Fastboot requires USB. The TWL4030 PMIC on omap3_logic handles USB traffic.
This patch sets up the USB gadget and Android Fastboot to match what is done in the
omap3_beagle project.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Previously, Omap3_logic assumed X-loader was present. With this
patch, we can finally replace X-loader with an MLO generated by
U-Boot. This requires ECC to be setup to match the Linux Kernel
and the PBIAS confgured for the SD card.
Signed-off-by: Derald D. Woods <woods.technical@gmail.com>
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The P5 header was not present on "Model B" any board prior to Revision 2.0,
there's no need for a separate device tree.
Also, it looks like "rev2" is incorrectly used to only cover the 512MiB
memory models; there also were 256MiB 2.0 boards.
I don't have all of the boards to check this, I'm following this table:
http://elinux.org/RPi_HardwareHistory#Board_Revision_History
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
This source has been blessed by Dom Cobley at the RPi Foundation, so seems
like the best source to refer to. It's a superset of and consistent with
the other sources.
Cc: Lubomir Rintel <lkundrak@v3.sk>
Cc: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
This patch removes the uart clock enable from serial driver & move it in the
board code.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Correct spelling of "U-Boot" shall be used in all written text
(documentation, comments in source files etc.).
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
asm/arch/gpio.h is not needed anymore as we get the GPIO base from
PCH driver.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Implement board_mmc_get_env_dev for the boards.
Following is examples:
SD1/SD2/SD3: return devno;
SD2/SD3: return devno - 1;
SD2/SD4: if (devno == 2), return dev - 2; return dev - 1;
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Move mmc_get_env_devno to soc.c and rename to mmc_get_env_dev to
match the one in common/env_mmc.c.
Introduce a weak function board_mmc_get_env_dev. Different
boards can implement this according to sdhc controller which
is used by the board.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
The i.MX6SX SABRESD board supports MCIMX28LCD (800x480x24) at LCDIF1
port, enable this display feature by adding relevant BSP codes
and configurations.
Signed-off-by: Ye Li <ye.li@nxp.com>
The BOOTCFG value used by bmode for SABRESD eMMC boot are actually for SD card.
Fixed the value to correct one.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Fabio Estevam <fabio.estevam@nxp.com>
According to the LAN8720 datasheet tpurstd (time that reset line should
stay asserted) is 25ms.
So do as suggested by the LAN8720 datasheet.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Since commit 59370f3fcd ("net: phy: delay only if reset handler is
registered") Ethernet is no longer functional.
This commit does not have an issue in itself, but it revelead a problem
with the Ethernet initialization.
According to the LAN8720 datasheet tpurstd (time that reset line should
stay asserted) is 25ms.
So do as suggested in order to have Ethernet working again.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Initial version for mx6sx SABREAUTO board support with features:
PMIC, QSPI, NAND flash, SD/MMC, USB, Ethernet, I2C, IO Expander.
Signed-off-by: Ye Li <ye.li@nxp.com>
Enable the DDR calibration functionality on Novena to deal with the
memory SoDIMM on this board. Moreover, tweak the initial DDR DRAM
parameters so the calibration works properly.
Signed-off-by: Marek Vasut <marex@denx.de>
The sama5d2 Xplained SPL supports the boot medias: spi flash
and SD Card.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
Add struct atmel_mpddrc_config to accommodate the mpddrc register
configurations, not using the mpddrc register map structure,
struct atmel_mpddrc, in order to increase readability and reduce
run-time memory use.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
This adds support for Microchip PIC32MZ[DA] StarterKit board
based on a PIC32MZ[DA] family of microcontroller.
Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Rather than passing the I/O port base address to the Super I/O code,
switch it to using outb such that it makes use of the I/O port base
address automatically.
Drop the extern keyword to satisfy checkpatch whilst here.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Set the I/O port base earlier, from board_early_init_f, in preparation
for it being used by the serial driver.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
The call to pci_eth_init() should not be wrapped with CONFIG_TSEC_ENET.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The call to pci_eth_init() should not be wrapped with CONFIG_TSEC_ENET.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The call to pci_eth_init() should not be wrapped with CONFIG_TSEC_ENET.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The call to pci_eth_init() should not be wrapped with CONFIG_TSEC_ENET.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The call to pci_eth_init() should not be wrapped with CONFIG_TSEC_ENET.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The call to pci_eth_init() should not be wrapped with CONFIG_TSEC_ENET.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
The PMIC is configured such that its GPIOs have the correct configuration
at power-up, so no programming is required.
In fact, the current programming is actively wrong, since:
(a) the AS3722 driver configures the GPIO to be an output before setting
its output value, which causes a 0v glitch on the output.
(b) the AS3722 driver configures the GPIO to drive a high voltage from its
VSUP_GPIO power source rather than its VDD_GPIO_LV power source, so the pin
drives 5V not 1.8V as desired.
Solve these problems by removing the code which configures the PMIC GPIOs.
Note that this patch was tested directly on top of v2016.01; since then,
commit 96350f729c "dm: tegra: net: Convert tegra boards to driver model
for Ethernet" prevents PCIe from being initialized. Alternatively, simply
revert that commit to get PCIe Ethernet working again, then apply this
patch to test.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Enable the U-Boot Driver Model(DM) to use the Freescale QSPI driver.
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
QSPI and IFC are pin-multiplexed on LS1043A. So we use
ls1043aqds_sdcard_ifc_defconfig to support IFC in SD boot and
ls1043aqds_sdcard_qspi_defconfig to support QSPI in SD boot.
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Set Board Configuration Register to select the lpuart pins of various
muxes.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: York Sun <york.sun@nxp.com>
In case of error while executing esbc_validate command, SNVS
transition and issue of reset is required only for secure-boot.
If boot mode is non-secure, this is not required.
Similarly, esbc_halt command which puts the core in Spin Loop
is applicable only for Secure Boot.
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Chain of Trust is enabled for ARM platforms (LS1021 and LS1043).
In board_late_init(), fsl_setenv_chain_of_trust() is called which
will perform the following:
- If boot mode is non-secure, return (No Change)
- If boot mode is secure, set the following environmet variables:
bootdelay = 0 (To disable Boot Prompt)
bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script)
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
A function is created to detrmine if the boot mode is secure
or non-secure for differnt SoC's.
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
If the xparameters file contains a LL_TEMAC definition compile its
driver and the net commands.
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
board_pre_init was not called because CONFIG_BOARD_EARLY_INIT_F was not
set. Remove unused function.
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
board_pre_init was not called because CONFIG_BOARD_EARLY_INIT_F was not
set. Remove unused function.
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Now that the specific boards have been removed there is no need to
maintain the weak functions.
Fix also CamelCase to make checkpatch happy
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Now that the specific boards have been removed there is no need to
maintain the weak functions.
Fix also CamelCase to make checkpatch happy
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
xilinx_uartlite has been ported to DM, this patch makes the
xilinx-ppc405-generic and the xilinx-ppc440-generic boards use the new
DM driver.
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Use space instead of tab in checkboard print to aligned
it with others boards.
Reported-by: David Glessner <david.glessner@rockwellcollins.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Moritz Fischer <moritz.fischer@ettus.com>
When only sdhci1 IP is enabled and SD_MODE1 bootmode is selected
U-Boot using sdboot1 variable which refers to mmc dev 1.
But this device doesn't exist because only one controller is available.
This patch fix logic around sdboot mode with using sdbootdev internal
variable.
Reported-by: Chris Kohn <ckohn@xilinx.com>
Acked-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Show also EMMC bootmode if selected. There is difference compare to SD
bootmode. Use the same bootcommand till better boot command is created.
Reported-by: Sai Pavan Boddu <saipava@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Showing information about bootmode is very useful to make sure
that correct bootmode is selected.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Modify the SD bootmode value to 0x3 as per latest
spec. Also add new boot mode QSPI 32 bit boot mode
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Remove SECURE_IOU option which is not needed. U-Boot itself can detect
which EL level it is on and based on that use do platform setup.
It also simplify usage because one Kconfig entry is gone.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
board_init() is in final elf file but it is not called at all.
Use board_init_late() instead and call gpio_init() from it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add PHYLIB and MII dependencies and enable it by default for Microblaze.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
- Move config option out of board file.
- Remove uartlite address from config file
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Thomas Chou <thomas@wytron.com.tw>
-Remove UART address (It is now part of the dts).
-Include dummy ns16550 clock
-Fix address to last test
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
As a result of the specific board removal, the Makefiles can be
simplified.
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
As a result of the specific board removal, the Makefiles can be
simplified.
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
The old mail address will stop working soon.
Update it all the files
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
It is just a specialized version of xilinx-ppc440
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
It is just a specialized version of the xilinx-ppc405
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
ml507 is just a specialized version of the xilinx-ppc440-generic
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
This patch adds support for the Armada XP (MV78260) based theadorable
board. Its equipped with onboard DDR3, UART, ethernet, I2C, SPI NOR,
LCD and SATA (SSD) interfaces / devices.
Two defconfigs are added:
theadorable_defconfig:
The production U-Boot version with a stripped down drivers and feature
list. This removes networking, USB and PCI support.
theadorable_debug_defconfig:
The debugging / testing U-Boot version with full support for all drivers.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Signed-off-by: Stefan Roese <sr@denx.de>
Previously, AXP818 ALDO support was partially added to Kconfig, but
never enabled in the board file, nor properly set or configured in
Kconfig. The boards continue to work because the AXP818 is designed
to pair with the A83T/H8, and the default voltages match the reference
design's requirements.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Instead of one function for each DLDO regulator, make 1 function that
takes an extra "index". Since the control bits for the DLDO regulators
are contiguous, this makes the function very simple. This removes a lot
of duplicate code.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Add dts and defconfig for Banana-pi M3 board.
It has 2G LPDDR3, UART, ethernet, USB, HDMI, USB Sata, MIPI DSI,
mic, AP6212 Wifi, etc on it.
It is paired with AXP813 PMIC which is almost same as AXP818.
Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
[hdegoede@redhat.com: rename to Sinovoip_BPI_M3_defconfig/sun8i-a83t-sinovoip-bpi-m3.dts]
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Different A83T boards have different DRAM types. Banapi M3 has LPDDR3,
Allwinner Homlet v1.2 has DDR3.
This adds groundwork to support for new DRAM type for A83T.
Introduce CONFIG_DRAM_TYPE, It'll be 3 for DDR3 and 7 for LPDDR3, must
be set in respective board defconfig.
Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Now that we support PSCI and various security switches, we can let
U-boot boot Linux into non-secure and HYP mode.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The fuse status register provides the values from on-chip
voltage ID efuses programmed at the factory. These values
define the voltage requirements for the chip. u-boot reads
FUSESR and translates the values into the appropriate
commands to set the voltage output value of an external
voltage regulator.
Signed-off-by: Ying Zhang <b40530@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
IR chip on all the boards are required to be used in Intel mode
to support VID. VDD will not be adjusted if IR chip is used in
other modes.
Signed-off-by: Ying Zhang <b40530@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Users migrating Freescale's PowerPC SoC U-Boot code to their custom
board, often overlook the need to execute set_liodns() and
setup_portals() being called by platform files.
So Move set_liodns() and setup_portals() to common u-boot boot
sequence
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Some images to be validated are relocated to a dynamic
address at run time. So, these addresses cannot be known
befor hand while signing the images and creating the header
offline.
So, support is required to pass the image address to the
validate function as an argument.
If an address is provided to the function, the address
field in Header is not read and is treated as a reserved
field.
Signed-off-by: Saksham Jain <saksham@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The code for image hash calculation, hash calculation from
RSA signature and comparison of hashes has been mobed to a
separate function.
Signed-off-by: Saksham Jain <saksham@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Separate functions are created for reading and checking the
sanity of Public keys:
- read_validate_single_key
- read_validate_ie_tbl
- read_validate_srk_table
Signed-off-by: Saksham Jain <saksham@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The prototype and defination of function fsl_secboot_validate
has been changed to support calling this function from another
function within u-boot.
Only two aruments needed:
1) header address - Mandatory
2) SHA256 string - optional
Signed-off-by: Saksham Jain <saksham@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
1.Use "qixis_reset sd" to boot from SD
2.Use "qixis_reset sd_qspi" to boot from SD with QSPI support
3.Use "qixis_reset qspi" to boot from QSPI flash
On some SoCs such as LS1021A and LS1043A, IFC and QSPI could be
pin-multiplexed. So the switches are different between SD boot with
IFC support and SD boot with QSPI support. The default booting from
SD is with IFC support.
Once QSPI is enabled(IFC disabled), only use I2C to access QIXIS.
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This patch also exposes the complete DDR region(s) to Linux.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
With gcc 4.9, it produces the following warnings:
CC board/tqc/tqm834x/tqm834x.o
board/tqc/tqm834x/tqm834x.c: In function 'initdram':
board/tqc/tqm834x/tqm834x.c:325:12: warning: iteration 3u invokes undefined behavior [-Waggressive-loop-optimizations]
(((base + size - 1) >> CSBNDS_EA_SHIFT) &
^
board/tqc/tqm834x/tqm834x.c:80:2: note: containing loop
for(cs = 0; cs < 4; ++cs) {
^
There is an integer overflow when cs = 3. To fix it, change
parameters of set_cs_bounds() to ulong.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Currently buildman fails to build sh7753evb and reports the following:
board/renesas/sh7753evb/built-in.o: In function 'init_gether_mdio':
board/renesas/sh7753evb/sh7753evb.c:94: undefined reference to 'PMB_ADDR_BASE'
board/renesas/sh7753evb/sh7753evb.c:94: undefined reference to 'PMB_DATA_BASE'
board/renesas/sh7753evb/sh7753evb.c:94: undefined reference to 'mk_pmb_addr_val'
board/renesas/sh7753evb/sh7753evb.c:94: undefined reference to 'mk_pmb_data_val'
make: *** [u-boot] Error 1
The fix is to wrap any codes that access these macros with CONFIG_SH_32BIT.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Add pinmux settings.
Add related macro definitions.
Nand pin conflicts with emmc, so if want to enable nand, need to do
hardware rework. After hardware rework, define CONFIG_NAND_MXS in
board header file.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
As the lowlevel_init function is empty we should better
remove this assembly file entirely and use a dummy C
function instead.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Instead of calling the northbridge and PCH init from bd82x6x_init_extra()
when the PCI bus is probed, call it from the respective drivers. Also drop
the Northbridge init as it has no effect. The registers it touches appear to
be read-only.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This board includes an RK3288 SoC on a SOM. It can be mounted on a
base-board which provides a wide range of peripherals.
So far this is verified to boot to a prompt from a microSD card. The serial
console works as well as HDMI.
Thanks to Tom Cubie for sending me a board.
Signed-off-by: Simon Glass <sjg@chromium.org>
We will save boot mode flag in grf's os_reg[4], if fastboot
requested or fastboot key pressed, try to enter fastboot mode
at preboot stage.
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Jelle van der Waa <jelle@vdwaa.nl>
[hdegoede@redhat.com: Minor cleanups]
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
applied with fixing 2 checkpatch warnings:
WARNING: please, no space before tabs
Signed-off-by: Heiko Schocher <hs@denx.de>
Now that driver model support is available, convert sandbox over to use it.
We can remove a few of the special hooks that sandbox currently has.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Anatolij Gustschin <agust@denx.de>
- move chip reset to separate function
- use CONFIG_SMC911X_BASE instead of hardcoded value
- remove unneeded local variable from board_eth_init.
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Enric Balletbo Serra <enric.balletbo@collabora.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
The include/configs/yucca.h already has the same define:
#define CONFIG_SYS_TEXT_BASE 0xfffb0000
Remove the redundant one from board/amcc/yucca/config.mk.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Stefan Roese <sr@denx.de>
We can delete board/pb1x00/config.mk by moving the define of
CONFIG_SYS_TEXT_BASE to somewhere else. Other MIPS boards are
still defining it in include/config/${BOARD}.h, so I am following
that way here.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
We can delete board/dbau1x00/config.mk by moving the define of
CONFIG_SYS_TEXT_BASE to somewhere else. Other MIPS boards are
still defining it in include/config/${BOARD}.h, so I am following
that way here.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
We can delete board/micronas/vct/config.mk by moving the define of
CONFIG_SYS_TEXT_BASE to somewhere else. Other MIPS boards are
still defining it in include/config/${BOARD}.h, so I am following
that way here.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
This is how CONFIG options are defined by Kconfig.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
The board/freescale/m54418twr/config.mk defined TEXT_BASE, which has
the same value as CONFIG_SYS_TEXT_BASE. The TEXT_BASE is referenced
by two files:
- arch/m68k/cpu/mcf5445x/start.S and include/
- include/configs/M54418TWR.h
Replace the references with CONFIG_SYS_TEXT_BASE and delete
board/freescale/m54418twr/config.mk.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Angelo Dureghello <angelo at sysam.it>
For historical reason, CONFIG_SYS_TEXT_BASE has been specified
in various ways:
[1] by board/${VENDOR}/${BOARD}/config.mk
[2] by CONFIG_SYS_EXTRA_OPTIONS
(This was "options" field of boards.cfg before Kconfig conversion)
[3] by include/configs/${BOARD}.h
[4] by configs/${BOARD}_defconfig
Most of M68K boards use either [1] or [2], both of which we want to
deprecate. Switch them into [4], which is the newest way (Kconfig).
We still allow [3] too, because it is still used by many boards and
we expect much time for conversion.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Angelo Dureghello <angelo at sysam.it>
Reviewed-by: Simon Glass <sjg@chromium.org>
Change the dram_init() function on ThunderX to query ATF services for
the real installed DRAM size
Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com>
Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com>
In a number of places we had wordings of the GPL (or LGPL in a few
cases) license text that were split in such a way that it wasn't caught
previously. Convert all of these to the correct SPDX-License-Identifier
tag.
Signed-off-by: Tom Rini <trini@konsulko.com>
Use void pointers as address argument for readl( and writel()).
This is required for the upcoming MIPS asm header file and I/O
accessor update.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Use void pointer as address argument for readl(). This is required
for the upcoming MIPS asm header file and I/O accessor update.
Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
With format-security errors turned on, GCC picks up the use of sprintf with
a format parameter not being a string literal.
Simple uses of sprintf are also converted to use strcpy.
Signed-off-by: Ben Whitten <ben.whitten@gmail.com>
Acked-by: Wolfgang Denk <wd@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Synology keeps per item configuration in a dedicated 'partition' in SPI
flash, namely the one named 'vendor' in DTS file. It contains the two
NICs MAC addresses as well as the item's serial number. I didn't find a
way to have this information extracted automatically, therefore
implemented 'syno populate_env' command which extracts the three values
and puts them into environment. To make things permanent though, one has
to 'saveenv'.
Another command is 'syno clk_gate', which allows to change the clock
gating which is done in DS414 board file.
Signed-off-by: Phil Sutter <phil@nwl.cc>
Acked-by: Stefan Roese <sr@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
This adds support for the MV78230 based DS414 NAS by Synology. The
relevant bits have been extracted from the 'synogpl-5004-armadaxp'
package Synology kindly published, garnished with a fair amount of
trial-and-error.
Sadly, support is far from perfect. The major parts I have failed in
are SATA and XHCI support. Details about these and some other things
follow:
Device Tree
-----------
The device tree file armada-xp-synology-ds414.dts has been copied from
Linux and enhanced by recent U-Boot specific changes to
armada-xp-gp.dts.
SATA Support
------------
There is a Marvell 88SX7042 controller attached to PCIe which is
supported by Linux's sata_mv driver but sadly not U-Boot's sata_mv.
I'm not sure if extending the latter to support PCI devices is worth the
effort at all. Porting sata_mv from Linux exceeded my brain's
capacities. :(
XHCI Support
------------
There is an EtronTech EJ168A XHCI controller attached to PCIe which
drives the two rear USB3 ports. After a bit of playing around I managed
to get it recognized by xhci-pci, but never was able to access any
devices attached to it. Enabling it in ds414 board config shows that it
does not respond to commands for whatever reason. The (somewhat) bright
side to it is that it is not even supported in Synology's customized
U-Boot, but that also means nowhere to steal the relevant bits from.
EHCI Support
------------
This seems functional after issuing 'usb start'. At least it detects USB
storage devices, and IIRC reading from them was OK. OTOH Linux fails to
register the controller if 'usb start' wasn't given before in U-Boot.
According to Synology sources, this board seems to support USB device
(gadget?) mode. Though I didn't play around with it.
PCIe Support
------------
This is fine, but trying to gate the clocks of unused lanes will hang
PCI enum. In addition to that, pci_mvebu seems not to support DM_PCI.
DDR3 Training
-------------
Marvell/Synology uses eight PUPs instead of four. Does not look like
this is meant to be customized in mainline U-Boot at all. OTOH I have
no idea what a "PUP" actually is.
PEX Init
--------
Synology uses different values than mainline U-Boot with this patch:
pex_max_unit_get returns 2, pex_max_if_get returns 7 and
max_serdes_lines is set to 7. Not changing this seems to not have an
impact, although I'm not entirely sure it does not cause issues I am not
aware of.
Static Environment
------------------
This allows to boot stock Synology firmware at least. In order to be a
little more flexible when it comes to booting custom kernels, do not
only load zImage partition, but also rd.gz into memory. This way it is
possible to use about 7MB for kernel with piggyback initramfs.
Signed-off-by: Phil Sutter <phil@nwl.cc>
Acked-by: Stefan Roese <sr@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Merging all the board specific Kconfig options into the main Kconfig file
for mach-mvebu makes things easier to maintain.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
This patch adds basic support for the SolidRun ClearFog Armada 38x based
board to mainline U-Boot. Supported interfaces / devices are:
- DDR3
- UART
- MMC
- Ethernet port 0 (connected to dedicated PHY)
- I2C
The included DT source was taken from Russell King's ftp server:
http://www.home.arm.linux.org.uk/~rmk/clearfog/
With only minor modifications, like the addition of some aliases and the
"u-boot,dm-pre-reloc" property.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Rabeeh Khoury <rabeeh@solid-run.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Update this driver to support driver model. As all MVEBU boards using
this driver are converted with this patch, the non-driver-model code
can be removed completely. This is also the reason why this patch
is quite big and includes a) the driver change and b) the
platform change. As its not git-bisect save otherwise.
With this conversion, some parameters are now extracted from the
DT instread of using the config header defines. The supported
properties right now are:
PHY-mode ("phy-mode") and PHY-address ("reg").
The base addresses for the ethernet controllers can be removed from
the header files as well.
Please note that this patch also removes the E1000 network driver
from some MVEBU config headers. This is necessary, as with DM_ETH
configured and the e1000 driver enabled, the PCI driver also needs
to support DM. But the MVEBU PCI(e) driver still needs to get
ported to DM. When this is done, the E1000 driver can be enabled
again.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <dirk.eibach@gdsys.cc>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Simon Glass <sjg@chromium.org>
This patch adds full DM support to the SPL on MVEBU. Currently
only serial is supported. Other drivers will follow.
This patch also adds the necessary config values for the DEBUG UART
to the MVEBU defconfig files. This came in handy while implementing
this DM support.
Additionally, the mvebu specific SPL linker script is removed and
this common one is used instead:
arch/arm/cpu/u-boot-spl.lds
This common linker script already handles all special cases. No need
to reinvent the wheel for MVEBU here.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <dirk.eibach@gdsys.cc>
Cc: Simon Glass <sjg@chromium.org>
This cleans up the mux configuration a bit, setting mmc clock signals to input
enabled and specifying pull-down (0) when pull is not used.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
This will allow the implementation to make use of data in the block_dev
structure beyond the base device number. This will be useful so that eMMC
block devices can encompass the HW partition ID rather than treating this
out-of-band. Equally, the existence of the priv field is crying out for
this patch to exist.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Do not set HAVE_INTEL_ME by default as for some cases Intel ME
firmware even does not reside on the same SPI flash as U-Boot.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Adjust all Tegra boards to use driver model for Ethernet, now that the
required drivers are converted.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
'sf command' should receive the length in sector boundaries, so fix it
accordingly.
Also, show the steps to set the server and board IP addresses for
making the steps clearer.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
We currently support various versions of Solidrun mx6 boards, so
remove the obsolete comment.
Reported-by: Jon Nettleton <jon.nettleton@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Since commit 59370f3fcd ("net: phy: delay only if reset handler is
registered") Ethernet is no longer functional:
Booting from net ...
FEC Waiting for PHY auto negotiation to complete......... TIMEOUT !
BOOTP broadcast 1
BOOTP broadcast 2
BOOTP broadcast 3
BOOTP broadcast 4
This commit does not have an issue in itself, but it revelead a problem
with the Ethernet initialization.
As per the AR8035 datasheet:
"For a reliable power on reset, suggest to keep asserting the reset
low long enough (10ms) to ensure the clock is stable and clock-to-reset
1ms requirement is satisfied."
So do as suggested and keep the reset low for 10ms.
Also add a 100us delay after deasserting the reset line
to guarantee that the PHY ID can be read correctly and the Atheros
PHY can be loaded as per Troy Kisky's suggestion.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Tested-by: Tom Rini <trini@konsulko.com>
According to the Coverity result, a unsigned int variable is used fo less-
than-zero comparison, the result is never true. Need to fix the variable
type to signed int.
Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
As per the AR8031 datasheet:
"For a reliable power on reset, suggest to keep asserting the reset
low long enough (10ms) to ensure the clock is stable and clock-to-reset
1ms requirement is satisfied."
So do as suggested and also add a 100us delay after deasserting the
reset line to guarantee that the PHY ID can be read correctly and the
Atheros 8031 PHY driver can be loaded automatically.
This results in a simpler code.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
As per the AR8031 datasheet:
"For a reliable power on reset, suggest to keep asserting the reset
low long enough (10ms) to ensure the clock is stable and clock-to-reset
1ms requirement is satisfied."
So do as suggested and also add a 100us delay after deasserting the
reset line to guarantee that the PHY ID can be read correctly and the
Atheros 8031 PHY driver can be loaded automatically.
This results in a simpler code.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
In pci_map_region(), pass 'range_id' to fdt_read_range(),
otherwise the same address will be mapped again in other
calls to pci_map_region()
Signed-off-by: Miao Yan <yammiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alexander Graf <agraf@suse.de>
Move setup_display from board_early_init_f to board_init.
Add more clock settings.
Add blacklight iomux setting.
Add display_info_t info for the lvds screen.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Use the macro SETUP_IOMUX_PAD(...) rather than imx_iomux_v3_setup_multiple_pads(...) in order to setup
the pin configuration for ECSPI1.
ARRAY_SIZE(pads) provides the wrong size for imx_iomux_v3_setup_multiple_pads(pads, ARRAY_SIZE(pads)) in
case of MX6QDL. In the particular case, the content of GPR12 is overwritten and the IPG/AHB/ATB/ATP clocks
are deactivated. Therefore, the connection to the system via JTAG is not possible anymore. Furthermore,
kernel version 3.0.35 hangs during bootprocess in the function etm_init().
Signed-off-by: Michael Schanz <michael.schanz@congatec.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
This symbol is not used anywhere, so remove it. For spear600, remove
it from the board file, since the symbol is not defined for spear600
either.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
The Empire Electronix D709 tablet is a fairly standard 7" A13 tablet,
featuring usb-wifi, a micro-sd slot, micro-usb otg and headphone jack.
Empire Electronix is written on the back of the tablet, the D709 model
info can be found in the about tablet menu in android.
The PCB has no markings to speak of.
This dts file is identical to the one submitted to the upstream kernel.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Drop all the common board code, since it is not completely useless.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
This patch adds the necessary OF alias for the UDC node, which let's
the code locate the DWC2 UDC base address in OF instead of hard-coding
it into the U-Boot binary. The code is adjusted to use the address from
OF instead of the hard-coded one. Finally, the hard-coded address is
removed and USB DM support is enabled.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Lukasz Majewski <l.majewski@majess.pl>
Cc: Lukasz Majewski <l.majewski@samsung.com>
This patch adds the necessary OF alias for the UDC node, which let's
the code locate the DWC2 UDC base address in OF instead of hard-coding
it into the U-Boot binary. The code is adjusted to use the address from
OF instead of the hard-coded one. Finally, the hard-coded address is
removed and USB DM support is enabled.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Lukasz Majewski <l.majewski@majess.pl>
Cc: Lukasz Majewski <l.majewski@samsung.com>
This patch adds the necessary OF alias for the UDC node, which let's
the code locate the DWC2 UDC base address in OF instead of hard-coding
it into the U-Boot binary. The code is adjusted to use the address from
OF instead of the hard-coded one. Finally, the hard-coded address is
removed and USB DM support is enabled.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Lukasz Majewski <l.majewski@majess.pl>
Cc: Lukasz Majewski <l.majewski@samsung.com>
This patch adds the necessary OF alias for the UDC node, which let's
the code locate the DWC2 UDC base address in OF instead of hard-coding
it into the U-Boot binary. The code is adjusted to use the address from
OF instead of the hard-coded one. Finally, the hard-coded address is
removed and USB DM support is enabled.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Lukasz Majewski <l.majewski@majess.pl>
Cc: Lukasz Majewski <l.majewski@samsung.com>
This patch adds the necessary OF alias for the UDC node, which let's
the code locate the DWC2 UDC base address in OF instead of hard-coding
it into the U-Boot binary. The code is adjusted to use the address from
OF instead of the hard-coded one. Finally, the hard-coded address is
removed and USB DM support is enabled.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Lukasz Majewski <l.majewski@majess.pl>
Cc: Lukasz Majewski <l.majewski@samsung.com>
The Micrel PHY configuration is now done from OF, so hard-coding
the configuration into the board file is no longer necessary.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
The Micrel PHY configuration is now done from OF, so hard-coding
the configuration into the board file is no longer necessary.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
The Micrel PHY configuration is now done from OF, so hard-coding
the configuration into the board file is no longer necessary.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
The Micrel PHY configuration is now done from OF, so hard-coding
the configuration into the board file is no longer necessary.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
The Micrel PHY configuration is now done from OF, so hard-coding
the configuration into the board file is no longer necessary.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
LL_TEMAC is available at big endian MB and it is not properly tested
that's why the patch removes it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add ps7_init_gpl.c/h for the ZYBO board. This instance of the ps7_init
is generated by the Vivado 2015.3 tools using the system configuration
provided by Digilent located on their website.
Update the kconfig so that the defconfig is not overrided to use the
custom init ps7_init_gpl target by default.
Signed-off-by: Nathan Rossi <nathan@nathanrossi.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: "Sören Brinkmann" <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The driver is actually for the Designware DWC2 controller.
This patch renames the global s3c_udc.h header to dwc2_udc.h.
The rename is done automatically:
$ sed -i "s/s3c_udc\.h/dwc2_udc.h/g" \
`git grep "s3c_udc\.h" | cut -d : -f 1`
Signed-off-by: Marek Vasut <marex@denx.de>
The driver is actually for the Designware DWC2 controller.
This patch is the second and final to rename global symbol,
the s3c_udc_probe() function.
The rename is done automatically:
$ sed -i "s/s3c_udc_probe/dwc2_udc_probe/g" \
`git grep s3c_udc_probe | cut -d : -f 1`
Signed-off-by: Marek Vasut <marex@denx.de>
The driver is actually for the Designware DWC2 controller.
This patch is the first to rename global symbol, the struct
s3c_plat_otg_data.
The rename is done automatically:
$ sed -i "s/s3c_plat_otg_data/dwc2_plat_otg_data/g" \
`git grep s3c_plat_otg_data | cut -d : -f 1`
Signed-off-by: Marek Vasut <marex@denx.de>
LS1043ARDB Secure Boot Target from NOR has been added.
- Configs defined to enable esbc_validate.
- ESBC Address in header is made 64 bit.
- SMMU is re-configured in Bypass mode.
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
MC and debug server are not board-specific. Move reserving memory to SoC
file, using the new board_reserve_ram_top function. Reduce debug server
memory by 2MB to make room for secure memory.
In the system with MC and debug server, the top of u-boot memory
is not the end of memory. PRAM is not used for this reservation.
Signed-off-by: York Sun <yorksun@freescale.com>
DDR has been set as secure in MMU tables. Non-secure master such
as SDHC DMA cannot access data correctly. Mixing secure and non-
secure MMU entries requirs the MMU tables themselves in secure
memory. This patch moves MMU tables into a secure DDR area.
Early MMU tables are changed to set DDR as non-secure. A new
table is added into final MMU tables so secure memory can have
2MB granuality.
gd->secure_ram tracks the location of this secure memory. For
ARMv8 SoCs, the RAM base is not zero and RAM is divided into several
banks. gd->secure_ram needs to be maintained before using. This
maintenance is board-specific, depending on the SoC and memory
bank of the secure memory falls into.
Signed-off-by: York Sun <yorksun@freescale.com>
kylin board use rk3036 SOC, 512M sdram, 8G emmc.
This add some basic files required to allow the board
to output serial message and can run command(mmc info etc).
Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Create a soc.c file to put the code for soc special settings.
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch also expose the complete DDR region(s) to Linux.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
When creating phy-handle property, an unsigned int value is created by
fdt_create_phandle, and memcpy is used to get the value, since DTS is
big endian, the value cannot be used directly on little endian SoCs,
it should be converted by cpu_to_fdt32.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Support qspi flashes for mx7dsabresd
1. introduce pin mux settings
2. enable qspi clock
3. introduce related macro definitions
Default QSPI is not enabled, since we need hardware rework to use QSPI,
see SPF-28590, page 9:
"
QSPI signals are muxed with EPDC_D[7:0]
When using QSPI: de-populate R388-R391, R396-R399
populate R392-R395, R299, R300
"
After hardware rework, define CONFIG_FSL_QSPI in mx7dsabresd.h. qspi
flashes can be deteced and read/erase/write. Log info:
"
=> sf probe
SF: Detected MX25L51235F with page size 256 Bytes, erase size 64 KiB, total 64 MiB
=> sf read 0x80000000 0 0x4000000
device 0 whole chip
SF: 67108864 bytes @ 0x0 Read: OK
=> sf erase 0 0x4000000
SF: 67108864 bytes @ 0x0 Erased: OK
=> sf write 0x80000000 0 0x4000000
device 0 whole chip
SF: 67108864 bytes @ 0x0 Written: OK
"
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Adrian Alonso <aalonso@freescale.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Add dts and defconfig for h8homletv2 board.
H8Homlet Proto v2.0 Board is A83T Dev Board by Allwinner.
It has UART, ethernet, USB, HDMI, etc ports on it.
A83T patches are tested on this board.
Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Enabled support for AXP818 in SPL and u-boot.
DCDC1, DCDC2, DCDC3 and DCSC5 are enabled.
Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Allwinner A83T is octa-core cortex-a7 SOC.
This enables support for A83T.
SMP is not yet supported.
Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
These are currently dead codes. Until we have complete ACPI support,
we don't know if it works or not. Remove to avoid confusion.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
This Kconfig option name indicates it has something to do with cpu
socket, however it is actually not the case. Remove it and move
options inside it to NORTHBRIDGE_INTEL_IVYBRIDGE.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
There are some options which are never used, and also some options
which are selected by others but have never been a Kconfg option.
Clean these up.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Since commit 59370f3fcd ("net: phy: delay only if reset handler is
registered") Ethernet is no longer functional.
This commit does not have an issue in itself, but it revelead a problem
with the Ethernet initialization.
Fix this by calling enable_fec_anatop_clock() earlier and also
by adding a 10ms reset delay as recommended in the AR8031 datasheet.
Suggested-by: Jörg Krause <joerg.krause@embedded.rocks>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
- Enable DM_ETH by default for Zynq and ZynqMP
- Remove board_eth_init code
- Change miiphy_read function to return value instead of error code
based on DM requirement
- Do not enable EMIO DT support by default
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
The SR1500 board is a CycloneV based board, similar to the EBV
SoCrates, equipped with the following devices:
- SPI NOR
- eMMC
- Ethernet
Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Pavel Machek <pavel@denx.de>
The RPi has two different schemes for encoding board revision values.
When adding RPi 2 support, I thought that the conflicting type field
values were to be interpreted based on bcm2835-vs-bcm2836. In fact, the
scheme bit determines the encoding. The RPi Zero uses the bcm2835 yet
uses the new encoding scheme. Fix the code to cater for this correctly.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
There are two numbering schemes for the RPi revision values; old and new
scheme. The values within each scheme overlap. Hence, it doesn't make
sense to have absolute/global names for the revision IDs. Get rid of the
names and just use the raw revision/type values to set up the array of
per-revision data.
This change makes most sense when coupled with the next change. However,
it's split out so that the mechanical cut/paste is separate from the
logic changes for easier review and problem bisection.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
The following patch changed the PFUZE100 swbst register bit definitions
and broke PMIC configuration on multiple boards, at least on the novena
and gw_ventana. This patch fixes it.
commit 8fa46350a4
Author: Peng Fan <Peng.Fan@freescale.com>
Date: Fri Aug 7 16:43:45 2015 +0800
power: regulator: add pfuze100 support
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Peng Fan <Peng.Fan@freescale.com>
Cc: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Vagrant Cascadian <vagrant@aikidev.net>
Reviewed-by: Przemyslaw Marczak <p.marczak@samsung.com>
Tested-by: Vagrant Cascadian <vagrant@aikidev.net>
Reviewed-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Tim Harvey <tharvey@gateworks.com>
This add some basic files required to allow the board to dispaly
serial message and can run command(mmc info etc)
Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Moved board Kconfig fragment from previous patch into this one to fix
build error:
Signed-off-by: Simon Glass <sjg@chromium.org>
Series-changes: 8
- moved board Kconfig fragment from previous patch into this one
The board supports following features:
- Boot media support: SD card/e.MMC/SPI flash,
- Support LCD display (optional, disabled by default),
- Support ethernet,
- Support USB mass storage.
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
[fix checkpatch warnings]
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
DPMACx to PHY mapping for SGMII is mentioned as QSGMII.
So fix typo in README for QSGMII rise card.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: Change from ls2085aqds to ls2080aqds]
Reviewed-by: York Sun <yorksun@freescale.com>
Add support for the third USB controller for LS1043A.
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
LS1043AQDS Specification:
-------------------------
Memory subsystem:
* 2GByte DDR4 DIMM
* 128 Mbyte NOR flash single-chip memory
* 512 Mbyte NAND flash
* 16 Mbyte high-speed SPI flash
* SD connector to interface with the SD memory card
Ethernet:
* Two RGMII ports
* XFI 10G port
* SGMII
* QSGMII with 4x 1G ports
PCIe: supports Gen 1 and Gen 2
SATA 3.0: one SATA 3.0 port
USB 3.0: two micro AB connector and one type A connector
UART: supports two UARTs up to 115200 bps for console
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
[York Sun: Add CONFIG_SYS_NS16550=y in defconfig]
Reviewed-by: York Sun <yorksun@freescale.com>
Freescale's LS2085A is a another personality of LS2080A SoC with
support of AIOP and DP-DDR.
This Patch adds support of LS2085A Personality.
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: Updated MAINTAINERS files
Dropped #ifdef in cpu.h
Add CONFIG_SYS_NS16550=y in defconfig]
Reviewed-by: York Sun <yorksun@freescale.com>
LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP
personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc.
So renaming existing LS2085A code base to reflect LS2080A (Prime personality)
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: Dropped #ifdef in cpu.c for cpu_type_list]
Reviewed-by: York Sun <yorksun@freescale.com>
Freescale's DPAA2 ethernet driver depends upon the static DPL for the
DPRC, DPNI, DPBP, DPIO objects.
Instead of static objects, Create DPNI, DPBP, DPIO objects at run-time.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Print function name along with SerDes Protocol during SerDes Protocol
not supported error.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This board was constantly parasiting on the CV SoCDK, so split it
into it's own separate directory. Moreover, the board config was
missing important bits, like simple-bus support in SPL, the DRAM
configuration was incorrect and the DTS was also missing the pre
reloc bits.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefan Roese <sr@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Dinh Nguyen <dinh.linux@gmail.com>
Cc: Jan Viktorin <viktorin@rehivetech.com>
In preparation of some new Liebherr boards to be added soon, a new
"liebherr" vendor directory gets created, and the "lwmon5" board
directory is moved into this new vendor directory.
cc: Stefan Roese <sr@denx.de>
Signed-off-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Stefan Roese <sr@denx.de>
This patch add ZyXEL NSA310S 1-Bay Media Server
The ZyXEL NSA310S device is a Kirkwood based NAS:
- SoC: Marvell 88F6702 1000Mhz
- SDRAM memory: 256MB DDR2 400Mhz
- Gigabit ethernet: PHY Marvell 88E1318
- Flash memory: 128MB
- 1 Power button
- 1 Power LED (blue)
- 4 Status LED (green)
- 1 Copy/Sync button
- 1 Reset button
- 1 SATA II port
- 2 USB 2.0 ports (front and back)
- Smart fan
Signed-off-by: Gerald Kerma <dreagle@doukki.net>
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Signed-off-by: Luka Perkov <luka.perkov@sartura.hr>
Add board_usb_phy_mode function for detecting whether a port is
being used as host or client using a GPIO. On Colibri Vybrid we
provide GPIO 102 for this very same purpose.
Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
Congatec has several MX6 boards based on quad, dual, dual-lite and solo.
Add SPL support so that all the variants can be supported
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
The lamobo-r1 board, sometimes called the BPI-R1 but not labelled as such
on the PCB, is meant as a A20 based router board. As such the board comes
with a built-in switch chip giving it 5 gigabit ethernet ports, and it
has a large empty area on the pcb with mounting holes which will fit a
2.5 inch harddisk. To complete its networking features it has a
Realtek RTL8192CU for WiFi 802.11 b/g/n.
The dts file is identical to the one submitted upstream.
Signed-off-by: Jelle de Jong <jelledejong@powercraft.nl>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Based on existing A23/A33 code and the original H3 boot0.
Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Add initial sun8i H3 support, only uart + mmc are supported for now.
Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This patch makes the 2nd DRAM bank available on Juno only and not on
other vexpress64 targets, eg. the FVP models.
The commit below added a 2nd bank of NOR flash for Juno, but also for
all vexpress64 targets:
commit 2d0cee1ca2
Author: Liviu Dudau <Liviu.Dudau@foss.arm.com>
Date: Mon Oct 19 11:08:31 2015 +0100
vexpress64: Juno: Declare all 8GB of RAM and make them visible to the kernel.
Juno comes with 8GB RAM, but U-Boot only passes 2GB to the kernel.
Declare a secondary memory bank and set the sizes correctly.
Signed-off-by: Liviu Dudau <Liviu.Dudau@foss.arm.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Unfortunately, I only fully tested on Juno R0, R1 and the FVP Foundation
model. Whilst FVP Base AEMV8 models run U-Boot OK, they fail to boot
the kernel.
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Acked-by: Liviu Dudau <liviu.dudau@foss.arm.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Only compile in PCIe support if the board really uses it. Provide
a __weak stub for the init function if e.g. FVP is being built.
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
On a Juno r1 the PCI controller init routine outputs the rather boring
ATR entry information.
Do this only with DEBUG defined to avoid cluttering the user's
terminal.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Ryan Harkin <ryan.harkin@linaro.org>
This rewrite uses lately promoted eeprom_init(int) function to choose the
right I2C bus when writing data to the EEPROM.
Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Heiko Schocher <hs@denx.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
The WAKEUP_X pins are always an input no matter the pinmux mode.
However, the 18th bit that typical configures a pin as an input is
considered reserved for the WAKEUP_X pins. Therefore, for any WAKEUP
pin remove any configuration that sets that pin as an input. Since
those pins are only inputs remove any output configuration from those
pins.
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Unify serial_omap, and use the generic binding.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Tom Rini <trini@konsulko.com>
Acked-by: Simon Glass <sjg@chromium.org>
The console includes a global variable and several functions that are only
used by a small subset of U-Boot files. Before adding more functions, move
the definitions into their own header file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Add support for the German keymap, taken from i8042.c. This can be selected
when the input library it initialised.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Add a sandbox timer which get time from host os and a basic
test.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Reviewed-by: Simon Glass <sjg@chromium.org>
Require the caller to add the keycode translation tables separately so that
it can select which ones to use. In a later patch we will add the option to
add German tables.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This board uses the same CPU (8309) as VECT1. The memory however is
different since it has NAND Flash, the NOR Flash partitioning is
different and of course the FPGAs as well.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Christoph Dietrich <christoph.dietrich@keymile.com>
Setting dip_switch 3 and 4 also will run bootloader in COGE3 and COGE6
It is required remove local mgmt IP address, when DIP Switch PIN3 is
enabled. DIP Switch 4 also enabled to avoid u-boot update in future
for DIP switch enhancements.
Signed-off-by: Bagavathiannan Palanisamy <Bagavathiannan.Palanisamy@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
commit 0a4f88b98 removed the usage of our setports function, but the
function itself were not removed. So toss it it's dead code.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
We use CONFIG_OF_LIBFDT and CONFIG_OF_BOARD_SETUP on all our powerpc
targets, so there is no need to check these defines within our C code.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
On mgcoge3ne we also want to start the test application if the testpin
is asserted. But we don't have a full POST test support yet. So simply
add a function to read the testpin value.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
The get_pin and set_pin funciton was only used for pins on Port D and
therefore the value was hard coded in the function. Enhance this with a
parameter, that we are able to use this functions for other ports too.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
This board is similar to TUXX1, but it has differend FPGAs.
Signed-off-by: Christoph Dietrich <christoph.dietrich@keymile.com>
Signed-off-by: Andreas Huber <andreas.huber@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Search for the kernel and DTBs in a folder named PRODUCTNAME (found in the IVM)
at the TFTP server instead of the u-boot boardname.
Signed-off-by: Tobias Müller <Tobias.Mueller@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
When loading the dtb file via tftp we should load the one which matches
boardId and hwKey and not a common one for the boardname. We have boards
were different hwKeys are used and then we may load an incorrect dtb
file. If no fdt_bid_kwkey.dtb file is not a fallback to boardname.dtb is used.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Tobias Müller <Tobias.Mueller@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
There was a small typo for KM_COGE5UN that resulted in the dip switch
not to behave as expected.
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Similar to kmcoge5un we need to check the dip switch at startup
connected to the kirkwood at MPP43. If it's set we need to set the
actual_bank to zero to boot from SW bank zero. Additional to kmcoge5un
we need to check also the pin in misc_init to decide wether we wait for
the ne to start or not. If the dip_switch is set we don't wait and
continue immediately.
Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Configure PHY LED register for Marvell 88E1118R PHY used on PIGGY3 to
match with printed descriptions on PCB
Signed-off-by: Tobias Müller <Tobias.Mueller@keymile.com>
Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
[trini: Fix typo, CRTL_PAGE -> CTRL_PAGE]
Signed-off-by: Tom Rini <trini@konsulko.com>
SeeedStudio BeagleBone Green (BBG) is clone of the BeagleBone Black (BBB) minus
the HDMI port and addition of two Grove connectors (i2c2 and usart2).
This board can be identified by the 1A value after A335BNLT (BBB) in the at24 eeprom:
1A: [aa 55 33 ee 41 33 33 35 42 4e 4c 54 1a 00 00 00 |.U3.A335BNLT....|]
http://beagleboard.org/greenhttp://www.seeedstudio.com/wiki/Beaglebone_green
In Mainline Kernel as of:
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=79a4e64c679d8a0b1037da174e4aea578c80c4e6
Patch tested on BeagleBone Black (rev C) and BeagleBone Green (production model)
Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
CC: Tom Rini <trini@konsulko.com>
CC: Jason Kridner <jkridner@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
CM-T3517 has several HW revisions.
Add board specific get_board_rev() callback to retrieve revision number.
Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
Reviewed-by: Igor Grinberg <grinberg@compulab.co.il>
Use spl alternate boot device feature to define fallback to
the main boot device as it is defined by hardware.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
BeagleBoard X15 (http://beagleboard.org/x15) support in u-boot does
actually support two different platform configuration offered by
TI. In addition to BeagleBoard X15, it also supports the TMDXEVM5728
(or more commonly known as AM5728-evm).
Information about the TI AM57xx EVM can be found here
http://www.ti.com/tool/tmdxevm5728
The EVM configuration is 1-1 compatible with BeagleBoard X15 with the
additional support for mPCIe, mSATA, LCD, touchscreen, Camera, push
button and TI's wlink8 offering.
Hence, we rename the beagle_x15 directory to am57xx to support TI
EVMs that use the AM57xx processor. By doing this we have common code
reuse. This sets the stage to have a common u-boot image solution for
multiple TI EVMs such as that already done for am335x and am437x. This
sets the stage for upcoming multiple TI EVMs that share the same code
base.
NOTE: Commit eae7ae1853 ("am437x: Add am57xx_evm_defconfig using
CONFIG_DM") introduced DT support for beagle_x15 under am57xx_evm
platform name. However, this ignored the potential confusion arising for
users as a result. To prevent this, existing beagle_x15_defconfig is
renamed as am57xx_evm_nodt_defconfig to denote that this is the "non
device tree" configuration for the same platform. We still retain
am57xx-beagle-x15.dts at this point, since we just require the common
minimum dts.
As a result of this change, users should expect changes in build
procedures('make am57xx_evm_nodt_defconfig' instead of 'make
beagle_x15_defconfig'). Hopefully, this would be a one-time change.
Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
Signed-off-by: Schuyler Patton <spatton@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Instead of allocating space in the driver for the serdes
specification table, just allow the board file to set a pointer
to it. Also, allow the board to only specify the lanes that are
used instead of including unused lanes.
Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Acked-by: Stefan Roese <sr@denx.de>
Cc: Dirk Eibach <eibach@gdsys.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
A lot of extra configuration information was left over in the
Marvell serdes and DDR3 initialization code for boards that
U-boot does not support. Remove this extra config information,
and the concept of fixing up board topologies with information
loaded from an EEPROM. If this needs to be done, it should be
handled in the board file, not in core code.
Signed-off-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Acked-by: Stefan Roese <sr@denx.de>
Cc: Dirk Eibach <eibach@gdsys.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
With this change Synopsys DesignWare SDP board is switched to driver
model for both serial port (serial_dw) and Ethernet (Designware GMAC).
This simplifies include/configs/axs101.h and allows for reuse of Linux's
Device Tree description.
For simplicity Linux's .dts files are not blindly copied but only very
few extracts of them are really used (those that are supported in U-Boot
at the moment).
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Add the following splash locations to cm-fx6:
* filesystem formatted mmc
* filesystem formatted usb
* filesystem formatted sata
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Tom Rini <trini@konsulko.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Add support for loading splash image from an SD card formatted with
a filesystem. Update boards to maintain original behavior where needed.
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Tom Rini <trini@konsulko.com>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
-> Add National instrument ethernet transceiver configuration used (DP83848)
-> Change cpsw slave phy address
-> modify nand configuration to use the correct ECC and correct nand features
- i2c addresses for the videoboard port expanders were
wrong.
- the fpga reset signal was not initialized.
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
The gdsys strider board is based on a Freescale MPC8308 SOC.
It boots from NOR-Flash, kernel and rootfs are stored on
SD-Card.
On board peripherals include:
- 1x 10/100 Mbit/s Ethernet (optional)
- Lattice ECP3 FPGA connected via eLBC
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
[trini: Drop setting CONFIG_SYS_GENERIC_BOARD, this is always true now]
Signed-off-by: Tom Rini <trini@konsulko.com>
DP501 only supports DP 1.1a.
Limit settings for link bandwidth and lane count to
values allowed by DP 1.1a.
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
With Club 3D dual link adapter there are AUX-channel timeouts
when EDID is read. Increasing retry interval time to max (400us)
fixes this.
Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Reviewed-by: Heiko Schocher <hs@denx.de>
On the BeagleBone these i2c1 pins are routed to the expanasion header, where
they can be defined as either pr1_usart0_Xxd/pwm0/spi0/i2c1, dont assume i2c1
Fixes: https://e2e.ti.com/support/arm/sitara_arm/f/791/p/313894/1387696
Signed-off-by: Robert Nelson <robertcnelson@gmail.com>
Reported-by: Matthijs van Duin <matthijsvanduin@gmail.com>
CC: Tom Rini <trini@konsulko.com>
Since we don't have for sure a valid IP-setup during
board_late_init(...) because it maybe allready stored in environment or
not, we cannot form a proper vxWorks bootline at this place.
So we move to the way, forming the bootline just before
executing/launching vxWorks. To do this we use the bootvx command
instead go.
We only have to form the "othbootargs" environment variable, the rest is
done pretty good by the "bootvx" commannd.
Signed-off-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Support LCDIF for mx7dsabresd board:
1. Add pinmux settings
2. Add VIDEO related macro definition and videomode env settings.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Adrian Alonso <aalonso@freescale.com>
Support lcdif display:
1. Add pinmux and pad settings for LCDIF
2. Introduce setup_lcd to do the settings for LCDIF
3. Enable VIDEO related macros in board header files
4. Add a new env videomode which is needed by mxsfb.c. The
settings for videomode in this patch is for TFT43AB.
5. Tested on mx6ul 14x14/9x9 evk.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
board_mxsfb_system_setup must be renamed mxsfb_system_setup.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
There is really no need to provide an empty reset_cpu() implementation,
so just remove it.
Cc: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Tim Harvey <tharvey@gateworks.com>
There is really no need to provide an empty reset_cpu() implementation,
so just remove it.
Cc: Christian Gmeiner <christian.gmeiner@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Christian Gmeiner <christian.gmeiner@gmail.com>
There is really no need to provide an empty reset_cpu() implementation,
so just remove it.
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
There is really no need to provide an empty reset_cpu() implementation,
so just remove it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Enable the GPU node in the system-wide ft_system_setup() hook instead of
the board-specific ft_board_hook(). This allows us to enable GPU per SoC
generation instead of per-board as we did initially.
Reported-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
p2371-2180 has two PCI ports; a regular x4 slot and a x1 M.2 slot. This
patch adds the relevant DT to enable the PCI controller and configure
the XUSB padctl pin muxing, and code to turn on the PCI power and enable
PCI features in U-Boot. I have only tested the x4 slot.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
ls1043ardb_nand_defconfig and ls1043ardb_sdcard_defconfig are missing
in the MAINTAINERS file, so add them for completeness.
Reported-by: Albert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
A few config files have been added without updating MAINTAINERS.
Reported-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Tom Rini <trini@konsulko.com>
In 522b021 we dropped 'PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4)' lines in
the mpc85xx linker scripts as this is not required and breaks newer
binutils. This commit cleans up the rest of the powerpc linker scripts.
Signed-off-by: Tom Rini <trini@konsulko.com>
A few config files have been added without updating MAINTAINERS.
Reported-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
Signed-off-by: Tom Rini <trini@konsulko.com>
After consulting with some of the SPDX team, the conclusion is that
Makefiles are worth adding SPDX-License-Identifier tags too, and most of
ours have one. This adds tags to ones that lack them and converts a few
that had full (or in one case, very partial) license blobs into the
equivalent tag.
Cc: Kate Stewart <kstewart@linuxfoundation.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Revert commit 7a2c1b13 which dropped OpenRD boards.
Assume maintainership of OpenRD.
Remove OpenRD from scrapyard.
Switch OpenRD to generic board.
Switch to Thumb build.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
This board runs a P5020 or P5040 chip, and utilizes
an EEPROM with similar formatting to the Freescale P5020DS.
Large amounts of this code were developed by
Adrian Cox <adrian at humboldt dot co dot uk>
Signed-off-by: Andy Fleming <afleming@gmail.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Remove zc70x target which was one setting for zc702 and zc706.
Currently zc702 and zc706 are separated.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
When detecting SDHC Adapter Card Type 2(SD/MMC Legacy Adapter Card),
enable EVDD automatic control via SDHC_VS. This could support SD card
IO voltage switching for UHS-1 speed mode.
Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
If adapter card type identification is supported for platform, we would
enable dat[4:7] for eMMC4.5 Adapter Card.
Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
qe-tdm is muxed with diu, if hwconfig setted as qe-tdm,
assign muxed pins to qe-tdm, then delete diu node from
device tree.
Signed-off-by: Zhao Qiang <qiang.zhao@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch will fix these checkpatch issues.
CHECK: Alignment should match open parenthesis
+ printf("Enter: %s %s\n", mode_name[mode][0],
+ mode_info[mode]);
CHECK: Alignment should match open parenthesis
+ lcd_printf("\n\n\t%s %s\n", mode_name[mode][0],
+ mode_info[mode]);
CHECK: Alignment should match open parenthesis
+ lcd_printf("\t%s %s - %s\n\n", selection[i],
+ mode_name[i][0],
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch will fix these checkpatch issues.
+static const char *mmc_regulators[] = {
CHECK: Blank lines aren't necessary before a close brace '}'
+
+}
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This patch will fix these checkpatch issues.
ERROR: spaces required around that '==' (ctx:VxV)
+#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */
ERROR: spaces required around that '==' (ctx:VxV)
+#elif FCLK_SPEED==1 /* Fout = 202.8MHz */
ERROR: spaces required around that '==' (ctx:VxV)
+#if USB_CLOCK==0
ERROR: spaces required around that '==' (ctx:VxV)
+#elif USB_CLOCK==1
CHECK: spaces required around that ':' (ctx:VxV)
+ "bne 1b":"=r" (loops):"0" (loops));
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This commit adds additional file with implementation of board
detection code for Odroid-XU3/XU4.
The detection depends on compatible found in fdt:
- "samsung,exynos5" - uses Exynos5 generic code
- "samsung,odroidxu3" - try detect XU3 revision
There are few revisions of Odroid XU3/XU4, each can be detected
by checking the value of channel 9 of built-in ADC:
Rev ADC Board
0.1 0 XU3 0.1
0.2 372 XU3 0.2 | XU3L - no DISPLAYPORT
0.3 1280 XU4 0.1
The detection code depends on the ADC+10% value.
Implementation of functions:
- set_board_type() - read ADC and set type
- get_board_rev() - returns board revision: 1..3
- get_board_type() - returns board type string
Additional functions with return values of bool:
- board_is_generic() - true if found compatible "samsung,exynos5"
but not "samsung,odroidxu3"
- board_is_odroidxu3() - true if found compatible "samsung,odroidxu3"
and one of XU3 revision.
- board_is_odroidxu4() - true if found compatible "samsung,odroidxu3"
and XU4 revision.
After I2C controller init, the get_board_type() can check
if the XU3 board is a "Lite" variant, by probing chip
0x40 on I2C0 (INA231 - exists only on non-lite).
This is useful for setting fdt file name at misc_init_r().
Enabled configs:
- CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
- CONFIG_ODROID_REV_AIN
- CONFIG_REVISION_TAG
- CONFIG_BOARD_TYPES
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
The function get_board_type() is called in two places by common code,
but the returned pointer was never check.
This commit adds checking the returned pointer, before use it.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
It will take more than 1s when wake up from deep sleep. Most of the
time is spent on outputing information. This patch reduced the deep
sleep latency by:
1. avoid outputing system informaton
2. remove flush cache after DDR restore
3. skip reloading second stage uboot binary when SD boot
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
The ITS bit was being read incorrectly beacause of operator
precedence. The same ahs been corrected.
Signed-off-by: Lawish Deshmukh <lawish.deshmukh@freescale.com>
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Add i.MX6DQP-Sabresd board support:
1. set fdt_file according to board_rev which is set at runtime.
2. Add mx6dqp_ddr_ioregs and calibration value for this board.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
setting the gpr 1,8 and 12 registers to a fix value.
This is needed because after a WDT reset, this registers
are not correct resettet, and prevent linux from booting
again.
Signed-off-by: Heiko Schocher <hs@denx.de>
Freescale ARM-based Layerscape LS102xA contain a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds SATA feature on ls1021aqds and ls1021atwr boards.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch adds esdhc support for ls1043ardb.
Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
LS1043ARDB Specification:
-------------------------
Memory subsystem:
* 2GByte DDR4 SDRAM (32bit bus)
* 128 Mbyte NOR flash single-chip memory
* 512 Mbyte NAND flash
* 16 Mbyte high-speed SPI flash
* SD connector to interface with the SD memory card
Ethernet:
* XFI 10G port
* QSGMII with 4x 1G ports
* Two RGMII ports
PCIe:
* PCIe2 (Lanes C) to mini-PCIe slot
* PCIe3 (Lanes D) to PCIe slot
USB 3.0: two super speed USB 3.0 type A ports
UART: supports two UARTs up to 115200 bps for console
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
There are two LS series processors are built on ARMv8 Layersacpe
architecture currently, LS2085A and LS1043A. They are based on
ARMv8 core although use different chassis, so create fsl-layerscape
to refactor the common code for the LS series processors which also
paves the way for adding LS1043A platform.
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
The fsl_dtsec.h & fsl_tgec.h & fsl_fman.h can be shared on both ARM
and PPC, move it out of ppc to include/, and change the path in
drivers accordingly.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Config Security Level Register is different between different SoCs,
so put the CSL register definition into the arch specific directory.
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
For the Chain of Trust, the esbc_validate command supports
32 bit fields for location of the image. In the header structure
definition, these were declared as pointers which made them
64 bit on a 64 bit core.
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This board has not compiled for me for quite some time due to size
constraints, remove.
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This board has not compiled for me for quite some time due to size
constraints, remove.
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This board has not compiled for me for quite some time due to size
constraints, remove.
Cc: Stefan Roese <sr@denx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
This board has not compiled for me for quite some time due to size
constraints, remove.
Cc: John Otken <jotken@softadvances.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Stefan Roese <sr@denx.de>
As QSPI and IFC are pin-multiplexed on LS1021A, only IFC is supported in
SD boot now. For the customer's demand, QSPI needs to be supported in SD
boot too.
This patch adds QSPI or IFC support in SD boot according to the
corresponding defconfig. For detail, ls1021atwr_sdcard_ifc_defconfig is
used to support IFC in SD boot and ls1021atwr_sdcard_qspi_defconfig is
used to support QSPI in SD boot.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
In the "Getting Started with Coccinelle - KVM edition" presentation that
has been held by Julia Lawall at the KVM forum 2015 (see the slides at
http://events.linuxfoundation.org/sites/events/files/slides/tutorial_kvm_0.pdf),
she pointed out some bad return value checks in U-Boot that can be
detected with Coccinelle by using the following config file:
@@
identifier x,y;
identifier f;
statement S;
@@
x = f(...);
(
if (x < 0) S
|
if (
- y
+ x
< 0) S
)
This patch now fixes these issues.
Signed-off-by: Thomas Huth <huth@tuxfamily.org>
Add CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG support and enable it to set
'board_rev' and 'board_name' envs.
'board_rev' can be used in scripts to determine what board we are running on
and 'board_name' for pretty printing.
Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Convert altera sysid to driver model with misc uclass.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Chin Liang See <clsee@altera.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Convert altera_pio to driver model.
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Chin Liang See <clsee@altera.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
As altera_pio_init() uses BSS, it should be moved to
board_early_init_r().
Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Marek Vasut <marex@denx.de>
Currently omap_hsmmc driver doesn't use sdcd pin to detect
whether the card is present or not. Instead the same pin is used
as GPIO to detect card presence. So change the pin mux mode from
mmc0_sdcd to gpio0_6.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Add MMC support for k2g
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Tested-by: Mugunthan V N <mugunthanvnm@ti.com>
Add Ethernet support for tftp support
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Phy mode is a board property and it can be different between
multiple board and ports, so it should not be hardcoded in
driver to one specific mode. So adding a field in eth_priv_t
structure to pass phy mode to driver.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Add clock information for Galileo
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Prepare board file so that ethernet registration are
commented for DM conversion
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Since there is a common function to grab the serial number from the die id bits,
it makes sense have one to parse that serial number and feed it to the serial
ATAG.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
This introduces omap_die_id_display to display the full die id.
There is no need to store it in an environment variable, that no boot script
is using anyway.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
Now that we have a common prototype to grab the omap die id, functions to figure
out a serial number and usb ethernet address can use it directly.
Those also get an omap_die_id prefix for better consistency.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
This introduces omap5 support for omap_die_id, which matches the common
omap_die_id definition. It replaces board-specific code to grab the die id bits.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
This introduces omap4 support for omap_die_id, which matches the common
omap_die_id definition. It replaces board-specific code to grab the die id bits.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
This replaces the previous get_dieid definition with omap_die_id, that matches
the common omap_die_id definition.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
board_name environment variable was not getting set correctly for Pandaboard A4 and ES
Signed-off-by: David Batzle <dbatzle@dcbcyber.com>
CC: Albert Aribaud <albert.u.boot@aribaud.net>; Tom Rini <trini@ti.com>; Peter Robinson <pbrobinson@gmail.com>
The C.H.I.P. is a small SBC with an Allwinner R8, 8GB of NAND, 512MB of
RAM, USB host and OTG, a wifi / bluetooth combo chip, an audio/video jack
and two connectors to plug additional boards on top of it.
The DT is identical to the DT submitted to the upstream kernel.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Not all sunxi boards have an MMC embedded. Switching to the Kconfig option
will allow to enable or disable the support in each boards' defconfig.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The Sinovoip BPI-M2 is a SBC board based on the A31s SoC it features
1G RAM, a microsd slot, Gbit ethernet, 4 usb-a USB-2 ports, ir receiver,
stereo headphone jack and hdmi video output.
The dts changes are identical to the dts files submitted upstream.
A few notes on the use if dldo and aldo regulators. DLDO1 is used
for Vdd for the ethernet phy, ALDO2 is used for AVdd for the ethernet
phy. ALDO1 is used to power the sdio wifi module.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Stop prefixing the axp functions for setting voltages, etc. with the
model number, there ever is only one pmic driver built into u-boot,
this allows simplifying the callers.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
On boards with axp221/223 pmic-s we already allow configuring most
voltages. Make the Kconfig options for these also apply to boards with
axp152 / axp209 pmic-s and extend them to configure all voltages.
The Kconfig defaults are chosen so that this commit does not introduce any
functional changes.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
We now have generic q8_a?3_defconfig files for Q8 formfactor tablets with
an A13 / A23 / A33 SoC, there is no need for these PCB variant specific
defconfig-s and they only serve to confuse the user.
Note that in case of the forfun_q88db_defconfig and TZX-Q8-713B7_defconfig
for A13 based Q8 tablets there is not even a dts file for these in the
upstream kernel, which is all the more reason to remove them.
The generic q8_a?3_defconfig files have been tested on an Et_q8_v1_6,
Ippo_q8h_v1_2_a33_1024x600, Ippo_q8h_v1_2 and TZX-Q8-713B7 tablet, and the
forfun_q88db_defconfig is identical to q8_a13_tablet_defconfig.
This leaves only the Ippo_q8h_v5 untested with the new generic defconfigs
but there is no reason to assume that it will not work.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Select CONFIG_SPL_STACK_R for sunxi boards, this gives us much more
room on the stack once we've the DRAM running.
Besides being a good change to have on itself, this also paves the
way for switching to using malloc_simple in the SPL which cuts of
close to 4KiB of the SPL size.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Between v2015.07-rc1 and v2015.07-rc2 this board started
silent boot failure. A bisect led to commit 6eed3786c6
("net: Move the CMD_NET config to defconfigs"). This commit
looks harmless in itself, but it did implicitly add a feature
to the image which led to this:
u-boot$git describe 6eed3786c6
v2015.07-rc1-412-g6eed3786c68c
^^^
u-boot$ls -l ../41*/u-boot.bin
-rwxrwxr-x 1 paul paul 261476 Oct 16 16:47 ../411/u-boot.bin
-rwxrwxr-x 1 paul paul 266392 Oct 16 16:43 ../412/u-boot.bin
u-boot$bc
bc 1.06.95
Copyright 1991-1994, 1997, 1998, 2000, 2004, 2006 Free Software Foundation, Inc.
This is free software with ABSOLUTELY NO WARRANTY.
For details type `warranty'.
256*1024
262144
i.e. we finally broke through the 256k monitor size. Jump it
up to 384k and fix the hard coded value used in the env offset
at the same time.
We were probably flirting with the 256k size issue without
knowing it when testing on different baselines in earlier
commits, but since this is all board specific, a rebase or
reorder to put this commit 1st is of little value.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Juno R1 has an XpressRICH3 PCIe host bridge that needs to be initialised
in order for the Linux kernel to be able to enumerate the bus. Add
support code here that enables the host bridge, trains the links and
sets up the Address Translation Tables.
Signed-off-by: Liviu Dudau <Liviu.Dudau@foss.arm.com>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
[trini: Always declare vexpress64_pcie_init and continue handling logic
inside the function]
Signed-off-by: Tom Rini <trini@konsulko.com>
Juno comes with 8GB RAM, but U-Boot only passes 2GB to the kernel.
Declare a secondary memory bank and set the sizes correctly.
Signed-off-by: Liviu Dudau <Liviu.Dudau@foss.arm.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Ryan Harkin <ryan.harkin@linaro.org>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Upon further review when populating README.scrapyard, d2net_v2 is a
variant on net2big_v2 and not just an orphan config. To help in the
future also add this to board/LaCie/net2big_v2/MAINTAINERS which needed
a little consolidation anyhow.
This reverts commit 1363740e79.
Cc: Simon Guinot <simon.guinot@sequanux.org>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Seen this one in the wild. Is labelled "Raspberry Pi Model A+ V1.1,
(C) Raspberry Pi 2014". A standard A+ board, much like the one with
version 0x12, didn't notice any differencies.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
On keystone2 Lamarr and Edison platforms, the PA clocksource
mux in PLL REG1, can be changed only after enabling its clock
domain.
So selecting the output of PASS PLL as input to PA only after
enabling the clockdomain.
This is as per the debug done by "Vitaly Andrianov <vitalya@ti.com>"
and based on the previous work done by "Hao Zhang <hzhang@ti.com>"
Fixes: d634a0775bcf ("ARM: keystone2: Cleanup PLL init code")
Reported-by: Vitaly Andrianov <vitalya@ti.com>
Tested-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This commit fixes a typo in vf610twr DRAM init that was causing a hang in
U-Boot for the Vybrid Tower. This typo was introduced in commit 3f353cecc
(vf610: refactor DDRMC code).
Signed-off-by: Anthony Felice <tony.felice@timesys.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Commit 3f353cecc ("vf610: refactor DDRMC code") changed the original
bstlen field from 3 to 0.
Restore the original value for proper behaviour.
Based on the patch from Anthony Felice <tony.felice@timesys.com>
for the vf610twr board.
Reported-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
According to ARM PrimeCell PL175 documentation WAIT_OEN config value
is defined without any additional clocks added to the value set by a
client, the change fixes the wrong interface to WAIT_OEN config.
The change also touches a single user of LPC32xx EMC and corrects
configured "output enable delay" value on its side according to the
changed interface.
No functional change intended.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
This platform has not gone into production. So lets remove it.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Add CONFIG_SYS_GENERIC_BOARD to lwmon5.h and CONFIG_DISPLAY_BOARDINFO
to Kconfig file.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
This reverts commit 8fe11b8901.
I'll add support to lwmon5 in the next patch and will remove
support for the broken lcd4_lwmon5 as well.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Create an additional FVP configuration to boot images pre-loaded into
DRAM.
Sometimes it's preferential to boot the model by loading the files
directly into DRAM via model parameters, rather than using
SemiHosting.
An example of model parmaters that are used to pre-load the files
into DRAM:
--data cluster0.cpu0=Image@0x80080000 \
--data cluster0.cpu0=fvp-base-gicv2-psci.dtb@0x83000000 \
--data cluster0.cpu0=uInitrd@0x84000000
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
[trini: Update board/armltd/vexpress64/Kconfig logic]
Signed-off-by: Tom Rini <trini@konsulko.com>
The FVP and Juno settings were identical, but duplicated, so I removed
the duplication with this patch.
Signed-off-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
[trini: Adjust logic to keep if/endif in the file]
Signed-off-by: Tom Rini <trini@konsulko.com>
It turned out with some boards (FPGA firmwares?) and cards combos
current clock settings doesn't work as expected leading to strange
card freezes or corrupted data being read from the card.
Especially this was seen with Transcend 2Gb cards shipped as a part of
ARC SDP:
----------------->8---------------
AXS# mmcinfo
Device: Synopsys Mobile storage
Manufacturer ID: 74
OEM: 4a60
Name: SDC
Tran Speed: 50000000
Rd Block Len: 512
SD version 3.0
High Capacity: No
Capacity: 1.8 GiB
Bus Width: 4-bit
Erase Group Size: 512 Bytes
AXS# fatload mmc 0
** Unrecognized filesystem type **
----------------->8---------------
With this change that problem is fixed.
Note "Tran Speed" above doesn't match clock value set in DW MMC.
It is max value for card's speed class.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
The 7" Q8 tablet enclosure is used for a ton of slightly different cheap
chinese tablets. There are some differences in which accelerometer /
wifi is used, but other then that these are all the same from a u-boot /
kernel pov.
When we get to adding accelerometer support the plan is to add some kind
of autodetection and mangle the dt accordingly (likely using the new quirks
mechanism).
For now this is a non issue as we do not yet have accelerometer
support, and in the future, some sort of auto-detect is the way to go
as we cannot expect users to exactly know what is inside their tablet.
The dts files this commit adds are identical to the ones submitted
to the upstream kernel.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
In order to avoid any assumptions about any device connected to
P2371-2180's expansion connector, the latest pinmux spreadsheet
configures all muxable pins on that connector to be GPIO inputs, with
on-chip pulls where appropriate.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
The VF610 DDRMC driver code contains settings which are
board-specific. Move these out to boards so that new boards
can define their own without having to modify the driver.
Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
The 7" Q8 tablet enclosure is used for a ton of slightly different cheap
chinese tablets. There are some differences in which accelerometer /
wifi is used, but other then that these are all the same from a u-boot /
kernel pov.
When we get to adding accelerometer support the plan is to add some kind
of autodetection and mangle the dt accordingly (likely using the new quirks
mechanism).
For now this is a non issue as we do not yet have accelerometer
support, and in the future, some sort of auto-detect is the way to go
as we cannot expect users to exactly know what is inside their tablet.
The dts[i] files this commit adds are identical to the ones submitted
to the upstream kernel.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
This patch extends the misc_init_r() function on sunxi boards
to test for the presence of a suitable "sunxi" SPL header. If
found, and the loader ("fel" utility) provided a non-zero value
for the boot.scr address, then the corresponding environment
variable fel_scriptaddr gets set.
misc_init_r() also sets (or clears) the "fel_booted" variable depending
on the active boot device, using the same logic as spl_boot_device().
The goal is to provide sufficient information (within the U-Boot
environment) to make intelligent decisions on how to continue the boot
process, allowing specific customizations for the "FEL boot" case.
Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
We only prefix the board defconfig name with the SoC if the SoC is part
of the official board-name, such as with Olimex OLinuxIno boards, for the
Wobo i5 this is not the case so remove the A10s prefix from the defconfig
filename.
Also fix the double listing of A10s-OLinuXino-M_defconfig in MAINTAINERS
which the original Wobo i5 addition commit introduced.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Use DM for the pl01x serial driver on hikey. Also allow UART0 or
UART3 to be chosen via Kconfig.
By default we now output to UART3 as the latest version of ATF outputs
to this UART. Also UART3 comes out on the LS connector, as opposed to
UART0 which goes to a unpopulated header.
As part of this change we also enable CONFIG_BOARD_EARLY_INIT_F and
call the pinmux configuration code for the UART. Before we were
relying on ATF having already configured the pin configuration.
NB: Upstream Linux kernel doesn't yet support UART3, so serial console
will still be output on UART0 when booting a upstream kernel.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
This causes exceptions and other strange behaviour
when enabling CONFIG_SYS_MALLOC_F_LEN which is required to
migrate the serial driver over to DM_SERIAL.
As GD_FLG_FULL_MALLOC_INIT flag gets reset, after relocation
we don't end up using the full malloc which ultimately ends up
causing a synchronus abort.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Rather than relying on an external URL in the README
include the Makefile in the hikey directory.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
The README had a few mistakes, and one of the URL's
had changed. Also update the boot log with the latest
boot trace from ATF, which now includes the mcuimage.bin.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
We use outer pmic reset and drop internal reset signal, bmode will
not work as expected, so drop boot mode code for 7dsabresd board.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Adrian Alonso <aalonso@freescale.com>
Add MAINTAINERS info for mx6slevk_spl, mx6ul_9x9_evk and mx6qpsabreauto.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
commit "arm: socfpga: rename socfpga_cyclone5 and socfpga_arria5 config files"
renames the configs files, so we should update the MAINTAINERS' entry. At
the same time, update the email for Dinh Nguyen.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
We have defined this kconfig entry in arch/arm/cpu/armv7/mx7/Kconfig,
no need to redefine it in board Kconfig.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
get_board_rev() is not actually providing the board revision.
It just returns the CPU revision instead.
As the CPU revision is already printed on boot, there is no
reason to have get_board_rev(), so let's remove it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
get_board_rev() is not actually providing the board revision.
It just returns the CPU revision instead.
As the CPU revision is already printed on boot, there is no
reason to have get_board_rev(), so let's remove it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Include <usb/ehci-fsl.h> in order to fix the following sparse warning:
board/freescale/mx7dsabresd/mx7dsabresd.c:538:5: warning: symbol 'board_ehci_hcd_init' was not declared. Should it be static?
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
We use trigger pmic reset to reset the board, so set bit SRS to
disable internal WDOG_RESET_B_DEB to make reset stable.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Adrian Alonso <aalonso@freescale.com>
Tested-by: Fabio Estevam <fabio.estevam@freescale.com>
P2371-2180 is a P2180 CPU board married to a P2597 I/O board. The
combination contains SoC, DRAM, eMMC, SD card slot, HDMI, USB
micro-B port, Ethernet via USB3, USB3 host port, SATA, PCIe, and
two GPIO expansion headers.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Tested on my TI186x rev E. (PG2.0) and take over maintainership.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Take over maintainership as well. Not tested as PG2.0 (which I have)
needs additional work over PG1.0 (which Matt has).
Cc: Matt Porter <mporter@konsulko.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
We should not return 0 on failure, so return a negative error code
instead.
Also centralize the error path so that is easier to follow.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
We should not return 0 on failure, so return a negative error code
instead.
Also centralize the error path so that is easier to follow.
Cc: Markus Niebel <Markus.Niebel@tq-group.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
We should not return 0 on failure, so return a negative error code
instead.
Also centralize the error path so that is easier to follow.
Cc: Christian Gmeiner <christian.gmeiner@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
We should not return 0 on failure, so return a negative error code
instead.
Also centralize the error path so that is easier to follow.
Cc: Troy Kisky <troy.kisky@boundarydevices.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Troy Kisky <troy.kisky@boundarydevices.com>
Old revisions of Utilite (a miniature PC based on cm-fx6) do not have
a card detect for mmc, and thus the kernel needs to be told that
there's a persistent storage on usdhc3 to force it to probe the mmc
card.
Check the baseboard revision and modify the device tree accordingly
if needed.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
