Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

This commit is contained in:
Tom Rini 2015-11-30 15:18:30 -05:00
commit 1670c8c219
132 changed files with 5065 additions and 600 deletions

3
README
View file

@ -611,6 +611,9 @@ The following options need to be configured:
CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
Number of controllers used for other than main memory.
CONFIG_SYS_FSL_HAS_DP_DDR
Defines the SoC has DP-DDR used for DPAA.
CONFIG_SYS_FSL_SEC_BE
Defines the SEC controller register space as Big Endian

View file

@ -589,36 +589,46 @@ config TARGET_VEXPRESS64_JUNO
bool "Support Versatile Express Juno Development Platform"
select ARM64
config TARGET_LS2085A_EMU
bool "Support ls2085a_emu"
config TARGET_LS2080A_EMU
bool "Support ls2080a_emu"
select ARM64
select ARMV8_MULTIENTRY
config TARGET_LS2085A_SIMU
bool "Support ls2085a_simu"
select ARM64
select ARMV8_MULTIENTRY
config TARGET_LS2085AQDS
bool "Support ls2085aqds"
select ARM64
select ARMV8_MULTIENTRY
select SUPPORT_SPL
help
Support for Freescale LS2085AQDS platform
The LS2085A Development System (QDS) is a high-performance
development platform that supports the QorIQ LS2085A
Support for Freescale LS2080A_EMU platform
The LS2080A Development System (EMULATOR) is a pre silicon
development platform that supports the QorIQ LS2080A
Layerscape Architecture processor.
config TARGET_LS2085ARDB
bool "Support ls2085ardb"
config TARGET_LS2080A_SIMU
bool "Support ls2080a_simu"
select ARM64
select ARMV8_MULTIENTRY
help
Support for Freescale LS2080A_SIMU platform
The LS2080A Development System (QDS) is a pre silicon
development platform that supports the QorIQ LS2080A
Layerscape Architecture processor.
config TARGET_LS2080AQDS
bool "Support ls2080aqds"
select ARM64
select ARMV8_MULTIENTRY
select SUPPORT_SPL
help
Support for Freescale LS2085ARDB platform.
The LS2085A Reference design board (RDB) is a high-performance
development platform that supports the QorIQ LS2085A
Support for Freescale LS2080AQDS platform
The LS2080A Development System (QDS) is a high-performance
development platform that supports the QorIQ LS2080A
Layerscape Architecture processor.
config TARGET_LS2080ARDB
bool "Support ls2080ardb"
select ARM64
select ARMV8_MULTIENTRY
select SUPPORT_SPL
help
Support for Freescale LS2080ARDB platform.
The LS2080A Reference design board (RDB) is a high-performance
development platform that supports the QorIQ LS2080A
Layerscape Architecture processor.
config TARGET_HIKEY
@ -640,6 +650,14 @@ config TARGET_LS1021ATWR
select CPU_V7
select SUPPORT_SPL
config TARGET_LS1043AQDS
bool "Support ls1043aqds"
select ARM64
select ARMV8_MULTIENTRY
select SUPPORT_SPL
help
Support for Freescale LS1043AQDS platform.
config TARGET_LS1043ARDB
bool "Support ls1043ardb"
select ARM64
@ -759,10 +777,11 @@ source "board/compulab/cm_t43/Kconfig"
source "board/creative/xfi3/Kconfig"
source "board/denx/m28evk/Kconfig"
source "board/denx/m53evk/Kconfig"
source "board/freescale/ls2085a/Kconfig"
source "board/freescale/ls2085aqds/Kconfig"
source "board/freescale/ls2085ardb/Kconfig"
source "board/freescale/ls2080a/Kconfig"
source "board/freescale/ls2080aqds/Kconfig"
source "board/freescale/ls2080ardb/Kconfig"
source "board/freescale/ls1021aqds/Kconfig"
source "board/freescale/ls1043aqds/Kconfig"
source "board/freescale/ls1021atwr/Kconfig"
source "board/freescale/ls1043ardb/Kconfig"
source "board/freescale/mx23evk/Kconfig"

View file

@ -372,3 +372,13 @@ void reset_cpu(ulong addr)
*/
}
}
void arch_preboot_os(void)
{
unsigned long ctrl;
/* Disable PL1 Physical Timer */
asm("mrc p15, 0, %0, c14, c2, 1" : "=r" (ctrl));
ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
asm("mcr p15, 0, %0, c14, c2, 1" : : "r" (ctrl));
}

View file

@ -56,7 +56,8 @@ static inline unsigned long long us_to_tick(unsigned long long usec)
int timer_init(void)
{
struct sctr_regs *sctr = (struct sctr_regs *)SCTR_BASE_ADDR;
unsigned long ctrl, val, freq;
unsigned long ctrl, freq;
unsigned long long val;
/* Enable System Counter */
writel(SYS_COUNTER_CTRL_ENABLE, &sctr->cntcr);

View file

@ -13,13 +13,13 @@ DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_SYS_DCACHE_OFF
inline void set_pgtable_section(u64 *page_table, u64 index, u64 section,
u64 memory_type, u64 share)
u64 memory_type, u64 attribute)
{
u64 value;
value = section | PMD_TYPE_SECT | PMD_SECT_AF;
value |= PMD_ATTRINDX(memory_type);
value |= share;
value |= attribute;
page_table[index] = value;
}

View file

@ -21,10 +21,14 @@ obj-$(CONFIG_SYS_HAS_SERDES) += fsl_lsch2_serdes.o
endif
endif
ifneq ($(CONFIG_LS2080A),)
obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o
endif
ifneq ($(CONFIG_LS2085A),)
obj-$(CONFIG_SYS_HAS_SERDES) += ls2085a_serdes.o
else
obj-$(CONFIG_SYS_HAS_SERDES) += ls2080a_serdes.o
endif
ifneq ($(CONFIG_LS1043A),)
obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o
endif
endif

View file

@ -7,7 +7,7 @@
Freescale LayerScape with Chassis Generation 3
This architecture supports Freescale ARMv8 SoCs with Chassis generation 3,
for example LS2085A.
for example LS2080A.
DDR Layout
============
@ -152,7 +152,7 @@ u-boot command
nand write <rcw image in memory> 0 <size of rcw image>
To form the NAND image, build u-boot with NAND config, for example,
ls2085aqds_nand_defconfig. The image needed is u-boot-with-spl.bin.
ls2080aqds_nand_defconfig. The image needed is u-boot-with-spl.bin.
The u-boot image should be written to match SRC_ADDR, in above example 0x20000.
nand write <u-boot image in memory> 200000 <size of u-boot image>
@ -242,3 +242,84 @@ MMU Translation Tables
| 0x81_0000_0000 | | 0x08_0080_0000 |
------------------ ------------------
... ...
DPAA2 commands to manage Management Complex (MC)
------------------------------------------------
DPAA2 commands has been introduced to manage Management Complex
(MC). These commands are used to start mc, aiop and apply DPL
from u-boot command prompt.
Please note Management complex Firmware(MC), DPL and DPC are no
more deployed during u-boot boot-sequence.
Commands:
a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
b) fsl_mc apply DPL <DPL_addr> - Apply DPL file
c) fsl_mc start aiop <FW_addr> - Start AIOP
How to use commands :-
1. Command sequence for u-boot ethernet:
a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
b) DPMAC net-devices are now available for use
Example-
Assumption: MC firmware, DPL and DPC dtb is already programmed
on NOR flash.
=> fsl_mc start mc 580300000 580800000
=> setenv ethact DPMAC1@xgmii
=> ping $serverip
2. Command sequence for Linux boot:
a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
b) fsl_mc apply DPL <DPL_addr> - Apply DPL file
c) No DPMAC net-devices are available for use in u-boot
d) boot Linux
Example-
Assumption: MC firmware, DPL and DPC dtb is already programmed
on NOR flash.
=> fsl_mc start mc 580300000 580800000
=> setenv ethact DPMAC1@xgmii
=> tftp a0000000 kernel.itb
=> fsl_mc apply dpl 580700000
=> bootm a0000000
3. Command sequence for AIOP boot:
a) fsl_mc start mc <FW_addr> <DPC_addr> - Start Management Complex
b) fsl_mc start aiop <FW_addr> - Start AIOP
c) fsl_mc apply DPL <DPL_addr> - Apply DPL file
d) No DPMAC net-devices are availabe for use in u-boot
Please note actual AIOP start will happen during DPL parsing of
Management complex
Example-
Assumption: MC firmware, DPL, DPC dtb and AIOP firmware is already
programmed on NOR flash.
=> fsl_mc start mc 580300000 580800000
=> fsl_mc start aiop 0x580900000
=> setenv ethact DPMAC1@xgmii
=> fsl_mc apply dpl 580700000
Errata A009635
---------------
If the core runs at higher than x3 speed of the platform, there is
possiblity about sev instruction to getting missed by other cores.
This is because of SoC Run Control block may not able to sample
the EVENTI(Sev) signals.
Workaround: Configure Run Control and EPU to periodically send out EVENTI signals to
wake up A57 cores
Errata workaround uses Env variable "a009635_interval_val". It uses decimal
value.
- Default value of env variable is platform clock (MHz)
- User can modify default value by updating the env variable
setenv a009635_interval_val 600; saveenv;
It configure platform clock as 600 MHz
- Env variable as 0 signifies no workaround

View file

@ -76,7 +76,7 @@ static int set_block_entry(const struct sys_mmu_table *list,
index,
block_addr,
list->memory_type,
list->share);
list->attribute);
block_addr += block_size;
index++;
}
@ -438,7 +438,7 @@ int print_cpuinfo(void)
#ifdef CONFIG_SYS_DPAA_FMAN
printf(" FMAN: %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
#endif
#ifdef CONFIG_FSL_LSCH3
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
printf(" DP-DDR: %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus2));
#endif
puts("\n");
@ -484,7 +484,13 @@ int arch_early_init_r(void)
{
#ifdef CONFIG_MP
int rv = 1;
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
erratum_a009635();
#endif
#ifdef CONFIG_MP
rv = fsl_layerscape_wake_seconday_cores();
if (rv)
printf("Did not wake secondary cores\n");

View file

@ -141,7 +141,7 @@ void append_mmu_masters(void *blob, const char *smmu_path,
/*
* The info below summarizes how streamID partitioning works
* for ls2085a and how it is conveyed to the OS via the device tree.
* for ls2080a and how it is conveyed to the OS via the device tree.
*
* -non-PCI legacy, platform devices (USB, SD/MMC, SATA, DMA)
* -all legacy devices get a unique ICID assigned and programmed in

View file

@ -18,6 +18,11 @@ static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
#endif
#ifdef CONFIG_FSL_MC_ENET
int xfi_dpmac[XFI8 + 1];
int sgmii_dpmac[SGMII16 + 1];
#endif
int is_serdes_configured(enum srds_prtcl device)
{
int ret = 0;
@ -116,9 +121,15 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
wriop_init_dpmac(sd, 12, (int)lane_prtcl);
break;
default:
if (lane_prtcl >= XFI1 && lane_prtcl <= XFI8)
wriop_init_dpmac(sd,
xfi_dpmac[lane_prtcl],
(int)lane_prtcl);
if (lane_prtcl >= SGMII1 &&
lane_prtcl <= SGMII16)
wriop_init_dpmac(sd, lane + 1,
lane_prtcl <= SGMII16)
wriop_init_dpmac(sd, sgmii_dpmac[
lane_prtcl],
(int)lane_prtcl);
break;
}
@ -129,6 +140,16 @@ void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
void fsl_serdes_init(void)
{
#ifdef CONFIG_FSL_MC_ENET
int i , j;
for (i = XFI1, j = 1; i <= XFI8; i++, j++)
xfi_dpmac[i] = j;
for (i = SGMII1, j = 1; i <= SGMII16; i++, j++)
sgmii_dpmac[i] = j;
#endif
#ifdef CONFIG_SYS_FSL_SRDS_1
serdes_init(FSL_SRDS_1,
CONFIG_SYS_FSL_LSCH3_SERDES_ADDR,

View file

@ -11,6 +11,7 @@
#include <fsl_ifc.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/arch-fsl-layerscape/immap_lsch3.h>
#include <asm/arch/clock.h>
#include <asm/arch/soc.h>
#include "cpu.h"
@ -77,10 +78,14 @@ void get_sys_info(struct sys_info *sys_info)
sys_info->freq_systembus = sysclk;
#ifdef CONFIG_DDR_CLK_FREQ
sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
sys_info->freq_ddrbus2 = CONFIG_DDR_CLK_FREQ;
#endif
#else
sys_info->freq_ddrbus = sysclk;
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
sys_info->freq_ddrbus2 = sysclk;
#endif
#endif
sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
@ -91,9 +96,11 @@ void get_sys_info(struct sys_info *sys_info)
sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_SHIFT) &
FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK;
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
sys_info->freq_ddrbus2 *= (gur_in32(&gur->rcwsr[0]) >>
FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT) &
FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK;
#endif
for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
/*
@ -133,7 +140,9 @@ int get_clocks(void)
gd->cpu_clk = sys_info.freq_processor[0];
gd->bus_clk = sys_info.freq_systembus;
gd->mem_clk = sys_info.freq_ddrbus;
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
gd->arch.mem2_clk = sys_info.freq_ddrbus2;
#endif
#if defined(CONFIG_FSL_ESDHC)
gd->arch.sdhc_clk = gd->bus_clk / 2;
#endif /* defined(CONFIG_FSL_ESDHC) */
@ -169,8 +178,10 @@ ulong get_ddr_freq(ulong ctrl_num)
* DDR controller 0 & 1 are on memory complex 0
* DDR controler 2 is on memory complext 1
*/
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
if (ctrl_num >= 2)
return gd->arch.mem2_clk;
#endif
return gd->mem_clk;
}

View file

@ -28,7 +28,12 @@ static struct serdes_config serdes1_cfg_tbl[] = {
SGMII1 } },
{0x26, {SGMII8, SGMII7, SGMII6, SGMII5, SGMII4, SGMII3, XFI2, XFI1 } },
{0x28, {SGMII8, SGMII7, SGMII6, SGMII5, XFI4, XFI3, XFI2, XFI1 } },
#ifdef CONFIG_LS2080A
{0x2A, {NONE, NONE, NONE, XFI5, XFI4, XFI3, XFI2, XFI1 } },
#endif
#ifdef CONFIG_LS2085A
{0x2A, {XFI8, XFI7, XFI6, XFI5, XFI4, XFI3, XFI2, XFI1 } },
#endif
{0x2B, {SGMII8, SGMII7, SGMII6, SGMII5, XAUI1, XAUI1, XAUI1, XAUI1 } },
{0x32, {XAUI2, XAUI2, XAUI2, XAUI2, XAUI1, XAUI1, XAUI1, XAUI1 } },
{0x33, {PCIE2, PCIE2, PCIE2, PCIE2, QSGMII_C, QSGMII_D, QSGMII_A,

View file

@ -192,6 +192,12 @@ int cpu_release(int nr, int argc, char * const argv[])
(unsigned long)table + SPIN_TABLE_ELEM_SIZE);
asm volatile("dsb st");
smp_kick_all_cpus(); /* only those with entry addr set will run */
/*
* When the first release command runs, all cores are set to go. Those
* without a valid entry address will be trapped by "wfe". "sev" kicks
* them off to check the address again. When set, they continue to run.
*/
asm volatile("sev");
return 0;
}

View file

@ -9,10 +9,53 @@
#include <asm/arch/soc.h>
#include <asm/io.h>
#include <asm/global_data.h>
#include <asm/arch-fsl-layerscape/config.h>
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_LS2085A
#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
#define PLATFORM_CYCLE_ENV_VAR "a009635_interval_val"
static unsigned long get_internval_val_mhz(void)
{
char *interval = getenv(PLATFORM_CYCLE_ENV_VAR);
/*
* interval is the number of platform cycles(MHz) between
* wake up events generated by EPU.
*/
ulong interval_mhz = get_bus_freq(0) / (1000 * 1000);
if (interval)
interval_mhz = simple_strtoul(interval, NULL, 10);
return interval_mhz;
}
void erratum_a009635(void)
{
u32 val;
unsigned long interval_mhz = get_internval_val_mhz();
if (!interval_mhz)
return;
val = in_le32(DCSR_CGACRE5);
writel(val | 0x00000200, DCSR_CGACRE5);
val = in_le32(EPU_EPCMPR5);
writel(interval_mhz, EPU_EPCMPR5);
val = in_le32(EPU_EPCCR5);
writel(val | 0x82820000, EPU_EPCCR5);
val = in_le32(EPU_EPSMCR5);
writel(val | 0x002f0000, EPU_EPSMCR5);
val = in_le32(EPU_EPECR5);
writel(val | 0x20000000, EPU_EPECR5);
val = in_le32(EPU_EPGCR);
writel(val | 0x80000000, EPU_EPGCR);
}
#endif /* CONFIG_SYS_FSL_ERRATUM_A009635 */
static void erratum_a008751(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A008751

View file

@ -44,11 +44,9 @@ u32 spl_boot_mode(void)
#ifdef CONFIG_SPL_BUILD
void board_init_f(ulong dummy)
{
/* Set global data pointer */
gd = &gdata;
/* Clear global data */
memset((void *)gd, 0, sizeof(gd_t));
#ifdef CONFIG_LS2085A
#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
arch_cpu_init();
#endif
#ifdef CONFIG_FSL_IFC
@ -56,7 +54,7 @@ void board_init_f(ulong dummy)
#endif
board_early_init_f();
timer_init();
#ifdef CONFIG_LS2085A
#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
env_init();
#endif
get_clocks();

View file

@ -87,8 +87,10 @@ dtb-$(CONFIG_TARGET_STV0991) += stv0991.dtb
dtb-$(CONFIG_LS102XA) += ls1021a-qds.dtb \
ls1021a-twr.dtb
dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2085a-qds.dtb \
fsl-ls2085a-rdb.dtb
dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
fsl-ls2080a-rdb.dtb
dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds.dtb \
fsl-ls1043a-rdb.dtb
dtb-$(CONFIG_MACH_SUN4I) += \
sun4i-a10-a1000.dtb \

View file

@ -0,0 +1,124 @@
/*
* Device Tree Include file for Freescale Layerscape-1043A family SoC.
*
* Copyright (C) 2015, Freescale Semiconductor
*
* Mingkai Hu <Mingkai.hu@freescale.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
/dts-v1/;
/include/ "fsl-ls1043a.dtsi"
/ {
model = "LS1043A QDS Board";
};
&i2c0 {
status = "okay";
pca9547@77 {
compatible = "philips,pca9547";
reg = <0x77>;
#address-cells = <1>;
#size-cells = <0>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0>;
rtc@68 {
compatible = "dallas,ds3232";
reg = <0x68>;
/* IRQ10_B */
interrupts = <0 150 0x4>;
};
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x2>;
ina220@40 {
compatible = "ti,ina220";
reg = <0x40>;
shunt-resistor = <1000>;
};
ina220@41 {
compatible = "ti,ina220";
reg = <0x41>;
shunt-resistor = <1000>;
};
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3>;
eeprom@56 {
compatible = "at24,24c512";
reg = <0x56>;
};
eeprom@57 {
compatible = "at24,24c512";
reg = <0x57>;
};
adt7461a@4c {
compatible = "adt7461a";
reg = <0x4c>;
};
};
};
};
&ifc {
#address-cells = <2>;
#size-cells = <1>;
/* NOR, NAND Flashes and FPGA on board */
ranges = <0x0 0x0 0x0 0x60000000 0x08000000
0x2 0x0 0x0 0x7e800000 0x00010000
0x3 0x0 0x0 0x7fb00000 0x00000100>;
status = "okay";
nor@0,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "cfi-flash";
reg = <0x0 0x0 0x8000000>;
bank-width = <2>;
device-width = <1>;
};
nand@2,0 {
compatible = "fsl,ifc-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x1 0x0 0x10000>;
};
fpga: board-control@3,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
reg = <0x3 0x0 0x0000100>;
bank-width = <1>;
device-width = <1>;
ranges = <0 3 0 0x100>;
};
};
&duart0 {
status = "okay";
};
&duart1 {
status = "okay";
};

View file

@ -0,0 +1,103 @@
/*
* Device Tree Include file for Freescale Layerscape-1043A family SoC.
*
* Copyright (C) 2015, Freescale Semiconductor
*
* Mingkai Hu <Mingkai.hu@freescale.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
/dts-v1/;
/include/ "fsl-ls1043a.dtsi"
/ {
model = "LS1043A RDB Board";
aliases {
spi1 = &dspi0;
};
};
&dspi0 {
bus-num = <0>;
status = "okay";
dspiflash: n25q12a {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
reg = <0>;
spi-max-frequency = <1000000>; /* input clock */
};
};
&i2c0 {
status = "okay";
ina220@40 {
compatible = "ti,ina220";
reg = <0x40>;
shunt-resistor = <1000>;
};
adt7461a@4c {
compatible = "adi,adt7461a";
reg = <0x4c>;
};
eeprom@56 {
compatible = "at24,24c512";
reg = <0x52>;
};
eeprom@57 {
compatible = "at24,24c512";
reg = <0x53>;
};
rtc@68 {
compatible = "pericom,pt7c4338";
reg = <0x68>;
};
};
&ifc {
status = "okay";
#address-cells = <2>;
#size-cells = <1>;
/* NOR, NAND Flashes and FPGA on board */
ranges = <0x0 0x0 0x0 0x60000000 0x08000000
0x2 0x0 0x0 0x7e800000 0x00010000
0x3 0x0 0x0 0x7fb00000 0x00000100>;
nor@0,0 {
compatible = "cfi-flash";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0 0x0 0x8000000>;
bank-width = <2>;
device-width = <1>;
};
nand@1,0 {
compatible = "fsl,ifc-nand";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x1 0x0 0x10000>;
};
cpld: board-control@2,0 {
compatible = "fsl,ls1043ardb-cpld";
reg = <0x2 0x0 0x0000100>;
};
};
&duart0 {
status = "okay";
};
&duart1 {
status = "okay";
};

View file

@ -0,0 +1,186 @@
/*
* Device Tree Include file for Freescale Layerscape-1043A family SoC.
*
* Copyright (C) 2014-2015, Freescale Semiconductor
*
* Mingkai Hu <Mingkai.hu@freescale.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
/include/ "skeleton64.dtsi"
/ {
compatible = "fsl,ls1043a";
interrupt-parent = <&gic>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
clocks = <&clockgen 1 0>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
clocks = <&clockgen 1 0>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
clocks = <&clockgen 1 0>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
clocks = <&clockgen 1 0>;
};
};
sysclk: sysclk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "sysclk";
};
gic: interrupt-controller@1400000 {
compatible = "arm,gic-400";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x0 0x1401000 0 0x1000>, /* GICD */
<0x0 0x1402000 0 0x2000>, /* GICC */
<0x0 0x1404000 0 0x2000>, /* GICH */
<0x0 0x1406000 0 0x2000>; /* GICV */
interrupts = <1 9 0xf08>;
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
clockgen: clocking@1ee1000 {
compatible = "fsl,ls1043a-clockgen";
reg = <0x0 0x1ee1000 0x0 0x1000>;
#clock-cells = <2>;
clocks = <&sysclk>;
};
dspi0: dspi@2100000 {
compatible = "fsl,vf610-dspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2100000 0x0 0x10000>;
interrupts = <0 64 0x4>;
clock-names = "dspi";
clocks = <&clockgen 4 0>;
num-cs = <6>;
big-endian;
status = "disabled";
};
dspi1: dspi@2110000 {
compatible = "fsl,vf610-dspi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2110000 0x0 0x10000>;
interrupts = <0 65 0x4>;
clock-names = "dspi";
clocks = <&clockgen 4 0>;
num-cs = <6>;
big-endian;
status = "disabled";
};
ifc: ifc@1530000 {
compatible = "fsl,ifc", "simple-bus";
reg = <0x0 0x1530000 0x0 0x10000>;
interrupts = <0 43 0x4>;
};
i2c0: i2c@2180000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2180000 0x0 0x10000>;
interrupts = <0 56 0x4>;
clock-names = "i2c";
clocks = <&clockgen 4 0>;
status = "disabled";
};
i2c1: i2c@2190000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x2190000 0x0 0x10000>;
interrupts = <0 57 0x4>;
clock-names = "i2c";
clocks = <&clockgen 4 0>;
status = "disabled";
};
i2c2: i2c@21a0000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x21a0000 0x0 0x10000>;
interrupts = <0 58 0x4>;
clock-names = "i2c";
clocks = <&clockgen 4 0>;
status = "disabled";
};
i2c3: i2c@21b0000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0 0x21b0000 0x0 0x10000>;
interrupts = <0 59 0x4>;
clock-names = "i2c";
clocks = <&clockgen 4 0>;
status = "disabled";
};
duart0: serial@21c0500 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x00 0x21c0500 0x0 0x100>;
interrupts = <0 54 0x4>;
clocks = <&clockgen 4 0>;
};
duart1: serial@21c0600 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x00 0x21c0600 0x0 0x100>;
interrupts = <0 54 0x4>;
clocks = <&clockgen 4 0>;
};
duart2: serial@21d0500 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x0 0x21d0500 0x0 0x100>;
interrupts = <0 55 0x4>;
clocks = <&clockgen 4 0>;
};
duart3: serial@21d0600 {
compatible = "fsl,ns16550", "ns16550a";
reg = <0x0 0x21d0600 0x0 0x100>;
interrupts = <0 55 0x4>;
clocks = <&clockgen 4 0>;
};
};
};

View file

@ -1,5 +1,5 @@
/*
* Freescale ls2085a QDS board device tree source
* Freescale ls2080a QDS board device tree source
*
* Copyright 2013-2015 Freescale Semiconductor, Inc.
*
@ -8,11 +8,11 @@
/dts-v1/;
#include "fsl-ls2085a.dtsi"
#include "fsl-ls2080a.dtsi"
/ {
model = "Freescale Layerscape 2085a QDS Board";
compatible = "fsl,ls2085a-qds", "fsl,ls2085a";
model = "Freescale Layerscape 2080a QDS Board";
compatible = "fsl,ls2080a-qds", "fsl,ls2080a";
aliases {
spi1 = &dspi;

View file

@ -1,5 +1,5 @@
/*
* Freescale ls2085a RDB board device tree source
* Freescale ls2080a RDB board device tree source
*
* Copyright 2013-2015 Freescale Semiconductor, Inc.
*
@ -8,11 +8,11 @@
/dts-v1/;
#include "fsl-ls2085a.dtsi"
#include "fsl-ls2080a.dtsi"
/ {
model = "Freescale Layerscape 2085a RDB Board";
compatible = "fsl,ls2085a-rdb", "fsl,ls2085a";
model = "Freescale Layerscape 2080a RDB Board";
compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
aliases {
spi1 = &dspi;

View file

@ -1,5 +1,5 @@
/*
* Freescale ls2085a SOC common device tree source
* Freescale ls2080a SOC common device tree source
*
* Copyright 2013-2015 Freescale Semiconductor, Inc.
*
@ -7,7 +7,7 @@
*/
/ {
compatible = "fsl,ls2085a";
compatible = "fsl,ls2080a";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;

View file

@ -17,10 +17,16 @@
#define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0
#if defined(CONFIG_LS2085A)
#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
#define CONFIG_MAX_CPUS 16
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#ifdef CONFIG_LS2080A
#define CONFIG_NUM_DDR_CONTROLLERS 2
#endif
#ifdef CONFIG_LS2085A
#define CONFIG_NUM_DDR_CONTROLLERS 3
#define CONFIG_SYS_FSL_HAS_DP_DDR
#endif
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
#define SRDS_MAX_LANES 8
#define CONFIG_SYS_FSL_SRDS_1
@ -44,6 +50,7 @@
#define CONFIG_SYS_FSL_CCSR_SCFG_LE
#define CONFIG_SYS_FSL_ESDHC_LE
#define CONFIG_SYS_FSL_IFC_LE
#define CONFIG_SYS_FSL_PEX_LUT_LE
#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
@ -60,6 +67,13 @@
#define CCI_MN_DVM_DOMAIN_CTL 0x200
#define CCI_MN_DVM_DOMAIN_CTL_SET 0x210
#define CCI_HN_F_0_BASE (CCI_MN_BASE + 0x200000)
#define CCI_HN_F_1_BASE (CCI_MN_BASE + 0x210000)
#define CCN_HN_F_SAM_CTL 0x8 /* offset on base HN_F base */
#define CCN_HN_F_SAM_NODEID_MASK 0x7f
#define CCN_HN_F_SAM_NODEID_DDR0 0x4
#define CCN_HN_F_SAM_NODEID_DDR1 0xe
#define CCI_RN_I_0_BASE (CCI_MN_BASE + 0x800000)
#define CCI_RN_I_2_BASE (CCI_MN_BASE + 0x820000)
#define CCI_RN_I_6_BASE (CCI_MN_BASE + 0x860000)
@ -84,11 +98,20 @@
#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C)
#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820)
#define DCSR_CGACRE5 0x700070914ULL
#define EPU_EPCMPR5 0x700060914ULL
#define EPU_EPCCR5 0x700060814ULL
#define EPU_EPSMCR5 0x700060228ULL
#define EPU_EPECR5 0x700060314ULL
#define EPU_EPCTR5 0x700060a14ULL
#define EPU_EPGCR 0x700060000ULL
#define CONFIG_SYS_FSL_ERRATUM_A008336
#define CONFIG_SYS_FSL_ERRATUM_A008511
#define CONFIG_SYS_FSL_ERRATUM_A008514
#define CONFIG_SYS_FSL_ERRATUM_A008585
#define CONFIG_SYS_FSL_ERRATUM_A008751
#define CONFIG_SYS_FSL_ERRATUM_A009635
#elif defined(CONFIG_LS1043A)
#define CONFIG_MAX_CPUS 4
#define CONFIG_SYS_CACHELINE_SIZE 64
@ -113,6 +136,7 @@
#define CONFIG_SYS_FSL_WDOG_BE
#define CONFIG_SYS_FSL_DSPI_BE
#define CONFIG_SYS_FSL_QSPI_BE
#define CONFIG_SYS_FSL_PEX_LUT_BE
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1

View file

@ -8,8 +8,8 @@
#define _FSL_LAYERSCAPE_CPU_H
static struct cpu_type cpu_type_list[] = {
CPU_TYPE_ENTRY(LS2085, LS2085, 8),
CPU_TYPE_ENTRY(LS2080, LS2080, 8),
CPU_TYPE_ENTRY(LS2085, LS2085, 8),
CPU_TYPE_ENTRY(LS2045, LS2045, 4),
CPU_TYPE_ENTRY(LS1043, LS1043, 4),
};
@ -103,7 +103,7 @@ struct sys_mmu_table {
u64 phys_addr;
u64 size;
u64 memory_type;
u64 share;
u64 attribute;
};
struct table_info {
@ -115,7 +115,8 @@ struct table_info {
static const struct sys_mmu_table early_mmu_table[] = {
#ifdef CONFIG_FSL_LSCH3
{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE,
PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
/* For IFC Region #1, only the first 4MB is cache-enabled */
@ -129,17 +130,24 @@ static const struct sys_mmu_table early_mmu_table[] = {
CONFIG_SYS_FSL_IFC_SIZE1, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
/* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
{ CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE,
PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
#elif defined(CONFIG_FSL_LSCH2)
{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE,
PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE,
PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
@ -152,72 +160,93 @@ static const struct sys_mmu_table early_mmu_table[] = {
static const struct sys_mmu_table final_mmu_table[] = {
#ifdef CONFIG_FSL_LSCH3
{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE,
PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
{ CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE,
PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
CONFIG_SYS_FSL_IFC_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE,
PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
CONFIG_SYS_FSL_MC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
CONFIG_SYS_FSL_MC_SIZE, MT_DEVICE_NGNRNE,
PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
CONFIG_SYS_FSL_NI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
CONFIG_SYS_FSL_NI_SIZE, MT_DEVICE_NGNRNE,
PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
/* For QBMAN portal, only the first 64MB is cache-enabled */
{ CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
CONFIG_SYS_FSL_QBMAN_SIZE_1, MT_NORMAL, PMD_SECT_NON_SHARE },
CONFIG_SYS_FSL_QBMAN_SIZE_1, MT_NORMAL,
PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE,
PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE,
PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
#ifdef CONFIG_LS2085A
CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE,
PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
{ CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE,
PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
#endif
{ CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
CONFIG_SYS_FSL_WRIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
CONFIG_SYS_FSL_WRIOP1_SIZE, MT_DEVICE_NGNRNE,
PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
CONFIG_SYS_FSL_AIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
CONFIG_SYS_FSL_AIOP1_SIZE, MT_DEVICE_NGNRNE,
PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE,
PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
#elif defined(CONFIG_FSL_LSCH2)
{ CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
CONFIG_SYS_FSL_BOOTROM_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
CONFIG_SYS_FSL_BOOTROM_SIZE, MT_DEVICE_NGNRNE,
PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE,
PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE,
PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE,
PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
PMD_SECT_OUTER_SHARE | PMD_SECT_NS },
{ CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
CONFIG_SYS_FSL_QBMAN_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
CONFIG_SYS_FSL_QBMAN_SIZE, MT_DEVICE_NGNRNE,
PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
{ CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE,
PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE,
PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE,
PMD_SECT_NON_SHARE | PMD_SECT_PXN | PMD_SECT_UXN },
{ CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL, PMD_SECT_OUTER_SHARE },
#endif

View file

@ -11,4 +11,5 @@ void alloc_stream_ids(int start_id, int count, u32 *stream_ids, int max_cnt);
void append_mmu_masters(void *blob, const char *smmu_path,
const char *master_name, u32 *stream_ids, int count);
void fdt_fixup_smmu_pcie(void *blob);
void fdt_fixup_board_enet(void *fdt);
#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_FDT_H_ */

View file

@ -9,7 +9,7 @@
#include <config.h>
#if defined(CONFIG_LS2085A)
#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
enum srds_prtcl {
NONE = 0,
PCIE1,

View file

@ -30,9 +30,9 @@
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600)
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500)
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_IMMR + 0x011d0600)
#define CONFIG_SYS_FSL_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000)
#define CONFIG_SYS_FSL_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000)
#define CONFIG_SYS_FSL_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000)
#define CONFIG_SYS_LS1043A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x01f00000)
#define CONFIG_SYS_LS1043A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02000000)
#define CONFIG_SYS_LS1043A_XHCI_USB3_ADDR (CONFIG_SYS_IMMR + 0x02100000)
#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_IMMR + 0x2400000)
#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
@ -60,6 +60,10 @@
#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x4000000000ULL
#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x4800000000ULL
#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x5000000000ULL
/* LUT registers */
#define PCIE_LUT_BASE 0x10000
#define PCIE_LUT_LCTRL0 0x7F8
#define PCIE_LUT_DBG 0x7FC
/* TZ Address Space Controller Definitions */
#define TZASC1_BASE 0x01100000 /* as per CCSR map. */

View file

@ -51,8 +51,8 @@
#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000)
#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000)
#define CONFIG_SYS_LS2085A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
#define CONFIG_SYS_LS2085A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000)
#define CONFIG_SYS_LS2080A_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
#define CONFIG_SYS_LS2080A_XHCI_USB2_ADDR (CONFIG_SYS_IMMR + 0x02110000)
/* TZ Address Space Controller Definitions */
#define TZASC1_BASE 0x01100000 /* as per CCSR map. */
@ -78,6 +78,10 @@
#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x1200000000ULL
#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x1400000000ULL
#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x1600000000ULL
/* LUT registers */
#define PCIE_LUT_BASE 0x80000
#define PCIE_LUT_LCTRL0 0x7F8
#define PCIE_LUT_DBG 0x7FC
/* Device Configuration */
#define DCFG_BASE 0x01e00000
@ -115,7 +119,9 @@ struct sys_info {
unsigned long freq_processor[CONFIG_MAX_CPUS];
unsigned long freq_systembus;
unsigned long freq_ddrbus;
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
unsigned long freq_ddrbus2;
#endif
unsigned long freq_localbus;
unsigned long freq_qe;
#ifdef CONFIG_SYS_DPAA_FMAN

View file

@ -7,7 +7,7 @@
#ifndef __FSL_STREAM_ID_H
#define __FSL_STREAM_ID_H
/* Stream IDs on ls2085a devices are not hardwired and are
/* Stream IDs on ls2080a devices are not hardwired and are
* programmed by sw. There are a limited number of stream IDs
* available, and the partitioning of them is scenario dependent.
* This header defines the partitioning between legacy, PCI,
@ -17,7 +17,7 @@
* on the specific hardware config-- e.g. perhaps not all
* PEX controllers are in use.
*
* On LS2085 stream IDs are programmed in AMQ registers (32-bits) for
* On LS2080 stream IDs are programmed in AMQ registers (32-bits) for
* each of the different bus masters. The relationship between
* the AMQ registers and stream IDs is defined in the table below:
* AMQ bit streamID bit

View file

@ -23,6 +23,14 @@
#define scfg_out32(a, v) out_be32(a, v)
#endif
#ifdef CONFIG_SYS_FSL_PEX_LUT_LE
#define pex_lut_in32(a) in_le32(a)
#define pex_lut_out32(a, v) out_le32(a, v)
#elif defined(CONFIG_SYS_FSL_PEX_LUT_BE)
#define pex_lut_in32(a) in_be32(a)
#define pex_lut_out32(a, v) out_be32(a, v)
#endif
struct cpu_type {
char name[15];
u32 soc_ver;
@ -50,4 +58,7 @@ void fsl_lsch2_early_init_f(void);
#endif
void cpu_name(char *name);
#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
void erratum_a009635(void);
#endif
#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */

View file

@ -31,7 +31,7 @@
#define RCWSR4_SRDS1_PRTCL_SHIFT 24
#define RCWSR4_SRDS1_PRTCL_MASK 0xff000000
#define TIMER_COMP_VAL 0xffffffff
#define TIMER_COMP_VAL 0xffffffffffffffffull
#define ARCH_TIMER_CTRL_ENABLE (1 << 0)
#define SYS_COUNTER_CTRL_ENABLE (1 << 24)

View file

@ -119,7 +119,7 @@
void set_pgtable_section(u64 *page_table, u64 index,
u64 section, u64 memory_type,
u64 share);
u64 attribute);
void set_pgtable_table(u64 *page_table, u64 index,
u64 *table_addr);

View file

@ -46,7 +46,7 @@ struct arch_global_data {
u32 omap_boot_mode;
u8 omap_ch_flags;
#endif
#ifdef CONFIG_FSL_LSCH3
#if defined(CONFIG_FSL_LSCH3) && defined(CONFIG_SYS_FSL_HAS_DP_DDR)
unsigned long mem2_clk;
#endif
};

View file

@ -7,7 +7,12 @@
#include <common.h>
#include <command.h>
#include <i2c.h>
#include <asm/io.h>
#ifdef CONFIG_LS1043A
#include <asm/arch/immap_lsch2.h>
#else
#include <asm/immap_85xx.h>
#endif
#include "vid.h"
DECLARE_GLOBAL_DATA_PTR;
@ -240,7 +245,11 @@ static int set_voltage_to_IR(int i2caddress, int vdd)
* SoC before converting into an IR VID value
*/
vdd += board_vdd_drop_compensation();
#ifdef CONFIG_LS1043A
vid = DIV_ROUND_UP(vdd - 265, 5);
#else
vid = DIV_ROUND_UP(vdd - 245, 5);
#endif
ret = i2c_write(i2caddress, IR36021_LOOP1_MANUAL_ID_OFFSET,
1, (void *)&vid, sizeof(vid));
@ -276,8 +285,12 @@ static int set_voltage(int i2caddress, int vdd)
int adjust_vdd(ulong vdd_override)
{
int re_enable = disable_interrupts();
#ifdef CONFIG_LS1043A
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
#else
ccsr_gur_t __iomem *gur =
(void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#endif
u32 fusesr;
u8 vid;
int vdd_target, vdd_current, vdd_last;
@ -352,12 +365,21 @@ int adjust_vdd(ulong vdd_override)
* | T | | | | |
* ------------------------------------------------------
*/
#ifdef CONFIG_LS1043A
vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT) &
FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK;
if ((vid == 0) || (vid == FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK)) {
vid = (fusesr >> FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT) &
FSL_CHASSIS2_DCFG_FUSESR_VID_MASK;
}
#else
vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
if ((vid == 0) || (vid == FSL_CORENET_DCFG_FUSESR_ALTVID_MASK)) {
vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) &
FSL_CORENET_DCFG_FUSESR_VID_MASK;
}
#endif
vdd_target = vdd[vid];
/* check override variable for overriding VDD */

View file

@ -0,0 +1,15 @@
if TARGET_LS1043AQDS
config SYS_BOARD
default "ls1043aqds"
config SYS_VENDOR
default "freescale"
config SYS_SOC
default "fsl-layerscape"
config SYS_CONFIG_NAME
default "ls1043aqds"
endif

View file

@ -0,0 +1,9 @@
LS1043AQDS BOARD
M: Mingkai Hu <Mingkai.Hu@freescale.com>
S: Maintained
F: board/freescale/ls1043aqds/
F: include/configs/ls1043aqds.h
F: configs/ls1043aqds_defconfig
F: configs/ls1043aqds_nor_ddr3_defconfig
F: configs/ls1043aqds_nand_defconfig
F: configs/ls1043aqds_sdcard_ifc_defconfig

View file

@ -0,0 +1,9 @@
#
# Copyright 2015 Freescale Semiconductor, Inc.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += ddr.o
obj-y += eth.o
obj-y += ls1043aqds.o

View file

@ -0,0 +1,96 @@
Overview
--------
The LS1043A Development System (QDS) is a high-performance computing,
evaluation, and development platform that supports the QorIQ LS1043A
LayerScape Architecture processor. The LS1043AQDS provides SW development
platform for the Freescale LS1043A processor series, with a complete
debugging environment.
LS1043A SoC Overview
--------------------
The LS1043A integrated multicore processor combines four ARM Cortex-A53
processor cores with datapath acceleration optimized for L2/3 packet
processing, single pass security offload and robust traffic management
and quality of service.
The LS1043A SoC includes the following function and features:
- Four 64-bit ARM Cortex-A53 CPUs
- 1 MB unified L2 Cache
- One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
support
- Data Path Acceleration Architecture (DPAA) incorporating acceleration the
the following functions:
- Packet parsing, classification, and distribution (FMan)
- Queue management for scheduling, packet sequencing, and congestion
management (QMan)
- Hardware buffer management for buffer allocation and de-allocation (BMan)
- Cryptography acceleration (SEC)
- Ethernet interfaces by FMan
- Up to 1 x XFI supporting 10G interface
- Up to 1 x QSGMII
- Up to 4 x SGMII supporting 1000Mbps
- Up to 2 x SGMII supporting 2500Mbps
- Up to 2 x RGMII supporting 1000Mbps
- High-speed peripheral interfaces
- Three PCIe 2.0 controllers, one supporting x4 operation
- One serial ATA (SATA 3.0) controllers
- Additional peripheral interfaces
- Three high-speed USB 3.0 controllers with integrated PHY
- Enhanced secure digital host controller (eSDXC/eMMC)
- Quad Serial Peripheral Interface (QSPI) Controller
- Serial peripheral interface (SPI) controller
- Four I2C controllers
- Two DUARTs
- Integrated flash controller supporting NAND and NOR flash
- QorIQ platform's trust architecture 2.1
LS1043AQDS board Overview
-----------------------
- SERDES Connections, 4 lanes supporting:
- PCI Express - 3.0
- SGMII, SGMII 2.5
- QSGMII
- SATA 3.0
- XFI
- DDR Controller
- 2GB 40bits (8-bits ECC) DDR4 SDRAM. Support rates of up to 1600MT/s
-IFC/Local Bus
- One in-socket 128 MB NOR flash 16-bit data bus
- One 512 MB NAND flash with ECC support
- PromJet Port
- FPGA connection
- USB 3.0
- Three high speed USB 3.0 ports
- First USB 3.0 port configured as Host with Type-A connector
- The other two USB 3.0 ports configured as OTG with micro-AB connector
- SDHC port connects directly to an adapter card slot, featuring:
- Optional clock feedback paths, and optional high-speed voltage translation assistance
- SD slots for SD, SDHC (1x, 4x, 8x), and/or MMC
- eMMC memory devices
- DSPI: Onboard support for three SPI flash memory devices
- 4 I2C controllers
- One SATA onboard connectors
- UART
- Two 4-pin serial ports at up to 115.2 Kbit/s
- Two DB9 D-Type connectors supporting one Serial port each
- ARM JTAG support
Memory map from core's view
----------------------------
Start Address End Address Description Size
0x00_0000_0000 0x00_000F_FFFF Secure Boot ROM 1MB
0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB
0x00_1000_0000 0x00_1000_FFFF OCRAM0 64KB
0x00_1001_0000 0x00_1001_FFFF OCRAM1 64KB
0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB
0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB
0x00_7E80_0000 0x00_7E80_FFFF IFC - NAND Flash 64KB
0x00_7FB0_0000 0x00_7FB0_0FFF IFC - FPGA 4KB
0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB
Booting Options
---------------
a) Promjet Boot
b) NOR boot
c) NAND boot
d) SD boot

View file

@ -0,0 +1,131 @@
/*
* Copyright 2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#ifdef CONFIG_FSL_DEEP_SLEEP
#include <fsl_sleep.h>
#endif
#include "ddr.h"
DECLARE_GLOBAL_DATA_PTR;
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
{
const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
ulong ddr_freq;
if (ctrl_num > 3) {
printf("Not supported controller number %d\n", ctrl_num);
return;
}
if (!pdimm->n_ranks)
return;
pbsp = udimms[0];
/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
* freqency and n_banks specified in board_specific_parameters table.
*/
ddr_freq = get_ddr_freq(0) / 1000000;
while (pbsp->datarate_mhz_high) {
if (pbsp->n_ranks == pdimm->n_ranks) {
if (ddr_freq <= pbsp->datarate_mhz_high) {
popts->clk_adjust = pbsp->clk_adjust;
popts->wrlvl_start = pbsp->wrlvl_start;
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
popts->cpo_override = pbsp->cpo_override;
popts->write_data_delay =
pbsp->write_data_delay;
goto found;
}
pbsp_highest = pbsp;
}
pbsp++;
}
if (pbsp_highest) {
printf("Error: board specific timing not found for %lu MT/s\n",
ddr_freq);
printf("Trying to use the highest speed (%u) parameters\n",
pbsp_highest->datarate_mhz_high);
popts->clk_adjust = pbsp_highest->clk_adjust;
popts->wrlvl_start = pbsp_highest->wrlvl_start;
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
} else {
panic("DIMM is not supported by this board");
}
found:
debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
/* force DDR bus width to 32 bits */
popts->data_bus_width = 1;
popts->otf_burst_chop_en = 0;
popts->burst_length = DDR_BL8;
popts->bstopre = 0; /* enable auto precharge */
/*
* Factors to consider for half-strength driver enable:
* - number of DIMMs installed
*/
popts->half_strength_driver_enable = 1;
/*
* Write leveling override
*/
popts->wrlvl_override = 1;
popts->wrlvl_sample = 0xf;
/*
* Rtt and Rtt_WR override
*/
popts->rtt_override = 0;
/* Enable ZQ calibration */
popts->zq_en = 1;
#ifdef CONFIG_SYS_FSL_DDR4
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
#else
popts->cswl_override = DDR_CSWL_CS0;
/* DHC_EN =1, ODT = 75 Ohm */
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
#endif
}
phys_size_t initdram(int board_type)
{
phys_size_t dram_size;
#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
return fsl_ddr_sdram_size();
#else
puts("Initializing DDR....using SPD\n");
dram_size = fsl_ddr_sdram();
#endif
#ifdef CONFIG_FSL_DEEP_SLEEP
fsl_dp_ddr_restore();
#endif
return dram_size;
}
void dram_init_banksize(void)
{
gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
gd->bd->bi_dram[0].size = gd->ram_size;
}

View file

@ -0,0 +1,60 @@
/*
* Copyright 2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __DDR_H__
#define __DDR_H__
struct board_specific_parameters {
u32 n_ranks;
u32 datarate_mhz_high;
u32 rank_gb;
u32 clk_adjust;
u32 wrlvl_start;
u32 wrlvl_ctl_2;
u32 wrlvl_ctl_3;
u32 cpo_override;
u32 write_data_delay;
u32 force_2t;
};
/*
* These tables contain all valid speeds we want to override with board
* specific parameters. datarate_mhz_high values need to be in ascending order
* for each n_ranks group.
*/
static const struct board_specific_parameters udimm0[] = {
/*
* memory controller 0
* num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
* ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
*/
#ifdef CONFIG_SYS_FSL_DDR4
{2, 1666, 0, 4, 7, 0x0808090B, 0x0C0D0E0A,},
{2, 1900, 0, 4, 6, 0x08080A0C, 0x0D0E0F0A,},
{1, 1666, 0, 4, 6, 0x0708090B, 0x0C0D0E0A,},
{1, 1900, 0, 4, 9, 0x0A0B0C0B, 0x0D0E0F0D,},
{1, 2200, 0, 4, 10, 0x0B0C0D0C, 0x0E0F110E,},
#elif defined(CONFIG_SYS_FSL_DDR3)
{1, 833, 1, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
{1, 1350, 1, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
{1, 833, 2, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
{1, 1350, 2, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
{2, 833, 4, 6, 8, 0x06060607, 0x08080807, 0x1f, 2, 0},
{2, 1350, 4, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
{2, 1350, 0, 6, 8, 0x0708080A, 0x0A0B0C09, 0x1f, 2, 0},
{2, 1666, 4, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0},
{2, 1666, 0, 4, 0xa, 0x0B08090C, 0x0B0E0D0A, 0x1f, 2, 0},
#else
#error DDR type not defined
#endif
{}
};
static const struct board_specific_parameters *udimms[] = {
udimm0,
};
#endif

View file

@ -0,0 +1,492 @@
/*
* Copyright 2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <netdev.h>
#include <fm_eth.h>
#include <fsl_mdio.h>
#include <fsl_dtsec.h>
#include <malloc.h>
#include <asm/arch/fsl_serdes.h>
#include "../common/qixis.h"
#include "../common/fman.h"
#include "ls1043aqds_qixis.h"
#define EMI_NONE 0xFF
#define EMI1_RGMII1 0
#define EMI1_RGMII2 1
#define EMI1_SLOT1 2
#define EMI1_SLOT2 3
#define EMI1_SLOT3 4
#define EMI1_SLOT4 5
#define EMI2 6
static int mdio_mux[NUM_FM_PORTS];
static const char * const mdio_names[] = {
"LS1043AQDS_MDIO_RGMII1",
"LS1043AQDS_MDIO_RGMII2",
"LS1043AQDS_MDIO_SLOT1",
"LS1043AQDS_MDIO_SLOT2",
"LS1043AQDS_MDIO_SLOT3",
"LS1043AQDS_MDIO_SLOT4",
"NULL",
};
/* Map SerDes1 4 lanes to default slot, will be initialized dynamically */
static u8 lane_to_slot[] = {1, 2, 3, 4};
static const char *ls1043aqds_mdio_name_for_muxval(u8 muxval)
{
return mdio_names[muxval];
}
struct mii_dev *mii_dev_for_muxval(u8 muxval)
{
struct mii_dev *bus;
const char *name;
if (muxval > EMI2)
return NULL;
name = ls1043aqds_mdio_name_for_muxval(muxval);
if (!name) {
printf("No bus for muxval %x\n", muxval);
return NULL;
}
bus = miiphy_get_dev_by_name(name);
if (!bus) {
printf("No bus by name %s\n", name);
return NULL;
}
return bus;
}
struct ls1043aqds_mdio {
u8 muxval;
struct mii_dev *realbus;
};
static void ls1043aqds_mux_mdio(u8 muxval)
{
u8 brdcfg4;
if (muxval < 7) {
brdcfg4 = QIXIS_READ(brdcfg[4]);
brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
QIXIS_WRITE(brdcfg[4], brdcfg4);
}
}
static int ls1043aqds_mdio_read(struct mii_dev *bus, int addr, int devad,
int regnum)
{
struct ls1043aqds_mdio *priv = bus->priv;
ls1043aqds_mux_mdio(priv->muxval);
return priv->realbus->read(priv->realbus, addr, devad, regnum);
}
static int ls1043aqds_mdio_write(struct mii_dev *bus, int addr, int devad,
int regnum, u16 value)
{
struct ls1043aqds_mdio *priv = bus->priv;
ls1043aqds_mux_mdio(priv->muxval);
return priv->realbus->write(priv->realbus, addr, devad,
regnum, value);
}
static int ls1043aqds_mdio_reset(struct mii_dev *bus)
{
struct ls1043aqds_mdio *priv = bus->priv;
return priv->realbus->reset(priv->realbus);
}
static int ls1043aqds_mdio_init(char *realbusname, u8 muxval)
{
struct ls1043aqds_mdio *pmdio;
struct mii_dev *bus = mdio_alloc();
if (!bus) {
printf("Failed to allocate ls1043aqds MDIO bus\n");
return -1;
}
pmdio = malloc(sizeof(*pmdio));
if (!pmdio) {
printf("Failed to allocate ls1043aqds private data\n");
free(bus);
return -1;
}
bus->read = ls1043aqds_mdio_read;
bus->write = ls1043aqds_mdio_write;
bus->reset = ls1043aqds_mdio_reset;
sprintf(bus->name, ls1043aqds_mdio_name_for_muxval(muxval));
pmdio->realbus = miiphy_get_dev_by_name(realbusname);
if (!pmdio->realbus) {
printf("No bus with name %s\n", realbusname);
free(bus);
free(pmdio);
return -1;
}
pmdio->muxval = muxval;
bus->priv = pmdio;
return mdio_register(bus);
}
void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
enum fm_port port, int offset)
{
struct fixed_link f_link;
if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
if (port == FM1_DTSEC9) {
fdt_set_phy_handle(fdt, compat, addr,
"sgmii_riser_s1_p1");
} else if (port == FM1_DTSEC2) {
fdt_set_phy_handle(fdt, compat, addr,
"sgmii_riser_s2_p1");
} else if (port == FM1_DTSEC5) {
fdt_set_phy_handle(fdt, compat, addr,
"sgmii_riser_s3_p1");
} else if (port == FM1_DTSEC6) {
fdt_set_phy_handle(fdt, compat, addr,
"sgmii_riser_s4_p1");
}
} else if (fm_info_get_enet_if(port) ==
PHY_INTERFACE_MODE_SGMII_2500) {
/* 2.5G SGMII interface */
f_link.phy_id = port;
f_link.duplex = 1;
f_link.link_speed = 1000;
f_link.pause = 0;
f_link.asym_pause = 0;
/* no PHY for 2.5G SGMII */
fdt_delprop(fdt, offset, "phy-handle");
fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
fdt_setprop_string(fdt, offset, "phy-connection-type",
"sgmii-2500");
} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) {
switch (mdio_mux[port]) {
case EMI1_SLOT1:
switch (port) {
case FM1_DTSEC1:
fdt_set_phy_handle(fdt, compat, addr,
"qsgmii_s1_p1");
break;
case FM1_DTSEC2:
fdt_set_phy_handle(fdt, compat, addr,
"qsgmii_s1_p2");
break;
case FM1_DTSEC5:
fdt_set_phy_handle(fdt, compat, addr,
"qsgmii_s1_p3");
break;
case FM1_DTSEC6:
fdt_set_phy_handle(fdt, compat, addr,
"qsgmii_s1_p4");
break;
default:
break;
}
break;
case EMI1_SLOT2:
switch (port) {
case FM1_DTSEC1:
fdt_set_phy_handle(fdt, compat, addr,
"qsgmii_s2_p1");
break;
case FM1_DTSEC2:
fdt_set_phy_handle(fdt, compat, addr,
"qsgmii_s2_p2");
break;
case FM1_DTSEC5:
fdt_set_phy_handle(fdt, compat, addr,
"qsgmii_s2_p3");
break;
case FM1_DTSEC6:
fdt_set_phy_handle(fdt, compat, addr,
"qsgmii_s2_p4");
break;
default:
break;
}
break;
default:
break;
}
fdt_delprop(fdt, offset, "phy-connection-type");
fdt_setprop_string(fdt, offset, "phy-connection-type",
"qsgmii");
} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII &&
port == FM1_10GEC1) {
/* XFI interface */
f_link.phy_id = port;
f_link.duplex = 1;
f_link.link_speed = 10000;
f_link.pause = 0;
f_link.asym_pause = 0;
/* no PHY for XFI */
fdt_delprop(fdt, offset, "phy-handle");
fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
fdt_setprop_string(fdt, offset, "phy-connection-type", "xgmii");
}
}
void fdt_fixup_board_enet(void *fdt)
{
int i;
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 srds_s1;
srds_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_SGMII:
case PHY_INTERFACE_MODE_QSGMII:
switch (mdio_mux[i]) {
case EMI1_SLOT1:
fdt_status_okay_by_alias(fdt, "emi1_slot1");
break;
case EMI1_SLOT2:
fdt_status_okay_by_alias(fdt, "emi1_slot2");
break;
case EMI1_SLOT3:
fdt_status_okay_by_alias(fdt, "emi1_slot3");
break;
case EMI1_SLOT4:
fdt_status_okay_by_alias(fdt, "emi1_slot4");
break;
default:
break;
}
break;
case PHY_INTERFACE_MODE_XGMII:
break;
default:
break;
}
}
}
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_FMAN_ENET
int i, idx, lane, slot, interface;
struct memac_mdio_info dtsec_mdio_info;
struct memac_mdio_info tgec_mdio_info;
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 srds_s1;
srds_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
/* Initialize the mdio_mux array so we can recognize empty elements */
for (i = 0; i < NUM_FM_PORTS; i++)
mdio_mux[i] = EMI_NONE;
dtsec_mdio_info.regs =
(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
/* Register the 1G MDIO bus */
fm_memac_mdio_init(bis, &dtsec_mdio_info);
tgec_mdio_info.regs =
(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
/* Register the 10G MDIO bus */
fm_memac_mdio_init(bis, &tgec_mdio_info);
/* Register the muxing front-ends to the MDIO buses */
ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
ls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
ls1043aqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
/* Set the two on-board RGMII PHY address */
fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
switch (srds_s1) {
case 0x2555:
/* 2.5G SGMII on lane A, MAC 9 */
fm_info_set_phy_address(FM1_DTSEC9, 9);
break;
case 0x4555:
case 0x4558:
/* QSGMII on lane A, MAC 1/2/5/6 */
fm_info_set_phy_address(FM1_DTSEC1,
QSGMII_CARD_PORT1_PHY_ADDR_S1);
fm_info_set_phy_address(FM1_DTSEC2,
QSGMII_CARD_PORT2_PHY_ADDR_S1);
fm_info_set_phy_address(FM1_DTSEC5,
QSGMII_CARD_PORT3_PHY_ADDR_S1);
fm_info_set_phy_address(FM1_DTSEC6,
QSGMII_CARD_PORT4_PHY_ADDR_S1);
break;
case 0x1355:
/* SGMII on lane B, MAC 2*/
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
break;
case 0x2355:
/* 2.5G SGMII on lane A, MAC 9 */
fm_info_set_phy_address(FM1_DTSEC9, 9);
/* SGMII on lane B, MAC 2*/
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
break;
case 0x3335:
/* SGMII on lane C, MAC 5 */
fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);
case 0x3355:
case 0x3358:
/* SGMII on lane B, MAC 2 */
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
case 0x3555:
case 0x3558:
/* SGMII on lane A, MAC 9 */
fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
break;
case 0x1455:
/* QSGMII on lane B, MAC 1/2/5/6 */
fm_info_set_phy_address(FM1_DTSEC1,
QSGMII_CARD_PORT1_PHY_ADDR_S2);
fm_info_set_phy_address(FM1_DTSEC2,
QSGMII_CARD_PORT2_PHY_ADDR_S2);
fm_info_set_phy_address(FM1_DTSEC5,
QSGMII_CARD_PORT3_PHY_ADDR_S2);
fm_info_set_phy_address(FM1_DTSEC6,
QSGMII_CARD_PORT4_PHY_ADDR_S2);
break;
case 0x2455:
/* 2.5G SGMII on lane A, MAC 9 */
fm_info_set_phy_address(FM1_DTSEC9, 9);
/* QSGMII on lane B, MAC 1/2/5/6 */
fm_info_set_phy_address(FM1_DTSEC1,
QSGMII_CARD_PORT1_PHY_ADDR_S2);
fm_info_set_phy_address(FM1_DTSEC2,
QSGMII_CARD_PORT2_PHY_ADDR_S2);
fm_info_set_phy_address(FM1_DTSEC5,
QSGMII_CARD_PORT3_PHY_ADDR_S2);
fm_info_set_phy_address(FM1_DTSEC6,
QSGMII_CARD_PORT4_PHY_ADDR_S2);
break;
case 0x2255:
/* 2.5G SGMII on lane A, MAC 9 */
fm_info_set_phy_address(FM1_DTSEC9, 9);
/* 2.5G SGMII on lane B, MAC 2 */
fm_info_set_phy_address(FM1_DTSEC2, 2);
break;
case 0x3333:
/* SGMII on lane A/B/C/D, MAC 9/2/5/6 */
fm_info_set_phy_address(FM1_DTSEC9,
SGMII_CARD_PORT1_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2,
SGMII_CARD_PORT1_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC5,
SGMII_CARD_PORT1_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC6,
SGMII_CARD_PORT1_PHY_ADDR);
break;
default:
printf("Invalid SerDes protocol 0x%x for LS1043AQDS\n",
srds_s1);
break;
}
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
idx = i - FM1_DTSEC1;
interface = fm_info_get_enet_if(i);
switch (interface) {
case PHY_INTERFACE_MODE_SGMII:
case PHY_INTERFACE_MODE_SGMII_2500:
case PHY_INTERFACE_MODE_QSGMII:
if (interface == PHY_INTERFACE_MODE_SGMII) {
lane = serdes_get_first_lane(FSL_SRDS_1,
SGMII_FM1_DTSEC1 + idx);
} else if (interface == PHY_INTERFACE_MODE_SGMII_2500) {
lane = serdes_get_first_lane(FSL_SRDS_1,
SGMII_2500_FM1_DTSEC1 + idx);
} else {
lane = serdes_get_first_lane(FSL_SRDS_1,
QSGMII_FM1_A);
}
if (lane < 0)
break;
slot = lane_to_slot[lane];
debug("FM1@DTSEC%u expects SGMII in slot %u\n",
idx + 1, slot);
if (QIXIS_READ(present2) & (1 << (slot - 1)))
fm_disable_port(i);
switch (slot) {
case 1:
mdio_mux[i] = EMI1_SLOT1;
fm_info_set_mdio(i, mii_dev_for_muxval(
mdio_mux[i]));
break;
case 2:
mdio_mux[i] = EMI1_SLOT2;
fm_info_set_mdio(i, mii_dev_for_muxval(
mdio_mux[i]));
break;
case 3:
mdio_mux[i] = EMI1_SLOT3;
fm_info_set_mdio(i, mii_dev_for_muxval(
mdio_mux[i]));
break;
case 4:
mdio_mux[i] = EMI1_SLOT4;
fm_info_set_mdio(i, mii_dev_for_muxval(
mdio_mux[i]));
break;
default:
break;
}
break;
case PHY_INTERFACE_MODE_RGMII:
if (i == FM1_DTSEC3)
mdio_mux[i] = EMI1_RGMII1;
else if (i == FM1_DTSEC4)
mdio_mux[i] = EMI1_RGMII2;
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
break;
default:
break;
}
}
cpu_eth_init(bis);
#endif /* CONFIG_FMAN_ENET */
return pci_eth_init(bis);
}

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/*
* Copyright 2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <i2c.h>
#include <fdt_support.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/fdt.h>
#include <asm/arch/soc.h>
#include <ahci.h>
#include <hwconfig.h>
#include <mmc.h>
#include <scsi.h>
#include <fm_eth.h>
#include <fsl_csu.h>
#include <fsl_esdhc.h>
#include <fsl_ifc.h>
#include <spl.h>
#include "../common/qixis.h"
#include "ls1043aqds_qixis.h"
DECLARE_GLOBAL_DATA_PTR;
enum {
MUX_TYPE_GPIO,
};
/* LS1043AQDS serdes mux */
#define CFG_SD_MUX1_SLOT2 0x0 /* SLOT2 TX/RX0 */
#define CFG_SD_MUX1_SLOT1 0x1 /* SLOT1 TX/RX1 */
#define CFG_SD_MUX2_SLOT3 0x0 /* SLOT3 TX/RX0 */
#define CFG_SD_MUX2_SLOT1 0x1 /* SLOT1 TX/RX2 */
#define CFG_SD_MUX3_SLOT4 0x0 /* SLOT4 TX/RX0 */
#define CFG_SD_MUX3_MUX4 0x1 /* MUX4 */
#define CFG_SD_MUX4_SLOT3 0x0 /* SLOT3 TX/RX1 */
#define CFG_SD_MUX4_SLOT1 0x1 /* SLOT1 TX/RX3 */
int checkboard(void)
{
char buf[64];
#ifndef CONFIG_SD_BOOT
u8 sw;
#endif
puts("Board: LS1043AQDS, boot from ");
#ifdef CONFIG_SD_BOOT
puts("SD\n");
#else
sw = QIXIS_READ(brdcfg[0]);
sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
if (sw < 0x8)
printf("vBank: %d\n", sw);
else if (sw == 0x8)
puts("PromJet\n");
else if (sw == 0x9)
puts("NAND\n");
else if (sw == 0x15)
printf("IFCCard\n");
else
printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
#endif
printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
QIXIS_READ(id), QIXIS_READ(arch));
printf("FPGA: v%d (%s), build %d\n",
(int)QIXIS_READ(scver), qixis_read_tag(buf),
(int)qixis_read_minor());
return 0;
}
bool if_board_diff_clk(void)
{
u8 diff_conf = QIXIS_READ(brdcfg[11]);
return diff_conf & 0x40;
}
unsigned long get_board_sys_clk(void)
{
u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
switch (sysclk_conf & 0x0f) {
case QIXIS_SYSCLK_64:
return 64000000;
case QIXIS_SYSCLK_83:
return 83333333;
case QIXIS_SYSCLK_100:
return 100000000;
case QIXIS_SYSCLK_125:
return 125000000;
case QIXIS_SYSCLK_133:
return 133333333;
case QIXIS_SYSCLK_150:
return 150000000;
case QIXIS_SYSCLK_160:
return 160000000;
case QIXIS_SYSCLK_166:
return 166666666;
}
return 66666666;
}
unsigned long get_board_ddr_clk(void)
{
u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
if (if_board_diff_clk())
return get_board_sys_clk();
switch ((ddrclk_conf & 0x30) >> 4) {
case QIXIS_DDRCLK_100:
return 100000000;
case QIXIS_DDRCLK_125:
return 125000000;
case QIXIS_DDRCLK_133:
return 133333333;
}
return 66666666;
}
int select_i2c_ch_pca9547(u8 ch)
{
int ret;
ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
if (ret) {
puts("PCA: failed to select proper channel\n");
return ret;
}
return 0;
}
int dram_init(void)
{
/*
* When resuming from deep sleep, the I2C channel may not be
* in the default channel. So, switch to the default channel
* before accessing DDR SPD.
*/
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
gd->ram_size = initdram(0);
return 0;
}
int i2c_multiplexer_select_vid_channel(u8 channel)
{
return select_i2c_ch_pca9547(channel);
}
void board_retimer_init(void)
{
u8 reg;
/* Retimer is connected to I2C1_CH7_CH5 */
reg = I2C_MUX_CH7;
i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &reg, 1);
reg = I2C_MUX_CH5;
i2c_write(I2C_MUX_PCA_ADDR_SEC, 0, 1, &reg, 1);
/* Access to Control/Shared register */
reg = 0x0;
i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
/* Read device revision and ID */
i2c_read(I2C_RETIMER_ADDR, 1, 1, &reg, 1);
debug("Retimer version id = 0x%x\n", reg);
/* Enable Broadcast. All writes target all channel register sets */
reg = 0x0c;
i2c_write(I2C_RETIMER_ADDR, 0xff, 1, &reg, 1);
/* Reset Channel Registers */
i2c_read(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
reg |= 0x4;
i2c_write(I2C_RETIMER_ADDR, 0, 1, &reg, 1);
/* Enable override divider select and Enable Override Output Mux */
i2c_read(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
reg |= 0x24;
i2c_write(I2C_RETIMER_ADDR, 9, 1, &reg, 1);
/* Select VCO Divider to full rate (000) */
i2c_read(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
reg &= 0x8f;
i2c_write(I2C_RETIMER_ADDR, 0x18, 1, &reg, 1);
/* Selects active PFD MUX Input as Re-timed Data (001) */
i2c_read(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
reg &= 0x3f;
reg |= 0x20;
i2c_write(I2C_RETIMER_ADDR, 0x1e, 1, &reg, 1);
/* Set data rate as 10.3125 Gbps */
reg = 0x0;
i2c_write(I2C_RETIMER_ADDR, 0x60, 1, &reg, 1);
reg = 0xb2;
i2c_write(I2C_RETIMER_ADDR, 0x61, 1, &reg, 1);
reg = 0x90;
i2c_write(I2C_RETIMER_ADDR, 0x62, 1, &reg, 1);
reg = 0xb3;
i2c_write(I2C_RETIMER_ADDR, 0x63, 1, &reg, 1);
reg = 0xcd;
i2c_write(I2C_RETIMER_ADDR, 0x64, 1, &reg, 1);
}
int board_early_init_f(void)
{
fsl_lsch2_early_init_f();
return 0;
}
#ifdef CONFIG_FSL_DEEP_SLEEP
/* determine if it is a warm boot */
bool is_warm_boot(void)
{
#define DCFG_CCSR_CRSTSR_WDRFR (1 << 3)
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
return 1;
return 0;
}
#endif
int config_board_mux(int ctrl_type)
{
u8 reg14;
reg14 = QIXIS_READ(brdcfg[14]);
switch (ctrl_type) {
case MUX_TYPE_GPIO:
reg14 = (reg14 & (~0x30)) | 0x20;
break;
default:
puts("Unsupported mux interface type\n");
return -1;
}
QIXIS_WRITE(brdcfg[14], reg14);
return 0;
}
int config_serdes_mux(void)
{
return 0;
}
#ifdef CONFIG_MISC_INIT_R
int misc_init_r(void)
{
if (hwconfig("gpio"))
config_board_mux(MUX_TYPE_GPIO);
return 0;
}
#endif
int board_init(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)
CONFIG_SYS_CCI400_ADDR;
/* Set CCI-400 control override register to enable barrier
* transaction */
out_le32(&cci->ctrl_ord,
CCI400_CTRLORD_EN_BARRIER);
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
board_retimer_init();
#ifdef CONFIG_SYS_FSL_SERDES
config_serdes_mux();
#endif
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
enable_layerscape_ns_access();
#endif
#ifdef CONFIG_ENV_IS_NOWHERE
gd->env_addr = (ulong)&default_environment[0];
#endif
return 0;
}
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_SYS_DPAA_FMAN
fdt_fixup_fman_ethernet(blob);
fdt_fixup_board_enet(blob);
#endif
return 0;
}
#endif
u8 flash_read8(void *addr)
{
return __raw_readb(addr + 1);
}
void flash_write16(u16 val, void *addr)
{
u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
__raw_writew(shftval, addr);
}
u16 flash_read16(void *addr)
{
u16 val = __raw_readw(addr);
return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
}

View file

@ -0,0 +1,14 @@
#Configure Scratch register
09570600 00000000
09570604 10000000
#Alt base register
09570158 00001000
#Disable CCI barrier tranaction
09570178 0000e010
09180000 00000008
#USB PHY frequency sel
09570418 0000009e
0957041c 0000009e
09570420 0000009e
#flush PBI data
096100c0 000fffff

View file

@ -0,0 +1,39 @@
/*
* Copyright 2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __LS1043AQDS_QIXIS_H__
#define __LS1043AQDS_QIXIS_H__
/* Definitions of QIXIS Registers for LS1043AQDS */
/* BRDCFG4[4:7] select EC1 and EC2 as a pair */
#define BRDCFG4_EMISEL_MASK 0xe0
#define BRDCFG4_EMISEL_SHIFT 5
/* SYSCLK */
#define QIXIS_SYSCLK_66 0x0
#define QIXIS_SYSCLK_83 0x1
#define QIXIS_SYSCLK_100 0x2
#define QIXIS_SYSCLK_125 0x3
#define QIXIS_SYSCLK_133 0x4
#define QIXIS_SYSCLK_150 0x5
#define QIXIS_SYSCLK_160 0x6
#define QIXIS_SYSCLK_166 0x7
#define QIXIS_SYSCLK_64 0x8
/* DDRCLK */
#define QIXIS_DDRCLK_66 0x0
#define QIXIS_DDRCLK_100 0x1
#define QIXIS_DDRCLK_125 0x2
#define QIXIS_DDRCLK_133 0x3
/* BRDCFG2 - SD clock*/
#define QIXIS_SDCLK1_100 0x0
#define QIXIS_SDCLK1_125 0x1
#define QIXIS_SDCLK1_165 0x2
#define QIXIS_SDCLK1_100_SP 0x3
#endif

View file

@ -0,0 +1,7 @@
#PBL preamble and RCW header
aa55aa55 01ee0100
# serdes protocol
0810000f 0c000000 00000000 00000000
14550002 80004012 e0106000 61002000
00000000 00000000 00000000 00038800
00000000 00001100 00000096 00000001

View file

@ -0,0 +1,8 @@
#PBL preamble and RCW header
aa55aa55 01ee0100
# RCW
# Enable IFC; disable QSPI
0810000f 0c000000 00000000 00000000
14550002 80004012 60040000 61002000
00000000 00000000 00000000 00038800
00000000 00001100 00000096 00000001

View file

@ -69,7 +69,23 @@ int dram_init(void)
int board_early_init_f(void)
{
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
u32 usb_pwrfault;
fsl_lsch2_early_init_f();
#ifdef CONFIG_HAS_FSL_XHCI_USB
out_be32(&scfg->rcwpmuxcr0, 0x3333);
out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
SCFG_USBPWRFAULT_USB3_SHIFT) |
(SCFG_USBPWRFAULT_DEDICATED <<
SCFG_USBPWRFAULT_USB2_SHIFT) |
(SCFG_USBPWRFAULT_SHARED <<
SCFG_USBPWRFAULT_USB1_SHIFT);
out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
#endif
return 0;
}

View file

@ -1,7 +1,7 @@
if TARGET_LS2085A_EMU
if TARGET_LS2080A_EMU
config SYS_BOARD
default "ls2085a"
default "ls2080a"
config SYS_VENDOR
default "freescale"
@ -10,14 +10,14 @@ config SYS_SOC
default "fsl-layerscape"
config SYS_CONFIG_NAME
default "ls2085a_emu"
default "ls2080a_emu"
endif
if TARGET_LS2085A_SIMU
if TARGET_LS2080A_SIMU
config SYS_BOARD
default "ls2085a"
default "ls2080a"
config SYS_VENDOR
default "freescale"
@ -26,6 +26,6 @@ config SYS_SOC
default "fsl-layerscape"
config SYS_CONFIG_NAME
default "ls2085a_simu"
default "ls2080a_simu"
endif

View file

@ -0,0 +1,10 @@
LS2080A BOARD
M: York Sun <yorksun@freescale.com>
S: Maintained
F: board/freescale/ls2080a/
F: include/configs/ls2080a_emu.h
F: configs/ls2080a_emu_defconfig
F: include/configs/ls2080a_simu.h
F: configs/ls2080a_simu_defconfig
F: configs/ls2085a_emu_defconfig
F: configs/ls2085a_simu_defconfig

View file

@ -0,0 +1,8 @@
#
# Copyright 2014-15 Freescale Semiconductor
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += ls2080a.o
obj-y += ddr.o

View file

@ -1,4 +1,4 @@
Freescale ls2085a_emu
Freescale ls2080a_emu
This is a emulator target with limited peripherals.

View file

@ -71,7 +71,7 @@ found:
pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
pbsp->wrlvl_ctl_3);
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
if (ctrl_num == CONFIG_DP_DDR_CTRL) {
/* force DDR bus width to 32 bits */
popts->data_bus_width = 1;
@ -79,6 +79,7 @@ found:
popts->burst_length = DDR_BL8;
popts->bstopre = 0; /* enable auto precharge */
}
#endif
/*
* Factors to consider for half-strength driver enable:
* - number of DIMMs installed

View file

@ -41,11 +41,13 @@ void detail_board_ddr_info(void)
puts("\nDDR ");
print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
print_ddr_info(0);
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
if (gd->bd->bi_dram[2].size) {
puts("\nDP-DDR ");
print_size(gd->bd->bi_dram[2].size, "");
print_ddr_info(CONFIG_DP_DDR_CTRL);
}
#endif
}
int dram_init(void)

View file

@ -1,8 +1,8 @@
if TARGET_LS2085ARDB
if TARGET_LS2080AQDS
config SYS_BOARD
default "ls2085ardb"
default "ls2080aqds"
config SYS_VENDOR
default "freescale"
@ -11,6 +11,6 @@ config SYS_SOC
default "fsl-layerscape"
config SYS_CONFIG_NAME
default "ls2085ardb"
default "ls2080aqds"
endif

View file

@ -0,0 +1,10 @@
LS2080A BOARD
M: Prabhakar Kushwaha <prabhakar@freescale.com>
S: Maintained
F: board/freescale/ls2080aqds/
F: board/freescale/ls2080a/ls2080aqds.c
F: include/configs/ls2080aqds.h
F: configs/ls2080aqds_defconfig
F: configs/ls2080aqds_nand_defconfig
F: configs/ls2085aqds_defconfig
F: configs/ls2085aqds_nand_defconfig

View file

@ -4,6 +4,6 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += ls2085aqds.o
obj-y += ls2080aqds.o
obj-y += ddr.o
obj-y += eth.o

View file

@ -1,19 +1,19 @@
Overview
--------
The LS2085A Development System (QDS) is a high-performance computing,
evaluation, and development platform that supports the QorIQ LS2085A
Layerscape Architecture processor. The LS2085AQDS provides validation and
SW development platform for the Freescale LS2085A processor series, with
The LS2080A Development System (QDS) is a high-performance computing,
evaluation, and development platform that supports the QorIQ LS2080A
Layerscape Architecture processor. The LS2080AQDS provides validation and
SW development platform for the Freescale LS2080A processor series, with
a complete debugging environment.
LS2085A SoC Overview
LS2080A SoC Overview
------------------
The LS2085A integrated multicore processor combines eight ARM Cortex-A57
The LS2080A integrated multicore processor combines eight ARM Cortex-A57
processor cores with high-performance data path acceleration logic and network
and peripheral bus interfaces required for networking, telecom/datacom,
wireless infrastructure, and mil/aerospace applications.
The LS2085A SoC includes the following function and features:
The LS2080A SoC includes the following function and features:
- Eight 64-bit ARM Cortex-A57 CPUs
- 1 MB platform cache with ECC
@ -50,7 +50,7 @@ The LS2085A SoC includes the following function and features:
- Service processor (SP) provides pre-boot initialization and secure-boot
capabilities
LS2085AQDS board Overview
LS2080AQDS board Overview
-----------------------
- SERDES Connections, 16 lanes supporting:
- PCI Express - 3.0
@ -172,7 +172,7 @@ Supported PHY addresses during SGMII:
#define XQSGMII_CARD_PHY4_PORT0_ADDR 0xc
#define XQSGMII_CARD_PHY4_PORT2_ADDR 0xe
Mapping DPMACx to PHY during QSGMII
Mapping DPMACx to PHY during SGMII
DPMAC1 -> PHY1-P0
DPMAC2 -> PHY2-P0
DPMAC3 -> PHY3-P0

View file

@ -15,7 +15,9 @@ void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
{
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
u8 dq_mapping_0, dq_mapping_2, dq_mapping_3;
#endif
const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
ulong ddr_freq;
int slot;
@ -79,7 +81,7 @@ found:
pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
pbsp->wrlvl_ctl_3);
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
if (ctrl_num == CONFIG_DP_DDR_CTRL) {
/* force DDR bus width to 32 bits */
popts->data_bus_width = 1;
@ -114,6 +116,7 @@ found:
pdimm[slot].dq_mapping[16] = 0;
pdimm[slot].dq_mapping[17] = 0;
}
#endif
/* To work at higher than 1333MT/s */
popts->half_strength_driver_enable = 0;
/*

View file

@ -18,16 +18,16 @@
#include "../common/qixis.h"
#include "ls2085aqds_qixis.h"
#include "ls2080aqds_qixis.h"
#ifdef CONFIG_FSL_MC_ENET
/* - In LS2085A there are only 16 SERDES lanes, spread across 2 SERDES banks.
/* - In LS2080A there are only 16 SERDES lanes, spread across 2 SERDES banks.
* Bank 1 -> Lanes A, B, C, D, E, F, G, H
* Bank 2 -> Lanes A,B, C, D, E, F, G, H
*/
/* Mapping of 16 SERDES lanes to LS2085A QDS board slots. A value of '0' here
/* Mapping of 16 SERDES lanes to LS2080A QDS board slots. A value of '0' here
* means that the mapping must be determined dynamically, or that the lane
* maps to something other than a board slot.
*/
@ -74,16 +74,16 @@ static int sgmii_riser_phy_addr[] = {
#define SFP_TX 0
static const char * const mdio_names[] = {
"LS2085A_QDS_MDIO0",
"LS2085A_QDS_MDIO1",
"LS2085A_QDS_MDIO2",
"LS2085A_QDS_MDIO3",
"LS2085A_QDS_MDIO4",
"LS2085A_QDS_MDIO5",
"LS2080A_QDS_MDIO0",
"LS2080A_QDS_MDIO1",
"LS2080A_QDS_MDIO2",
"LS2080A_QDS_MDIO3",
"LS2080A_QDS_MDIO4",
"LS2080A_QDS_MDIO5",
DEFAULT_WRIOP_MDIO2_NAME,
};
struct ls2085a_qds_mdio {
struct ls2080a_qds_mdio {
u8 muxval;
struct mii_dev *realbus;
};
@ -95,7 +95,7 @@ static void sgmii_configure_repeater(int serdes_port)
int i, j, ret;
int dpmac_id = 0, dpmac, mii_bus = 0;
unsigned short value;
char dev[2][20] = {"LS2085A_QDS_MDIO0", "LS2085A_QDS_MDIO3"};
char dev[2][20] = {"LS2080A_QDS_MDIO0", "LS2080A_QDS_MDIO3"};
uint8_t i2c_addr[] = {0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5f, 0x60};
uint8_t ch_a_eq[] = {0x1, 0x2, 0x3, 0x7};
@ -222,7 +222,7 @@ static void qsgmii_configure_repeater(int dpmac)
uint8_t ch_b_eq[] = {0x1, 0x2, 0x3, 0x7};
uint8_t ch_b_ctl2[] = {0x81, 0x82, 0x83, 0x84};
const char *dev = "LS2085A_QDS_MDIO0";
const char *dev = "LS2080A_QDS_MDIO0";
int ret = 0;
unsigned short value;
@ -318,7 +318,7 @@ error:
return;
}
static const char *ls2085a_qds_mdio_name_for_muxval(u8 muxval)
static const char *ls2080a_qds_mdio_name_for_muxval(u8 muxval)
{
return mdio_names[muxval];
}
@ -326,7 +326,7 @@ static const char *ls2085a_qds_mdio_name_for_muxval(u8 muxval)
struct mii_dev *mii_dev_for_muxval(u8 muxval)
{
struct mii_dev *bus;
const char *name = ls2085a_qds_mdio_name_for_muxval(muxval);
const char *name = ls2080a_qds_mdio_name_for_muxval(muxval);
if (!name) {
printf("No bus for muxval %x\n", muxval);
@ -343,7 +343,7 @@ struct mii_dev *mii_dev_for_muxval(u8 muxval)
return bus;
}
static void ls2085a_qds_enable_SFP_TX(u8 muxval)
static void ls2080a_qds_enable_SFP_TX(u8 muxval)
{
u8 brdcfg9;
@ -353,7 +353,7 @@ static void ls2085a_qds_enable_SFP_TX(u8 muxval)
QIXIS_WRITE(brdcfg[9], brdcfg9);
}
static void ls2085a_qds_mux_mdio(u8 muxval)
static void ls2080a_qds_mux_mdio(u8 muxval)
{
u8 brdcfg4;
@ -365,54 +365,54 @@ static void ls2085a_qds_mux_mdio(u8 muxval)
}
}
static int ls2085a_qds_mdio_read(struct mii_dev *bus, int addr,
static int ls2080a_qds_mdio_read(struct mii_dev *bus, int addr,
int devad, int regnum)
{
struct ls2085a_qds_mdio *priv = bus->priv;
struct ls2080a_qds_mdio *priv = bus->priv;
ls2085a_qds_mux_mdio(priv->muxval);
ls2080a_qds_mux_mdio(priv->muxval);
return priv->realbus->read(priv->realbus, addr, devad, regnum);
}
static int ls2085a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
static int ls2080a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
int regnum, u16 value)
{
struct ls2085a_qds_mdio *priv = bus->priv;
struct ls2080a_qds_mdio *priv = bus->priv;
ls2085a_qds_mux_mdio(priv->muxval);
ls2080a_qds_mux_mdio(priv->muxval);
return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
}
static int ls2085a_qds_mdio_reset(struct mii_dev *bus)
static int ls2080a_qds_mdio_reset(struct mii_dev *bus)
{
struct ls2085a_qds_mdio *priv = bus->priv;
struct ls2080a_qds_mdio *priv = bus->priv;
return priv->realbus->reset(priv->realbus);
}
static int ls2085a_qds_mdio_init(char *realbusname, u8 muxval)
static int ls2080a_qds_mdio_init(char *realbusname, u8 muxval)
{
struct ls2085a_qds_mdio *pmdio;
struct ls2080a_qds_mdio *pmdio;
struct mii_dev *bus = mdio_alloc();
if (!bus) {
printf("Failed to allocate ls2085a_qds MDIO bus\n");
printf("Failed to allocate ls2080a_qds MDIO bus\n");
return -1;
}
pmdio = malloc(sizeof(*pmdio));
if (!pmdio) {
printf("Failed to allocate ls2085a_qds private data\n");
printf("Failed to allocate ls2080a_qds private data\n");
free(bus);
return -1;
}
bus->read = ls2085a_qds_mdio_read;
bus->write = ls2085a_qds_mdio_write;
bus->reset = ls2085a_qds_mdio_reset;
sprintf(bus->name, ls2085a_qds_mdio_name_for_muxval(muxval));
bus->read = ls2080a_qds_mdio_read;
bus->write = ls2080a_qds_mdio_write;
bus->reset = ls2080a_qds_mdio_reset;
sprintf(bus->name, ls2080a_qds_mdio_name_for_muxval(muxval));
pmdio->realbus = miiphy_get_dev_by_name(realbusname);
@ -474,8 +474,8 @@ static void initialize_dpmac_to_slot(void)
serdes1_prtcl);
break;
default:
printf("qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
serdes1_prtcl);
printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
__func__, serdes1_prtcl);
break;
}
@ -505,13 +505,13 @@ static void initialize_dpmac_to_slot(void)
}
break;
default:
printf("qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
serdes2_prtcl);
printf(" %s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
__func__ , serdes2_prtcl);
break;
}
}
void ls2085a_handle_phy_interface_sgmii(int dpmac_id)
void ls2080a_handle_phy_interface_sgmii(int dpmac_id)
{
int lane, slot;
struct mii_dev *bus;
@ -580,8 +580,8 @@ void ls2085a_handle_phy_interface_sgmii(int dpmac_id)
}
break;
default:
printf("qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
serdes1_prtcl);
printf("%s qds: WRIOP: Unsupported SerDes1 Protocol 0x%02x\n",
__func__ , serdes1_prtcl);
break;
}
@ -626,13 +626,13 @@ serdes2:
}
break;
default:
printf("qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
serdes2_prtcl);
printf("%s qds: WRIOP: Unsupported SerDes2 Protocol 0x%02x\n",
__func__, serdes2_prtcl);
break;
}
}
void ls2085a_handle_phy_interface_qsgmii(int dpmac_id)
void ls2080a_handle_phy_interface_qsgmii(int dpmac_id)
{
int lane = 0, slot;
struct mii_dev *bus;
@ -706,7 +706,7 @@ void ls2085a_handle_phy_interface_qsgmii(int dpmac_id)
qsgmii_configure_repeater(dpmac_id);
}
void ls2085a_handle_phy_interface_xsgmii(int i)
void ls2080a_handle_phy_interface_xsgmii(int i)
{
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
@ -725,7 +725,7 @@ void ls2085a_handle_phy_interface_xsgmii(int i)
* error.
*/
wriop_set_phy_address(i, i + 4);
ls2085a_qds_enable_SFP_TX(SFP_TX);
ls2080a_qds_enable_SFP_TX(SFP_TX);
break;
default:
@ -778,25 +778,25 @@ int board_eth_init(bd_t *bis)
fm_memac_mdio_init(bis, memac_mdio1_info);
/* Register the muxing front-ends to the MDIO buses */
ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1);
ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT2);
ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT3);
ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT4);
ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT5);
ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT6);
ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT1);
ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT2);
ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT3);
ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT4);
ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT5);
ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO1_NAME, EMI1_SLOT6);
ls2085a_qds_mdio_init(DEFAULT_WRIOP_MDIO2_NAME, EMI2);
ls2080a_qds_mdio_init(DEFAULT_WRIOP_MDIO2_NAME, EMI2);
for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
switch (wriop_get_enet_if(i)) {
case PHY_INTERFACE_MODE_QSGMII:
ls2085a_handle_phy_interface_qsgmii(i);
ls2080a_handle_phy_interface_qsgmii(i);
break;
case PHY_INTERFACE_MODE_SGMII:
ls2085a_handle_phy_interface_sgmii(i);
ls2080a_handle_phy_interface_sgmii(i);
break;
case PHY_INTERFACE_MODE_XGMII:
ls2085a_handle_phy_interface_xsgmii(i);
ls2080a_handle_phy_interface_xsgmii(i);
break;
default:
break;

View file

@ -21,7 +21,7 @@
#include <hwconfig.h>
#include "../common/qixis.h"
#include "ls2085aqds_qixis.h"
#include "ls2080aqds_qixis.h"
#define PIN_MUX_SEL_SDHC 0x00
#define PIN_MUX_SEL_DSPI 0x0a
@ -226,11 +226,13 @@ void detail_board_ddr_info(void)
puts("\nDDR ");
print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
print_ddr_info(0);
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
if (gd->bd->bi_dram[2].size) {
puts("\nDP-DDR ");
print_size(gd->bd->bi_dram[2].size, "");
print_ddr_info(CONFIG_DP_DDR_CTRL);
}
#endif
}
int dram_init(void)
@ -294,6 +296,7 @@ void fdt_fixup_board_enet(void *fdt)
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
int err;
u64 base[CONFIG_NR_DRAM_BANKS];
u64 size[CONFIG_NR_DRAM_BANKS];
@ -309,7 +312,9 @@ int ft_board_setup(void *blob, bd_t *bd)
#ifdef CONFIG_FSL_MC_ENET
fdt_fixup_board_enet(blob);
fsl_mc_ldpaa_exit(bd);
err = fsl_mc_ldpaa_exit(bd);
if (err)
return err;
#endif
return 0;

View file

@ -1,8 +1,8 @@
if TARGET_LS2085AQDS
if TARGET_LS2080ARDB
config SYS_BOARD
default "ls2085aqds"
default "ls2080ardb"
config SYS_VENDOR
default "freescale"
@ -11,6 +11,6 @@ config SYS_SOC
default "fsl-layerscape"
config SYS_CONFIG_NAME
default "ls2085aqds"
default "ls2080ardb"
endif

View file

@ -0,0 +1,10 @@
LS2080A BOARD
M: Prabhakar Kushwaha <prabhakar@freescale.com>
S: Maintained
F: board/freescale/ls2080ardb/
F: board/freescale/ls2080a/ls2080ardb.c
F: include/configs/ls2080ardb.h
F: configs/ls2080ardb_defconfig
F: configs/ls2080ardb_nand_defconfig
F: configs/ls2085ardb_defconfig
F: configs/ls2085ardb_nand_defconfig

View file

@ -4,5 +4,5 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += ls2085ardb.o eth_ls2085rdb.o
obj-y += ls2080ardb.o eth_ls2080rdb.o
obj-y += ddr.o

View file

@ -1,17 +1,17 @@
Overview
--------
The LS2085A Reference Design (RDB) is a high-performance computing,
evaluation, and development platform that supports the QorIQ LS2085A
The LS2080A Reference Design (RDB) is a high-performance computing,
evaluation, and development platform that supports the QorIQ LS2080A
Layerscape Architecture processor.
LS2085A SoC Overview
LS2080A SoC Overview
------------------
The LS2085A integrated multicore processor combines eight ARM Cortex-A57
The LS2080A integrated multicore processor combines eight ARM Cortex-A57
processor cores with high-performance data path acceleration logic and network
and peripheral bus interfaces required for networking, telecom/datacom,
wireless infrastructure, and mil/aerospace applications.
The LS2085A SoC includes the following function and features:
The LS2080A SoC includes the following function and features:
- Eight 64-bit ARM Cortex-A57 CPUs
- 1 MB platform cache with ECC
@ -48,7 +48,7 @@ The LS2085A SoC includes the following function and features:
- Service processor (SP) provides pre-boot initialization and secure-boot
capabilities
LS2085ARDB board Overview
LS2080ARDB board Overview
-----------------------
- SERDES Connections, 16 lanes supporting:
- PCI Express - 3.0

View file

@ -15,7 +15,9 @@ void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
{
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
u8 dq_mapping_0, dq_mapping_2, dq_mapping_3;
#endif
const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
ulong ddr_freq;
int slot;
@ -79,7 +81,7 @@ found:
pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
pbsp->wrlvl_ctl_3);
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
if (ctrl_num == CONFIG_DP_DDR_CTRL) {
/* force DDR bus width to 32 bits */
popts->data_bus_width = 1;
@ -114,6 +116,7 @@ found:
pdimm[slot].dq_mapping[16] = 0;
pdimm[slot].dq_mapping[17] = 0;
}
#endif
/* To work at higher than 1333MT/s */
popts->half_strength_driver_enable = 0;
/*

View file

@ -97,7 +97,7 @@ int board_eth_init(bd_t *bis)
break;
default:
printf("SerDes1 protocol 0x%x is not supported on LS2085aRDB\n",
printf("SerDes1 protocol 0x%x is not supported on LS2080aRDB\n",
srds_s1);
break;
}

View file

@ -20,7 +20,7 @@
#include <asm/arch/soc.h>
#include "../common/qixis.h"
#include "ls2085ardb_qixis.h"
#include "ls2080ardb_qixis.h"
#define PIN_MUX_SEL_SDHC 0x00
#define PIN_MUX_SEL_DSPI 0x0a
@ -192,11 +192,13 @@ void detail_board_ddr_info(void)
puts("\nDDR ");
print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
print_ddr_info(0);
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
if (gd->bd->bi_dram[2].size) {
puts("\nDP-DDR ");
print_size(gd->bd->bi_dram[2].size, "");
print_ddr_info(CONFIG_DP_DDR_CTRL);
}
#endif
}
int dram_init(void)
@ -260,6 +262,7 @@ void fdt_fixup_board_enet(void *fdt)
#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, bd_t *bd)
{
int err;
u64 base[CONFIG_NR_DRAM_BANKS];
u64 size[CONFIG_NR_DRAM_BANKS];
@ -275,7 +278,9 @@ int ft_board_setup(void *blob, bd_t *bd)
#ifdef CONFIG_FSL_MC_ENET
fdt_fixup_board_enet(blob);
fsl_mc_ldpaa_exit(bd);
err = fsl_mc_ldpaa_exit(bd);
if (err)
return err;
#endif
return 0;

View file

@ -1,8 +0,0 @@
LS2085A BOARD
M: York Sun <yorksun@freescale.com>
S: Maintained
F: board/freescale/ls2085a/
F: include/configs/ls2085a_emu.h
F: configs/ls2085a_emu_defconfig
F: include/configs/ls2085a_simu.h
F: configs/ls2085a_simu_defconfig

View file

@ -1,8 +0,0 @@
#
# Copyright 2014 Freescale Semiconductor
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += ls2085a.o
obj-y += ddr.o

View file

@ -1,8 +0,0 @@
LS2085A BOARD
M: Prabhakar Kushwaha <prabhakar@freescale.com>
S: Maintained
F: board/freescale/ls2085aqds/
F: board/freescale/ls2085a/ls2085aqds.c
F: include/configs/ls2085aqds.h
F: configs/ls2085aqds_defconfig
F: configs/ls2085aqds_nand_defconfig

View file

@ -1,8 +0,0 @@
LS2085A BOARD
M: Prabhakar Kushwaha <prabhakar@freescale.com>
S: Maintained
F: board/freescale/ls2085ardb/
F: board/freescale/ls2085a/ls2085ardb.c
F: include/configs/ls2085ardb.h
F: configs/ls2085ardb_defconfig
F: configs/ls2085ardb_nand_defconfig

View file

@ -0,0 +1,6 @@
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
CONFIG_ARM=y
CONFIG_TARGET_LS1043AQDS=y
CONFIG_SYS_NS16550=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-qds"
CONFIG_OF_CONTROL=y

View file

@ -0,0 +1,5 @@
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
CONFIG_ARM=y
CONFIG_TARGET_LS1043AQDS=y
CONFIG_SYS_NS16550=y

View file

@ -0,0 +1,3 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1043AQDS=y
CONFIG_SYS_NS16550=y

View file

@ -0,0 +1,5 @@
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
CONFIG_ARM=y
CONFIG_TARGET_LS1043AQDS=y
CONFIG_SYS_NS16550=y

View file

@ -2,3 +2,8 @@ CONFIG_ARM=y
CONFIG_TARGET_LS1043ARDB=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
CONFIG_SYS_NS16550=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
CONFIG_DM_SPI=y

View file

@ -3,3 +3,8 @@ CONFIG_TARGET_LS1043ARDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT,SYS_FSL_DDR4"
CONFIG_SYS_NS16550=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
CONFIG_DM_SPI=y

View file

@ -3,3 +3,8 @@ CONFIG_TARGET_LS1043ARDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SYS_FSL_DDR4"
CONFIG_SYS_NS16550=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1043a-rdb"
CONFIG_OF_CONTROL=y
CONFIG_DM=y
CONFIG_SPI_FLASH=y
CONFIG_DM_SPI=y

View file

@ -0,0 +1,15 @@
CONFIG_ARM=y
CONFIG_TARGET_LS2080A_EMU=y
CONFIG_SYS_EXTRA_OPTIONS="EMU,SYS_FSL_DDR4, LS2080A"
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_ENV_EXISTS is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
CONFIG_SYS_NS16550=y

View file

@ -0,0 +1,16 @@
CONFIG_ARM=y
CONFIG_TARGET_LS2080A_SIMU=y
CONFIG_SYS_EXTRA_OPTIONS="SIMU, LS2080A"
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_ENV_EXISTS is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NFS is not set
# CONFIG_CMD_MISC is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SYS_NS16550=y

View file

@ -0,0 +1,15 @@
CONFIG_ARM=y
CONFIG_TARGET_LS2080AQDS=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_DM_SPI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A"
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_DSPI=y

View file

@ -0,0 +1,9 @@
CONFIG_ARM=y
CONFIG_TARGET_LS2080AQDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A"
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y

View file

@ -0,0 +1,15 @@
CONFIG_ARM=y
CONFIG_TARGET_LS2080ARDB=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_DM_SPI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2080A"
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_DM=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y
CONFIG_FSL_DSPI=y

View file

@ -0,0 +1,9 @@
CONFIG_ARM=y
CONFIG_TARGET_LS2080ARDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, NAND, LS2080A"
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETDEVICES=y
CONFIG_E1000=y
CONFIG_SYS_NS16550=y

View file

@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_TARGET_LS2085A_EMU=y
CONFIG_SYS_EXTRA_OPTIONS="EMU,SYS_FSL_DDR4"
CONFIG_TARGET_LS2080A_EMU=y
CONFIG_SYS_EXTRA_OPTIONS="EMU,SYS_FSL_DDR4, LS2085A"
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set

View file

@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_TARGET_LS2085A_SIMU=y
CONFIG_SYS_EXTRA_OPTIONS="SIMU"
CONFIG_TARGET_LS2080A_SIMU=y
CONFIG_SYS_EXTRA_OPTIONS="SIMU, LS2085A"
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set

View file

@ -1,10 +1,10 @@
CONFIG_ARM=y
CONFIG_TARGET_LS2085AQDS=y
CONFIG_TARGET_LS2080AQDS=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_DM_SPI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2085a-qds"
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-qds"
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2085A"
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y

View file

@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_TARGET_LS2085AQDS=y
CONFIG_TARGET_LS2080AQDS=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND"
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND,LS2085A"
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETDEVICES=y

View file

@ -1,10 +1,10 @@
CONFIG_ARM=y
CONFIG_TARGET_LS2085ARDB=y
CONFIG_TARGET_LS2080ARDB=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_DM_SPI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2085a-rdb"
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2080a-rdb"
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4, LS2085A"
# CONFIG_CMD_SETEXPR is not set
CONFIG_OF_CONTROL=y
CONFIG_NET_RANDOM_ETHADDR=y

View file

@ -1,7 +1,7 @@
CONFIG_ARM=y
CONFIG_TARGET_LS2085ARDB=y
CONFIG_TARGET_LS2080ARDB=y
CONFIG_SPL=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND"
CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4,NAND,LS2085A"
# CONFIG_CMD_SETEXPR is not set
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_NETDEVICES=y

View file

@ -1,4 +1,4 @@
Freescale ARM64 SoCs like LS2085A have ARM TrustZone components like
Freescale ARM64 SoCs like LS2080A have ARM TrustZone components like
TZPC-BP147 (TrustZone Protection Controller) and TZASC-400 (TrustZone
Address Space Controller).
@ -7,7 +7,7 @@ is left to a root-of-trust security software layer (running in EL3
privilege mode), but still some configurations of these peripherals
might be required while the bootloader is executing in EL3 privilege
mode. The following sections define how to turn on these features for
LS2085A like SoCs.
LS2080A like SoCs.
TZPC-BP147 (TrustZone Protection Controller)
============================================

View file

@ -107,14 +107,14 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
goto step2;
#ifdef CONFIG_SYS_FSL_ERRATUM_A008336
#ifdef CONFIG_LS2085A
#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
/* A008336 only applies to general DDR controllers */
if ((ctrl_num == 0) || (ctrl_num == 1))
#endif
ddr_out32(eddrtqcr1, 0x63b30002);
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A008514
#ifdef CONFIG_LS2085A
#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
/* A008514 only applies to DP-DDR controler */
if (ctrl_num == 2)
#endif
@ -423,16 +423,16 @@ step2:
if (getenv_f("ddr_bist", buffer, CONFIG_SYS_CBSIZE) >= 0) {
puts("Running BIST test. This will take a while...");
cs0_config = ddr_in32(&ddr->cs0_config);
cs0_bnds = ddr_in32(&ddr->cs0_bnds);
cs1_bnds = ddr_in32(&ddr->cs1_bnds);
cs2_bnds = ddr_in32(&ddr->cs2_bnds);
cs3_bnds = ddr_in32(&ddr->cs3_bnds);
if (cs0_config & CTLR_INTLV_MASK) {
cs0_bnds = ddr_in32(&cs0_bnds);
cs1_bnds = ddr_in32(&cs1_bnds);
cs2_bnds = ddr_in32(&cs2_bnds);
cs3_bnds = ddr_in32(&cs3_bnds);
/* set bnds to non-interleaving */
ddr_out32(&cs0_bnds, (cs0_bnds & 0xfffefffe) >> 1);
ddr_out32(&cs1_bnds, (cs1_bnds & 0xfffefffe) >> 1);
ddr_out32(&cs2_bnds, (cs2_bnds & 0xfffefffe) >> 1);
ddr_out32(&cs3_bnds, (cs3_bnds & 0xfffefffe) >> 1);
ddr_out32(&ddr->cs0_bnds, (cs0_bnds & 0xfffefffe) >> 1);
ddr_out32(&ddr->cs1_bnds, (cs1_bnds & 0xfffefffe) >> 1);
ddr_out32(&ddr->cs2_bnds, (cs2_bnds & 0xfffefffe) >> 1);
ddr_out32(&ddr->cs3_bnds, (cs3_bnds & 0xfffefffe) >> 1);
}
ddr_out32(&ddr->mtp1, BIST_PATTERN1);
ddr_out32(&ddr->mtp2, BIST_PATTERN1);
@ -469,10 +469,10 @@ step2:
if (cs0_config & CTLR_INTLV_MASK) {
/* restore bnds registers */
ddr_out32(&cs0_bnds, cs0_bnds);
ddr_out32(&cs1_bnds, cs1_bnds);
ddr_out32(&cs2_bnds, cs2_bnds);
ddr_out32(&cs3_bnds, cs3_bnds);
ddr_out32(&ddr->cs0_bnds, cs0_bnds);
ddr_out32(&ddr->cs1_bnds, cs1_bnds);
ddr_out32(&ddr->cs2_bnds, cs2_bnds);
ddr_out32(&ddr->cs3_bnds, cs3_bnds);
}
}
#endif

View file

@ -813,6 +813,7 @@ phys_size_t fsl_ddr_sdram(void)
info.board_need_mem_reset = board_need_mem_reset;
info.board_mem_reset = board_assert_mem_reset;
info.board_mem_de_reset = board_deassert_mem_reset;
remove_unused_controllers(&info);
return __fsl_ddr_sdram(&info);
}

View file

@ -385,3 +385,43 @@ void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl,
ddr_out32(ddrc_debug2_p[i], ddrc_debug2[i]);
}
#endif /* CONFIG_FSL_DDR_SYNC_REFRESH */
void remove_unused_controllers(fsl_ddr_info_t *info)
{
#ifdef CONFIG_FSL_LSCH3
int i;
u64 nodeid;
void *hnf_sam_ctrl = (void *)(CCI_HN_F_0_BASE + CCN_HN_F_SAM_CTL);
bool ddr0_used = false;
bool ddr1_used = false;
for (i = 0; i < 8; i++) {
nodeid = in_le64(hnf_sam_ctrl) & CCN_HN_F_SAM_NODEID_MASK;
if (nodeid == CCN_HN_F_SAM_NODEID_DDR0) {
ddr0_used = true;
} else if (nodeid == CCN_HN_F_SAM_NODEID_DDR1) {
ddr1_used = true;
} else {
printf("Unknown nodeid in HN-F SAM control: 0x%llx\n",
nodeid);
}
hnf_sam_ctrl += (CCI_HN_F_1_BASE - CCI_HN_F_0_BASE);
}
if (!ddr0_used && !ddr1_used) {
printf("Invalid configuration in HN-F SAM control\n");
return;
}
if (!ddr0_used && info->first_ctrl == 0) {
info->first_ctrl = 1;
info->num_ctrls = 1;
debug("First DDR controller disabled\n");
return;
}
if (!ddr1_used && info->first_ctrl + info->num_ctrls > 1) {
info->num_ctrls = 1;
debug("Second DDR controller disabled\n");
}
#endif
}

View file

@ -10,5 +10,6 @@ obj-y += mc.o \
dpmng.o \
dprc.o \
dpbp.o \
dpni.o
dpni.o \
dpmac.o
obj-y += dpio/

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