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https://github.com/AsahiLinux/u-boot
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ARM: k2g: Add pin mux data
Add pin mux data for k2g-evm Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
This commit is contained in:
Vitaly Andrianov
Tom Rini
parent
5dd6af2ecb
commit
dd78b8cf30
2 changed files with 316 additions and 0 deletions
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@ -8,6 +8,7 @@
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*/
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#include <common.h>
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#include <asm/arch/clock.h>
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#include "mux-k2g.h"
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#define SYS_CLK 24000000
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@ -61,6 +62,8 @@ int board_early_init_f(void)
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{
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init_plls();
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k2g_mux_config();
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return 0;
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}
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#endif
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313
board/ti/ks2_evm/mux-k2g.h
Normal file
313
board/ti/ks2_evm/mux-k2g.h
Normal file
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@ -0,0 +1,313 @@
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/*
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* K2G EVM: Pinmux configuration
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*
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* (C) Copyright 2015
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/mux-k2g.h>
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#include <asm/arch/hardware.h>
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struct pin_cfg k2g_evm_pin_cfg[] = {
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/* GPMC */
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{ 0, MODE(0) }, /* GPMCAD0 */
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{ 1, MODE(0) }, /* GPMCAD1 */
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{ 2, MODE(0) }, /* GPMCAD2 */
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{ 3, MODE(0) }, /* GPMCAD3 */
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{ 4, MODE(0) }, /* GPMCAD4 */
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{ 5, MODE(0) }, /* GPMCAD5 */
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{ 6, MODE(0) }, /* GPMCAD6 */
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{ 7, MODE(0) }, /* GPMCAD7 */
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{ 8, MODE(0) }, /* GPMCAD8 */
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{ 9, MODE(0) }, /* GPMCAD9 */
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{ 10, MODE(0) }, /* GPMCAD10 */
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{ 11, MODE(0) }, /* GPMCAD11 */
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{ 12, MODE(0) }, /* GPMCAD12 */
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{ 13, MODE(0) }, /* GPMCAD13 */
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{ 14, MODE(0) }, /* GPMCAD14 */
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{ 15, MODE(0) }, /* GPMCAD15 */
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{ 17, MODE(0) }, /* GPMCADVNALE */
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{ 18, MODE(0) }, /* GPMCOENREN */
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{ 19, MODE(0) }, /* GPMCWEN */
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{ 20, MODE(0) }, /* GPMCBE0NCLE */
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{ 22, MODE(0) }, /* GPMCWAIT0 */
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{ 24, MODE(0) }, /* GPMCWPN */
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{ 26, MODE(0) }, /* GPMCCSN0 */
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/* GPIOs */
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{ 16, MODE(3) | PIN_IEN }, /* GPIO0_16 - PRSNT1# */
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{ 21, MODE(3) | PIN_IEN }, /* GPIO0_21 - DC_BRD_DET */
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{ 82, MODE(3) | PIN_IEN }, /* GPIO0_82 - TPS_INT1 */
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{ 83, MODE(3) }, /* GPIO0_83 - TPS_SLEEP */
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{ 84, MODE(3) }, /* GPIO0_84 - SEL_HDMIn_GPIO */
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{ 87, MODE(3) }, /* GPIO0_87 - SD_LP2996A */
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{ 106, MODE(3) | PIN_IEN}, /* GPIO0_100 - SOC_INT */
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{ 201, MODE(3) | PIN_IEN}, /* GPIO1_26 - GPIO_EXP_INT */
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{ 202, MODE(3) }, /* GPIO1_27 - SEL_LCDn_GPIO */
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{ 203, MODE(3) | PIN_IEN}, /* GPIO1_28 - SOC_MLB_GPIO2 */
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{ 204, MODE(3) | PIN_IEN}, /* GPIO1_29 - SOC_PCIE_WAKEn */
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{ 205, MODE(3) | PIN_IEN}, /* GPIO1_30 - BMC_INT1 */
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{ 206, MODE(3) | PIN_IEN}, /* GPIO1_31 - HDMI_INTn*/
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{ 207, MODE(3) | PIN_IEN}, /* GPIO1_32 - CS2000_AUX_OUT */
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{ 208, MODE(3) | PIN_IEN}, /* GPIO1_33 - TEMP_INT */
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{ 209, MODE(3) | PIN_IEN}, /* GPIO1_34 - WLAN_IRQ */
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{ 216, MODE(3) }, /* GPIO1_41 - FLASH_HOLD */
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{ 217, MODE(3) | PIN_IEN}, /* GPIO1_42 - TOUCH_INTn */
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/* MLB */
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{ 23, MODE(2) }, /* SOC_MLBCLK */
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{ 25, MODE(2) }, /* SOC_MLBSIG */
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{ 27, MODE(2) }, /* SOC_MLBDAT */
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/* DSS */
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{ 30, MODE(0) }, /* SOC_DSSDATA23 */
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{ 31, MODE(0) }, /* SOC_DSSDATA22 */
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{ 32, MODE(0) }, /* SOC_DSSDATA21 */
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{ 33, MODE(0) }, /* SOC_DSSDATA20 */
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{ 34, MODE(0) }, /* SOC_DSSDATA19 */
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{ 35, MODE(0) }, /* SOC_DSSDATA18 */
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{ 36, MODE(0) }, /* SOC_DSSDATA17 */
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{ 37, MODE(0) }, /* SOC_DSSDATA16 */
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{ 38, MODE(0) }, /* SOC_DSSDATA15 */
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{ 39, MODE(0) }, /* SOC_DSSDATA14 */
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{ 40, MODE(0) }, /* SOC_DSSDATA13 */
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{ 41, MODE(0) }, /* SOC_DSSDATA12 */
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{ 42, MODE(0) }, /* SOC_DSSDATA11 */
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{ 43, MODE(0) }, /* SOC_DSSDATA10 */
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{ 44, MODE(0) }, /* SOC_DSSDATA9 */
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{ 45, MODE(0) }, /* SOC_DSSDATA8 */
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{ 46, MODE(0) }, /* SOC_DSSDATA7 */
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{ 47, MODE(0) }, /* SOC_DSSDATA6 */
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{ 48, MODE(0) }, /* SOC_DSSDATA5 */
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{ 49, MODE(0) }, /* SOC_DSSDATA4 */
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{ 50, MODE(0) }, /* SOC_DSSDATA3 */
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{ 51, MODE(0) }, /* SOC_DSSDATA2 */
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{ 52, MODE(0) }, /* SOC_DSSDATA1 */
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{ 53, MODE(0) }, /* SOC_DSSDATA0 */
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{ 54, MODE(0) }, /* SOC_DSSVSYNC */
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{ 55, MODE(0) }, /* SOC_DSSHSYNC */
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{ 56, MODE(0) }, /* SOC_DSSPCLK */
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{ 57, MODE(0) }, /* SOC_DSS_DE */
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{ 58, MODE(0) }, /* SOC_DSS_FID */
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{ 221, MODE(4) }, /* PWM0 - SOC_BACKLIGHT_PWM */
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/* MMC1 */
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{ 59, MODE(0) }, /* SOC_MMC1_DAT7 */
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{ 60, MODE(0) }, /* SOC_MMC1_DAT6 */
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{ 61, MODE(0) }, /* SOC_MMC1_DAT5 */
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{ 62, MODE(0) }, /* SOC_MMC1_DAT4 */
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{ 63, MODE(0) }, /* SOC_MMC1_DAT3 */
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{ 64, MODE(0) }, /* SOC_MMC1_DAT2 */
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{ 65, MODE(0) }, /* SOC_MMC1_DAT1 */
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{ 66, MODE(0) }, /* SOC_MMC1_DAT0 */
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{ 67, MODE(0) }, /* SOC_MMC1_CLK */
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{ 68, MODE(0) }, /* SOC_MMC1_CMD */
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{ 69, MODE(0) }, /* MMC1SDCD TP125 */
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{ 70, MODE(0) }, /* SOC_MMC1_SDWP */
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{ 71, MODE(0) }, /* MMC1POW TP124 */
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/* RGMII */
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{ 72, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXCLK */
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{ 77, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXD3 */
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{ 78, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXD2 */
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{ 79, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXD1 */
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{ 80, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXD0 */
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{ 81, MODE(1) | PIN_IEN }, /* SOC_RGMII_RXCTL */
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{ 85, MODE(1) }, /* SOC_RGMII_TXCLK */
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{ 91, MODE(1) }, /* SOC_RGMII_TXD3 */
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{ 92, MODE(1) }, /* SOC_RGMII_TXD2 */
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{ 93, MODE(1) }, /* SOC_RGMII_TXD1 */
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{ 94, MODE(1) }, /* SOC_RGMII_TXD0 */
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{ 95, MODE(1) }, /* SOC_RGMII_TXCTL */
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{ 98, MODE(0) }, /* SOC_MDIO_DATA */
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{ 99, MODE(0) }, /* SOC_MDIO_CLK */
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/* PWM */
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{ 73, MODE(4) }, /* SOC_EHRPWM3A */
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{ 74, MODE(4) }, /* SOC_EHRPWM3B */
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{ 75, MODE(4) }, /* SOC_EHRPWM3_SYNCI */
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{ 76, MODE(4) }, /* SOC_EHRPWM3_SYNCO */
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{ 96, MODE(4) }, /* SOC_EHRPWM_TRIPZONE_INPUT3 */
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{ 198, MODE(4) }, /* SOC_EHRPWM_TRIPZONE_INPUT4 */
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{ 199, MODE(4) }, /* SOC_EHRPWM4A */
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{ 200, MODE(4) }, /* SOC_EHRPWM4B */
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{ 218, MODE(4) }, /* SOC_EHRPWM_TRIPZONE_INPUT5 */
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{ 219, MODE(4) }, /* SOC_EHRPWM5A */
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{ 220, MODE(4) }, /* SOC_EHRPWM5B */
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{ 222, MODE(4) }, /* SOC_ECAP1_IN_PWM1_OUT */
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/* SPI3 */
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{ 86, MODE(1) }, /* SOC_SPI3_SCS0 */
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{ 88, MODE(1) }, /* SOC_SPI3_CLK */
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{ 89, MODE(1) }, /* SOC_SPI3_MISO */
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{ 90, MODE(1) }, /* SOC_SPI3_MOSI */
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/* CLK */
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{ 97, MODE(0) }, /* SMD - TP132 */
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/* SPI0 */
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{ 100, MODE(0) }, /* SOC_SPI0_SCS0 */
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{ 101, MODE(0) }, /* SOC_SPI0_SCS1 */
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{ 102, MODE(0) }, /* SOC_SPI0_CLK */
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{ 103, MODE(0) }, /* SOC_SPI0_MISO */
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{ 104, MODE(0) }, /* SOC_SPI0_MOSI */
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/* SPI1 NORFLASH */
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{ 105, MODE(0) }, /* SOC_SPI1_SCS0 */
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{ 107, MODE(0) }, /* SOC_SPI1_CLK */
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{ 108, MODE(0) }, /* SOC_SPI1_MISO */
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{ 109, MODE(0) }, /* SOC_SPI1_MOSI */
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/* SPI2 */
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{ 110, MODE(0) }, /* SOC_SPI2_SCS0 */
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{ 111, MODE(1) }, /* SOC_HOUT */
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{ 112, MODE(0) }, /* SOC_SPI2_CLK */
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{ 113, MODE(0) }, /* SOC_SPI2_MISO */
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{ 114, MODE(0) }, /* SOC_SPI2_MOSI */
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/* UART0 */
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{ 115, MODE(0) }, /* SOC_UART0_RXD */
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{ 116, MODE(0) }, /* SOC_UART0_TXD */
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{ 117, MODE(0) }, /* SOC_UART0_CTSn */
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{ 118, MODE(0) }, /* SOC_UART0_RTSn */
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/* UART1 */
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{ 119, MODE(0) }, /* SOC_UART1_RXD */
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{ 120, MODE(0) }, /* SOC_UART1_TXD */
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{ 121, MODE(0) }, /* SOC_UART1_CTSn */
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{ 122, MODE(0) }, /* SOC_UART1_RTSn */
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/* UART2 */
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{ 123, MODE(0) }, /* SOC_UART2_RXD */
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{ 124, MODE(0) }, /* SOC_UART2_TXD */
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{ 125, MODE(0) }, /* UART0_TXVR_EN */
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{ 126, MODE(4) }, /* SOC_CPTS_TS_COMP */
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/* DCAN */
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{ 127, MODE(0) }, /* SOC_DCAN0_TX */
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{ 128, MODE(0) }, /* SOC_DCAN0_RX */
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{ 137, MODE(1) }, /* SOC_DCAN1_TX */
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{ 138, MODE(1) }, /* SOC_DCAN1_RX */
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/* QSPI */
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{ 129, MODE(0) }, /* SOC_QSPI_CLK */
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{ 130, MODE(0) }, /* SOC_QSPI_RTCLK */
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{ 131, MODE(0) }, /* SOC_QSPI_D0 */
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{ 132, MODE(0) }, /* SOC_QSPI_D1 */
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{ 133, MODE(0) }, /* SOC_QSPI_D2 */
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{ 134, MODE(0) }, /* SOC_QSPI_D3 */
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{ 135, MODE(0) }, /* SOC_QSPI_CSN0 */
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{ 136, MODE(1) }, /* DNI <-> WLAN_SLOW_CLK */
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/* MCASP2 */
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{ 139, MODE(3) }, /* SOC_MCASP2AXR0 - (GPIO0_108)SOC_LED0 */
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{ 140, MODE(4) }, /* SOC_MCASP2AXR1 */
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{ 141, MODE(4) }, /* SOC_MCASP2AXR2 */
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{ 142, MODE(4) }, /* SOC_MCASP2AXR3 */
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{ 143, MODE(4) }, /* SOC_MCASP2AXR4 */
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{ 144, MODE(4) }, /* SOC_MCASP2AXR5 */
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{ 145, MODE(4) }, /* SOC_McASP2ACLKR */
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{ 146, MODE(4) }, /* SOC_McASP2FSR */
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{ 147, MODE(4) }, /* SOC_McASP2AHCLKR */
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{ 148, MODE(3) }, /* GPIO0_117 - WLAN_TRANS_EN */
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{ 149, MODE(4) }, /* SOC_McASP2FSX */
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{ 150, MODE(4) }, /* SOC_McASP2AHCLKX */
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{ 151, MODE(4) }, /* SOC_McASP2ACLKX */
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/* MCASP1 */
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{ 152, MODE(4) }, /* SOC_MCASP1ACLKR */
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{ 153, MODE(4) }, /* SOC_MCASP1FSR */
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{ 154, MODE(4) }, /* SOC_MCASP1AHCLKR */
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{ 155, MODE(4) }, /* SOC_MCASP1ACLKX */
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{ 156, MODE(4) }, /* SOC_MCASP1FSX */
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{ 157, MODE(4) }, /* SOC_MCASP1AHCLKX */
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{ 158, MODE(4) }, /* SOC_MCASP1AMUTE */
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{ 159, MODE(4) }, /* SOC_MCASP1AXR0 */
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{ 160, MODE(4) }, /* SOC_MCASP1AXR1 */
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{ 161, MODE(4) }, /* SOC_MCASP1AXR2 */
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{ 162, MODE(4) }, /* SOC_MCASP1AXR3 */
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{ 163, MODE(4) }, /* SOC_MCASP1AXR4 */
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{ 164, MODE(4) }, /* SOC_MCASP1AXR5 */
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{ 165, MODE(4) }, /* SOC_MCASP1AXR6 */
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{ 166, MODE(4) }, /* SOC_MCASP1AXR7 */
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{ 167, MODE(4) }, /* SOC_MCASP1AXR8 */
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{ 168, MODE(4) }, /* SOC_MCASP1AXR9 */
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/* MCASP0 */
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{ 169, MODE(4) }, /* SOC_MCASP0AMUTE */
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{ 170, MODE(4) }, /* SOC_MCASP0ACLKR */
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{ 171, MODE(4) }, /* SOC_MCASP0FSR */
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{ 172, MODE(4) }, /* SOC_MCASP0AHCLKR */
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{ 173, MODE(4) }, /* SOC_MCASP0ACLKX */
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{ 174, MODE(4) }, /* SOC_MCASP0FSX */
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{ 175, MODE(4) }, /* SOC_MCASP0AHCLKX */
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{ 176, MODE(4) }, /* SOC_MCASP0AXR0 */
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{ 177, MODE(4) }, /* SOC_MCASP0AXR1 */
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{ 178, MODE(4) }, /* SOC_MCASP0AXR2 */
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{ 179, MODE(4) }, /* SOC_MCASP0AXR3 */
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{ 180, MODE(4) }, /* SOC_MCASP0AXR4 */
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{ 181, MODE(4) }, /* SOC_MCASP0AXR5 */
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{ 182, MODE(4) }, /* SOC_MCASP0AXR6 */
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{ 183, MODE(4) }, /* SOC_MCASP0AXR7 */
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{ 184, MODE(4) }, /* SOC_MCASP0AXR8 */
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{ 185, MODE(4) }, /* SOC_MCASP0AXR9 */
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{ 186, MODE(3) }, /* SOC_MCASP0AXR10 - (GPIO1_11)SOC_LED1 */
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{ 188, MODE(4) }, /* SOC_MCASP0AXR12 */
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{ 189, MODE(4) }, /* SOC_MCASP0AXR13 */
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{ 190, MODE(4) }, /* SOC_MCASP0AXR14 */
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{ 191, MODE(4) }, /* SOC_MCASP0AXR15 */
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/* MMC0 */
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{ 192, MODE(2) }, /* SOC_MMC0_DAT3 */
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{ 193, MODE(2) }, /* SOC_MMC0_DAT2 */
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{ 194, MODE(2) }, /* SOC_MMC0_DAT1 */
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{ 195, MODE(2) }, /* SOC_MMC0_DAT0 */
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{ 196, MODE(2) }, /* SOC_MMC0_CLK */
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{ 197, MODE(2) }, /* SOC_MMC0_CMD */
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{ 187, MODE(2) }, /* SOC_MMC0_SDCD */
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/* McBSP */
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{ 28, MODE(2) | PIN_IEN }, /* SOC_TIMI1 */
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{ 29, MODE(2) }, /* SOC_TIMO1 */
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{ 210, MODE(2) }, /* SOC_MCBSPDR */
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{ 211, MODE(2) }, /* SOC_MCBSPDX */
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{ 212, MODE(2) }, /* SOC_MCBSPFSX */
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{ 213, MODE(2) }, /* SOC_MCBSPCLKX */
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{ 214, MODE(2) }, /* SOC_MCBSPFSR */
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{ 215, MODE(2) }, /* SOC_MCBSPCLKR */
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/* I2C */
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{ 223, MODE(0) }, /* SOC_I2C0_SCL */
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{ 224, MODE(0) }, /* SOC_I2C0_SDA */
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{ 225, MODE(0) }, /* SOC_I2C1_SCL */
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{ 226, MODE(0) }, /* SOC_I2C1_SDA */
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{ 227, MODE(0) }, /* SOC_I2C2_SCL */
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{ 228, MODE(0) }, /* SOC_I2C2_SDA */
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{ 229, MODE(0) }, /* NMIz */
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{ 230, MODE(0) }, /* LRESETz */
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{ 231, MODE(0) }, /* LRESETNMIENz */
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{ 235, MODE(0) },
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{ 236, MODE(0) },
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{ 237, MODE(0) },
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{ 238, MODE(0) },
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{ 239, MODE(0) },
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{ 240, MODE(0) },
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{ 241, MODE(0) },
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{ 242, MODE(0) },
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{ 243, MODE(0) },
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{ 244, MODE(0) },
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{ 258, MODE(0) }, /* USB0DRVVBUS */
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{ 259, MODE(0) }, /* USB1DRVVBUS */
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{ MAX_PIN_N, }
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};
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void k2g_mux_config(void)
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{
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configure_pin_mux(k2g_evm_pin_cfg);
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}
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