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board: axs10x switch serial port and Ethernet to driver model
With this change Synopsys DesignWare SDP board is switched to driver model for both serial port (serial_dw) and Ethernet (Designware GMAC). This simplifies include/configs/axs101.h and allows for reuse of Linux's Device Tree description. For simplicity Linux's .dts files are not blindly copied but only very few extracts of them are really used (those that are supported in U-Boot at the moment). Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit is contained in:
Alexey Brodkin
parent
db1f17f894
commit
fb2dea60e8
6 changed files with 72 additions and 39 deletions
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@ -2,6 +2,7 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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dtb-$(CONFIG_TARGET_AXS101) += axs10x.dtb
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dtb-$(CONFIG_TARGET_ARCANGEL4) += arcangel4.dtb
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dtb-$(CONFIG_TARGET_TB100) += abilis_tb100.dtb
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45
arch/arc/dts/axs10x.dts
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45
arch/arc/dts/axs10x.dts
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@ -0,0 +1,45 @@
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/*
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* Copyright (C) 2015 Synopsys, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/dts-v1/;
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#include "skeleton.dtsi"
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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console = &uart0;
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};
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clocks {
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apbclk: apbclk {
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compatible = "fixed-clock";
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clock-frequency = <50000000>;
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#clock-cells = <0>;
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};
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};
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uart0: serial0@e0022000 {
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compatible = "snps,dw-apb-uart";
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reg = <0xe0022000 0x1000>;
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reg-shift = <2>;
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reg-io-width = <4>;
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};
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ethernet@e0018000 {
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#interrupt-cells = <1>;
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compatible = "altr,socfpga-stmmac";
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reg = < 0xe0018000 0x2000 >;
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interrupts = < 25 >;
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interrupt-names = "macirq";
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phy-mode = "gmii";
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snps,pbl = < 32 >;
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clocks = <&apbclk>;
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clock-names = "stmmaceth";
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max-speed = <100>;
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};
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};
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@ -7,8 +7,6 @@
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#include <common.h>
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#include <dwmmc.h>
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#include <malloc.h>
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#include <netdev.h>
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#include <phy.h>
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#include "axs10x.h"
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DECLARE_GLOBAL_DATA_PTR;
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@ -35,16 +33,6 @@ int board_mmc_init(bd_t *bis)
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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if (designware_initialize(ARC_DWGMAC_BASE,
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PHY_INTERFACE_MODE_RGMII) >= 0)
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return 1;
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return 0;
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}
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#define AXS_MB_CREG 0xE0011000
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int board_early_init_f(void)
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@ -1,12 +1,21 @@
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CONFIG_ARC=y
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CONFIG_SYS_DCACHE_OFF=y
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CONFIG_ARC_CACHE_LINE_SHIFT=5
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CONFIG_DM_SERIAL=y
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CONFIG_SYS_CLK_FREQ=750000000
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CONFIG_SYS_TEXT_BASE=0x81000000
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CONFIG_DEFAULT_DEVICE_TREE="axs10x"
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CONFIG_SYS_PROMPT="AXS# "
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# CONFIG_CMD_IMLS is not set
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# CONFIG_CMD_FLASH is not set
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_NETDEVICES=y
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CONFIG_CMD_DHCP=y
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CONFIG_CMD_PING=y
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CONFIG_OF_CONTROL=y
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CONFIG_OF_EMBED=y
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CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_DM=y
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CONFIG_CLK=y
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CONFIG_DM_ETH=y
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CONFIG_ETH_DESIGNWARE=y
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CONFIG_USE_PRIVATE_LIBGCC=y
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@ -1,11 +1,20 @@
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CONFIG_ARC=y
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CONFIG_ISA_ARCV2=y
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CONFIG_DM_SERIAL=y
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CONFIG_SYS_CLK_FREQ=50000000
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CONFIG_SYS_TEXT_BASE=0x81000000
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CONFIG_DEFAULT_DEVICE_TREE="axs10x"
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CONFIG_SYS_PROMPT="AXS# "
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# CONFIG_CMD_IMLS is not set
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# CONFIG_CMD_FLASH is not set
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_NETDEVICES=y
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CONFIG_CMD_DHCP=y
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CONFIG_CMD_PING=y
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CONFIG_OF_CONTROL=y
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CONFIG_OF_EMBED=y
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CONFIG_NET_RANDOM_ETHADDR=y
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CONFIG_DM=y
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CONFIG_CLK=y
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CONFIG_DM_ETH=y
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CONFIG_ETH_DESIGNWARE=y
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CONFIG_USE_PRIVATE_LIBGCC=y
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@ -39,6 +39,8 @@
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#define CONFIG_BOARD_TYPES
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#define CONFIG_BOARD_EARLY_INIT_F
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#define CONFIG_OF_LIBFDT
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/*
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* NAND Flash configuration
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*/
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@ -48,28 +50,14 @@
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/*
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* UART configuration
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*
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* CONFIG_CONS_INDEX = 1 - Debug UART
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* CONFIG_CONS_INDEX = 4 - FPGA UART connected to FTDI/USB
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*/
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#define CONFIG_CONS_INDEX 4
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#define CONFIG_DW_SERIAL
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE -4
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#if (CONFIG_CONS_INDEX == 1)
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/* Debug UART */
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# define CONFIG_SYS_NS16550_CLK 33333000
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#else
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/* FPGA UARTs use different clock */
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# define CONFIG_SYS_NS16550_CLK 33333333
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#endif
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#define CONFIG_SYS_NS16550_COM1 (ARC_APB_PERIPHERAL_BASE + 0x5000)
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#define CONFIG_SYS_NS16550_COM2 (ARC_FPGA_PERIPHERAL_BASE + 0x20000)
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#define CONFIG_SYS_NS16550_COM3 (ARC_FPGA_PERIPHERAL_BASE + 0x21000)
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#define CONFIG_SYS_NS16550_COM4 (ARC_FPGA_PERIPHERAL_BASE + 0x22000)
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#define CONFIG_SYS_NS16550_CLK 33333333
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#define CONFIG_SYS_NS16550_MEM32
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#define CONFIG_BAUDRATE 115200
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/*
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* I2C configuration
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*/
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@ -119,18 +107,11 @@
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#define CONFIG_DW_AUTONEG
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/*
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* Command line configuration
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* Commands still not supported in Kconfig
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*/
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_MMC
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#define CONFIG_CMD_NAND
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_RARP
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#define CONFIG_OF_LIBFDT
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#define CONFIG_AUTO_COMPLETE
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#define CONFIG_SYS_MAXARGS 16
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