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Merge branch 'master' of git://git.denx.de/u-boot-arm

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This commit is contained in:
Tom Rini 2015-11-10 13:38:08 -05:00
commit cad0499071
36 changed files with 855 additions and 17 deletions
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2
Makefile
View file

@ -609,6 +609,8 @@ KBUILD_CFLAGS += $(KCFLAGS)
UBOOTINCLUDE := \
-Iinclude \
$(if $(KBUILD_SRC), -I$(srctree)/include) \
$(if $(CONFIG_SYS_THUMB_BUILD), $(if $(CONFIG_HAS_THUMB2),, \
-I$(srctree)/arch/$(ARCH)/thumb1/include),) \
-I$(srctree)/arch/$(ARCH)/include \
-include $(srctree)/include/linux/kconfig.h

5
arch/arm/Kconfig
View file

@ -10,6 +10,9 @@ config ARM64
config HAS_VBAR
bool
config HAS_THUMB2
bool
config CPU_ARM720T
bool
@ -32,9 +35,11 @@ config CPU_ARM1176
config CPU_V7
bool
select HAS_VBAR
select HAS_THUMB2
config CPU_V7M
bool
select HAS_THUMB2
config CPU_PXA
bool

11
arch/arm/cpu/arm926ejs/Makefile
View file

@ -20,3 +20,14 @@ obj-$(CONFIG_MX25) += mx25/
obj-$(CONFIG_MX27) += mx27/
obj-$(if $(filter mxs,$(SOC)),y) += mxs/
obj-$(if $(filter spear,$(SOC)),y) += spear/
# some files can only build in ARM or THUMB2, not THUMB1
ifdef CONFIG_SYS_THUMB_BUILD
ifndef CONFIG_HAS_THUMB2
CFLAGS_cpu.o := -marm
CFLAGS_cache.o := -marm
endif
endif

5
arch/arm/cpu/arm926ejs/cache.c
View file

@ -82,4 +82,9 @@ void flush_dcache_all(void)
/*
* Stub implementations for l2 cache operations
*/
__weak void l2_cache_disable(void) {}
#if defined CONFIG_SYS_THUMB_BUILD
__weak void invalidate_l2_cache(void) {}
#endif

5
arch/arm/cpu/armv7m/stm32f4/flash.c
View file

@ -97,6 +97,9 @@ int flash_erase(flash_info_t *info, int first, int last)
while (readl(&STM32_FLASH->sr) & STM32_FLASH_SR_BSY)
;
/* clear old sector number before writing a new one */
clrbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_SNB_MASK);
if (bank == 0) {
setbits_le32(&STM32_FLASH->cr,
(i << STM32_FLASH_CR_SNB_OFFSET));
@ -114,9 +117,9 @@ int flash_erase(flash_info_t *info, int first, int last)
;
clrbits_le32(&STM32_FLASH->cr, STM32_FLASH_CR_SER);
stm32f4_flash_lock(1);
}
stm32f4_flash_lock(1);
return 0;
}

2
arch/arm/cpu/armv8/cache_v8.c
View file

@ -32,7 +32,7 @@ inline void set_pgtable_table(u64 *page_table, u64 index, u64 *table_addr)
}
/* to activate the MMU we need to set up virtual memory */
static void mmu_setup(void)
__weak void mmu_setup(void)
{
bd_t *bd = gd->bd;
u64 *page_table = (u64 *)gd->arch.tlb_addr, i, j;

1
arch/arm/include/asm/arch-stm32f4/stm32.h
View file

@ -104,6 +104,7 @@ struct stm32_flash_regs {
#define STM32_FLASH_CR_STRT (1 << 16)
#define STM32_FLASH_CR_LOCK (1 << 31)
#define STM32_FLASH_CR_SNB_OFFSET 3
#define STM32_FLASH_CR_SNB_MASK (15 << STM32_FLASH_CR_SNB_OFFSET)
enum clock {
CLOCK_CORE,

4
arch/arm/include/asm/cache.h
View file

@ -16,6 +16,9 @@
/*
* Invalidate L2 Cache using co-proc instruction
*/
#ifdef CONFIG_SYS_THUMB_BUILD
void invalidate_l2_cache(void);
#else
static inline void invalidate_l2_cache(void)
{
unsigned int val=0;
@ -24,6 +27,7 @@ static inline void invalidate_l2_cache(void)
: : "r" (val) : "cc");
isb();
}
#endif
void l2_cache_enable(void);
void l2_cache_disable(void);

11
arch/arm/include/asm/system.h
View file

@ -17,6 +17,7 @@
#define PGTABLE_SIZE (0x10000)
/* 2MB granularity */
#define MMU_SECTION_SHIFT 21
#define MMU_SECTION_SIZE (1 << MMU_SECTION_SHIFT)
#ifndef __ASSEMBLY__
@ -278,11 +279,6 @@ enum {
*/
void mmu_page_table_flush(unsigned long start, unsigned long stop);
#ifdef CONFIG_SYS_NONCACHED_MEMORY
void noncached_init(void);
phys_addr_t noncached_alloc(size_t size, size_t align);
#endif /* CONFIG_SYS_NONCACHED_MEMORY */
#endif /* __ASSEMBLY__ */
#define arch_align_stack(x) (x)
@ -302,6 +298,11 @@ phys_addr_t noncached_alloc(size_t size, size_t align);
void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
enum dcache_option option);
#ifdef CONFIG_SYS_NONCACHED_MEMORY
void noncached_init(void);
phys_addr_t noncached_alloc(size_t size, size_t align);
#endif /* CONFIG_SYS_NONCACHED_MEMORY */
#endif /* __ASSEMBLY__ */
#endif

24
arch/arm/lib/Makefile
View file

@ -60,3 +60,27 @@ obj-$(CONFIG_DEBUG_LL) += debug.o
ifneq (,$(findstring -mabi=aapcs-linux,$(PLATFORM_CPPFLAGS)))
extra-y += eabi_compat.o
endif
# some files can only build in ARM or THUMB2, not THUMB1
ifdef CONFIG_SYS_THUMB_BUILD
ifndef CONFIG_HAS_THUMB2
# for C files, just apend -marm, which will override previous -mthumb*
CFLAGS_cache.o := -marm
CFLAGS_cache-cp15.o := -marm
# For .S, drop -mthumb* and other thumb-related options.
# CFLAGS_REMOVE_* would not have an effet, so AFLAGS_REMOVE_*
# was implemented and is used here.
# Also, define ${target}_NO_THUMB_BUILD for these two targets
# so that the code knows it should not use Thumb.
AFLAGS_REMOVE_memset.o := -mthumb -mthumb-interwork
AFLAGS_REMOVE_memcpy.o := -mthumb -mthumb-interwork
AFLAGS_memset.o := -DMEMSET_NO_THUMB_BUILD
AFLAGS_memcpy.o := -DMEMCPY_NO_THUMB_BUILD
endif
endif

11
arch/arm/lib/cache.c
View file

@ -88,3 +88,14 @@ phys_addr_t noncached_alloc(size_t size, size_t align)
return next;
}
#endif /* CONFIG_SYS_NONCACHED_MEMORY */
#if defined(CONFIG_SYS_THUMB_BUILD)
void invalidate_l2_cache(void)
{
unsigned int val = 0;
asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache"
: : "r" (val) : "cc");
isb();
}
#endif

4
arch/arm/lib/memcpy.S
View file

@ -13,7 +13,7 @@
#include <linux/linkage.h>
#include <asm/assembler.h>
#ifdef CONFIG_SYS_THUMB_BUILD
#if defined(CONFIG_SYS_THUMB_BUILD) && !defined(MEMCPY_NO_THUMB_BUILD)
#define W(instr) instr.w
#else
#define W(instr) instr
@ -62,7 +62,7 @@
/* Prototype: void *memcpy(void *dest, const void *src, size_t n); */
.syntax unified
#ifdef CONFIG_SYS_THUMB_BUILD
#if defined(CONFIG_SYS_THUMB_BUILD) && !defined(MEMCPY_NO_THUMB_BUILD)
.thumb
.thumb_func
#endif

2
arch/arm/lib/memset.S
View file

@ -16,7 +16,7 @@
.align 5
.syntax unified
#ifdef CONFIG_SYS_THUMB_BUILD
#if defined(CONFIG_SYS_THUMB_BUILD) && !defined(MEMSET_NO_THUMB_BUILD)
.thumb
.thumb_func
#endif

6
arch/arm/lib/semihosting.c
View file

@ -31,6 +31,8 @@ static noinline long smh_trap(unsigned int sysnum, void *addr)
register long result asm("r0");
#if defined(CONFIG_ARM64)
asm volatile ("hlt #0xf000" : "=r" (result) : "0"(sysnum), "r"(addr));
#elif defined(CONFIG_CPU_V7M)
asm volatile ("bkpt #0xAB" : "=r" (result) : "0"(sysnum), "r"(addr));
#else
/* Note - untested placeholder */
asm volatile ("svc #0x123456" : "=r" (result) : "0"(sysnum), "r"(addr));
@ -90,7 +92,7 @@ static long smh_read(long fd, void *memp, size_t len)
size_t len;
} read;
debug("%s: fd %ld, memp %p, len %lu\n", __func__, fd, memp, len);
debug("%s: fd %ld, memp %p, len %zu\n", __func__, fd, memp, len);
read.fd = fd;
read.memp = memp;
@ -104,7 +106,7 @@ static long smh_read(long fd, void *memp, size_t len)
* hard to maintain partial read loops and such, just fail
* with an error message.
*/
printf("%s: ERROR ret %ld, fd %ld, len %lu memp %p\n",
printf("%s: ERROR ret %ld, fd %ld, len %zu memp %p\n",
__func__, ret, fd, len, memp);
return -1;
}

4
arch/arm/mach-kirkwood/Kconfig
View file

@ -4,6 +4,9 @@ choice
prompt "Marvell Kirkwood board select"
optional
config TARGET_OPENRD
bool "Marvell OpenRD Board"
config TARGET_DREAMPLUG
bool "DreamPlug Board"
@ -51,6 +54,7 @@ endchoice
config SYS_SOC
default "kirkwood"
source "board/Marvell/openrd/Kconfig"
source "board/Marvell/dreamplug/Kconfig"
source "board/Marvell/guruplug/Kconfig"
source "board/Marvell/sheevaplug/Kconfig"

6
arch/arm/mach-kirkwood/Makefile
View file

@ -9,3 +9,9 @@
obj-y = cpu.o
obj-y += cache.o
obj-y += mpp.o
# cpu.o and cache.o contain CP15 instructions which cannot be run in
# Thumb state, so build them for ARM state even with CONFIG_SYS_THUMB_BUILD
CFLAGS_cpu.o := -marm
CFLAGS_cache.o := -marm

10
arch/arm/mach-orion5x/Makefile
View file

@ -16,3 +16,13 @@ obj-y += timer.o
ifndef CONFIG_SKIP_LOWLEVEL_INIT
obj-y += lowlevel_init.o
endif
# some files can only build in ARM or THUMB2, not THUMB1
ifdef CONFIG_SYS_THUMB_BUILD
ifndef CONFIG_HAS_THUMB2
CFLAGS_cpu.o := -marm
endif
endif

1
arch/arm/mach-tegra/Makefile
View file

@ -15,6 +15,7 @@ obj-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o
obj-$(CONFIG_PWM_TEGRA) += pwm.o
endif
obj-$(CONFIG_ARM64) += arm64-mmu.o
obj-y += ap.o
obj-y += board.o board2.o
obj-y += cache.o

131
arch/arm/mach-tegra/arm64-mmu.c Normal file
View file

@ -0,0 +1,131 @@
/*
* (C) Copyright 2014 - 2015 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com>
* (This file derived from arch/arm/cpu/armv8/zynqmp/cpu.c)
*
* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/system.h>
#include <asm/armv8/mmu.h>
DECLARE_GLOBAL_DATA_PTR;
#define SECTION_SHIFT_L1 30UL
#define SECTION_SHIFT_L2 21UL
#define BLOCK_SIZE_L0 0x8000000000UL
#define BLOCK_SIZE_L1 (1 << SECTION_SHIFT_L1)
#define BLOCK_SIZE_L2 (1 << SECTION_SHIFT_L2)
#define TCR_TG1_4K (1 << 31)
#define TCR_EPD1_DISABLE (1 << 23)
#define TEGRA_VA_BITS 40
#define TEGRA_TCR TCR_TG1_4K | \
TCR_EPD1_DISABLE | \
TCR_SHARED_OUTER | \
TCR_SHARED_INNER | \
TCR_IRGN_WBWA | \
TCR_ORGN_WBWA | \
TCR_T0SZ(TEGRA_VA_BITS)
#define MEMORY_ATTR PMD_SECT_AF | PMD_SECT_INNER_SHARE | \
PMD_ATTRINDX(MT_NORMAL) | \
PMD_TYPE_SECT
#define DEVICE_ATTR PMD_SECT_AF | PMD_SECT_PXN | \
PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_NGNRNE) | \
PMD_TYPE_SECT
/* 4K size is required to place 512 entries in each level */
#define TLB_TABLE_SIZE 0x1000
/*
* This mmu table looks as below
* Level 0 table contains two entries to 512GB sizes. One is Level1 Table 0
* and other Level1 Table1.
* Level1 Table0 contains entries for each 1GB from 0 to 511GB.
* Level1 Table1 contains entries for each 1GB from 512GB to 1TB.
* Level2 Table0, Level2 Table1, Level2 Table2 and Level2 Table3 contains
* entries for each 2MB starting from 0GB, 1GB, 2GB and 3GB respectively.
*/
void mmu_setup(void)
{
int el;
u64 i, section_l1t0, section_l1t1;
u64 section_l2t0, section_l2t1, section_l2t2, section_l2t3;
u64 *level0_table = (u64 *)gd->arch.tlb_addr;
u64 *level1_table_0 = (u64 *)(gd->arch.tlb_addr + TLB_TABLE_SIZE);
u64 *level1_table_1 = (u64 *)(gd->arch.tlb_addr + (2 * TLB_TABLE_SIZE));
u64 *level2_table_0 = (u64 *)(gd->arch.tlb_addr + (3 * TLB_TABLE_SIZE));
u64 *level2_table_1 = (u64 *)(gd->arch.tlb_addr + (4 * TLB_TABLE_SIZE));
u64 *level2_table_2 = (u64 *)(gd->arch.tlb_addr + (5 * TLB_TABLE_SIZE));
u64 *level2_table_3 = (u64 *)(gd->arch.tlb_addr + (6 * TLB_TABLE_SIZE));
/* Invalidate all table entries */
memset(level0_table, 0, PGTABLE_SIZE);
level0_table[0] =
(u64)level1_table_0 | PMD_TYPE_TABLE;
level0_table[1] =
(u64)level1_table_1 | PMD_TYPE_TABLE;
/*
* set level 1 table 0, covering 0 to 512GB
* set level 1 table 1, covering 512GB to 1TB
*/
section_l1t0 = 0;
section_l1t1 = BLOCK_SIZE_L0;
for (i = 0; i < 512; i++) {
level1_table_0[i] = section_l1t0;
if (i >= 4)
level1_table_0[i] |= MEMORY_ATTR;
level1_table_1[i] = section_l1t1;
level1_table_1[i] |= MEMORY_ATTR;
section_l1t0 += BLOCK_SIZE_L1;
section_l1t1 += BLOCK_SIZE_L1;
}
level1_table_0[0] =
(u64)level2_table_0 | PMD_TYPE_TABLE;
level1_table_0[1] =
(u64)level2_table_1 | PMD_TYPE_TABLE;
level1_table_0[2] =
(u64)level2_table_2 | PMD_TYPE_TABLE;
level1_table_0[3] =
(u64)level2_table_3 | PMD_TYPE_TABLE;
section_l2t0 = 0;
section_l2t1 = section_l2t0 + BLOCK_SIZE_L1; /* 1GB */
section_l2t2 = section_l2t1 + BLOCK_SIZE_L1; /* 2GB */
section_l2t3 = section_l2t2 + BLOCK_SIZE_L1; /* 3GB */
for (i = 0; i < 512; i++) {
level2_table_0[i] = section_l2t0 | DEVICE_ATTR;
level2_table_1[i] = section_l2t1 | DEVICE_ATTR;
level2_table_2[i] = section_l2t2 | MEMORY_ATTR;
level2_table_3[i] = section_l2t3 | MEMORY_ATTR;
section_l2t0 += BLOCK_SIZE_L2;
section_l2t1 += BLOCK_SIZE_L2;
section_l2t2 += BLOCK_SIZE_L2;
section_l2t3 += BLOCK_SIZE_L2;
}
/* flush new MMU table */
flush_dcache_range(gd->arch.tlb_addr,
gd->arch.tlb_addr + gd->arch.tlb_size);
/* point TTBR to the new table */
el = current_el();
set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
TEGRA_TCR, MEMORY_ATTRIBUTES);
set_sctlr(get_sctlr() | CR_M);
}
u64 *arch_get_page_table(void)
{
return (u64 *)(gd->arch.tlb_addr + (3 * TLB_TABLE_SIZE));
}

69
arch/arm/thumb1/include/asm/proc-armv/system.h Normal file
View file

@ -0,0 +1,69 @@
/*
* Thumb-1 drop-in for the linux/include/asm-arm/proc-armv/system.h
*
* (C) Copyright 2015
* Albert ARIBAUD <albert.u.boot@aribaud.net>
*
* The original file does not build in Thumb mode. However, in U-Boot
* we don't use interrupt context, so we can redefine these as empty
* memory barriers, which makes Thumb-1 compiler happy.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/*
* Use the same macro name as linux/include/asm-arm/proc-armv/system.h
* here, so that if the original ever gets included after us, it won't
* try to re-redefine anything.
*/
#ifndef __ASM_PROC_SYSTEM_H
#define __ASM_PROC_SYSTEM_H
/*
* Redefine all original macros with static inline functions containing
* a simple memory barrier, so that they produce the same instruction
* ordering constraints as their original counterparts.
* We use static inline functions rather than macros so that we can tell
* the compiler to not complain about unused arguments.
*/
static inline void local_irq_save(
unsigned long flags __attribute__((unused)))
{
__asm__ __volatile__ ("" : : : "memory");
}
static inline void local_irq_enable(void)
{
__asm__ __volatile__ ("" : : : "memory");
}
static inline void local_irq_disable(void)
{
__asm__ __volatile__ ("" : : : "memory");
}
static inline void __stf(void)
{
__asm__ __volatile__ ("" : : : "memory");
}
static inline void __clf(void)
{
__asm__ __volatile__ ("" : : : "memory");
}
static inline void local_save_flags(
unsigned long flags __attribute__((unused)))
{
__asm__ __volatile__ ("" : : : "memory");
}
static inline void local_irq_restore(
unsigned long flags __attribute__((unused)))
{
__asm__ __volatile__ ("" : : : "memory");
}
#endif /* __ASM_PROC_SYSTEM_H */

12
board/Marvell/openrd/Kconfig Normal file
View file

@ -0,0 +1,12 @@
if TARGET_OPENRD
config SYS_BOARD
default "openrd"
config SYS_VENDOR
default "Marvell"
config SYS_CONFIG_NAME
default "openrd"
endif

12
board/Marvell/openrd/MAINTAINERS Normal file
View file

@ -0,0 +1,12 @@
OPENRD BOARD
M: Albert ARIBAUD <albert-u-boot@aribaud.net>
S: Maintained
F: board/Marvell/openrd/
F: include/configs/openrd.h
F: configs/openrd_base_defconfig
OPENRD_CLIENT BOARD
M: Albert ARIBAUD <albert-u-boot@aribaud.net>
S: Maintained
F: configs/openrd_client_defconfig
F: configs/openrd_ultimate_defconfig

14
board/Marvell/openrd/Makefile Normal file
View file

@ -0,0 +1,14 @@
#
# (C) Copyright 2009
# Net Insight <www.netinsight.net>
# Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
#
# Based on sheevaplug:
# (C) Copyright 2009
# Marvell Semiconductor <www.marvell.com>
# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y := openrd.o

152
board/Marvell/openrd/kwbimage.cfg Normal file
View file

@ -0,0 +1,152 @@
#
# (C) Copyright 2009
# Marvell Semiconductor <www.marvell.com>
# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
#
# SPDX-License-Identifier: GPL-2.0+
#
# Refer doc/README.kwbimage for more details about how-to configure
# and create kirkwood boot image
#
# Boot Media configurations
BOOT_FROM nand
NAND_ECC_MODE default
NAND_PAGE_SIZE 0x0800
# SOC registers configuration using bootrom header extension
# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
# Configure RGMII-0 interface pad voltage to 1.8V
DATA 0xFFD100e0 0x1b1b1b9b
#Dram initalization for SINGLE x16 CL=5 @ 400MHz
DATA 0xFFD01400 0x43000c30 # DDR Configuration register
# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
# bit23-14: zero
# bit24: 1= enable exit self refresh mode on DDR access
# bit25: 1 required
# bit29-26: zero
# bit31-30: 01
DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
# bit 4: 0=addr/cmd in smame cycle
# bit 5: 0=clk is driven during self refresh, we don't care for APX
# bit 6: 0=use recommended falling edge of clk for addr/cmd
# bit14: 0=input buffer always powered up
# bit18: 1=cpu lock transaction enabled
# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
# bit30-28: 3 required
# bit31: 0=no additional STARTBURST delay
DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
# bit3-0: TRAS lsbs
# bit7-4: TRCD
# bit11- 8: TRP
# bit15-12: TWR
# bit19-16: TWTR
# bit20: TRAS msb
# bit23-21: 0x0
# bit27-24: TRRD
# bit31-28: TRTP
DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
# bit6-0: TRFC
# bit8-7: TR2R
# bit10-9: TR2W
# bit12-11: TW2W
# bit31-13: zero required
DATA 0xFFD01410 0x000000cc # DDR Address Control
# bit1-0: 00, Cs0width=x8
# bit3-2: 11, Cs0size=1Gb
# bit5-4: 00, Cs1width=x8
# bit7-6: 11, Cs1size=1Gb
# bit9-8: 00, Cs2width=nonexistent
# bit11-10: 00, Cs2size =nonexistent
# bit13-12: 00, Cs3width=nonexistent
# bit15-14: 00, Cs3size =nonexistent
# bit16: 0, Cs0AddrSel
# bit17: 0, Cs1AddrSel
# bit18: 0, Cs2AddrSel
# bit19: 0, Cs3AddrSel
# bit31-20: 0 required
DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
# bit0: 0, OpenPage enabled
# bit31-1: 0 required
DATA 0xFFD01418 0x00000000 # DDR Operation
# bit3-0: 0x0, DDR cmd
# bit31-4: 0 required
DATA 0xFFD0141C 0x00000C52 # DDR Mode
# bit2-0: 2, BurstLen=2 required
# bit3: 0, BurstType=0 required
# bit6-4: 4, CL=5
# bit7: 0, TestMode=0 normal
# bit8: 0, DLL reset=0 normal
# bit11-9: 6, auto-precharge write recovery ????????????
# bit12: 0, PD must be zero
# bit31-13: 0 required
DATA 0xFFD01420 0x00000042 # DDR Extended Mode
# bit0: 0, DDR DLL enabled
# bit1: 1, DDR drive strength reduced
# bit2: 0, DDR ODT control lsd (disabled)
# bit5-3: 000, required
# bit6: 1, DDR ODT control msb, (disabled)
# bit9-7: 000, required
# bit10: 0, differential DQS enabled
# bit11: 0, required
# bit12: 0, DDR output buffer enabled
# bit31-13: 0 required
DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
# bit2-0: 111, required
# bit3 : 1 , MBUS Burst Chop disabled
# bit6-4: 111, required
# bit7 : 0
# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
# bit9 : 0 , no half clock cycle addition to dataout
# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
# bit15-12: 1111 required
# bit31-16: 0 required
DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
# bit0: 1, Window enabled
# bit1: 0, Write Protect disabled
# bit3-2: 00, CS0 hit selected
# bit23-4: ones, required
# bit31-24: 0x0F, Size (i.e. 256MB)
DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low)
# bit3-0: 0010, (read) M_ODT[0] is asserted during read from DRAM CS1
# bit7-4: 0001, (read) M_ODT[1] is asserted during read from DRAM CS0
# bit19-16: 0010, (write) M_ODT[0] is asserted during write to DRAM CS1.
# bit23-20: 0001, (write) M_ODT[1] is asserted during write to DRAM CS0.
DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
DATA 0xFFD0149C 0x0000E40f # CPU ODT Control
# bit3-0: 1111, internal ODT is asserted during read from DRAM bank 0-3
# bit11-10: 01, M_DQ, M_DM, and M_DQS I/O buffer ODT Select: 150 ohm
# bit13-12: 10, M_STARTBURST_IN I/O buffer ODT Select: 75 ohm
# bit14: 1, M_STARTBURST_IN ODT: Enabled
# bit15: 1, DDR IO ODT Unit: Use ODT block
DATA 0xFFD01480 0x00000001 # DDR Initialization Control
#bit0=1, enable DDR init upon this register write
# End of Header extension
DATA 0x0 0x0

160
board/Marvell/openrd/openrd.c Normal file
View file

@ -0,0 +1,160 @@
/*
* (C) Copyright 2009
* Net Insight <www.netinsight.net>
* Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
*
* Based on sheevaplug.c:
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <miiphy.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include <asm/arch/mpp.h>
#include "openrd.h"
DECLARE_GLOBAL_DATA_PTR;
int board_early_init_f(void)
{
/*
* default gpio configuration
* There are maximum 64 gpios controlled through 2 sets of registers
* the below configuration configures mainly initial LED status
*/
mvebu_config_gpio(OPENRD_OE_VAL_LOW,
OPENRD_OE_VAL_HIGH,
OPENRD_OE_LOW, OPENRD_OE_HIGH);
/* Multi-Purpose Pins Functionality configuration */
static const u32 kwmpp_config[] = {
MPP0_NF_IO2,
MPP1_NF_IO3,
MPP2_NF_IO4,
MPP3_NF_IO5,
MPP4_NF_IO6,
MPP5_NF_IO7,
MPP6_SYSRST_OUTn,
MPP7_GPO,
MPP8_TW_SDA,
MPP9_TW_SCK,
MPP10_UART0_TXD,
MPP11_UART0_RXD,
MPP12_SD_CLK,
MPP13_SD_CMD, /* Alt UART1_TXD */
MPP14_SD_D0, /* Alt UART1_RXD */
MPP15_SD_D1,
MPP16_SD_D2,
MPP17_SD_D3,
MPP18_NF_IO0,
MPP19_NF_IO1,
MPP20_GE1_0,
MPP21_GE1_1,
MPP22_GE1_2,
MPP23_GE1_3,
MPP24_GE1_4,
MPP25_GE1_5,
MPP26_GE1_6,
MPP27_GE1_7,
MPP28_GPIO,
MPP29_TSMP9,
MPP30_GE1_10,
MPP31_GE1_11,
MPP32_GE1_12,
MPP33_GE1_13,
MPP34_GPIO, /* UART1 / SD sel */
MPP35_TDM_CH0_TX_QL,
MPP36_TDM_SPI_CS1,
MPP37_TDM_CH2_TX_QL,
MPP38_TDM_CH2_RX_QL,
MPP39_AUDIO_I2SBCLK,
MPP40_AUDIO_I2SDO,
MPP41_AUDIO_I2SLRC,
MPP42_AUDIO_I2SMCLK,
MPP43_AUDIO_I2SDI,
MPP44_AUDIO_EXTCLK,
MPP45_TDM_PCLK,
MPP46_TDM_FS,
MPP47_TDM_DRX,
MPP48_TDM_DTX,
MPP49_TDM_CH0_RX_QL,
0
};
kirkwood_mpp_conf(kwmpp_config, NULL);
return 0;
}
int board_init(void)
{
/*
* arch number of board
*/
#if defined(CONFIG_BOARD_IS_OPENRD_BASE)
gd->bd->bi_arch_number = MACH_TYPE_OPENRD_BASE;
#elif defined(CONFIG_BOARD_IS_OPENRD_CLIENT)
gd->bd->bi_arch_number = MACH_TYPE_OPENRD_CLIENT;
#elif defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE)
gd->bd->bi_arch_number = MACH_TYPE_OPENRD_ULTIMATE;
#endif
/* adress of boot parameters */
gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
return 0;
}
#ifdef CONFIG_RESET_PHY_R
/* Configure and enable MV88E1116/88E1121 PHY */
void mv_phy_init(char *name)
{
u16 reg;
u16 devadr;
if (miiphy_set_current_dev(name))
return;
/* command to read PHY dev address */
if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) {
printf("Err..%s could not read PHY dev address\n", __func__);
return;
}
/*
* Enable RGMII delay on Tx and Rx for CPU port
* Ref: sec 4.7.2 of chip datasheet
*/
miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
/* reset the phy */
miiphy_reset(name, devadr);
printf(PHY_NO" Initialized on %s\n", name);
}
void reset_phy(void)
{
mv_phy_init("egiga0");
#ifdef CONFIG_BOARD_IS_OPENRD_CLIENT
/* Kirkwood ethernet driver is written with the assumption that in case
* of multiple PHYs, their addresses are consecutive. But unfortunately
* in case of OpenRD-Client, PHY addresses are not consecutive.*/
miiphy_write("egiga1", 0xEE, 0xEE, 24);
#endif
#if defined(CONFIG_BOARD_IS_OPENRD_CLIENT) || \
defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE)
/* configure and initialize both PHY's */
mv_phy_init("egiga1");
#endif
}
#endif /* CONFIG_RESET_PHY_R */

30
board/Marvell/openrd/openrd.h Normal file
View file

@ -0,0 +1,30 @@
/*
* (C) Copyright 2009
* Net Insight <www.netinsight.net>
* Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
*
* Based on sheevaplug.h:
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __OPENRD_BASE_H
#define __OPENRD_BASE_H
#define OPENRD_OE_LOW (~(1<<28)) /* RS232 / RS485 */
#define OPENRD_OE_HIGH (~(1<<2)) /* SD / UART1 */
#define OPENRD_OE_VAL_LOW (0) /* Sel RS232 */
#define OPENRD_OE_VAL_HIGH (1 << 2) /* Sel SD */
/* PHY related */
#define MV88E1116_LED_FCTRL_REG 10
#define MV88E1116_CPRSP_CR3_REG 21
#define MV88E1116_MAC_CTRL_REG 21
#define MV88E1116_PGADR_REG 22
#define MV88E1116_RGMII_TXTM_CTRL (1 << 4)
#define MV88E1116_RGMII_RXTM_CTRL (1 << 5)
#endif /* __OPENRD_BASE_H */

2
board/freescale/ls1043ardb/MAINTAINERS
View file

@ -5,3 +5,5 @@ F: board/freescale/ls1043ardb/
F: board/freescale/ls1043ardb/ls1043ardb.c
F: include/configs/ls1043ardb.h
F: configs/ls1043ardb_defconfig
F: configs/ls1043ardb_nand_defconfig
F: configs/ls1043ardb_sdcard_defconfig

7
configs/openrd_base_defconfig Normal file
View file

@ -0,0 +1,7 @@
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_OPENRD=y
CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_BASE"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set

7
configs/openrd_client_defconfig Normal file
View file

@ -0,0 +1,7 @@
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_OPENRD=y
CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_CLIENT"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set

7
configs/openrd_ultimate_defconfig Normal file
View file

@ -0,0 +1,7 @@
CONFIG_ARM=y
CONFIG_KIRKWOOD=y
CONFIG_TARGET_OPENRD=y
CONFIG_SYS_EXTRA_OPTIONS="BOARD_IS_OPENRD_ULTIMATE"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set

3
doc/README.scrapyard
View file

@ -64,9 +64,6 @@ nhk8815 arm arm926ejs 0abdd9d0 2015-08-30 Nomadik Linu
nhk8815_onenand arm arm926ejs 0abdd9d0 2015-08-30 Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com>
omap3_mvblx arm armv7 8dc372f9 2015-08-30 Michael Jones <michael.jones@matrix-vision.de>
omap3_sdp3430 arm armv7 93b25c08 2015-08-30 Nishanth Menon <nm@ti.com>
openrd_base arm arm926ejs 7a2c1b13 2015-08-30 Prafulla Wadaskar <prafulla@marvell.com>
openrd_client arm arm926ejs 7a2c1b13 2015-08-30 Prafulla Wadaskar <prafulla@marvell.com>
openrd_ultimate arm arm926ejs 7a2c1b13 2015-08-30 Prafulla Wadaskar <prafulla@marvell.com>
otc570 arm arm926ejs 819216dd 2015-08-30 Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
otc570_dataflash arm arm926ejs 819216dd 2015-08-30 Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
palmld arm pxa 35782e9c 2015-08-30 Marek Vasut <marex@denx.de>

10
examples/standalone/Makefile
View file

@ -73,3 +73,13 @@ $(obj)/%.srec: $(obj)/% FORCE
$(obj)/%.bin: OBJCOPYFLAGS := -O binary
$(obj)/%.bin: $(obj)/% FORCE
$(call if_changed,objcopy)
# some files can only build in ARM or THUMB2, not THUMB1
ifdef CONFIG_SYS_THUMB_BUILD
ifndef CONFIG_HAS_THUMB2
CFLAGS_stubs.o := -marm
endif
endif

138
include/configs/openrd.h Normal file
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@ -0,0 +1,138 @@
/*
* (C) Copyright 2009
* Net Insight <www.netinsight.net>
* Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
*
* Based on sheevaplug.h:
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _CONFIG_OPENRD_H
#define _CONFIG_OPENRD_H
/*
* Version number information
*/
#ifdef CONFIG_BOARD_IS_OPENRD_ULTIMATE
# define CONFIG_IDENT_STRING "\nOpenRD-Ultimate"
#else
# ifdef CONFIG_BOARD_IS_OPENRD_CLIENT
# define CONFIG_IDENT_STRING "\nOpenRD-Client"
# else
# ifdef CONFIG_BOARD_IS_OPENRD_BASE
# define CONFIG_IDENT_STRING "\nOpenRD-Base"
# else
# error Unknown OpenRD board specified
# endif
# endif
#endif
/*
* High Level Configuration Options (easy to change)
*/
#define CONFIG_SHEEVA_88SV131 1 /* CPU Core subversion */
#define CONFIG_KW88F6281 1 /* SOC Name */
#define CONFIG_MACH_OPENRD_BASE /* Machine type */
#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
#define CONFIG_SYS_THUMB_BUILD
/*
* Commands configuration
*/
#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
#define CONFIG_SYS_MVFS
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ENV
#define CONFIG_CMD_MII
#define CONFIG_CMD_MMC
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PING
#define CONFIG_CMD_USB
#define CONFIG_CMD_IDE
/*
* mv-common.h should be defined after CMD configs since it used them
* to enable certain macros
*/
#include "mv-common.h"
/*
* Environment variables configurations
*/
#ifdef CONFIG_CMD_NAND
#define CONFIG_ENV_IS_IN_NAND 1
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K */
#else
#define CONFIG_ENV_IS_NOWHERE 1 /* if env in SDRAM */
#endif
/*
* max 4k env size is enough, but in case of nand
* it has to be rounded to sector size
*/
#define CONFIG_ENV_SIZE 0x20000 /* 128k */
#define CONFIG_ENV_ADDR 0x60000
#define CONFIG_ENV_OFFSET 0x60000 /* env starts here */
/*
* Environment is right behind U-Boot in flash. Make sure U-Boot
* doesn't grow into the environment area.
*/
#define CONFIG_BOARD_SIZE_LIMIT CONFIG_ENV_OFFSET
/*
* Default environment variables
*/
#define CONFIG_BOOTCOMMAND "${x_bootcmd_kernel}; " \
"setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \
"${x_bootcmd_usb}; bootm 0x6400000;"
#define MTDIDS_DEFAULT "nand0=nand_mtd"
#define MTDPARTS_DEFAULT "mtdparts=nand_mtd:0x100000@0x000000(uboot),"\
"0x400000@0x100000(uImage),"\
"0x1fb00000@0x500000(rootfs)"
#define CONFIG_EXTRA_ENV_SETTINGS "x_bootargs=console" \
"=ttyS0,115200 "MTDPARTS_DEFAULT " rw ubi.mtd=2,2048\0" \
"x_bootcmd_kernel=nand read 0x6400000 0x100000 0x300000\0" \
"x_bootcmd_usb=usb start\0" \
"x_bootargs_root=root=ubi0:rootfs rootfstype=ubifs\0" \
"mtdids="MTDIDS_DEFAULT"\0" \
"mtdparts="MTDPARTS_DEFAULT"\0"
/*
* Ethernet Driver configuration
*/
#ifdef CONFIG_CMD_NET
# ifdef CONFIG_BOARD_IS_OPENRD_BASE
# define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
# else
# define CONFIG_MVGBE_PORTS {1, 1} /* enable both ports */
# endif
# ifdef CONFIG_BOARD_IS_OPENRD_ULTIMATE
# define CONFIG_PHY_BASE_ADR 0x0
# define PHY_NO "88E1121"
# else
# define CONFIG_PHY_BASE_ADR 0x8
# define PHY_NO "88E1116"
# endif
#endif /* CONFIG_CMD_NET */
/*
* SATA Driver configuration
*/
#ifdef CONFIG_MVSATA_IDE
#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
#define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
#endif /*CONFIG_MVSATA_IDE*/
#ifdef CONFIG_CMD_MMC
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_MVEBU_MMC
#define CONFIG_SYS_MMC_BASE KW_SDIO_BASE
#endif /* CONFIG_CMD_MMC */
#endif /* _CONFIG_OPENRD_BASE_H */

1
include/configs/stm32f429-discovery.h
View file

@ -9,6 +9,7 @@
#define __CONFIG_H
#define CONFIG_STM32F4
#define CONFIG_SYS_THUMB_BUILD
#define CONFIG_STM32F4DISCOVERY
#define CONFIG_OF_LIBFDT

2
include/configs/tegra-common-post.h
View file

@ -19,9 +19,7 @@
#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */
#endif
#ifndef CONFIG_ARM64
#define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */
#endif
#ifndef CONFIG_SPL_BUILD
#define BOOT_TARGET_DEVICES(func) \

1
include/configs/tricorder.h
View file

@ -17,6 +17,7 @@
#define __CONFIG_H
/* High Level Configuration Options */
#define CONFIG_SYS_THUMB_BUILD
#define CONFIG_OMAP /* in a TI OMAP core */
#define CONFIG_OMAP_COMMON
/* Common ARM Erratas */