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https://github.com/AsahiLinux/u-boot
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sunxi: Add support for Allwinner A64 SoCs
The Allwinner A64 SoC is used in the Pine64. This patch adds all bits necessary to compile U-Boot for it running in AArch64 mode. Unfortunately SPL is not ready yet due to legal problems, so we need to boot using the binary boot0 for now. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> [agraf: remove SPL code, move to AArch64] Signed-off-by: Alexander Graf <agraf@suse.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This commit is contained in:
Siarhei Siamashka
Hans de Goede
parent
0ea5a04fbc
commit
d96ebc468d
17 changed files with 694 additions and 20 deletions
564
arch/arm/dts/a64.dtsi
Normal file
564
arch/arm/dts/a64.dtsi
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@ -0,0 +1,564 @@
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/*
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* Copyright (C) 2016 ARM Ltd.
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* based on the Allwinner H3 dtsi:
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* Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/sun4i-a10.h>
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/ {
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compatible = "allwinner,a64";
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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serial3 = &uart3;
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serial4 = &uart4;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <0>;
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enable-method = "psci";
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};
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cpu@1 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <1>;
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enable-method = "psci";
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};
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cpu@2 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <2>;
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enable-method = "psci";
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};
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cpu@3 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <3>;
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enable-method = "psci";
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};
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};
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psci {
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compatible = "arm,psci-0.2", "arm,psci";
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method = "smc";
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cpu_suspend = <0xc4000001>;
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cpu_off = <0x84000002>;
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cpu_on = <0xc4000003>;
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};
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memory {
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device_type = "memory";
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reg = <0x40000000 0>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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osc24M: osc24M_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "osc24M";
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};
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osc32k: osc32k_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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clock-output-names = "osc32k";
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};
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pll1: clk@01c20000 {
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#clock-cells = <0>;
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compatible = "allwinner,sun8i-a23-pll1-clk";
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reg = <0x01c20000 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll1";
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};
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pll6: clk@01c20028 {
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#clock-cells = <1>;
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compatible = "allwinner,sun6i-a31-pll6-clk";
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reg = <0x01c20028 0x4>;
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clocks = <&osc24M>;
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clock-output-names = "pll6", "pll6x2";
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};
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pll6d2: pll6d2_clk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <2>;
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clock-mult = <1>;
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clocks = <&pll6 0>;
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clock-output-names = "pll6d2";
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};
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/* dummy clock until pll6 can be reused */
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pll8: pll8_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <1>;
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clock-output-names = "pll8";
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};
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cpu: cpu_clk@01c20050 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-cpu-clk";
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reg = <0x01c20050 0x4>;
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clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
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clock-output-names = "cpu";
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};
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axi: axi_clk@01c20050 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-axi-clk";
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reg = <0x01c20050 0x4>;
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clocks = <&cpu>;
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clock-output-names = "axi";
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};
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ahb1: ahb1_clk@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun6i-a31-ahb1-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
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clock-output-names = "ahb1";
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};
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ahb2: ahb2_clk@01c2005c {
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#clock-cells = <0>;
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compatible = "allwinner,sun8i-h3-ahb2-clk";
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reg = <0x01c2005c 0x4>;
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clocks = <&ahb1>, <&pll6d2>;
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clock-output-names = "ahb2";
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};
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apb1: apb1_clk@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-apb0-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&ahb1>;
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clock-output-names = "apb1";
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};
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apb2: apb2_clk@01c20058 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-a10-apb1-clk";
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reg = <0x01c20058 0x4>;
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clocks = <&osc32k>, <&osc24M>, <&pll6 1>, <&pll6 1>;
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clock-output-names = "apb2";
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};
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bus_gates: clk@01c20060 {
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#clock-cells = <1>;
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compatible = "allwinner,a64-bus-gates-clk",
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"allwinner,sun8i-h3-bus-gates-clk";
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reg = <0x01c20060 0x14>;
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clocks = <&ahb1>, <&ahb2>, <&apb1>, <&apb2>;
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clock-names = "ahb1", "ahb2", "apb1", "apb2";
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clock-indices = <1>,
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<5>, <6>, <8>,
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<9>, <10>, <13>,
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<14>, <17>, <18>,
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<19>, <20>,
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<21>, <23>,
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<24>, <25>,
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<28>, <29>,
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<32>, <35>,
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<36>, <37>,
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<40>, <43>,
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<44>, <52>, <53>,
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<54>, <64>,
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<65>, <69>, <72>,
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<76>, <77>, <78>,
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<96>, <97>, <98>,
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<101>,
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<112>, <113>,
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<114>, <115>,
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<116>, <135>;
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clock-output-names = "bus_mipidsi",
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"bus_ce", "bus_dma", "bus_mmc0",
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"bus_mmc1", "bus_mmc2", "bus_nand",
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"bus_sdram", "bus_gmac", "bus_ts",
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"bus_hstimer", "bus_spi0",
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"bus_spi1", "bus_otg",
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"bus_otg_ehci0", "bus_ehci0",
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"bus_otg_ohci0", "bus_ohci0",
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"bus_ve", "bus_lcd0",
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"bus_lcd1", "bus_deint",
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"bus_csi", "bus_hdmi",
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"bus_de", "bus_gpu", "bus_msgbox",
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"bus_spinlock", "bus_codec",
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"bus_spdif", "bus_pio", "bus_ths",
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"bus_i2s0", "bus_i2s1", "bus_i2s2",
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"bus_i2c0", "bus_i2c1", "bus_i2c2",
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"bus_scr",
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"bus_uart0", "bus_uart1",
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"bus_uart2", "bus_uart3",
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"bus_uart4", "bus_dbg";
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};
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mmc0_clk: clk@01c20088 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-mmc-clk";
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reg = <0x01c20088 0x4>;
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clocks = <&osc24M>, <&pll6 0>, <&pll8>;
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clock-output-names = "mmc0",
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"mmc0_output",
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"mmc0_sample";
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};
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mmc1_clk: clk@01c2008c {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-mmc-clk";
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reg = <0x01c2008c 0x4>;
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clocks = <&osc24M>, <&pll6 0>, <&pll8>;
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clock-output-names = "mmc1",
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"mmc1_output",
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"mmc1_sample";
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};
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mmc2_clk: clk@01c20090 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-a10-mmc-clk";
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reg = <0x01c20090 0x4>;
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clocks = <&osc24M>, <&pll6 0>, <&pll8>;
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clock-output-names = "mmc2",
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"mmc2_output",
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"mmc2_sample";
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};
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};
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regulators {
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reg_vcc3v3: vcc3v3 {
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compatible = "regulator-fixed";
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regulator-name = "vcc3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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mmc0: mmc@01c0f000 {
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compatible = "allwinner,sun5i-a13-mmc";
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reg = <0x01c0f000 0x1000>;
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clocks = <&bus_gates 8>,
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<&mmc0_clk 0>,
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<&mmc0_clk 1>,
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<&mmc0_clk 2>;
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clock-names = "ahb",
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"mmc",
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"output",
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"sample";
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resets = <&ahb_rst 8>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mmc1: mmc@01c10000 {
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compatible = "allwinner,sun5i-a13-mmc";
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reg = <0x01c10000 0x1000>;
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clocks = <&bus_gates 9>,
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<&mmc1_clk 0>,
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<&mmc1_clk 1>,
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<&mmc1_clk 2>;
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clock-names = "ahb",
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"mmc",
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"output",
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"sample";
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resets = <&ahb_rst 9>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mmc2: mmc@01c11000 {
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compatible = "allwinner,sun5i-a13-mmc";
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reg = <0x01c11000 0x1000>;
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clocks = <&bus_gates 10>,
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<&mmc2_clk 0>,
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<&mmc2_clk 1>,
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<&mmc2_clk 2>;
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clock-names = "ahb",
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"mmc",
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"output",
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"sample";
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resets = <&ahb_rst 10>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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pio: pinctrl@01c20800 {
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compatible = "allwinner,a64-pinctrl";
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reg = <0x01c20800 0x400>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&bus_gates 69>;
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gpio-controller;
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#gpio-cells = <3>;
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interrupt-controller;
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#interrupt-cells = <2>;
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uart0_pins_a: uart0@0 {
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allwinner,pins = "PB8", "PB9";
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allwinner,function = "uart0";
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allwinner,drive = <SUN4I_PINCTRL_10_MA>;
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allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
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};
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uart0_pins_b: uart0@1 {
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allwinner,pins = "PF2", "PF3";
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allwinner,function = "uart0";
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allwinner,drive = <SUN4I_PINCTRL_10_MA>;
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allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
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};
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uart1_pins: uart1@0 {
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allwinner,pins = "PG6", "PG7", "PG8", "PG9";
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allwinner,function = "uart1";
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allwinner,drive = <SUN4I_PINCTRL_10_MA>;
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allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
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};
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uart2_pins: uart2@0 {
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allwinner,pins = "PB0", "PB1", "PB2", "PB3";
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allwinner,function = "uart2";
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allwinner,drive = <SUN4I_PINCTRL_10_MA>;
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allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
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};
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uart3_pins_a: uart3@0 {
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allwinner,pins = "PD0", "PD1";
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allwinner,function = "uart3";
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allwinner,drive = <SUN4I_PINCTRL_10_MA>;
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allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
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};
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uart3_pins_b: uart3@1 {
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allwinner,pins = "PH4", "PH5", "PH6", "PH7";
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allwinner,function = "uart3";
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allwinner,drive = <SUN4I_PINCTRL_10_MA>;
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allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
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};
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uart4_pins: uart4@0 {
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allwinner,pins = "PD2", "PD3", "PD4", "PD5";
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allwinner,function = "uart4";
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allwinner,drive = <SUN4I_PINCTRL_10_MA>;
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allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
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};
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mmc0_pins: mmc0@0 {
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allwinner,pins = "PF0", "PF1", "PF2", "PF3",
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"PF4", "PF5";
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allwinner,function = "mmc0";
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allwinner,drive = <SUN4I_PINCTRL_30_MA>;
|
||||
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
||||
};
|
||||
|
||||
mmc0_default_cd_pin: mmc0_cd_pin@0 {
|
||||
allwinner,pins = "PF6";
|
||||
allwinner,function = "gpio_in";
|
||||
allwinner,drive = <SUN4I_PINCTRL_10_MA>;
|
||||
allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
|
||||
};
|
||||
|
||||
mmc1_pins: mmc1@0 {
|
||||
allwinner,pins = "PG0", "PG1", "PG2", "PG3",
|
||||
"PG4", "PG5";
|
||||
allwinner,function = "mmc1";
|
||||
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
|
||||
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
||||
};
|
||||
|
||||
mmc2_pins: mmc2@0 {
|
||||
allwinner,pins = "PC1", "PC5", "PC6", "PC8",
|
||||
"PC9", "PC10";
|
||||
allwinner,function = "mmc2";
|
||||
allwinner,drive = <SUN4I_PINCTRL_30_MA>;
|
||||
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
|
||||
};
|
||||
};
|
||||
|
||||
ahb_rst: reset@01c202c0 {
|
||||
#reset-cells = <1>;
|
||||
compatible = "allwinner,sun6i-a31-ahb1-reset";
|
||||
reg = <0x01c202c0 0xc>;
|
||||
};
|
||||
|
||||
apb1_rst: reset@01c202d0 {
|
||||
#reset-cells = <1>;
|
||||
compatible = "allwinner,sun6i-a31-clock-reset";
|
||||
reg = <0x01c202d0 0x4>;
|
||||
};
|
||||
|
||||
apb2_rst: reset@01c202d8 {
|
||||
#reset-cells = <1>;
|
||||
compatible = "allwinner,sun6i-a31-clock-reset";
|
||||
reg = <0x01c202d8 0x4>;
|
||||
};
|
||||
|
||||
uart0: serial@01c28000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x01c28000 0x400>;
|
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&bus_gates 112>;
|
||||
resets = <&apb2_rst 16>;
|
||||
reset-names = "apb2";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@01c28400 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x01c28400 0x400>;
|
||||
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&bus_gates 113>;
|
||||
resets = <&apb2_rst 17>;
|
||||
reset-names = "apb2";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@01c28800 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x01c28800 0x400>;
|
||||
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&bus_gates 114>;
|
||||
resets = <&apb2_rst 18>;
|
||||
reset-names = "apb2";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@01c28c00 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x01c28c00 0x400>;
|
||||
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&bus_gates 115>;
|
||||
resets = <&apb2_rst 19>;
|
||||
reset-names = "apb2";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: serial@01c29000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x01c29000 0x400>;
|
||||
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&bus_gates 116>;
|
||||
resets = <&apb2_rst 20>;
|
||||
reset-names = "apb2";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rtc: rtc@01f00000 {
|
||||
compatible = "allwinner,sun6i-a31-rtc";
|
||||
reg = <0x01f00000 0x54>;
|
||||
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
gic: interrupt-controller@{
|
||||
compatible = "arm,gic-400";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
|
||||
reg = <0x01C81000 0x1000>,
|
||||
<0x01C82000 0x2000>,
|
||||
<0x01C84000 0x2000>,
|
||||
<0x01C86000 0x2000>;
|
||||
interrupts = <GIC_PPI 9
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
};
|
||||
};
|
||||
|
|
@ -17,7 +17,8 @@
|
|||
/* clock control module regs definition */
|
||||
#if defined(CONFIG_MACH_SUN8I_A83T)
|
||||
#include <asm/arch/clock_sun8i_a83t.h>
|
||||
#elif defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I)
|
||||
#elif defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || \
|
||||
defined(CONFIG_MACH_SUN50I)
|
||||
#include <asm/arch/clock_sun6i.h>
|
||||
#elif defined(CONFIG_MACH_SUN9I)
|
||||
#include <asm/arch/clock_sun9i.h>
|
||||
|
|
|
|||
|
|
@ -350,10 +350,12 @@ struct sunxi_ccm_reg {
|
|||
#define CCM_HDMI_CTRL_DDC_GATE (0x1 << 30)
|
||||
#define CCM_HDMI_CTRL_GATE (0x1 << 31)
|
||||
|
||||
#ifndef CONFIG_MACH_SUN8I
|
||||
#define MBUS_CLK_DEFAULT 0x81000001 /* PLL6 / 2 */
|
||||
#else
|
||||
#if defined(CONFIG_MACH_SUN50I)
|
||||
#define MBUS_CLK_DEFAULT 0x81000002 /* PLL6x2 / 3 */
|
||||
#elif defined(CONFIG_MACH_SUN8I)
|
||||
#define MBUS_CLK_DEFAULT 0x81000003 /* PLL6 / 4 */
|
||||
#else
|
||||
#define MBUS_CLK_DEFAULT 0x81000001 /* PLL6 / 2 */
|
||||
#endif
|
||||
#define MBUS_CLK_GATE (0x1 << 31)
|
||||
|
||||
|
|
|
|||
|
|
@ -159,6 +159,7 @@ enum sunxi_gpio_number {
|
|||
#define SUN8I_GPB_UART2 2
|
||||
#define SUN8I_A33_GPB_UART0 3
|
||||
#define SUN8I_A83T_GPB_UART0 2
|
||||
#define SUN50I_GPB_UART0 4
|
||||
|
||||
#define SUNXI_GPC_NAND 2
|
||||
#define SUNXI_GPC_SDC2 3
|
||||
|
|
|
|||
|
|
@ -12,8 +12,11 @@
|
|||
#define SPL_SIGNATURE "SPL" /* marks "sunxi" SPL header */
|
||||
#define SPL_HEADER_VERSION 1
|
||||
|
||||
/* Note: A80 will require special handling here: SPL_ADDR 0x10000 */
|
||||
#if defined(CONFIG_MACH_SUN9I) || defined(CONFIG_MACH_SUN50I)
|
||||
#define SPL_ADDR 0x10000
|
||||
#else
|
||||
#define SPL_ADDR 0x0
|
||||
#endif
|
||||
|
||||
/* boot head definition from sun4i boot code */
|
||||
struct boot_file_head {
|
||||
|
|
|
|||
|
|
@ -26,6 +26,7 @@ obj-$(CONFIG_MACH_SUN4I) += clock_sun4i.o
|
|||
obj-$(CONFIG_MACH_SUN5I) += clock_sun4i.o
|
||||
obj-$(CONFIG_MACH_SUN6I) += clock_sun6i.o
|
||||
obj-$(CONFIG_MACH_SUN7I) += clock_sun4i.o
|
||||
obj-$(CONFIG_MACH_SUN50I) += clock_sun6i.o
|
||||
ifdef CONFIG_MACH_SUN8I_A83T
|
||||
obj-y += clock_sun8i_a83t.o
|
||||
else
|
||||
|
|
|
|||
|
|
@ -40,6 +40,30 @@ struct fel_stash {
|
|||
|
||||
struct fel_stash fel_stash __attribute__((section(".data")));
|
||||
|
||||
#ifdef CONFIG_MACH_SUN50I
|
||||
#include <asm/armv8/mmu.h>
|
||||
|
||||
static struct mm_region sunxi_mem_map[] = {
|
||||
{
|
||||
/* SRAM, MMIO regions */
|
||||
.base = 0x0UL,
|
||||
.size = 0x40000000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
||||
PTE_BLOCK_NON_SHARE
|
||||
}, {
|
||||
/* RAM */
|
||||
.base = 0x40000000UL,
|
||||
.size = 0x80000000UL,
|
||||
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
||||
PTE_BLOCK_INNER_SHARE
|
||||
}, {
|
||||
/* List terminator */
|
||||
0,
|
||||
}
|
||||
};
|
||||
struct mm_region *mem_map = sunxi_mem_map;
|
||||
#endif
|
||||
|
||||
static int gpio_init(void)
|
||||
{
|
||||
#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
|
||||
|
|
@ -76,6 +100,10 @@ static int gpio_init(void)
|
|||
sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0);
|
||||
sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0);
|
||||
sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP);
|
||||
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I)
|
||||
sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN50I_GPB_UART0);
|
||||
sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_GPB_UART0);
|
||||
sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
|
||||
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T)
|
||||
sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
|
||||
sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
|
||||
|
|
@ -265,7 +293,7 @@ void reset_cpu(ulong addr)
|
|||
#endif
|
||||
}
|
||||
|
||||
#ifndef CONFIG_SYS_DCACHE_OFF
|
||||
#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
|
||||
void enable_caches(void)
|
||||
{
|
||||
/* Enable D-cache. I-cache is already enabled in start.S */
|
||||
|
|
|
|||
|
|
@ -89,6 +89,8 @@ int print_cpuinfo(void)
|
|||
printf("CPU: Allwinner H3 (SUN8I %04x)\n", sunxi_get_sram_id());
|
||||
#elif defined CONFIG_MACH_SUN9I
|
||||
puts("CPU: Allwinner A80 (SUN9I)\n");
|
||||
#elif defined CONFIG_MACH_SUN50I
|
||||
puts("CPU: Allwinner A64 (SUN50I)\n");
|
||||
#else
|
||||
#warning Please update cpu_info.c with correct CPU information
|
||||
puts("CPU: SUNXI Family\n");
|
||||
|
|
|
|||
|
|
@ -77,6 +77,11 @@ config MACH_SUN8I_H3
|
|||
select SUPPORT_SPL
|
||||
select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
|
||||
|
||||
config MACH_SUN50I
|
||||
bool "sun50i (Allwinner A64)"
|
||||
select ARM64
|
||||
select SUNXI_GEN_SUN6I
|
||||
|
||||
config MACH_SUN8I_A83T
|
||||
bool "sun8i (Allwinner A83T)"
|
||||
select CPU_V7
|
||||
|
|
@ -213,6 +218,7 @@ config DRAM_ODT_CORRECTION
|
|||
endif
|
||||
|
||||
config SYS_CLK_FREQ
|
||||
default 816000000 if MACH_SUN50I
|
||||
default 912000000 if MACH_SUN7I
|
||||
default 1008000000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
|
||||
|
||||
|
|
@ -223,6 +229,7 @@ config SYS_CONFIG_NAME
|
|||
default "sun7i" if MACH_SUN7I
|
||||
default "sun8i" if MACH_SUN8I
|
||||
default "sun9i" if MACH_SUN9I
|
||||
default "sun50i" if MACH_SUN50I
|
||||
|
||||
config SYS_BOARD
|
||||
default "sunxi"
|
||||
|
|
@ -604,7 +611,7 @@ config GMAC_TX_DELAY
|
|||
Set the GMAC Transmit Clock Delay Chain value.
|
||||
|
||||
config SPL_STACK_R_ADDR
|
||||
default 0x4fe00000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I
|
||||
default 0x4fe00000 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN7I || MACH_SUN8I || MACH_SUN50I
|
||||
default 0x2fe00000 if MACH_SUN9I
|
||||
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -21,6 +21,9 @@
|
|||
#include <asm/arch/gpio.h>
|
||||
#include <asm/arch/mmc.h>
|
||||
#include <asm/arch/usb_phy.h>
|
||||
#ifndef CONFIG_ARM64
|
||||
#include <asm/armv7.h>
|
||||
#endif
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/io.h>
|
||||
#include <nand.h>
|
||||
|
|
@ -73,18 +76,38 @@ DECLARE_GLOBAL_DATA_PTR;
|
|||
/* add board specific code here */
|
||||
int board_init(void)
|
||||
{
|
||||
int id_pfr1, ret;
|
||||
__maybe_unused int id_pfr1, ret;
|
||||
|
||||
gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
|
||||
|
||||
#ifndef CONFIG_ARM64
|
||||
asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
|
||||
debug("id_pfr1: 0x%08x\n", id_pfr1);
|
||||
/* Generic Timer Extension available? */
|
||||
if ((id_pfr1 >> 16) & 0xf) {
|
||||
if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) {
|
||||
uint32_t freq;
|
||||
|
||||
debug("Setting CNTFRQ\n");
|
||||
/* CNTFRQ == 24 MHz */
|
||||
asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r"(24000000));
|
||||
|
||||
/*
|
||||
* CNTFRQ is a secure register, so we will crash if we try to
|
||||
* write this from the non-secure world (read is OK, though).
|
||||
* In case some bootcode has already set the correct value,
|
||||
* we avoid the risk of writing to it.
|
||||
*/
|
||||
asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
|
||||
if (freq != CONFIG_TIMER_CLK_FREQ) {
|
||||
debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
|
||||
freq, CONFIG_TIMER_CLK_FREQ);
|
||||
#ifdef CONFIG_NON_SECURE
|
||||
printf("arch timer frequency is wrong, but cannot adjust it\n");
|
||||
#else
|
||||
asm volatile("mcr p15, 0, %0, c14, c0, 0"
|
||||
: : "r"(CONFIG_TIMER_CLK_FREQ));
|
||||
#endif
|
||||
}
|
||||
}
|
||||
#endif /* !CONFIG_ARM64 */
|
||||
|
||||
ret = axp_gpio_init();
|
||||
if (ret)
|
||||
|
|
@ -264,7 +287,7 @@ static void mmc_pinmux_setup(int sdc)
|
|||
sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
|
||||
sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
|
||||
}
|
||||
#elif defined(CONFIG_MACH_SUN8I)
|
||||
#elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
|
||||
/* SDC2: PC5-PC6, PC8-PC16 */
|
||||
for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
|
||||
sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
|
||||
|
|
@ -547,7 +570,7 @@ void get_board_serial(struct tag_serialnr *serialnr)
|
|||
*/
|
||||
static void parse_spl_header(const uint32_t spl_addr)
|
||||
{
|
||||
struct boot_file_head *spl = (void *)spl_addr;
|
||||
struct boot_file_head *spl = (void *)(ulong)spl_addr;
|
||||
if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) == 0) {
|
||||
uint8_t spl_header_version = spl->spl_signature[3];
|
||||
if (spl_header_version == SPL_HEADER_VERSION) {
|
||||
|
|
|
|||
|
|
@ -480,6 +480,10 @@ struct mmc *sunxi_mmc_init(int sdc_no)
|
|||
|
||||
cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
|
||||
cfg->host_caps = MMC_MODE_4BIT;
|
||||
#ifdef CONFIG_MACH_SUN50I
|
||||
if (sdc_no == 2)
|
||||
cfg->host_caps = MMC_MODE_8BIT;
|
||||
#endif
|
||||
cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
|
||||
cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
|
||||
|
||||
|
|
|
|||
|
|
@ -10,7 +10,7 @@ choice
|
|||
default AXP209_POWER if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
|
||||
default AXP221_POWER if MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33
|
||||
default AXP818_POWER if MACH_SUN8I_A83T
|
||||
default SUNXI_NO_PMIC if MACH_SUN8I_H3
|
||||
default SUNXI_NO_PMIC if MACH_SUN8I_H3 || MACH_SUN50I
|
||||
|
||||
config SUNXI_NO_PMIC
|
||||
boolean "board without a pmic"
|
||||
|
|
|
|||
25
include/configs/sun50i.h
Normal file
25
include/configs/sun50i.h
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
/*
|
||||
* Configuration settings for the Allwinner A64 (sun50i) CPU
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*
|
||||
* A64 specific configuration
|
||||
*/
|
||||
|
||||
#define CONFIG_SUNXI_USB_PHYS 1
|
||||
|
||||
#define COUNTER_FREQUENCY CONFIG_TIMER_CLK_FREQ
|
||||
#define GICD_BASE 0x1c81000
|
||||
#define GICC_BASE 0x1c82000
|
||||
|
||||
/*
|
||||
* Include common sunxi configuration where most the settings are
|
||||
*/
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||||
#include <configs/sunxi-common.h>
|
||||
|
||||
#endif /* __CONFIG_H */
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||||
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|
@ -25,7 +25,6 @@
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|||
#define CONFIG_ARMV7_PSCI 1
|
||||
#define CONFIG_ARMV7_PSCI_NR_CPUS 4
|
||||
#define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE
|
||||
#define CONFIG_TIMER_CLK_FREQ 24000000
|
||||
|
||||
/*
|
||||
* Include common sunxi configuration where most the settings are
|
||||
|
|
|
|||
|
|
@ -22,7 +22,6 @@
|
|||
|
||||
#define CONFIG_ARMV7_PSCI 1
|
||||
#define CONFIG_ARMV7_SECURE_BASE SUNXI_SRAM_B_BASE
|
||||
#define CONFIG_TIMER_CLK_FREQ 24000000
|
||||
|
||||
/*
|
||||
* Include common sunxi configuration where most the settings are
|
||||
|
|
|
|||
|
|
@ -40,8 +40,6 @@
|
|||
#endif
|
||||
#endif
|
||||
|
||||
#define CONFIG_TIMER_CLK_FREQ 24000000
|
||||
|
||||
/*
|
||||
* Include common sunxi configuration where most the settings are
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -56,6 +56,7 @@
|
|||
/* CPU */
|
||||
#define CONFIG_DISPLAY_CPUINFO
|
||||
#define CONFIG_SYS_CACHELINE_SIZE 64
|
||||
#define CONFIG_TIMER_CLK_FREQ 24000000
|
||||
|
||||
/*
|
||||
* The DRAM Base differs between some models. We cannot use macros for the
|
||||
|
|
@ -90,7 +91,7 @@
|
|||
|
||||
#define CONFIG_SPL_BSS_MAX_SIZE 0x00080000 /* 512 KiB */
|
||||
|
||||
#ifdef CONFIG_MACH_SUN9I
|
||||
#if defined(CONFIG_MACH_SUN9I) || defined(CONFIG_MACH_SUN50I)
|
||||
/*
|
||||
* The A80's A1 sram starts at 0x00010000 rather then at 0x00000000 and is
|
||||
* slightly bigger. Note that it is possible to map the first 32 KiB of the
|
||||
|
|
@ -99,7 +100,7 @@
|
|||
* the 1 actually activates the mapping of the first 32 KiB to 0x00000000.
|
||||
*/
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0x10000
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x0a000 /* 40 KiB */
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x08000 /* FIXME: 40 KiB ? */
|
||||
#else
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0x0
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */
|
||||
|
|
@ -188,8 +189,16 @@
|
|||
|
||||
#define CONFIG_SPL_BOARD_LOAD_IMAGE
|
||||
|
||||
#if defined(CONFIG_MACH_SUN9I)
|
||||
#define CONFIG_SPL_TEXT_BASE 0x10020 /* sram start+header */
|
||||
#define CONFIG_SPL_MAX_SIZE 0x5fe0 /* ? KiB on sun9i */
|
||||
#elif defined(CONFIG_MACH_SUN50I)
|
||||
#define CONFIG_SPL_TEXT_BASE 0x10020 /* sram start+header */
|
||||
#define CONFIG_SPL_MAX_SIZE 0x7fe0 /* 32 KiB on sun50i */
|
||||
#else
|
||||
#define CONFIG_SPL_TEXT_BASE 0x20 /* sram start+header */
|
||||
#define CONFIG_SPL_MAX_SIZE 0x5fe0 /* 24KB on sun4i/sun7i */
|
||||
#endif
|
||||
|
||||
#define CONFIG_SPL_LIBDISK_SUPPORT
|
||||
|
||||
|
|
@ -197,14 +206,22 @@
|
|||
#define CONFIG_SPL_MMC_SUPPORT
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_ARM64
|
||||
#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 80 /* 40KiB */
|
||||
#define CONFIG_SPL_PAD_TO 32768 /* decimal for 'dd' */
|
||||
|
||||
#if defined(CONFIG_MACH_SUN9I) || defined(CONFIG_MACH_SUN50I)
|
||||
/* FIXME: 40 KiB instead of 32 KiB ? */
|
||||
#define LOW_LEVEL_SRAM_STACK 0x00018000
|
||||
#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
|
||||
#else
|
||||
/* end of 32 KiB in sram */
|
||||
#define LOW_LEVEL_SRAM_STACK 0x00008000 /* End of sram */
|
||||
#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
|
||||
#endif
|
||||
|
||||
/* I2C */
|
||||
#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
|
||||
|
|
|
|||
Loading…
Reference in a new issue