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ppc: xilinx-ppc4xx: Port to DM serial

Browse source 
xilinx_uartlite has been ported to DM, this patch makes the
xilinx-ppc405-generic and the xilinx-ppc440-generic boards use the new
DM driver.

Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
Ricardo Ribalda Delgado 2016-01-26 11:24:19 +01:00 committed by Michal Simek
parent 5af0855670
commit 80cce2629b
9 changed files with 37 additions and 24 deletions
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8
arch/powerpc/cpu/ppc4xx/Kconfig
View file

@ -111,9 +111,17 @@ config TARGET_XPEDITE1000
config TARGET_XILINX_PPC405_GENERIC
bool "Support xilinx-ppc405-generic"
select SUPPORT_SPL
select OF_CONTROL
select DM
select DM_SERIAL
config TARGET_XILINX_PPC440_GENERIC
bool "Support xilinx-ppc440-generic"
select SUPPORT_SPL
select OF_CONTROL
select DM
select DM_SERIAL
endchoice

4
board/xilinx/ppc405-generic/xilinx_ppc405_generic.c
View file

@ -46,3 +46,7 @@ void __get_sys_info(sys_info_t *sysInfo)
return;
}
void get_sys_info(sys_info_t *) __attribute__((weak, alias("__get_sys_info")));
int get_serial_clock(void){
return XPAR_UARTNS550_0_CLOCK_FREQ_HZ;
}

1
board/xilinx/ppc405-generic/xparameters.h
View file

@ -19,7 +19,6 @@
#define XPAR_CORE_CLOCK_FREQ_HZ 400000000
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 32
#define XPAR_SPI_0_NUM_TRANSFER_BITS 8
#define XPAR_UARTNS550_0_BASEADDR 0xdeadbeef
#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000
#endif

4
board/xilinx/ppc440-generic/xilinx_ppc440_generic.c
View file

@ -39,3 +39,7 @@ void __get_sys_info(sys_info_t *sysInfo)
return;
}
void get_sys_info(sys_info_t *) __attribute__((weak, alias("__get_sys_info")));
int get_serial_clock(void){
return XPAR_UARTNS550_0_CLOCK_FREQ_HZ;
}

1
board/xilinx/ppc440-generic/xparameters.h
View file

@ -17,7 +17,6 @@
#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
#define XPAR_CORE_CLOCK_FREQ_HZ 400000000
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 32
#define XPAR_UARTNS550_0_BASEADDR 0xdeadbeef
#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000
#endif

8
configs/xilinx-ppc405-generic_defconfig
View file

@ -7,3 +7,11 @@ CONFIG_SYS_PROMPT="xlx-ppc405:/# "
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
CONFIG_SYS_MALLOC_SIMPLE=y
CONFIG_XILINX_UARTLITE=y
CONFIG_SYS_NS16550=y
CONFIG_OF_EMBED=y
CONFIG_OF_CONTROL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_DEFAULT_DEVICE_TREE="xilinx-ppc440-generic"

12
configs/xilinx-ppc440-generic_defconfig
View file

@ -3,7 +3,11 @@ CONFIG_4xx=y
CONFIG_TARGET_XILINX_PPC440_GENERIC=y
CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1"
CONFIG_SYS_PROMPT="board:/# "
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
# CONFIG_CMD_NFS is not set
CONFIG_SYS_MALLOC_SIMPLE=y
CONFIG_XILINX_UARTLITE=y
CONFIG_SYS_NS16550=y
CONFIG_OF_EMBED=y
CONFIG_OF_CONTROL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_DEFAULT_DEVICE_TREE="xilinx-ppc440-generic"

2
drivers/serial/Kconfig
View file

@ -280,7 +280,7 @@ config UNIPHIER_SERIAL
config XILINX_UARTLITE
bool "Xilinx Uarlite support"
depends on DM_SERIAL && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP)
depends on DM_SERIAL && (MICROBLAZE || ARCH_ZYNQ || ARCH_ZYNQMP || 4xx)
help
If you have a Xilinx based board and want to use the uartlite
serial ports, say Y to this option. If unsure, say N.

21
include/configs/xilinx-ppc.h
View file

@ -101,23 +101,10 @@
#define CONFIG_SYS_NO_FLASH
#endif
/* serial communication */
#ifdef XPAR_UARTLITE_0_BASEADDR
#define CONFIG_XILINX_UARTLITE
#define XILINX_UARTLITE_BASEADDR XPAR_UARTLITE_0_BASEADDR
#define CONFIG_BAUDRATE XPAR_UARTLITE_0_BAUDRATE
#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
#else
#ifdef XPAR_UARTNS550_0_BASEADDR
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 4
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550_COM1 XPAR_UARTNS550_0_BASEADDR
#define CONFIG_SYS_NS16550_CLK XPAR_UARTNS550_0_CLOCK_FREQ_HZ
#define CONFIG_OF_LIBFDT 1
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 115200 }
#endif
#endif
/* The following table includes the supported baudrates */
# define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
#endif /* __CONFIG_H */