mirror of
https://github.com/AsahiLinux/u-boot
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taishan: Drop
This board has not compiled for me for quite some time due to size constraints, remove. Cc: Stefan Roese <sr@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Tom Rini
Stefan Roese
parent
9d9e2f5daf
commit
bb5553c618
12 changed files with 1 additions and 1123 deletions
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@ -1,16 +0,0 @@
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if TARGET_TAISHAN
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config SYS_BOARD
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default "taishan"
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config SYS_VENDOR
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default "amcc"
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config SYS_CONFIG_NAME
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default "taishan"
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config DISPLAY_BOARDINFO
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bool
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default y
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endif
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@ -1,6 +0,0 @@
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TAISHAN BOARD
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M: Stefan Roese <sr@denx.de>
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S: Maintained
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F: board/amcc/taishan/
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F: include/configs/taishan.h
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F: configs/taishan_defconfig
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@ -1,9 +0,0 @@
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#
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# (C) Copyright 2007
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y = taishan.o lcd.o update.o showinfo.o
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extra-y += init.o
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@ -1,20 +0,0 @@
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#
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# (C) Copyright 2004
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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#
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# AMCC 440GX Reference Platform (Taishan) board
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#
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PLATFORM_CPPFLAGS += -DCONFIG_440=1
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ifeq ($(debug),1)
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PLATFORM_CPPFLAGS += -DDEBUG
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endif
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ifeq ($(dbcr),1)
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PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
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endif
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@ -1,35 +0,0 @@
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/*
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* (C) Copyright 2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <ppc_asm.tmpl>
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#include <asm/mmu.h>
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#include <config.h>
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#include <asm/ppc4xx.h>
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/**************************************************************************
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* TLB TABLE
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*
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* This table is used by the cpu boot code to setup the initial tlb
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* entries. Rather than make broad assumptions in the cpu source tree,
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* this table lets each board set things up however they like.
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*
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* Pointer to the table is returned in r1
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*
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*************************************************************************/
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.section .bootpg,"ax"
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.globl tlbtab
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tlbtab:
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tlbtab_start
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tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_RWX | SA_IG)
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tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_RW | SA_IG)
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tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_RWX )
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tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_RWX | SA_IG )
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tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_RW | SA_IG )
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tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_RW | SA_IG )
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tlbtab_end
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@ -1,358 +0,0 @@
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/*
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* (C) Copyright 2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <common.h>
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#include <command.h>
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#include <i2c.h>
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#include <miiphy.h>
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#ifdef CONFIG_TAISHAN
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#define LCD_DELAY_NORMAL_US 100
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#define LCD_DELAY_NORMAL_MS 2
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#define LCD_CMD_ADDR ((volatile char *)(CONFIG_SYS_EBC2_LCM_BASE))
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#define LCD_DATA_ADDR ((volatile char *)(CONFIG_SYS_EBC2_LCM_BASE+1))
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#define LCD_BLK_CTRL ((volatile char *)(CONFIG_SYS_EBC1_FPGA_BASE+0x2))
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static int g_lcd_init_b = 0;
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static char *amcc_logo = " AMCC TAISHAN 440GX EvalBoard";
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static char addr_flag = 0x80;
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static void lcd_bl_ctrl(char val)
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{
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char cpld_val;
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cpld_val = *LCD_BLK_CTRL;
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*LCD_BLK_CTRL = val | cpld_val;
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}
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static void lcd_putc(char val)
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{
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int i = 100;
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char addr;
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while (i--) {
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if ((*LCD_CMD_ADDR & 0x80) != 0x80) { /*BF = 1 ? */
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udelay(LCD_DELAY_NORMAL_US);
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break;
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}
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udelay(LCD_DELAY_NORMAL_US);
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}
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if (*LCD_CMD_ADDR & 0x80) {
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printf("LCD is busy\n");
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return;
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}
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addr = *LCD_CMD_ADDR;
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udelay(LCD_DELAY_NORMAL_US);
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if ((addr != 0) && (addr % 0x10 == 0)) {
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addr_flag ^= 0x40;
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*LCD_CMD_ADDR = addr_flag;
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}
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udelay(LCD_DELAY_NORMAL_US);
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*LCD_DATA_ADDR = val;
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udelay(LCD_DELAY_NORMAL_US);
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}
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static void lcd_puts(char *s)
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{
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char *p = s;
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int i = 100;
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while (i--) {
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if ((*LCD_CMD_ADDR & 0x80) != 0x80) { /*BF = 1 ? */
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udelay(LCD_DELAY_NORMAL_US);
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break;
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}
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udelay(LCD_DELAY_NORMAL_US);
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}
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if (*LCD_CMD_ADDR & 0x80) {
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printf("LCD is busy\n");
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return;
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}
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while (*p)
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lcd_putc(*p++);
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}
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static void lcd_put_logo(void)
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{
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int i = 100;
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char *p = amcc_logo;
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while (i--) {
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if ((*LCD_CMD_ADDR & 0x80) != 0x80) { /*BF = 1 ? */
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udelay(LCD_DELAY_NORMAL_US);
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break;
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}
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udelay(LCD_DELAY_NORMAL_US);
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}
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if (*LCD_CMD_ADDR & 0x80) {
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printf("LCD is busy\n");
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return;
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}
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*LCD_CMD_ADDR = 0x80;
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while (*p)
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lcd_putc(*p++);
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}
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int lcd_init(void)
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{
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if (g_lcd_init_b == 0) {
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puts("LCD: ");
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mdelay(100); /* Waiting for the LCD initialize */
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*LCD_CMD_ADDR = 0x38; /*set function:8-bit,2-line,5x7 font type */
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udelay(LCD_DELAY_NORMAL_US);
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*LCD_CMD_ADDR = 0x0f; /*set display on,cursor on,blink on */
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udelay(LCD_DELAY_NORMAL_US);
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*LCD_CMD_ADDR = 0x01; /*display clear */
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mdelay(LCD_DELAY_NORMAL_MS);
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*LCD_CMD_ADDR = 0x06; /*set entry */
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udelay(LCD_DELAY_NORMAL_US);
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lcd_bl_ctrl(0x02);
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lcd_put_logo();
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puts(" ready\n");
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g_lcd_init_b = 1;
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}
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return 0;
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}
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static int do_lcd_test(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
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{
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lcd_init();
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return 0;
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}
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static int do_lcd_clear(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
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{
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*LCD_CMD_ADDR = 0x01;
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mdelay(LCD_DELAY_NORMAL_MS);
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return 0;
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}
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static int do_lcd_puts(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
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{
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if (argc < 2)
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return cmd_usage(cmdtp);
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lcd_puts(argv[1]);
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return 0;
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}
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static int do_lcd_putc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
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{
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if (argc < 2)
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return cmd_usage(cmdtp);
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lcd_putc((char)argv[1][0]);
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return 0;
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}
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static int do_lcd_cur(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
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{
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ulong count;
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ulong dir;
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char cur_addr;
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if (argc < 3)
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return cmd_usage(cmdtp);
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count = simple_strtoul(argv[1], NULL, 16);
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if (count > 31) {
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printf("unable to shift > 0x20\n");
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count = 0;
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}
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dir = simple_strtoul(argv[2], NULL, 16);
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cur_addr = *LCD_CMD_ADDR;
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udelay(LCD_DELAY_NORMAL_US);
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if (dir == 0x0) {
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if (addr_flag == 0x80) {
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if (count >= (cur_addr & 0xf)) {
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*LCD_CMD_ADDR = 0x80;
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udelay(LCD_DELAY_NORMAL_US);
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count = 0;
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}
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} else {
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if (count >= ((cur_addr & 0x0f) + 0x0f)) {
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*LCD_CMD_ADDR = 0x80;
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addr_flag = 0x80;
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udelay(LCD_DELAY_NORMAL_US);
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count = 0x0;
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} else if (count >= (cur_addr & 0xf)) {
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count -= cur_addr & 0xf;
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*LCD_CMD_ADDR = 0x80 | 0xf;
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addr_flag = 0x80;
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udelay(LCD_DELAY_NORMAL_US);
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}
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}
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} else {
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if (addr_flag == 0x80) {
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if (count >= (0x1f - (cur_addr & 0xf))) {
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count = 0x0;
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addr_flag = 0xc0;
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*LCD_CMD_ADDR = 0xc0 | 0xf;
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udelay(LCD_DELAY_NORMAL_US);
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} else if ((count + (cur_addr & 0xf)) >= 0x0f) {
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count = count + (cur_addr & 0xf) - 0x0f;
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addr_flag = 0xc0;
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*LCD_CMD_ADDR = 0xc0;
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udelay(LCD_DELAY_NORMAL_US);
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}
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} else if ((count + (cur_addr & 0xf)) >= 0x0f) {
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count = 0x0;
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*LCD_CMD_ADDR = 0xc0 | 0xf;
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udelay(LCD_DELAY_NORMAL_US);
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}
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}
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while (count--) {
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if (dir == 0) {
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*LCD_CMD_ADDR = 0x10;
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} else {
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*LCD_CMD_ADDR = 0x14;
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}
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udelay(LCD_DELAY_NORMAL_US);
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}
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return 0;
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}
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U_BOOT_CMD(lcd_test, 1, 1, do_lcd_test, "lcd test display", "");
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U_BOOT_CMD(lcd_cls, 1, 1, do_lcd_clear, "lcd clear display", "");
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U_BOOT_CMD(lcd_puts, 2, 1, do_lcd_puts,
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"display string on lcd",
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"<string> - <string> to be displayed");
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U_BOOT_CMD(lcd_putc, 2, 1, do_lcd_putc,
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"display char on lcd",
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"<char> - <char> to be displayed");
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U_BOOT_CMD(lcd_cur, 3, 1, do_lcd_cur,
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"shift cursor on lcd",
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"<count> <dir>- shift cursor on lcd <count> times, direction is <dir> \n"
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" <count> - 0~31\n" " <dir> - 0,backward; 1, forward");
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#if 0 /* test-only */
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void set_phy_loopback_mode(void)
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{
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char devemac2[32];
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char devemac3[32];
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sprintf(devemac2, "%s2", CONFIG_EMAC_DEV_NAME);
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sprintf(devemac3, "%s3", CONFIG_EMAC_DEV_NAME);
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#if 0
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unsigned short reg_short;
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miiphy_read(devemac2, 0x1, 1, ®_short);
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if (reg_short & 0x04) {
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/*
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* printf("EMAC2 link up,do nothing\n");
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*/
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} else {
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udelay(1000);
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miiphy_write(devemac2, 0x1, 0, 0x6000);
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udelay(1000);
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miiphy_read(devemac2, 0x1, 0, ®_short);
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if (reg_short != 0x6000) {
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printf
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("\nEMAC2 error set LOOPBACK mode error,reg2[0]=%x\n",
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reg_short);
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}
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}
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miiphy_read(devemac3, 0x3, 1, ®_short);
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if (reg_short & 0x04) {
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/*
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* printf("EMAC3 link up,do nothing\n");
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*/
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} else {
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udelay(1000);
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miiphy_write(devemac3, 0x3, 0, 0x6000);
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udelay(1000);
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miiphy_read(devemac3, 0x3, 0, ®_short);
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if (reg_short != 0x6000) {
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printf
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("\nEMAC3 error set LOOPBACK mode error,reg2[0]=%x\n",
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reg_short);
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}
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}
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#else
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/* Set PHY as LOOPBACK MODE, for Linux emac initializing */
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miiphy_write(devemac2, CONFIG_PHY2_ADDR, 0, 0x6000);
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udelay(1000);
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miiphy_write(devemac3, CONFIG_PHY3_ADDR, 0, 0x6000);
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udelay(1000);
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#endif /* 0 */
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}
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void set_phy_normal_mode(void)
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{
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char devemac2[32];
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char devemac3[32];
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unsigned short reg_short;
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sprintf(devemac2, "%s2", CONFIG_EMAC_DEV_NAME);
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sprintf(devemac3, "%s3", CONFIG_EMAC_DEV_NAME);
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/* Set phy of EMAC2 */
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miiphy_read(devemac2, CONFIG_PHY2_ADDR, 0x16, ®_short);
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reg_short &= ~(0x7);
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reg_short |= 0x6; /* RGMII DLL Delay */
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miiphy_write(devemac2, CONFIG_PHY2_ADDR, 0x16, reg_short);
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miiphy_read(devemac2, CONFIG_PHY2_ADDR, 0x17, ®_short);
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reg_short &= ~(0x40);
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miiphy_write(devemac2, CONFIG_PHY2_ADDR, 0x17, reg_short);
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miiphy_write(devemac2, CONFIG_PHY2_ADDR, 0x1c, 0x74f0);
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/* Set phy of EMAC3 */
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miiphy_read(devemac3, CONFIG_PHY3_ADDR, 0x16, ®_short);
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reg_short &= ~(0x7);
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reg_short |= 0x6; /* RGMII DLL Delay */
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miiphy_write(devemac3, CONFIG_PHY3_ADDR, 0x16, reg_short);
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miiphy_read(devemac3, CONFIG_PHY3_ADDR, 0x17, ®_short);
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reg_short &= ~(0x40);
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miiphy_write(devemac3, CONFIG_PHY3_ADDR, 0x17, reg_short);
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miiphy_write(devemac3, CONFIG_PHY3_ADDR, 0x1c, 0x74f0);
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}
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#endif /* 0 - test only */
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static int do_led_test_off(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
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{
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volatile unsigned int *GpioOr =
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(volatile unsigned int *)(CONFIG_SYS_PERIPHERAL_BASE + 0x700);
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*GpioOr |= 0x00300000;
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return 0;
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}
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static int do_led_test_on(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
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{
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volatile unsigned int *GpioOr =
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(volatile unsigned int *)(CONFIG_SYS_PERIPHERAL_BASE + 0x700);
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*GpioOr &= ~0x00300000;
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return 0;
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}
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U_BOOT_CMD(ledon, 1, 1, do_led_test_on,
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"led test light on", "");
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U_BOOT_CMD(ledoff, 1, 1, do_led_test_off,
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"led test light off", "");
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#endif
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@ -1,220 +0,0 @@
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/*
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* (C) Copyright 2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
|
||||
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <asm/processor.h>
|
||||
#include <pci.h>
|
||||
|
||||
void show_reset_reg(void)
|
||||
{
|
||||
unsigned long reg;
|
||||
|
||||
/* read clock regsiter */
|
||||
printf("===== Display reset and initialize register Start =========\n");
|
||||
mfcpr(CPR0_PLLC,reg);
|
||||
printf("cpr_pllc = %#010lx\n",reg);
|
||||
|
||||
mfcpr(CPR0_PLLD,reg);
|
||||
printf("cpr_plld = %#010lx\n",reg);
|
||||
|
||||
mfcpr(CPR0_PRIMAD0,reg);
|
||||
printf("cpr_primad = %#010lx\n",reg);
|
||||
|
||||
mfcpr(CPR0_PRIMBD0,reg);
|
||||
printf("cpr_primbd = %#010lx\n",reg);
|
||||
|
||||
mfcpr(CPR0_OPBD0,reg);
|
||||
printf("cpr_opbd = %#010lx\n",reg);
|
||||
|
||||
mfcpr(CPR0_PERD,reg);
|
||||
printf("cpr_perd = %#010lx\n",reg);
|
||||
|
||||
mfcpr(CPR0_MALD,reg);
|
||||
printf("cpr_mald = %#010lx\n",reg);
|
||||
|
||||
/* read sdr register */
|
||||
mfsdr(SDR0_EBC,reg);
|
||||
printf("SDR0_EBC = %#010lx\n",reg);
|
||||
|
||||
mfsdr(SDR0_CP440,reg);
|
||||
printf("SDR0_CP440 = %#010lx\n",reg);
|
||||
|
||||
mfsdr(SDR0_XCR,reg);
|
||||
printf("SDR0_XCR = %#010lx\n",reg);
|
||||
|
||||
mfsdr(SDR0_XPLLC,reg);
|
||||
printf("SDR0_XPLLC = %#010lx\n",reg);
|
||||
|
||||
mfsdr(SDR0_XPLLD,reg);
|
||||
printf("SDR0_XPLLD = %#010lx\n",reg);
|
||||
|
||||
mfsdr(SDR0_PFC0,reg);
|
||||
printf("SDR0_PFC0 = %#010lx\n",reg);
|
||||
|
||||
mfsdr(SDR0_PFC1,reg);
|
||||
printf("SDR0_PFC1 = %#010lx\n",reg);
|
||||
|
||||
mfsdr(SDR0_CUST0,reg);
|
||||
printf("SDR0_CUST0 = %#010lx\n",reg);
|
||||
|
||||
mfsdr(SDR0_CUST1,reg);
|
||||
printf("SDR0_CUST1 = %#010lx\n",reg);
|
||||
|
||||
mfsdr(SDR0_UART0,reg);
|
||||
printf("SDR0_UART0 = %#010lx\n",reg);
|
||||
|
||||
mfsdr(SDR0_UART1,reg);
|
||||
printf("SDR0_UART1 = %#010lx\n",reg);
|
||||
|
||||
printf("===== Display reset and initialize register End =========\n");
|
||||
}
|
||||
|
||||
void show_xbridge_info(void)
|
||||
{
|
||||
unsigned long reg;
|
||||
|
||||
printf("PCI-X chip control registers\n");
|
||||
mfsdr(SDR0_XCR, reg);
|
||||
printf("SDR0_XCR = %#010lx\n", reg);
|
||||
|
||||
mfsdr(SDR0_XPLLC, reg);
|
||||
printf("SDR0_XPLLC = %#010lx\n", reg);
|
||||
|
||||
mfsdr(SDR0_XPLLD, reg);
|
||||
printf("SDR0_XPLLD = %#010lx\n", reg);
|
||||
|
||||
printf("PCI-X Bridge Configure registers\n");
|
||||
printf("PCIL0_VENDID = %#06x\n", in16r(PCIL0_VENDID));
|
||||
printf("PCIL0_DEVID = %#06x\n", in16r(PCIL0_DEVID));
|
||||
printf("PCIL0_CMD = %#06x\n", in16r(PCIL0_CMD));
|
||||
printf("PCIL0_STATUS = %#06x\n", in16r(PCIL0_STATUS));
|
||||
printf("PCIL0_REVID = %#04x\n", in8(PCIL0_REVID));
|
||||
printf("PCIL0_CACHELS = %#04x\n", in8(PCIL0_CACHELS));
|
||||
printf("PCIL0_LATTIM = %#04x\n", in8(PCIL0_LATTIM));
|
||||
printf("PCIL0_HDTYPE = %#04x\n", in8(PCIL0_HDTYPE));
|
||||
printf("PCIL0_BIST = %#04x\n", in8(PCIL0_BIST));
|
||||
|
||||
printf("PCIL0_BAR0 = %#010lx\n", in32r(PCIL0_BAR0));
|
||||
printf("PCIL0_BAR1 = %#010lx\n", in32r(PCIL0_BAR1));
|
||||
printf("PCIL0_BAR2 = %#010lx\n", in32r(PCIL0_BAR2));
|
||||
printf("PCIL0_BAR3 = %#010lx\n", in32r(PCIL0_BAR3));
|
||||
printf("PCIL0_BAR4 = %#010lx\n", in32r(PCIL0_BAR4));
|
||||
printf("PCIL0_BAR5 = %#010lx\n", in32r(PCIL0_BAR5));
|
||||
|
||||
printf("PCIL0_CISPTR = %#010lx\n", in32r(PCIL0_CISPTR));
|
||||
printf("PCIL0_SBSSYSVID = %#010x\n", in16r(PCIL0_SBSYSVID));
|
||||
printf("PCIL0_SBSSYSID = %#010x\n", in16r(PCIL0_SBSYSID));
|
||||
printf("PCIL0_EROMBA = %#010lx\n", in32r(PCIL0_EROMBA));
|
||||
printf("PCIL0_CAP = %#04x\n", in8(PCIL0_CAP));
|
||||
printf("PCIL0_INTLN = %#04x\n", in8(PCIL0_INTLN));
|
||||
printf("PCIL0_INTPN = %#04x\n", in8(PCIL0_INTPN));
|
||||
printf("PCIL0_MINGNT = %#04x\n", in8(PCIL0_MINGNT));
|
||||
printf("PCIL0_MAXLTNCY = %#04x\n", in8(PCIL0_MAXLTNCY));
|
||||
|
||||
printf("PCIL0_BRDGOPT1 = %#010lx\n", in32r(PCIL0_BRDGOPT1));
|
||||
printf("PCIL0_BRDGOPT2 = %#010lx\n", in32r(PCIL0_BRDGOPT2));
|
||||
|
||||
printf("PCIL0_POM0LAL = %#010lx\n", in32r(PCIL0_POM0LAL));
|
||||
printf("PCIL0_POM0LAH = %#010lx\n", in32r(PCIL0_POM0LAH));
|
||||
printf("PCIL0_POM0SA = %#010lx\n", in32r(PCIL0_POM0SA));
|
||||
printf("PCIL0_POM0PCILAL = %#010lx\n", in32r(PCIL0_POM0PCIAL));
|
||||
printf("PCIL0_POM0PCILAH = %#010lx\n", in32r(PCIL0_POM0PCIAH));
|
||||
printf("PCIL0_POM1LAL = %#010lx\n", in32r(PCIL0_POM1LAL));
|
||||
printf("PCIL0_POM1LAH = %#010lx\n", in32r(PCIL0_POM1LAH));
|
||||
printf("PCIL0_POM1SA = %#010lx\n", in32r(PCIL0_POM1SA));
|
||||
printf("PCIL0_POM1PCILAL = %#010lx\n", in32r(PCIL0_POM1PCIAL));
|
||||
printf("PCIL0_POM1PCILAH = %#010lx\n", in32r(PCIL0_POM1PCIAH));
|
||||
printf("PCIL0_POM2SA = %#010lx\n", in32r(PCIL0_POM2SA));
|
||||
|
||||
printf("PCIL0_PIM0SA = %#010lx\n", in32r(PCIL0_PIM0SA));
|
||||
printf("PCIL0_PIM0LAL = %#010lx\n", in32r(PCIL0_PIM0LAL));
|
||||
printf("PCIL0_PIM0LAH = %#010lx\n", in32r(PCIL0_PIM0LAH));
|
||||
printf("PCIL0_PIM1SA = %#010lx\n", in32r(PCIL0_PIM1SA));
|
||||
printf("PCIL0_PIM1LAL = %#010lx\n", in32r(PCIL0_PIM1LAL));
|
||||
printf("PCIL0_PIM1LAH = %#010lx\n", in32r(PCIL0_PIM1LAH));
|
||||
printf("PCIL0_PIM2SA = %#010lx\n", in32r(PCIL0_PIM1SA));
|
||||
printf("PCIL0_PIM2LAL = %#010lx\n", in32r(PCIL0_PIM1LAL));
|
||||
printf("PCIL0_PIM2LAH = %#010lx\n", in32r(PCIL0_PIM1LAH));
|
||||
|
||||
printf("PCIL0_XSTS = %#010lx\n", in32r(PCIL0_STS));
|
||||
}
|
||||
|
||||
int do_show_xbridge_info(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
show_xbridge_info();
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(xbriinfo, 1, 1, do_show_xbridge_info,
|
||||
"Show PCIX bridge info", "");
|
||||
|
||||
#define TAISHAN_PCI_DEV_ID0 0x800
|
||||
#define TAISHAN_PCI_DEV_ID1 0x1000
|
||||
|
||||
void show_pcix_device_info(void)
|
||||
{
|
||||
int ii;
|
||||
int dev;
|
||||
u8 capp;
|
||||
u8 xcapid;
|
||||
u16 status;
|
||||
u16 xcommand;
|
||||
u32 xstatus;
|
||||
|
||||
for (ii = 0; ii < 2; ii++) {
|
||||
if (ii == 0)
|
||||
dev = TAISHAN_PCI_DEV_ID0;
|
||||
else
|
||||
dev = TAISHAN_PCI_DEV_ID1;
|
||||
|
||||
pci_read_config_word(dev, PCI_STATUS, &status);
|
||||
if (status & PCI_STATUS_CAP_LIST) {
|
||||
pci_read_config_byte(dev, PCI_CAPABILITY_LIST, &capp);
|
||||
|
||||
pci_read_config_byte(dev, (int)(capp), &xcapid);
|
||||
if (xcapid == 0x07) {
|
||||
pci_read_config_word(dev, (int)(capp + 2),
|
||||
&xcommand);
|
||||
pci_read_config_dword(dev, (int)(capp + 4),
|
||||
&xstatus);
|
||||
printf("BUS0 dev%d Xcommand=%#06x,Xstatus=%#010x\n",
|
||||
(ii + 1), xcommand, xstatus);
|
||||
} else {
|
||||
printf("BUS0 dev%d PCI-X CAP ID error,"
|
||||
"CAP=%#04x,XCAPID=%#04x\n",
|
||||
(ii + 1), capp, xcapid);
|
||||
}
|
||||
} else {
|
||||
printf("BUS0 dev%d not found PCI_STATUS_CAP_LIST supporting\n",
|
||||
ii + 1);
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
int do_show_pcix_device_info(cmd_tbl_t * cmdtp, int flag, int argc,
|
||||
char * const argv[])
|
||||
{
|
||||
show_pcix_device_info();
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(xdevinfo, 1, 1, do_show_pcix_device_info,
|
||||
"Show PCIX Device info", "");
|
||||
|
||||
extern void show_reset_reg(void);
|
||||
|
||||
int do_show_reset_reg_info(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
show_reset_reg();
|
||||
return 0;
|
||||
}
|
||||
|
||||
U_BOOT_CMD(resetinfo, 1, 1, do_show_reset_reg_info,
|
||||
"Show Reset REG info", "");
|
||||
|
|
@ -1,201 +0,0 @@
|
|||
/*
|
||||
* Copyright (C) 2004 PaulReynolds@lhsolutions.com
|
||||
*
|
||||
* (C) Copyright 2007
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/processor.h>
|
||||
#include <spd_sdram.h>
|
||||
#include <asm/ppc4xx-emac.h>
|
||||
#include <netdev.h>
|
||||
|
||||
#ifdef CONFIG_SYS_INIT_SHOW_RESET_REG
|
||||
void show_reset_reg(void);
|
||||
#endif
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int lcd_init(void);
|
||||
|
||||
int board_early_init_f (void)
|
||||
{
|
||||
unsigned long reg;
|
||||
volatile unsigned int *GpioOdr;
|
||||
volatile unsigned int *GpioTcr;
|
||||
volatile unsigned int *GpioOr;
|
||||
|
||||
/*-------------------------------------------------------------------------+
|
||||
| Initialize EBC CONFIG
|
||||
+-------------------------------------------------------------------------*/
|
||||
mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK |
|
||||
EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK |
|
||||
EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
|
||||
EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_DEFAULT |
|
||||
EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
|
||||
|
||||
/*-------------------------------------------------------------------------+
|
||||
| 64MB FLASH. Initialize bank 0 with default values.
|
||||
+-------------------------------------------------------------------------*/
|
||||
mtebc(PB0AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(15) |
|
||||
EBC_BXAP_BCE_DISABLE |
|
||||
EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1) |
|
||||
EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) |
|
||||
EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED |
|
||||
EBC_BXAP_BEM_WRITEONLY |
|
||||
EBC_BXAP_PEN_DISABLED);
|
||||
mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |
|
||||
EBC_BXCR_BS_64MB | EBC_BXCR_BU_RW|EBC_BXCR_BW_32BIT);
|
||||
|
||||
/*-------------------------------------------------------------------------+
|
||||
| FPGA. Initialize bank 1 with default values.
|
||||
+-------------------------------------------------------------------------*/
|
||||
mtebc(PB1AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(5) |
|
||||
EBC_BXAP_BCE_DISABLE |
|
||||
EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1) |
|
||||
EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) |
|
||||
EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED |
|
||||
EBC_BXAP_BEM_WRITEONLY |
|
||||
EBC_BXAP_PEN_DISABLED);
|
||||
mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x41000000) |
|
||||
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
|
||||
|
||||
/*-------------------------------------------------------------------------+
|
||||
| LCM. Initialize bank 2 with default values.
|
||||
+-------------------------------------------------------------------------*/
|
||||
mtebc(PB2AP, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(64) |
|
||||
EBC_BXAP_BCE_DISABLE |
|
||||
EBC_BXAP_CSN_ENCODE(3) | EBC_BXAP_OEN_ENCODE(3) |
|
||||
EBC_BXAP_WBN_ENCODE(3) | EBC_BXAP_WBF_ENCODE(3) |
|
||||
EBC_BXAP_TH_ENCODE(7) | EBC_BXAP_RE_DISABLED |
|
||||
EBC_BXAP_BEM_WRITEONLY |
|
||||
EBC_BXAP_PEN_DISABLED);
|
||||
mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(0x42000000) |
|
||||
EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
|
||||
|
||||
/*-------------------------------------------------------------------------+
|
||||
| TMP. Initialize bank 3 with default values.
|
||||
+-------------------------------------------------------------------------*/
|
||||
mtebc(PB3AP, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(128) |
|
||||
EBC_BXAP_BCE_DISABLE |
|
||||
EBC_BXAP_CSN_ENCODE(3) | EBC_BXAP_OEN_ENCODE(3) |
|
||||
EBC_BXAP_WBN_ENCODE(3) | EBC_BXAP_WBF_ENCODE(3) |
|
||||
EBC_BXAP_TH_ENCODE(7) | EBC_BXAP_RE_DISABLED |
|
||||
EBC_BXAP_BEM_WRITEONLY |
|
||||
EBC_BXAP_PEN_DISABLED);
|
||||
mtebc(PB3CR, EBC_BXCR_BAS_ENCODE(0x48000000) |
|
||||
EBC_BXCR_BS_64MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
|
||||
|
||||
/*-------------------------------------------------------------------------+
|
||||
| Connector 4~7. Initialize bank 3~ 7 with default values.
|
||||
+-------------------------------------------------------------------------*/
|
||||
mtebc(PB4AP,0);
|
||||
mtebc(PB4CR,0);
|
||||
mtebc(PB5AP,0);
|
||||
mtebc(PB5CR,0);
|
||||
mtebc(PB6AP,0);
|
||||
mtebc(PB6CR,0);
|
||||
mtebc(PB7AP,0);
|
||||
mtebc(PB7CR,0);
|
||||
|
||||
/*--------------------------------------------------------------------
|
||||
* Setup the interrupt controller polarities, triggers, etc.
|
||||
*-------------------------------------------------------------------*/
|
||||
/*
|
||||
* Because of the interrupt handling rework to handle 440GX interrupts
|
||||
* with the common code, we needed to change names of the UIC registers.
|
||||
* Here the new relationship:
|
||||
*
|
||||
* U-Boot name 440GX name
|
||||
* -----------------------
|
||||
* UIC0 UICB0
|
||||
* UIC1 UIC0
|
||||
* UIC2 UIC1
|
||||
* UIC3 UIC2
|
||||
*/
|
||||
mtdcr (UIC1SR, 0xffffffff); /* clear all */
|
||||
mtdcr (UIC1ER, 0x00000000); /* disable all */
|
||||
mtdcr (UIC1CR, 0x00000009); /* SMI & UIC1 crit are critical */
|
||||
mtdcr (UIC1PR, 0xfffffe13); /* per ref-board manual */
|
||||
mtdcr (UIC1TR, 0x01c00008); /* per ref-board manual */
|
||||
mtdcr (UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
|
||||
mtdcr (UIC1SR, 0xffffffff); /* clear all */
|
||||
|
||||
mtdcr (UIC2SR, 0xffffffff); /* clear all */
|
||||
mtdcr (UIC2ER, 0x00000000); /* disable all */
|
||||
mtdcr (UIC2CR, 0x00000000); /* all non-critical */
|
||||
mtdcr (UIC2PR, 0xffffe0ff); /* per ref-board manual */
|
||||
mtdcr (UIC2TR, 0x00ffc000); /* per ref-board manual */
|
||||
mtdcr (UIC2VR, 0x00000001); /* int31 highest, base=0x000 */
|
||||
mtdcr (UIC2SR, 0xffffffff); /* clear all */
|
||||
|
||||
mtdcr (UIC3SR, 0xffffffff); /* clear all */
|
||||
mtdcr (UIC3ER, 0x00000000); /* disable all */
|
||||
mtdcr (UIC3CR, 0x00000000); /* all non-critical */
|
||||
mtdcr (UIC3PR, 0xffffffff); /* per ref-board manual */
|
||||
mtdcr (UIC3TR, 0x00ff8c0f); /* per ref-board manual */
|
||||
mtdcr (UIC3VR, 0x00000001); /* int31 highest, base=0x000 */
|
||||
mtdcr (UIC3SR, 0xffffffff); /* clear all */
|
||||
|
||||
mtdcr (UIC0SR, 0xfc000000); /* clear all */
|
||||
mtdcr (UIC0ER, 0x00000000); /* disable all */
|
||||
mtdcr (UIC0CR, 0x00000000); /* all non-critical */
|
||||
mtdcr (UIC0PR, 0xfc000000); /* */
|
||||
mtdcr (UIC0TR, 0x00000000); /* */
|
||||
mtdcr (UIC0VR, 0x00000001); /* */
|
||||
|
||||
/* Enable two GPIO 10~11 and TraceA signal */
|
||||
mfsdr(SDR0_PFC0,reg);
|
||||
reg |= 0x00300000;
|
||||
mtsdr(SDR0_PFC0,reg);
|
||||
|
||||
mfsdr(SDR0_PFC1,reg);
|
||||
reg |= 0x00100000;
|
||||
mtsdr(SDR0_PFC1,reg);
|
||||
|
||||
/* Set GPIO 10 and 11 as output */
|
||||
GpioOdr = (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE+0x718);
|
||||
GpioTcr = (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE+0x704);
|
||||
GpioOr = (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE+0x700);
|
||||
|
||||
*GpioOdr &= ~(0x00300000);
|
||||
*GpioTcr |= 0x00300000;
|
||||
*GpioOr |= 0x00300000;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int misc_init_r(void)
|
||||
{
|
||||
lcd_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int checkboard (void)
|
||||
{
|
||||
char buf[64];
|
||||
int i = getenv_f("serial#", buf, sizeof(buf));
|
||||
|
||||
printf ("Board: Taishan - AMCC PPC440GX Evaluation Board");
|
||||
if (i > 0) {
|
||||
puts(", serial# ");
|
||||
puts(buf);
|
||||
}
|
||||
putc ('\n');
|
||||
|
||||
#ifdef CONFIG_SYS_INIT_SHOW_RESET_REG
|
||||
show_reset_reg();
|
||||
#endif
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
cpu_eth_init(bis);
|
||||
return pci_eth_init(bis);
|
||||
}
|
||||
|
|
@ -1,62 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <config.h>
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <asm/processor.h>
|
||||
#include <i2c.h>
|
||||
|
||||
#if defined(CONFIG_TAISHAN)
|
||||
|
||||
const uchar bootstrap_buf[16] = {
|
||||
0x86,
|
||||
0x78,
|
||||
0xc1,
|
||||
0xa6,
|
||||
0x09,
|
||||
0x67,
|
||||
0x04,
|
||||
0x63,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00,
|
||||
0x00
|
||||
};
|
||||
|
||||
static int update_boot_eeprom(void)
|
||||
{
|
||||
ulong len = 0x10;
|
||||
uchar chip = CONFIG_SYS_BOOTSTRAP_IIC_ADDR;
|
||||
uchar *pbuf = (uchar *)bootstrap_buf;
|
||||
int ii, jj;
|
||||
|
||||
for (ii = 0; ii < len; ii++) {
|
||||
if (i2c_write(chip, ii, 1, &pbuf[ii], 1) != 0) {
|
||||
printf("i2c_write failed\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* wait 10ms */
|
||||
for (jj = 0; jj < 10; jj++)
|
||||
udelay(1000);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int do_update_boot_eeprom(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
|
||||
{
|
||||
return update_boot_eeprom();
|
||||
}
|
||||
|
||||
U_BOOT_CMD(update_boot_eeprom, 1, 1, do_update_boot_eeprom,
|
||||
"update bootstrap eeprom content", "");
|
||||
#endif
|
||||
|
|
@ -1,3 +0,0 @@
|
|||
CONFIG_PPC=y
|
||||
CONFIG_4xx=y
|
||||
CONFIG_TARGET_TAISHAN=y
|
||||
|
|
@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
|
|||
|
||||
Board Arch CPU Commit Removed Last known maintainer/contact
|
||||
=================================================================================================
|
||||
taishan powerpc ppc4xx - - Stefan Roese <sr@denx.de>
|
||||
ebony powerpc ppc4xx - - Stefan Roese <sr@denx.de>
|
||||
taihu powerpc ppc4xx - - John Otken <jotken@softadvances.com>
|
||||
lcd4_lwmon5 powerpc ppc4xx b6b5e394 2015-10-02 Stefan Roese <sr@denx.de>
|
||||
|
|
|
|||
|
|
@ -1,193 +0,0 @@
|
|||
/*
|
||||
* (C) Copyright 2007
|
||||
* Stefan Roese, DENX Software Engineering, sr@denx.de.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
/************************************************************************
|
||||
* TAISHAN.h - configuration for AMCC 440GX Ref
|
||||
***********************************************************************/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* High Level Configuration Options
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_TAISHAN 1 /* Board is taishan */
|
||||
#define CONFIG_440GX 1 /* Specifc GX support */
|
||||
#define CONFIG_440 1 /* ... PPC440 family */
|
||||
#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
|
||||
|
||||
#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
|
||||
|
||||
/*
|
||||
* Include common defines/options for all AMCC eval boards
|
||||
*/
|
||||
#define CONFIG_HOSTNAME taishan
|
||||
#define CONFIG_USE_TTY ttyS1
|
||||
#include "amcc-common.h"
|
||||
|
||||
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
|
||||
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Base addresses -- Note these are effective addresses where the
|
||||
* actual resources get mapped (not physical addresses)
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */
|
||||
#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
|
||||
#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */
|
||||
#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
|
||||
|
||||
#define CONFIG_SYS_EBC0_FLASH_BASE CONFIG_SYS_FLASH_BASE
|
||||
#define CONFIG_SYS_EBC1_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x01000000)
|
||||
#define CONFIG_SYS_EBC2_LCM_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x02000000)
|
||||
#define CONFIG_SYS_EBC3_CONN_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
|
||||
|
||||
#define CONFIG_SYS_GPIO_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Initial RAM & stack pointer (placed in internal SRAM)
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_SYS_TEMP_STACK_OCM 1
|
||||
#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM*/
|
||||
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Serial Port
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_CONS_INDEX 2 /* Use UART1 */
|
||||
#define CONFIG_SYS_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Environment
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* FLASH related
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_SYS_FLASH_CFI
|
||||
#define CONFIG_FLASH_CFI_DRIVER
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
|
||||
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
|
||||
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
|
||||
|
||||
#undef CONFIG_SYS_FLASH_CHECKSUM
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
|
||||
|
||||
#define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
|
||||
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
|
||||
|
||||
/* Address and size of Redundant Environment Sector */
|
||||
#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
|
||||
#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* E2PROM bootstrap configure value
|
||||
*----------------------------------------------------------------------*/
|
||||
|
||||
/*
|
||||
* 800/133/66
|
||||
* IIC 0~15: 86 78 11 6a 61 A7 04 62 00 00 00 00 00 00 00 00
|
||||
*/
|
||||
|
||||
/*
|
||||
* 800/160/80
|
||||
* IIC 0~15: 86 78 c1 a6 09 67 04 63 00 00 00 00 00 00 00 00
|
||||
*/
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* DDR SDRAM
|
||||
*----------------------------------------------------------------------*/
|
||||
#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */
|
||||
#define CONFIG_SDRAM_BANK0 1 /* init onboard DDR SDRAM bank 0 */
|
||||
#define CONFIG_SYS_SDRAM0_TR0 0xC10A401A
|
||||
#undef CONFIG_SDRAM_ECC /* enable ECC support */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* I2C
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
|
||||
|
||||
#undef CONFIG_SYS_I2C_MULTI_EEPROMS
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
|
||||
|
||||
#define CONFIG_SYS_BOOTSTRAP_IIC_ADDR 0x50
|
||||
|
||||
/* I2C SYSMON (LM75, AD7414 is almost compatible) */
|
||||
#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
|
||||
#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
|
||||
#define CONFIG_SYS_DTT_MAX_TEMP 70
|
||||
#define CONFIG_SYS_DTT_LOW_TEMP -30
|
||||
#define CONFIG_SYS_DTT_HYSTERESIS 3
|
||||
|
||||
/*
|
||||
* Default environment variables
|
||||
*/
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
CONFIG_AMCC_DEF_ENV \
|
||||
CONFIG_AMCC_DEF_ENV_POWERPC \
|
||||
CONFIG_AMCC_DEF_ENV_PPC_OLD \
|
||||
CONFIG_AMCC_DEF_ENV_NOR_UPD \
|
||||
"kernel_addr=fc000000\0" \
|
||||
"ramdisk_addr=fc180000\0" \
|
||||
"kozio=bootm 0xffe00000\0" \
|
||||
""
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* Networking
|
||||
*----------------------------------------------------------------------*/
|
||||
#define CONFIG_EMAC_NR_START 2 /* start with EMAC 2 (skip 0&1) */
|
||||
#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */
|
||||
#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */
|
||||
#define CONFIG_PHY2_ADDR 0x1
|
||||
#define CONFIG_PHY3_ADDR 0x3
|
||||
#define CONFIG_ET1011C_PHY 1
|
||||
#define CONFIG_HAS_ETH0
|
||||
#define CONFIG_HAS_ETH1
|
||||
#define CONFIG_HAS_ETH2
|
||||
#define CONFIG_HAS_ETH3
|
||||
#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
|
||||
#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
|
||||
#define CONFIG_PHY_RESET_DELAY 1000
|
||||
|
||||
/*
|
||||
* Commands additional to the ones defined in amcc-common.h
|
||||
*/
|
||||
#define CONFIG_CMD_DTT
|
||||
#define CONFIG_CMD_PCI
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCI stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
/* General PCI */
|
||||
#define CONFIG_PCI /* include pci support */
|
||||
#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
|
||||
#define CONFIG_PCI_PNP /* do pci plug-and-play */
|
||||
#define CONFIG_EEPRO100 1 /* include PCI EEPRO100 */
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
|
||||
|
||||
/* Board-specific PCI */
|
||||
#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
|
||||
|
||||
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
|
||||
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in a new issue