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ppc: xilinx-ppc4xx-generic: Update xparameters.h
-Remove UART address (It is now part of the dts). -Include dummy ns16550 clock -Fix address to last test Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Acked-by: Stefan Roese <sr@denx.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Michal Simek <michal.simek@xilinx.com>
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3 changed files with 9 additions and 8 deletions
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@ -14,12 +14,12 @@
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#define XPAR_IIC_EEPROM_BASEADDR 0x81600000
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#define XPAR_INTC_0_BASEADDR 0x81800000
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#define XPAR_SPI_0_BASEADDR 0x83400000
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#define XPAR_UARTLITE_0_BASEADDR 0x84000000
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#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000
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#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
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#define XPAR_CORE_CLOCK_FREQ_HZ 400000000
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#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13
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#define XPAR_UARTLITE_0_BAUDRATE 9600
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#define XPAR_INTC_MAX_NUM_INTR_INPUTS 32
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#define XPAR_SPI_0_NUM_TRANSFER_BITS 8
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#define XPAR_UARTNS550_0_BASEADDR 0xdeadbeef
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#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000
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#endif
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@ -12,12 +12,12 @@
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#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000
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#define XPAR_IIC_EEPROM_BASEADDR 0x81600000
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#define XPAR_INTC_0_BASEADDR 0x81800000
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#define XPAR_UARTLITE_0_BASEADDR 0x84000000
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#define XPAR_FLASH_MEM0_BASEADDR 0xFE000000
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#define XPAR_INTC_0_BASEADDR 0x87000000
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#define XPAR_FLASH_MEM0_BASEADDR 0xF0000000
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#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
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#define XPAR_CORE_CLOCK_FREQ_HZ 400000000
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#define XPAR_INTC_MAX_NUM_INTR_INPUTS 13
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#define XPAR_UARTLITE_0_BAUDRATE 9600
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#define XPAR_INTC_MAX_NUM_INTR_INPUTS 32
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#define XPAR_UARTNS550_0_BASEADDR 0xdeadbeef
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#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000
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#endif
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@ -109,6 +109,7 @@
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#define CONFIG_SYS_BAUDRATE_TABLE { CONFIG_BAUDRATE }
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#else
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#ifdef XPAR_UARTNS550_0_BASEADDR
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 4
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#define CONFIG_CONS_INDEX 1
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