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x86: Drop all the old pin configuration code

Browse source 
We don't need this anymore - we can use device tree and the new pinconfig
driver instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Simon Glass 2016-03-11 22:07:15 -07:00 committed by Bin Meng
parent 15cf75ec15
commit 779653b0cb
13 changed files with 0 additions and 334 deletions
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141
arch/x86/include/asm/gpio.h
View file

@ -6,7 +6,6 @@
#ifndef _X86_GPIO_H_
#define _X86_GPIO_H_
#include <linux/compiler.h>
#include <asm-generic/gpio.h>
struct ich6_bank_platdata {
@ -15,144 +14,4 @@ struct ich6_bank_platdata {
int offset;
};
#define GPIO_MODE_NATIVE 0
#define GPIO_MODE_GPIO 1
#define GPIO_MODE_NONE 1
#define GPIO_DIR_OUTPUT 0
#define GPIO_DIR_INPUT 1
#define GPIO_NO_INVERT 0
#define GPIO_INVERT 1
#define GPIO_LEVEL_LOW 0
#define GPIO_LEVEL_HIGH 1
#define GPIO_NO_BLINK 0
#define GPIO_BLINK 1
#define GPIO_RESET_PWROK 0
#define GPIO_RESET_RSMRST 1
struct pch_gpio_set1 {
u32 gpio0:1;
u32 gpio1:1;
u32 gpio2:1;
u32 gpio3:1;
u32 gpio4:1;
u32 gpio5:1;
u32 gpio6:1;
u32 gpio7:1;
u32 gpio8:1;
u32 gpio9:1;
u32 gpio10:1;
u32 gpio11:1;
u32 gpio12:1;
u32 gpio13:1;
u32 gpio14:1;
u32 gpio15:1;
u32 gpio16:1;
u32 gpio17:1;
u32 gpio18:1;
u32 gpio19:1;
u32 gpio20:1;
u32 gpio21:1;
u32 gpio22:1;
u32 gpio23:1;
u32 gpio24:1;
u32 gpio25:1;
u32 gpio26:1;
u32 gpio27:1;
u32 gpio28:1;
u32 gpio29:1;
u32 gpio30:1;
u32 gpio31:1;
} __packed;
struct pch_gpio_set2 {
u32 gpio32:1;
u32 gpio33:1;
u32 gpio34:1;
u32 gpio35:1;
u32 gpio36:1;
u32 gpio37:1;
u32 gpio38:1;
u32 gpio39:1;
u32 gpio40:1;
u32 gpio41:1;
u32 gpio42:1;
u32 gpio43:1;
u32 gpio44:1;
u32 gpio45:1;
u32 gpio46:1;
u32 gpio47:1;
u32 gpio48:1;
u32 gpio49:1;
u32 gpio50:1;
u32 gpio51:1;
u32 gpio52:1;
u32 gpio53:1;
u32 gpio54:1;
u32 gpio55:1;
u32 gpio56:1;
u32 gpio57:1;
u32 gpio58:1;
u32 gpio59:1;
u32 gpio60:1;
u32 gpio61:1;
u32 gpio62:1;
u32 gpio63:1;
} __packed;
struct pch_gpio_set3 {
u32 gpio64:1;
u32 gpio65:1;
u32 gpio66:1;
u32 gpio67:1;
u32 gpio68:1;
u32 gpio69:1;
u32 gpio70:1;
u32 gpio71:1;
u32 gpio72:1;
u32 gpio73:1;
u32 gpio74:1;
u32 gpio75:1;
} __packed;
/*
* This hilariously complex structure came from Coreboot. The
* setup_pch_gpios() function uses it. It could be move to device tree, or
* adjust to use masks instead of bitfields.
*/
struct pch_gpio_map {
struct {
const struct pch_gpio_set1 *mode;
const struct pch_gpio_set1 *direction;
const struct pch_gpio_set1 *level;
const struct pch_gpio_set1 *reset;
const struct pch_gpio_set1 *invert;
const struct pch_gpio_set1 *blink;
} set1;
struct {
const struct pch_gpio_set2 *mode;
const struct pch_gpio_set2 *direction;
const struct pch_gpio_set2 *level;
const struct pch_gpio_set2 *reset;
} set2;
struct {
const struct pch_gpio_set3 *mode;
const struct pch_gpio_set3 *direction;
const struct pch_gpio_set3 *level;
const struct pch_gpio_set3 *reset;
} set3;
};
/*
* Deprecated functions to set up the GPIO map. The device tree should be used
* instead.
*/
int gpio_ich6_pinctrl_init(void);
void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio);
void ich_gpio_set_gpio_map(const struct pch_gpio_map *map);
#endif /* _X86_GPIO_H_ */

5
board/coreboot/coreboot/coreboot.c
View file

@ -12,8 +12,3 @@ int arch_early_init_r(void)
{
return 0;
}
void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
{
return;
}

5
board/efi/efi-x86/efi.c
View file

@ -11,8 +11,3 @@ int arch_early_init_r(void)
{
return 0;
}
void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
{
return;
}

138
board/google/chromebook_link/link.c
View file

@ -17,145 +17,7 @@ int arch_early_init_r(void)
return 0;
}
static const struct pch_gpio_set1 pch_gpio_set1_mode = {
.gpio0 = GPIO_MODE_GPIO, /* NMI_DBG# */
.gpio3 = GPIO_MODE_GPIO, /* ALS_INT# */
.gpio5 = GPIO_MODE_GPIO, /* SIM_DET */
.gpio7 = GPIO_MODE_GPIO, /* EC_SCI# */
.gpio8 = GPIO_MODE_GPIO, /* EC_SMI# */
.gpio9 = GPIO_MODE_GPIO, /* RECOVERY# */
.gpio10 = GPIO_MODE_GPIO, /* SPD vector D3 */
.gpio11 = GPIO_MODE_GPIO, /* smbalert#, let's keep it initialized */
.gpio12 = GPIO_MODE_GPIO, /* TP_INT# */
.gpio14 = GPIO_MODE_GPIO, /* Touch_INT_L */
.gpio15 = GPIO_MODE_GPIO, /* EC_LID_OUT# (EC_WAKE#) */
.gpio21 = GPIO_MODE_GPIO, /* EC_IN_RW */
.gpio24 = GPIO_MODE_GPIO, /* DDR3L_EN */
.gpio28 = GPIO_MODE_GPIO, /* SLP_ME_CSW_DEV# */
};
static const struct pch_gpio_set1 pch_gpio_set1_direction = {
.gpio0 = GPIO_DIR_INPUT,
.gpio3 = GPIO_DIR_INPUT,
.gpio5 = GPIO_DIR_INPUT,
.gpio7 = GPIO_DIR_INPUT,
.gpio8 = GPIO_DIR_INPUT,
.gpio9 = GPIO_DIR_INPUT,
.gpio10 = GPIO_DIR_INPUT,
.gpio11 = GPIO_DIR_INPUT,
.gpio12 = GPIO_DIR_INPUT,
.gpio14 = GPIO_DIR_INPUT,
.gpio15 = GPIO_DIR_INPUT,
.gpio21 = GPIO_DIR_INPUT,
.gpio24 = GPIO_DIR_OUTPUT,
.gpio28 = GPIO_DIR_INPUT,
};
static const struct pch_gpio_set1 pch_gpio_set1_level = {
.gpio1 = GPIO_LEVEL_HIGH,
.gpio6 = GPIO_LEVEL_HIGH,
.gpio24 = GPIO_LEVEL_LOW,
};
static const struct pch_gpio_set1 pch_gpio_set1_invert = {
.gpio7 = GPIO_INVERT,
.gpio8 = GPIO_INVERT,
.gpio12 = GPIO_INVERT,
.gpio14 = GPIO_INVERT,
.gpio15 = GPIO_INVERT,
};
static const struct pch_gpio_set2 pch_gpio_set2_mode = {
.gpio36 = GPIO_MODE_GPIO, /* W_DISABLE_L */
.gpio41 = GPIO_MODE_GPIO, /* SPD vector D0 */
.gpio42 = GPIO_MODE_GPIO, /* SPD vector D1 */
.gpio43 = GPIO_MODE_GPIO, /* SPD vector D2 */
.gpio57 = GPIO_MODE_GPIO, /* PCH_SPI_WP_D */
.gpio60 = GPIO_MODE_GPIO, /* DRAMRST_CNTRL_PCH */
};
static const struct pch_gpio_set2 pch_gpio_set2_direction = {
.gpio36 = GPIO_DIR_OUTPUT,
.gpio41 = GPIO_DIR_INPUT,
.gpio42 = GPIO_DIR_INPUT,
.gpio43 = GPIO_DIR_INPUT,
.gpio57 = GPIO_DIR_INPUT,
.gpio60 = GPIO_DIR_OUTPUT,
};
static const struct pch_gpio_set2 pch_gpio_set2_level = {
.gpio36 = GPIO_LEVEL_HIGH,
.gpio60 = GPIO_LEVEL_HIGH,
};
static const struct pch_gpio_set3 pch_gpio_set3_mode = {
};
static const struct pch_gpio_set3 pch_gpio_set3_direction = {
};
static const struct pch_gpio_set3 pch_gpio_set3_level = {
};
static const struct pch_gpio_map link_gpio_map = {
.set1 = {
.mode = &pch_gpio_set1_mode,
.direction = &pch_gpio_set1_direction,
.level = &pch_gpio_set1_level,
.invert = &pch_gpio_set1_invert,
},
.set2 = {
.mode = &pch_gpio_set2_mode,
.direction = &pch_gpio_set2_direction,
.level = &pch_gpio_set2_level,
},
.set3 = {
.mode = &pch_gpio_set3_mode,
.direction = &pch_gpio_set3_direction,
.level = &pch_gpio_set3_level,
},
};
int board_early_init_f(void)
{
ich_gpio_set_gpio_map(&link_gpio_map);
return 0;
}
void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
{
/* GPIO Set 1 */
if (gpio->set1.level)
outl(*((u32 *)gpio->set1.level), gpiobase + GP_LVL);
if (gpio->set1.mode)
outl(*((u32 *)gpio->set1.mode), gpiobase + GPIO_USE_SEL);
if (gpio->set1.direction)
outl(*((u32 *)gpio->set1.direction), gpiobase + GP_IO_SEL);
if (gpio->set1.reset)
outl(*((u32 *)gpio->set1.reset), gpiobase + GP_RST_SEL1);
if (gpio->set1.invert)
outl(*((u32 *)gpio->set1.invert), gpiobase + GPI_INV);
if (gpio->set1.blink)
outl(*((u32 *)gpio->set1.blink), gpiobase + GPO_BLINK);
/* GPIO Set 2 */
if (gpio->set2.level)
outl(*((u32 *)gpio->set2.level), gpiobase + GP_LVL2);
if (gpio->set2.mode)
outl(*((u32 *)gpio->set2.mode), gpiobase + GPIO_USE_SEL2);
if (gpio->set2.direction)
outl(*((u32 *)gpio->set2.direction), gpiobase + GP_IO_SEL2);
if (gpio->set2.reset)
outl(*((u32 *)gpio->set2.reset), gpiobase + GP_RST_SEL2);
/* GPIO Set 3 */
if (gpio->set3.level)
outl(*((u32 *)gpio->set3.level), gpiobase + GP_LVL3);
if (gpio->set3.mode)
outl(*((u32 *)gpio->set3.mode), gpiobase + GPIO_USE_SEL3);
if (gpio->set3.direction)
outl(*((u32 *)gpio->set3.direction), gpiobase + GP_IO_SEL3);
if (gpio->set3.reset)
outl(*((u32 *)gpio->set3.reset), gpiobase + GP_RST_SEL3);
}

4
board/google/chromebox_panther/panther.c
View file

@ -16,7 +16,3 @@ int board_early_init_f(void)
{
return 0;
}
void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
{
}

5
board/intel/bayleybay/bayleybay.c
View file

@ -6,8 +6,3 @@
#include <common.h>
#include <asm/gpio.h>
void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
{
return;
}

5
board/intel/cougarcanyon2/cougarcanyon2.c
View file

@ -52,8 +52,3 @@ int board_early_init_f(void)
return 0;
}
void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
{
return;
}

5
board/intel/crownbay/crownbay.c
View file

@ -18,8 +18,3 @@ int board_early_init_f(void)
return 0;
}
void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
{
return;
}

5
board/intel/galileo/galileo.c
View file

@ -65,8 +65,3 @@ void board_deassert_perst(void)
val |= (1 << 0);
outl(val, port);
}
void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
{
return;
}

8
board/intel/minnowmax/minnowmax.c
View file

@ -9,13 +9,5 @@
int arch_early_init_r(void)
{
/* do the pin-muxing */
gpio_ich6_pinctrl_init();
return 0;
}
void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio)
{
return;
}

11
drivers/gpio/intel_ich6_gpio.c
View file

@ -53,12 +53,6 @@ struct ich6_bank_priv {
#define GPIO_IOSEL_OFFSET(x) (x + 4)
#define GPIO_LVL_OFFSET(x) (x + 8)
/* TODO: Move this to device tree, or platform data */
void ich_gpio_set_gpio_map(const struct pch_gpio_map *map)
{
gd->arch.gpio_map = map;
}
static int _ich6_gpio_set_value(uint16_t base, unsigned offset, int value)
{
u32 val;
@ -90,11 +84,6 @@ static int _ich6_gpio_set_direction(uint16_t base, unsigned offset, int dir)
return 0;
}
int gpio_ich6_pinctrl_init(void)
{
return 0;
}
static int gpio_ich6_ofdata_to_platdata(struct udevice *dev)
{
struct ich6_bank_platdata *plat = dev_get_platdata(dev);

1
include/fdtdec.h
View file

@ -159,7 +159,6 @@ enum fdt_compat_id {
COMPAT_AMS_AS3722, /* AMS AS3722 PMIC */
COMPAT_INTEL_ICH_SPI, /* Intel ICH7/9 SPI controller */
COMPAT_INTEL_QRK_MRC, /* Intel Quark MRC */
COMPAT_INTEL_X86_PINCTRL, /* Intel ICH7/9 pin control */
COMPAT_SOCIONEXT_XHCI, /* Socionext UniPhier xHCI */
COMPAT_INTEL_PCH, /* Intel PCH */
COMPAT_ALTERA_SOCFPGA_DWMAC, /* SoCFPGA Ethernet controller */

1
lib/fdtdec.c
View file

@ -64,7 +64,6 @@ static const char * const compat_names[COMPAT_COUNT] = {
COMPAT(AMS_AS3722, "ams,as3722"),
COMPAT(INTEL_ICH_SPI, "intel,ich-spi"),
COMPAT(INTEL_QRK_MRC, "intel,quark-mrc"),
COMPAT(INTEL_X86_PINCTRL, "intel,x86-pinctrl"),
COMPAT(SOCIONEXT_XHCI, "socionext,uniphier-xhci"),
COMPAT(COMPAT_INTEL_PCH, "intel,bd82x6x"),
COMPAT(ALTERA_SOCFPGA_DWMAC, "altr,socfpga-stmmac"),