Commit graph

20023 commits

Author SHA1 Message Date
Vignesh Raghavendra
9e8a9b6457 ARM: dts: k3-j7200: Add wkup gpio node
Add wkup_gpio0 node required for detecting whether board mux is set
HyperFlash.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-08-11 20:34:46 +05:30
Vignesh Raghavendra
86c9bd4eb7 arm: dts: k3-j7200: Add USB related DT entries
Add USB related DT entries to enable USB device mode.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-08-11 20:34:46 +05:30
Dave Gerlach
7cc9855f31 arm: dts: k3-j7200: Add R5 specific dts support
Add the basic a72 basic dts for j7200. Following nodes were supported:
- UART
- MMC SD
- I2C
- TISCI communication
- LPDDR with 1600MTs configuration.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2020-08-11 20:34:46 +05:30
Lokesh Vutla
a7551cf05d arm: dts: k3-j7200: Add dts support
Add the basic a72 dts for j7200. Following nodes were supported:
- UART
- MMC SD
- I2C
- TISCI communication

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Vishal Mahaveer <vishalm@ti.com>
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-08-11 20:34:46 +05:30
Lokesh Vutla
01dbe366ba arm: mach-k3: j7200: Detect if ROM has already loaded sysfw
Detect if sysfw is already loaded by ROM and pass this information to
sysfw loader. Based on this information sysfw loader either loads the
sysfw image from boot media or just receives the boot notification
message form sysfw.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
2020-08-11 20:34:46 +05:30
Lokesh Vutla
9c8f41beea arm: mach-k3: j7200: Add support for storing extended boot info from ROM
Starting J7200 SoC, ROM supports for loading sysfw directly from boot
image. ROM passes this information on number of images that are loaded
to bootloader at certain location. Add support for storing this
information before it gets corrupted.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
2020-08-11 20:34:46 +05:30
Lokesh Vutla
30de1ba0d3 arm: mach-k3: j7200: Add support for SOC detection
The J7200 SoC is a part of the K3 Multicore SoC architecture platform.
It is targeted for automotive gateway, vehicle compute systems,
Vehicle-to-Vehicle (V2V) and Vehicle-to-Everything (V2X) applications.
The SoC aims to meet the complex processing needs of modern embedded
products.

Some highlights of this SoC are:
* Dual Cortex-A72s in a single cluster, two clusters of lockstep
  capable dual Cortex-R5F MCUs and a Centralized Device Management and
  Security Controller (DMSC).
* Configurable L3 Cache and IO-coherent architecture with high data
  throughput capable distributed DMA architecture under NAVSS.
* Integrated Ethernet switch supporting up to a total of 4 external ports
  in addition to legacy Ethernet switch of up to 2 ports.
* Upto 1 PCIe-GEN3 controller, 1 USB3.0 Dual-role device subsystems,
  20 MCANs, 3 McASP, eMMC and SD, OSPI/HyperBus memory controller, I3C and
  I2C, eCAP/eQEP, eHRPWM among other peripherals.
* One hardware accelerator block containing AES/DES/SHA/MD5 called SA2UL
  management.

See J7200 Technical Reference Manual (SPRUIU1, June 2020)
for further details: https://www.ti.com/lit/pdf/spruiu1

Add support for detection J7200 SoC

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
2020-08-11 20:34:46 +05:30
Lokesh Vutla
73108dcd7f arm: mach-k3: j721e: Fix unlocking control module registers
In main control mmr there is no partition 4 and partition 6 is available
only on J721e. Fix the same in ctrl_mmr_unlock function

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
2020-08-11 20:34:46 +05:30
Lokesh Vutla
2a18be77de arm: mach-k3: j721e: Add detection for j721e
Add an api soc_is_j721e(), and use it to enable certain functionality
that is available only on j721e. This detection is needed when DT is not
available.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
2020-08-11 20:34:46 +05:30
Lokesh Vutla
dc57a554a5 arm: mach-k3: sysfw-loader: Add support for rom loading sysfw image
Starting J7200 SoC, ROM supports for loading sysfw directly from boot
image. In such cases, SPL need not load sysfw from boot media, but need
to receive boot notification message from sysfw. So separate out
remoteproc calls for system controller from sysfw loader and just
receive the boot notification if sysfw is already loaded.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
2020-08-11 20:34:46 +05:30
Lokesh Vutla
58ccd6105c arm: mach-k3: Move mmr_unlock to a common location
mmr_unlock api is common for all k3 devices. Move it to a common
location.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Suman Anna <s-anna@ti.com>
2020-08-11 20:34:46 +05:30
Jean-Jacques Hiblot
d099db2829 arm: mach-k3: Fix platform hang when SPL_MULTI_DTB_FIT is not enabled
If SPL_MULTI_DTB_FIT is not enabled, then CONFIG_SPL_OF_LIST is not defined
And in turn tispl.bin ends up not embedding any DTB.
Fixing it by using CONFIG_DEFAULT_DEVICE_TREE if SPL_OF_LIST is empty.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-08-11 20:34:46 +05:30
Lokesh Vutla
b29a7cd09d board: ti: j721e: Probe eeprom only when CONFIG_TI_I2C_BOARD_DETECT is defined
Guard all eeprom probe with TI_I2C_BOARD_DETECT to avoid reading eeprom
when eeprom is not available

Reviewed-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
2020-08-11 20:34:46 +05:30
Faiz Abbas
c20aee3e28 arm: dts: k3-am654-base-board: Add support for USB0 in SPL
Add nodes for USB0 in SPL to enable USB host boot mode

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-08-11 20:34:46 +05:30
Faiz Abbas
5251eb13bd arm: dts: k3-am654-r5-base-board: Add USB0 nodes
Add USB0 nodes and set them to host mode to support USB host and
peripheral boot modes

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-08-11 20:34:46 +05:30
Faiz Abbas
897e83f0a5 arm: mach-k3: am6_init: Add support for USB boot mode
Add support for identifying USB host and device boot modes

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-08-11 20:34:46 +05:30
Faiz Abbas
403fc5c9cf arm: mach-k3: am6_init: Do USB fixups to facilitate host and device boot modes
U-boot only supports either USB host or device mode for a node at a
time in dts. To support both host and dfu bootmodes, set "peripheral"
as the default dr_mode but fixup property to "host" if host bootmode
is detected.

This needs to happen before the dwc3 generic layer binds the usb device
to a host or device driver. Therefore, add an fdtdec_setup_board()
implementation to fixup the dt based on the boot mode.

Also use the same fixup function to set the USB-PCIe Serdes mux to PCIe
in both the host and device cases. This is required for accessing the
interface at USB 2.0 speeds.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-08-11 20:34:46 +05:30
Faiz Abbas
febb47ac61 arm: mach-k3: am6_init: Gate mmc related configurations with the appropriate config
Gate mmc related system related configurations with DM_MMC to avoid build
errors when MMC is not enabled

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-08-11 20:34:46 +05:30
Faiz Abbas
f5838b1542 arm: mach-k3: sysfw-loader: Add support to load SYSFW from USB
Add support for loading system firmware from a USB mass storage device

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-08-11 20:34:46 +05:30
Faiz Abbas
f9916b6d3b armv7R: K3: am654: Use full malloc in SPL both pre and post reloc
In order to be able to use things like file system drivers early on in
SPL (before relocation) in a memory-constrained environment when DDR is
not yet available we cannot use the simple malloc scheme which does not
implement the freeing of previously allocated memory blocks. To address
this issue go ahead and enable the use of the full malloc by manually
initializing the required functionality inside board_init_f by creating
a full malloc pool inside the pre-relocation malloc pool.

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-08-11 20:34:46 +05:30
Suman Anna
f3f2018f66 arm: dts: k3-j721e: Fix interconnect node names
The various CBASS interconnect nodes on K3 J721E SoCs are defined
using the node name "interconnect". This is not a valid node name
as per the dt-schema. Fix these node names to use the standard name
used for SoC interconnects, "bus".

Signed-off-by: Suman Anna <s-anna@ti.com>
2020-08-11 20:34:45 +05:30
Suman Anna
58edc6f686 arm: dts: k3-am65: Fix interconnect node names
The various CBASS interconnect nodes on K3 AM65x SoCs are defined
using the node name "interconnect". This is not a valid node name
as per the dt-schema. Fix these node names to use the standard name
used for SoC interconnects, "bus".

Signed-off-by: Suman Anna <s-anna@ti.com>
2020-08-11 20:34:45 +05:30
Derald D. Woods
5297a956cb ARM: omap3: evm: Complete DM_ETH and DM_USB migrations
This commit completes the migrations for DM_ETH and DM_USB. The board
is now consistent with omap3_beagle and other remaining OMAP3 boards.

Cc: Tom Rini <trini@konsulko.com>
Cc: Adam Ford <aford173@gmail.com>
Signed-off-by: Derald D. Woods <woods.technical@gmail.com>
2020-08-11 20:34:45 +05:30
Andrew F. Davis
864e285739 arm: mach-k3: Clean non-coherent lines out of L3 cache
When switching on or off the ARM caches some care must be taken to ensure
existing cache line allocations are not left in an inconsistent state.
An example of this is when cache lines are considered non-shared by
and L3 controller even though the lines are shared. To prevent these
and other issues all cache lines should be cleared before enabling
or disabling a coherent master's cache. ARM cores and many L3 controllers
provide a way to efficiently clean out all cache lines to allow for
this, unfortunately there is no such easy way to do this on current K3
MSMC based systems.

We could explicitly clean out every valid external address tracked by
MSMC (all of DRAM), or we could attempt to identify only the set of
addresses accessed by a given boot stage and flush only those
specifically. This patch attempts the latter. We start with cleaning the
SPL load address. More addresses can be added here later as they are
identified.

Note that we perform a flush operation for both the flush and invalidate
operations, this is not a typo. We do this to avoid the situation that
some ARM cores will promote an invalidate to a clean+invalidate, but only
emit the invalidation operation externally, leading to a loss of data.

Signed-off-by: Andrew F. Davis <afd@ti.com>
Tested-by: Faiz Abbas <faiz_abbas@ti.com>
2020-08-11 10:18:27 +05:30
Jan Kiszka
e1c3668594 arm: dts: k3: Add RTI watchdogs
Add DT entries for main domain watchdog0 and 1 instances on the J721e
well as RTI1-based watchdog on the AM65x. RTI0 does not work for this
purpose on the AM65x, so leave it out.

On AM65x, we mark the power-domain as shared because RTI firmware such
as https://github.com/siemens/k3-rti-wdt may request it as well in order
to prevent accidental shutdown of the watchdog.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2020-08-11 10:18:27 +05:30
Jway Lin
edca8edd79 board: presidio: add LED support
Add LED support for Cortina Access Presidio Engineering Board

Signed-off-by: Jway Lin <jway.lin@cortina-access.com>
Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

CC: Simon Glass <sjg@chromium.org>
2020-08-07 22:31:32 -04:00
Ovidiu Panait
f1e504a3ea board_f: ppc: Factor out ppc-specific bdinfo setup
Factor out ppc-specific bdinfo setup from generic init sequence to
arch_setup_bdinfo in arch/powerpc/lib/bdinfo.c.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
2020-08-06 14:26:35 -04:00
Ovidiu Panait
ee9c3adc85 board_f: m68k: Factor out m68k-specific bdinfo setup
Factor out m68k-specific bdinfo setup to arch_setup_bdinfo in
arch/m68k/lib/bdinfo.c. Also, use if(IS_ENABLED()) instead of #ifdef where
possible.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
2020-08-06 14:26:35 -04:00
Ovidiu Panait
a4aa188948 board_f: Factor out bdinfo bi_mem{start, size} to setup_bdinfo
Move all assignments to gd->bd->bi_mem{start,size} to generic code in
setup_bdinfo.

Xtensa architecture is special in this regard as it defines its own
handling of gd->bd->bi_mem{start,size} fields. In order to avoid defining
a weak SDRAM function, let arch_setup_bdinfo overwrite the generic flags.

For ARC architecture, remove ARCH_EARLY_INIT_R from Kconfig since it is
not needed anymore.

Also, use gd->ram_base to populate bi_memstart to avoid an ifdef.

Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
Acked-by: Alexey Brodkin <abrokdin@synopsys.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-06 14:26:35 -04:00
Ovidiu Panait
6ecefcfb6d cmd: bdinfo: Move sram info prints to generic code
bi_sramstart and bi_sramsize are generic members of the bd_info structure,
so move the m68k/powerpc-specific prints to generic code. Also, print them
only if SRAM support is enabled via CONFIG_SYS_HAS_SRAM.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
2020-08-06 14:26:35 -04:00
Luka Kovacic
14133650d8 arm: mvebu: Update CRS305-1G-4S board flash layout
Update the MikroTik CRS305-1G-4S flash layout to support redundant UBI
partitions.
Additionally enable the UBI commands in crs305-1g-4s_defconfig.

Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Jakov Petrina <jakov.petrina@sartura.hr>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-08-06 14:12:14 +02:00
Luka Kovacic
537eaf4ea7 arm: mvebu: Add CRS328-4C-20S-4S board
MikroTik CRS328-4C-20S-4S board has a switch chip with an integrated
Marvell Prestera 98DX3236 CPU.

This commit includes two board variants, namely the factory
default one and a Bit variant. The Bit board variant has a
bigger Macronix flash.

Add basic U-Boot, UART and SPI flash support.

Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Jakov Petrina <jakov.petrina@sartura.hr>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-08-06 14:12:14 +02:00
Luka Kovacic
d4cc179fcd arm: mvebu: Add CRS326-24G-2S board
MikroTik CRS326-24G-2S board has a switch chip with an integrated
Marvell Prestera 98DX3236 CPU.

This commit includes two board variants, namely the factory
default one and a Bit variant. The Bit board variant has a
bigger Macronix flash.

Add basic U-Boot, UART and SPI flash support.

Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Jakov Petrina <jakov.petrina@sartura.hr>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-08-06 14:12:14 +02:00
Luka Kovacic
a263df59be arm: mvebu: Add CRS305-1G-4S Bit board
MikroTik CRS305-1G-4S Bit board has a switch chip with an integrated
Marvell Prestera 98DX3236 CPU.

The Bit board variant is added, which has a bigger Macronix flash.

Add basic U-Boot, UART and Winbond SPI flash support.

Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Jakov Petrina <jakov.petrina@sartura.hr>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-08-06 14:12:14 +02:00
Tom Rini
89150a9314 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-sh
- r2dplus updates
2020-08-05 16:06:42 -04:00
Icenowy Zheng
7f772fbcc0 ARM: add Kconfig option for PSCI 0.1
We still have some platforms that only implements functionalities in
PSCI 0.1 (e.g. Allwinner ARMv7 SoCs).

Add a Kconfig option for exporting only PSCI 0.1. The code to export
PSCI 0.1 is still available and gets activated by this patch.

In addition, default ARCH_SUNXI U-Boot PSCI implementation to export
PSCI 0.1, to fix poweroff/reboot regression on Allwinner multi-core
ARMv7 SoCs.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
2020-08-05 08:18:34 -04:00
Brian Moyer
dfd2390dff arm: Add SPL build check to SPL early bss clear
SPL_CLEAR_BSS is called regardless of build type if
CONFIG_SPL_EARLY_BSS is defined. Add a guard for CONFIG_SPL_BUILD
to fix.

Signed-off-by: Brian Moyer <bdm310@gmail.com>
2020-08-04 23:30:02 -04:00
John Chau
4a4830cf91 cmd: add clone command
This patch adds a feature for block device cloning similar to dd
command, this should be useful for boot-strapping a device where
usb gadget or networking is not available. For instance one can
clone a factory image into a blank emmc from an external sd card.

Signed-off-by: John Chau <john@harmon.hk>
2020-08-04 23:29:59 -04:00
Tom Rini
f1c0b7cd4b For 2020.10
-----------
 
 - fixes for Toradex board
 - fix warnings from previous PR
 - HAB: reset instead of panic after failure
 - new board:  MYiR Tech MYS-6ULX
 - mx6cuboxi: use OF_PLATDATA
 - further changes for DM
 
 Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/714513163
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Merge tag 'u-boot-imx-20200804' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

For 2020.10
-----------

- fixes for Toradex board
- fix warnings from previous PR
- HAB: reset instead of panic after failure
- new board:  MYiR Tech MYS-6ULX
- mx6cuboxi: use OF_PLATDATA
- further changes for DM

Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/714513163
2020-08-04 11:11:02 -04:00
Tom Rini
4d23857abd Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscv
- add DM based reset driver for SiFive SoC's.
2020-08-04 11:07:38 -04:00
Tom Rini
bb3694d5b1 - doc: fix qemu-mips build instructions
- MIPS: add GPIO, CLK and SPI drivers for Octeon MIPS64
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Merge tag 'mips-pull-2020-08-03' of https://gitlab.denx.de/u-boot/custodians/u-boot-mips

- doc: fix qemu-mips build instructions
- MIPS: add GPIO, CLK and SPI drivers for Octeon MIPS64
2020-08-04 11:07:16 -04:00
Simon Glass
dcd7c906d0 mscc: Drop dm.h header file
This header file should not be included in other header files. Remove it
from each one and use a forward declaration instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-03 22:19:54 -04:00
Simon Glass
153f269ebe mediatek: Drop dm.h header file
This header file should not be included in other header files. Remove it
and use a forward declaration instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-03 22:19:54 -04:00
Simon Glass
055efe5690 thermal: Drop dm.h header file
This header file should not be included in other header files. Remove it
and use a forward declaration instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-03 22:19:54 -04:00
Simon Glass
a00867b47a sf: Drop dm.h header file from spi_flash.h
This header file should not be included in other header files. Remove it
and use a forward declaration instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-08-03 22:19:54 -04:00
Sagar Shrikant Kadam
d04a46426b sifive: reset: add DM based reset driver for SiFive SoC's
PRCI module within SiFive SoC's has register with which we can
reset the sub-systems within the SoC. The resets to DDR and ethernet
sub systems within FU540-C000 SoC are active low, and are hold low
by default on power-up. Currently these are directly asserted within
prci driver via register read/write.
With the DM based reset driver support here, we bind the reset
driver with clock (prci) driver and assert the reset signals of
both sub-system's appropriately.

Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
2020-08-04 09:19:41 +08:00
Sagar Shrikant Kadam
ea4e9570eb fu540: dtsi: add reset producer and consumer entries
The resets to DDR and ethernet sub-system are connected to
PRCI device reset control register, these reset signals
are active low and are held low at power-up. Add these reset
producer and consumer details needed by the reset driver.

Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-08-04 09:19:41 +08:00
Stefan Roese
1015540d70 mips: octeon: Update Octeon Kconfig
This patch selects DM_SPI & DM_I2C for MIPS Octeon. DM_GPIO, DM_SERIAL
and DM_ETH are already selected.

Additionally the selections are now alphabetically sorted.

Signed-off-by: Stefan Roese <sr@denx.de>
2020-08-03 21:14:48 +02:00
Stefan Roese
9044ed2c68 mips: octeon: mrvl, octeon-ebb7304.dts: Add SPI flash DT node
Add the SPI flash DT node for the EBB7304.

Signed-off-by: Stefan Roese <sr@denx.de>
2020-08-03 21:14:48 +02:00
Stefan Roese
1032491904 mips: octeon: mrvl,cn73xx.dtsi: Add SPI DT node
Add the Octeon SPI DT node to the dtsi file.

Signed-off-by: Stefan Roese <sr@denx.de>
2020-08-03 21:14:48 +02:00
Stefan Roese
a078c65172 mips: octeon: dts: Add Octeon clock driver DT nodes
This patch adds the DT nodes for the Octeon clock support via the
common clk_ API.

Signed-off-by: Stefan Roese <sr@denx.de>
2020-08-03 21:11:41 +02:00
Stefan Roese
7ab932825d mips: octeon: dts: Add I2C DT nodes
Add I2C DT nodes to the Octeon dts / dtsi files.

Signed-off-by: Stefan Roese <sr@denx.de>
2020-08-03 21:11:41 +02:00
Stefan Roese
fad5ec5ecd mips: octeon: mrvl,cn73xx.dtsi: Add GPIO DT nodes
Add the Octeon GPIO DT node to the dtsi file.

Signed-off-by: Stefan Roese <sr@denx.de>
2020-08-03 21:11:41 +02:00
Marek Vasut
1e7a69f661 ARM: imx: hab: panic on authentication failure
Instead of hang()ing the system and thus disallowing any automated
recovery possibility from a HAB authentication failure, panic() .
The panic() function can be configured to hang() the system after
printing an error message, however the default is to reset the
system instead.

This allows redundant boot to work correctly. In case the primary
or secondary image cannot be authenticated, the system reboots and
bootrom can try to start the other one.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2020-08-03 17:03:57 +02:00
Parthiban Nallathambi
10e959a1ca imx: Add MYiR Tech MYS-6ULX support
MYS-6ULX is single board computer (SBC) comes with eMMC or NAND based
on imx6ULL SoC from NXP and provision for expansion board. This
commit adds support only for SBC with NAND.

CPU:   Freescale i.MX6ULL rev1.1 528 MHz (running at 396 MHz)
CPU:   Commercial temperature grade (0C to 95C) at 45C
Reset cause: WDOG
Model: MYiR i.MX6ULL MYS-6ULX Single Board Computer with NAND
Board: MYiR MYS-6ULX 6ULL Single Board Computer
DRAM:  256 MiB
NAND:  256 MiB
MMC:   FSL_SDHC: 0
In:    serial@2020000
Out:   serial@2020000
Err:   serial@2020000
Net:   FEC0

Working:
 - Eth0
 - MMC/SD
 - NAND
 - UART 1
 - USB host

Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
2020-08-03 17:03:57 +02:00
Tom Rini
68941e3b2c Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86
- ApolloLake: add u64 parameters support for FSP2 bindings
- ApolloLake: add missing parameters to support full configuration of
  the latest FSP MR6 release
- Append appropriate suffixes in various assembly codes
2020-08-03 10:25:47 -04:00
Andy Shevchenko
940185910f x86: call32: Append appropriate suffixes
Assembler is not happy:

arch/x86/cpu/call32.S: Assembler messages:
arch/x86/cpu/call32.S:36: Warning: no instruction mnemonic suffix given and no register operands; using default for `retf'

Fix this by adding appropriate suffixes to the assembler commands.

Fixes: 6f92ed8f1a ("x86: Add a way to call 32-bit code from 64-bit mode")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-08-03 10:46:56 +08:00
Andy Shevchenko
549c6f47e6 x86: sipi_vector: Append appropriate suffixes
Assembler is not happy:

arch/x86/cpu/sipi_vector.S: Assembler messages:
arch/x86/cpu/sipi_vector.S:134: Warning: no instruction mnemonic suffix given and no register operands; using default for `cmp'
arch/x86/cpu/sipi_vector.S:139: Warning: no instruction mnemonic suffix given and no register operands; using default for `bts'
arch/x86/cpu/sipi_vector.S:157: Warning: no instruction mnemonic suffix given and no register operands; using default for `cmp'

Fix this by adding appropriate suffixes to the assembler commands.

Fixes: 45b5a37836 ("x86: Add multi-processor init")
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-08-03 10:46:56 +08:00
Bernhard Messerklinger
a0186110af arch: x86: apl: Update FSP parameters
Add missing parameters to support full configuration of the latest FSP
MR6 release.

Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-03 10:46:56 +08:00
Bernhard Messerklinger
858e5a1a8b x86: apl: fsp_bindings: Add support for u64 parameters
Add FSP_UINT64 read support as preparation for FSP-M and FSP-S parameter
update.

Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-08-03 10:46:56 +08:00
Wolfgang Wallner
491135805e x86: irq: Fix some typos
Fix some typos in arch/x86/include/asm/irq.h.

Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-08-03 10:46:56 +08:00
Marek Vasut
f70ca794be sh: r2dplus: Add SCIF1 to the basic DT
Add simple DT and clock bindings to r2dplus DT to permit U-Boot
to bind the SCIF driver via DT probing instead of hard-coded
config options.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2020-08-02 19:58:27 +02:00
Marek Vasut
3223ca99ee sh: Set gd->malloc_base if MALLOC_F_LEN is set
The gd->malloc_base must be set before the C runtime if the MALLOC_F_LEN
is non-zero, otherwise we hit assertion in dlmalloc.c initf_malloc(). So
set it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2020-08-02 19:58:26 +02:00
Heinrich Schuchardt
74b869bae7 efi_loader: use CONFIG_STACK_SIZE in the UEFI sub-system
The Kconfig symbol CONFIG_STACK_SIZE is used both by ARM and Microblaze
with the same meaning. Move it to menu 'General setup' so that we can use
it for all architectures.

Use the value of CONFIG_STACK_SIZE instead of a hard coded 16 MiB value for
reserving memory in the UEFI sub-system.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-08-01 11:58:23 +02:00
Heinrich Schuchardt
4f0c4be1c3 x86: rename CONFIG_STACK_SIZE
Configuration variables should have the same meaning independent of the
architecture. x86 and ARM both use CONFIG_STACK_SIZE:

* x86: U-Boot's runtime stack size during reboot
* ARM: max stack size that can be used by U-Boot

Rename the x86 configuration variable to CONFIG_STACK_SIZE_REBOOT

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-08-01 11:58:23 +02:00
Tom Rini
719f42190d Use binman instead of one of the Rockchip build scripts
Refactor to allow any arch to create SPI-flash images
 New button uclass
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Merge tag 'dm-pull-28jul20' of git://git.denx.de/u-boot-dm

Use binman instead of one of the Rockchip build scripts
Refactor to allow any arch to create SPI-flash images
New button uclass
2020-07-29 21:16:08 -04:00
Tom Rini
7cb2060b4e Merge https://gitlab.denx.de/u-boot/custodians/u-boot-stm
- fix SPL boot issue due to early dbgmcu_init() call
- fix SPL boot issue due to dcache memory region configuration
- add support of CONFIG_ENV_IS_IN_MMC
- add specific SD/eMMC partition for U-Boot enviromnent
- enable env in SPL
- use "env info -q" to remove log during boot
- remove env location override for dh_stm32mp1
- update management of misc_read
- check result of find_mmc_device in stm32prog
- use regulator_set_enable_if_allowed for disabling vdd supply in usbphyc
- enable CMD_ADTIMG flag to handle Android images
- device tree alignment with Linux Kernel v5.8-rc1
- remove hnp-srp-disable for usbotg on dk1
- add reset support to uart nodes on stm32mp15x
- use correct weak function name spl_board_prepare_for_linux
- use cd-gpios for ST and DHSOM boards
- add seeed studio odyssey-stm32mp157c board support
- move ethernet PHY into SoM DT
- add DHSOM based DRC02 board support
2020-07-29 16:30:45 -04:00
Rayagonda Kokatanur
2ae7adc659 arch: arm: use dt and UCLASS_SYSCON to get gic lpi details
Use device tree and UCLASS_SYSCON driver to get
Generic Interrupt Controller (GIC) lpi address and
maximum GIC redistributors count.

Also update Kconfig to select REGMAP and SYSCON when
GIC_V3_ITS is enabled.

Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-29 10:37:11 -04:00
Rayagonda Kokatanur
a76bfe5693 arch: arm: use dt and UCLASS_IRQ to get gic details
Use device tree and UCLASS_IRQ driver to get following
Generic Interrupt Controller (GIC) details,

-GIC Distributor interface (GICD) base address and
-GIC Redistributors (GICR) base address.

Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-29 10:37:11 -04:00
Rayagonda Kokatanur
912fe3768f gpio: do not include <asm/arch/gpio.h> on TARGET_BCMNS3
As no gpio.h is defined for this architecture, to avoid
compilation failure, do not include <asm/arch/gpio.h> for
arch bcmns3.

Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-29 10:37:11 -04:00
Rayagonda Kokatanur
c8b98482d8 board: ns3: define ddr memory layout
Add both DRAM banks memory information and
the corresponding MMU page table mappings.

Signed-off-by: Bharat Kumar Reddy Gooty <bharat.gooty@broadcom.com>
Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-29 10:37:11 -04:00
Abhishek Shah
ef7192e404 board: ns3: add api to save boot parameters passed from BL31
Add API to save boot parameters passed from BL31

Use assembly implementation of save_boot_params instead of c function.
Because generally ATF does not set up SP_EL2 on exiting.
Thus, usage of a C function immediately after exiting with no stack
setup done by ATF explicitly, may cause SP_EL2 to be not sane,
which in turn causes a crash if this boot was not lucky to get
an SP_EL2 in valid range. Replace C implementation with assembly one
which does not use stack this early, and let u-boot to set up its stack
later.

Signed-off-by: Abhishek Shah <abhishek.shah@broadcom.com>
Signed-off-by: Rajesh Ravi <rajesh.ravi@broadcom.com>
Signed-off-by: Vladimir Olovyannikov <vladimir.olovyannikov@broadcom.com>
Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-29 10:13:41 -04:00
Rayagonda Kokatanur
5d9302d478 arm: cpu: armv8: add L3 memory flush support
Add L3 memory flush support for NS3.

Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-29 10:13:40 -04:00
Rayagonda Kokatanur
291635aecf board: ns3: add support for Broadcom Northstar 3
Add support for Broadcom Northstar 3 SoC.
NS3 is a octo-core 64-bit ARMv8 Cortex-A72 processors
targeting a broad range of networking applications.

Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-29 10:13:40 -04:00
David Woodhouse
3fad1ca28d board: mediatek: Add support for UniElec U7623 board
This is an MT7623A-based board, very similar to the Banana Pi R2.

http://www.unielecinc.com/q/news/cn/p/product/detail.html?qd_guid=OjXwKCaRlN

Signed-off-by: David Woodhouse <dwmw2@infradead.org>
2020-07-29 08:43:40 -04:00
Stefan Bosch
d1611086e0 arm: add support for SoC s5p4418 (cpu) / nanopi2 board
Changes in relation to FriendlyARM's U-Boot nanopi2-v2016.01:
- SPL not supported yet --> no spl-dir in arch/arm/cpu/armv7/s5p4418/.
  Appropriate line in Makefile removed.
- cpu.c: '#include <cpu_func.h>' added.
- arch/arm/cpu/armv7/s5p4418/u-boot.lds removed, is not required
  anylonger.
- "obj-$(CONFIG_ARCH_NEXELL) += s5p-common/" added to
  arch/arm/cpu/armv7/Makefile since s5p-common/pwm.c is used instead
  of drivers/pwm/pwm-nexell.c.
- s5p4418.dtsi: '#include "../../../include/generated/autoconf.h"'
  removed, is not necessary, error at out-of-tree building.
  '#ifdef CONFIG_CPU_NXP4330'-blocks (2x) removed. Some minor changes
  regarding mmc. 'u-boot,dm-pre-reloc' added to dp0 because of added
  DM_VIDEO support.
- board/s5p4418/ renamed to board/friendlyarm/
- All s5p4418-boards except nanopi2 removed because there is no
  possibility to test the other boards.
- Kconfig: Changes to have a structure like mach-bcm283x (RaspberryPi),
  e.g. "config ..." entries moved from/to other Kconfig.
- "CONFIG_" removed from several s5p4418/nanopi2 specific defines
  because the appropriate values do not need to be configurable.
- nanopi2/board.c: All getenv(), getenv_ulong(), setenv() and saveenv()
  renamed to env_get(), env_get_ulong(), env_set() and env_save(),
  respectively. MACH_TYPE_S5P4418 is not defined anymore, therefore
  appropriate code removed (not necessary for DT-kernels).
- nanopi2/onewire.c: All crc8() renamed to crc8_ow() because crc8() is
  already defined in lib/crc8.c (with different parameters).
- dts: "nexell,s5pxx18-i2c" used instead of "i2c-gpio", i2c0 and
  i2c1 added. gmac-, ehci- and dwc2otg-entries removed because the
  appropriate functionality is not supported yet. New mmc-property
  "mmcboost" added.
  s5p4418-pinctrl.dtsi: gmac-entries removed, mmc- and i2c-entries
  added.
- '#ifdef CONFIG...' changed to 'if (IS_ENABLED(CONFIG...))' where
  possible (and similar).

Signed-off-by: Stefan Bosch <stefan_b@posteo.net>
2020-07-29 08:43:40 -04:00
Stefan Bosch
18284c1d56 pwm: add driver for nexell
Changes in relation to FriendlyARM's U-Boot nanopi2-v2016.01:
- Since drivers/pwm/pwm-nexell.c is an adapted version of
  s5p-common/pwm.c an appropriately changed version of s5p-common/pwm.c
  is used instead. Therefore arch/arm/mach-s5pc1xx/include/mach/pwm.h
  copied to arch/arm/mach-nexell/include/mach and s5p-common/Makefile
  changed appropriately.
- '#ifdef CONFIG...' changed to 'if (IS_ENABLED(CONFIG...))' where
  possible (and similar).

Signed-off-by: Stefan Bosch <stefan_b@posteo.net>
2020-07-29 08:43:40 -04:00
Stefan Bosch
95e9a8e2cb arm: add mach-nexell (all files except header files)
Changes in relation to FriendlyARM's U-Boot nanopi2-v2016.01:
- SPL not supported yet --> no spl-directory in arch/arm/mach-nexell.
  Appropriate line in Makefile removed.
- clock.c: 'section(".data")' added to declaration of clk_periphs[] and
  core_hz.
- Kconfig: Changes to have a structure like in mach-bcm283x/Kconfig,
  e.g. "config ..." entries moved from other Kconfig.
- timer.c: 'section(".data")' added to declaration of timestamp and
  lastdec.
- arch/arm/mach-nexell/serial.c removed because this is for the UARTs
  of the S5P6818 SoC which is not supported yet. S5P4418 UARTs are
  different, here the (existing) PL011-code is used.
- '#ifdef CONFIG...' changed to 'if (IS_ENABLED(CONFIG...))' where
  possible (and similar).

Signed-off-by: Stefan Bosch <stefan_b@posteo.net>
2020-07-29 08:43:40 -04:00
Stefan Bosch
a1ce9ed063 arm: add mach-nexell (header files)
Changes in relation to FriendlyARM's U-Boot nanopi2-v2016.01:
- DM_VIDEO support (display_dev.h).
- boot0.h added, handles NSIH --> tools/nexell obsolete.
- gpio.h: Include-path to errno.h changed.

Signed-off-by: Stefan Bosch <stefan_b@posteo.net>
2020-07-29 08:43:40 -04:00
Ard Biesheuvel
6744ace5b3 arm: enable allocate-on-read for LPAE's DCACHE_WRITEBACK/_WRITETHROUGH
The LPAE versions of DCACHE_WRITEBACK and DCACHE_WRITETHROUGH are currently
defined as no-allocate for both reads and writes, which deviates from the
non-LPAE definition, and mostly defeats the purpose of enabling the caches
in the first place.

So align LPAE with !LPAE, and enable allocate-on-read for both. And while
at it, add some clarification about the meaning of the chosen values.

Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
2020-07-29 08:43:40 -04:00
Robert Marko
e479a7d52e arm: Add support for Qualcomm IPQ40xx family
This introduces initial support for the popular Qualcomm
IPQ40x8 and IPQ40x9 WiSoC series.

IPQ40xx series have 4x Cortex A7 ARM-v7A cores.
Supported are: IPQ4018, IPQ4019, IPQ4028 and IPQ4029.

IPQ40x8 and IPQ40x9 use the same cores, but differ in
addressable RAM size (1GB for IPQ40x9 and 256MB for IPQ40x8)
and supported peripherals (IPQ40x8 lacks RGMII, LCD controller
and EMMC/SDHCI controllers).

IQP4028/IPQ4029 models differ from IPQ4018/IPQ4019 only
by their rated temperatures rates with IPQ402X models being
rated for wider temperature ranges.

Initially this supports:
* Simple clock driver (Only for UART1 now, will be extended)
* Pinctrl driver (Supports UARTX and GPIO now, will be extended)
* GPIOs already supported by msm_gpio driver with updates
* UARTs already supported by serial_msm driver with updates

Further peripherals will come in later patches.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
2020-07-29 08:43:40 -04:00
MarkLee
f5b441fcbe arm: dts: mediatek: enable sgmii mode and mt7531 switch for mt7629
This patch enable sgmii mode and mt7531 switch support in mt7629
ethernet dts node

Signed-off-by: MarkLee <Mark-MC.Lee@mediatek.com>
2020-07-28 22:44:00 -04:00
Philippe Reynes
a6c6f0f0c8 test/py: add tests for the button commands
Adds tests for the button commands.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2020-07-28 19:30:39 -06:00
Philippe Reynes
bd3e4882c7 sandbox: dtsi: add buttons
Adds two buttons on sandbox so button framework may be tested.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
2020-07-28 19:30:39 -06:00
Philippe Reynes
037a56d6b1 sandbox, test: change hog gpio
Since commit 9ba84329dc ("sandbox, test: add test for GPIO_HOG
function"), the gpio_a 0,1,2 and 3 are used by hog in test.dts.
But 2 leds 'sandbox:red' and 'sandbox:green' are using gpio_a 0
and 1. As hog always request his gpios, the led command on both
led is broken:

=> led sandbox:red
LED 'sandbox:red' not found (err=-16)

The gpio is already requested by hog, so it can't be enabled
for led 'sandbox:red'.

This commit change the gpio used by hog to 10, 11, 12 and 13,
so the led command could be used again with 'sandbox:red' and
'sandbox:green'.

Signed-off-by: Philippe Reynes <philippe.reynes@softathome.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
2020-07-28 19:30:39 -06:00
Simon Glass
9589c447e8 x86: chromebook_panther: Correct the image layout
This board does not have microcode but at present that is not supported
by Kconfig nor the binman image layout. Fix both of these.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-28 19:30:39 -06:00
Simon Glass
a78466af82 x86: Move the fdtmap away from the binary blobs
This causes conflicts on chromebook_link64. Move it to after U-Boot where
there should be plenty of space.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-28 19:30:39 -06:00
Simon Glass
5a1140527d rockchip: Drop the fit_spl_optee.sh script
Now that all board use binman instead of this script, drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-28 19:30:39 -06:00
Simon Glass
a32dd07148 rockchip: Convert evb-rk3288 over to use binman
At present this board uses a custom script to produce the .its file.
Update it to use binman instead. Binman can create all the images that
are needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-07-28 19:30:39 -06:00
Simon Glass
e999bea485 mediatek: Makefile: Drop explicit targets built by binman
On mediatek various files that need to be created by binman. It does not
make sense to enumerate these in the Makefile. They are described in the
configuration (devicetree) for each board and we can simply run binman
(always) to generate them.

This avoid sprinkling the Makefile with arch-specific code.

Also update the binman definition so that idbloader.img is only needed
when SPL is actually being used.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
2020-07-28 19:30:39 -06:00
Simon Glass
be17bcb9af powerpc: mpc85xx: Only enable binman when it is needed
Quite a few boards using this SoC family don't use binman, yet
CONFIG_BINMAN is enabled for all of them. But the option should only be
enabled if we expect binman to produce an image. Calling binman when the
device tree is missing, etc. will cause failer.

Add a condition so that CONFIG_BINMAN is only enabled as needed.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-28 19:30:39 -06:00
Simon Glass
e6385c7e9c Makefile: Rename ALL-y to INPUTS-y
When binman is in use, most of the targets built by the Makefile are
inputs to binman. We then need a final rule to run binman to produce the
final outputs.

Rename the variable to indicate this, and add a new 'inputs' target.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-28 19:30:39 -06:00
Simon Glass
3077026ea1 tegra: Don't enable binman on ARMv8 SoCs
At present only the ARMv7 tegra SoCs actually use binman to create an
image. Change the config to reflect this, since otherwise running binman
will produce an error.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-07-28 19:30:39 -06:00
Simon Glass
c4cea2bbf9 rockchip: Enable building a SPI ROM image on bob
Add a simple binman config and enable CONFIG_HAS_ROM so that U-Boot
produces a ROM for bob.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-07-28 19:30:39 -06:00
Simon Glass
9b312e26fc rockchip: Enable building a SPI ROM image on jerry
Add a simple binman config and enable CONFIG_HAS_ROM so that U-Boot
produces a ROM for jerry.

Change the binman image definition to support multiple images, since it
may be used to build both u-boot-rockchip.bin and u-boot.rom

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-07-28 19:30:39 -06:00
Simon Glass
fab4f3231f rockchip: Allow Bob to use SPI boot
Bob is a Chromebook and can boot from SPI flash. Add it to the condition
check for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-07-28 19:30:39 -06:00
Simon Glass
bcd4e6f3bd x86: Change how selection of ROMs works
Most x86 boards build a u-boot.rom which is programmed into SPI flash. But
this is not unique to x86. For example some rockchip boards can also boot
from SPI flash.

Also, at least on x86, binary blobs are sadly quite common. It is not
possible to build a functional image without them, and U-Boot needs to
know this at build time.

Introduce a new CONFIG_HAS_ROM option which selects whether u-boot.rom is
built and a new CONFIG_ROM_NEEDS_BLOBS option to indicate whether binary
blobs are also needed. If they are not needed, it is safe to build the ROM
always. Otherwise we still require the BUILD_ROM environment variable.

For now this affects only x86, but future patches will enable this for
rockchip too.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-07-28 19:30:39 -06:00
Adam Ford
e91907a146 Convert CONFIG_ENV_OVERWRITE to Kconfig
This converts the following to Kconfig:
   CONFIG_ENV_OVERWRITE

Signed-off-by: Adam Ford <aford173@gmail.com>
[trini: Rerun migration, remove some comments]
Signed-off-by: Tom Rini <trini@konsulko.com>
2020-07-28 16:18:06 -04:00
Marek Vasut
0b263a905a ARM: dts: stm32: Add DHSOM based DRC02 board
Add DT for DH DRC02 unit, which is a universal controller device.
The system has two ethernet ports, two CANs, RS485 and RS232, USB,
capacitive buttons and an OLED display.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-07-28 18:35:01 +02:00
Marek Vasut
8791cf0923 ARM: dts: stm32: Move ethernet PHY into SoM DT
The PHY and the VIO regulator is populated on the SoM, move it
into the SoM DT.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-07-28 18:35:01 +02:00
Marcin Sloniewski
87e1e0fc7f ARM: dts: stm32: add seeed studio odyssey-stm32mp157c board
This commit adds device tree files supporting
SBC from Seeed Studio based on STM32MP157C.

This works with generic stm32mp1 config.
Right now only booting from SD card is supported.

Signed-off-by: Marcin Sloniewski <marcin.sloniewski@gmail.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-07-28 18:35:01 +02:00
Patrick Delaunay
5f865bb53b Revert "ARM: dts: stm32: Reinstate card detect behavior on ST boards"
Since commit f13ff88b61 ("gpio: stm32: add ops set_dir_flags")
the gpio flags are supported by stm32 pinctrl driver.

The cd-gpios is correctly handle in U-Boot and the patch on the
device tree can be removed.

This reverts commit 792919241b.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-07-28 18:15:23 +02:00
Patrick Delaunay
ed111e4f00 Revert "ARM: dts: stm32: Reinstate card detect behavior on DHSOM"
Since commit f13ff88b61 ("gpio: stm32: add ops set_dir_flags")
the gpio flags are supported by stm32 pinctrl driver.

The cd-gpios is correctly handle in U-Boot and the patch on the
device tree can be removed.

This reverts commit 3c2e2a1a79.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-07-28 18:14:58 +02:00
Patrick Delaunay
346034a7a8 arm: stm32mp: use correct weak function name spl_board_prepare_for_linux
Replace the function spl_board_prepare_for_boot_linux by the correct
name of the weak function spl_board_prepare_for_linux defined in spl.h.

This patch avoids warning with W=1 option:

u-boot/arch/arm/mach-stm32mp/spl.c:150:6:
warning: no previous prototype for ‘spl_board_prepare_for_boot_linux’
[-Wmissing-prototypes]

Fixes: dc7e5f190d ("arm: stm32mp: activate data cache on DDR in SPL")
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-07-28 18:14:15 +02:00
Patrick Delaunay
0b73355ba2 ARM: dts: stm32: add reset support to uart nodes on stm32mp15x
STM32 serial IP can be reset via reset controller.
Add the support of reset to uart nodes on stm32mp15-u-boot.dtsi,
the ad-dons file for U-Boot.

This patch fix issues when previous UART configuration, for example
done in TF-A or ROM code, is not handled in U-Boot stm32 serial driver
init.

This reset property won't be not added in Linux kernel device tree
as this reset is not used in Linux STM32 serial driver.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-07-28 18:11:58 +02:00
Patrick Delaunay
7ecbefd3ec ARM: dts: stm32mp: remove hnp-srp-disable for usbotg on dk1
Remove hnp-srp-disable for usbotg node because this feature is only needed
for usbotg in HOST mode (in drivers/usb/host/dwc2.c)
and this feature is not activated in stm32mp15 U-Boot
(stm32mp15_basic_defconfig and stm32mp15_trusted_defconfig);
only the device mode is activated and OTG is not supported in DWC2 driver.

This patch reduces the difference between U-Boot and Linux kernel
device-tree.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-07-28 18:10:06 +02:00
Patrick Delaunay
500327e2ea ARM: dts: stm32mp1: DT alignment with Linux kernel v5.8-rc1
DT alignment with Linux kernel v5.8-rc1 for the STM32MP15x soc
device tree files and the STMicroelectronics boards device tree files.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-07-28 18:06:45 +02:00
Patrick Delaunay
6ed83edfc0 ARM: dts: rename stm32mp15xx-avenger96 ethernet0_rgmii_pins
Alignment with pins name used in Linux kernel v5.8.

It is a preleminary step for device tree alignment.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-07-28 18:06:19 +02:00
Patrick Delaunay
ded48bec05 arm: stm32mp: stm32prog: check result of find_mmc_device
Check result of find_mmc_device() before calling mmc_init().

This patch avoid a data abort when the command try to acces
to sd/mmc device deactivated in device tree.

Fixes: aff4c5dd82 ("stm32mp: stm32prog: add MMC device")
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-07-28 17:43:46 +02:00
Patrick Delaunay
76db1681da stm32mp1: use a specific SD/eMMC partition for U-Boot enviromnent
Save the environment at the end of the U-Boot partition, the GPT
partition named "ssbl" in SD card or eMMC and avoid requirements
on the "bootfs" file system generated via specific raw tools
(like wic and genimage).

With the previous configuration of the U-Boot environment saved in ext4
file, U-Boot need to create/modify the file uenv.txt in the ext4 file
system; so this EXT4 file system need to be generated without some
functionality, like metadata_csum and dir_index, because they are not
supported by U-Boot.

Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-07-28 17:21:37 +02:00
Patrick Delaunay
43fe9d2fda stm32mp1: mmu_set_region_dcache_behaviour
Since commit d877f8fd0f ("arm: provide a function for boards init
code to modify MMU virtual-physical map") the parameter of
mmu_set_region_dcache_behaviour need to be MMU_SECTION_SIZE
aligned.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-07-28 17:21:37 +02:00
Patrick Delaunay
97f7e39def arm: stm32mp: move dbgmcu_init call when DT is ready
As the dbgmcu_init use the function bsec_dbgswenable which is based
on the DM and DT, its call can't be done before the spl is initialized
(driver model, DT and malloc) in board_init_f::spl_early_init().

This function call is moved later in spl_board_init().

Fixes: bd3f60d29c ("arm: stm32mp: protect DBGMCU_IDC access with BSEC")

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-07-28 17:21:37 +02:00
Tom Rini
8d1fc6fb89 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq
- Bug fixes and updates on ls2088a,ls1028a, ls1046a, ls1043a, ls1012a
- lx2-watchdog support
- layerscape: pci-endpoint support, spin table relocation fixes and
  cleanups
- fsl-crypto: RNG support and bug fixes
2020-07-27 15:18:15 -04:00
Tom Rini
4e05c167a7 binman support for FIT
new UCLASS_SOC
 patman switch 'test' command
 minor fdt fixes
 patman usability improvements
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Merge tag 'dm-pull-20jul20-take2a' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm

binman support for FIT
new UCLASS_SOC
patman switch 'test' command
minor fdt fixes
patman usability improvements
2020-07-27 11:15:37 -04:00
Fabio Estevam
68a699e1e8 imx8m: soc: Remove unneeded space
Checkpatch reports the following issue:

ERROR: space prohibited before that ',' (ctx:WxW)
#936: FILE: arch/arm/mach-imx/imx8m/soc.c:936:
+		      0, 0 , 0, 0, 0, 0, &res);

Remove the unneeded space.
 		           ^
Reported-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-07-27 14:02:37 +02:00
Igor Opaniuk
a5de86c1db ARM: dts: imx7-colibri: multiple node updates
1. Move u-boot specific nodes to u-boot dts include: legacy lcdif
node and aliases.
2. Add iomux configuration for LCD.
3. Drop un-needed u-boot,dm-pre-reloc for alias node.
4. Fix display-timings, use the one from Toradex downstream kernel [1]

[1]: https://git.toradex.com/cgit/linux-toradex.git/tree/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi?h=toradex_4.9-2.3.x-imx#n206
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2020-07-27 14:01:32 +02:00
Igor Opaniuk
07e939f0f5 ARM: dts: imx6ull-colibri: move u-boot specific node
1. Move aliases and legacy lcdif node to the u-boot specific dts include.
2. Provide proper display timings, as in the downstream Toradex kernel
[1].

[1]: https://git.toradex.com/cgit/linux-toradex.git/tree/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi?h=toradex_4.9-2.3.x-imx#n183
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2020-07-27 14:00:36 +02:00
Igor Opaniuk
8cc40fa2d3 ARM: dts: imx8mm-verdin: eeprom nodes adjustments
Rename EEPROM nodes.
Create aliases for EEPROM to unify their order:
    eeprom0 - on-module EEPROM
    eeprom1 - carrier-board EEPROM
    eeprom2 - MIPI-DSI to HDMI adapter EEPROM

Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2020-07-27 14:00:36 +02:00
Igor Opaniuk
fb99ac9caf imx: mx7: fix DDRC size in A7-M4 mapping table
According to i.MX 7Solo Applications Processor Reference Manual,
2.1.3 Cortex-M4 Memory Map, M4 can address only 1536MB of DDRC
(Start Address: 0x8000_0000; End Address: 0xDFFF_FFFF).
Correct DDRC size to 0x60000000.

Fixes: c0f037f6("mach-imx: bootaux: elf firmware support")
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2020-07-27 14:00:36 +02:00
Zhao Qiang
5c64d07f76 arm: dts: ls1028a: Add dspi flash device node to qds
Add dspi flash device node to fsl-ls1028a-qds.dtsi

Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27 14:24:15 +05:30
Zhao Qiang
0b7cac71e4 arm64: lx2160a: dts: Add watchdog node
Add watchdog node which is sbsa into lx2160a dtsi

Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27 14:24:15 +05:30
Xiaowei Bao
57fcc13738 armv8: dts: ls1046a: Add the PCIe EP node
Add the PCIe EP node for ls1046a.

Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27 14:24:15 +05:30
Wasim Khan
be2c7d764a arm: dts: lx2160a: Increase configuration window size
lx2160a rev2 requires 4KB space for type0 and 4KB
space for type1 iATU window. Increase configuration
size to 8KB to have sufficient space for type0
and type1 window.

Signed-off-by: Wasim Khan <wasim.khan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27 14:24:15 +05:30
Hou Zhiqiang
c5f8943965 arm64: ls1043a: Remove the workaround of erratum A-009929
The workaround has been implemented in PBI phase, so remove
the duplicated implementation from U-Boot.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27 14:16:28 +05:30
Yangbo Lu
4f73897b99 Drop global data sdhc_adapter for powerpc
The sdhc_adapter of global data has not been used, and we
do not have to use it as global data even we may need it
in the future.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27 14:16:28 +05:30
Zhao Qiang
8b307b146a armv8: dts: fsl-lx2160a: add flash node under dspi to qds dts
Add flash node under dspi into fsl-lx2160a-qds.dtsi

Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27 14:16:28 +05:30
Biwen Li
af0e08ca10 I2C: ls1043a, ls1046a: enable SYS_I2C_MXC
This enables SYS_I2C_MXC to fix a bug that
failed to boot from sd card with
image u-boot-with-spl-pbl.bin

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27 14:16:28 +05:30
Michael Walle
dd6df64c68 armv8: layerscape: rework spin table
There are two issues:

 (1) The spin table doesn't convert the endianness of the jump address.
     Although there is code for it, the result isn't used at all (x0).
 (2) If something goes wrong, the function returns. But that doesn't
     make sense at all.

Use the actual converted jump address as destination to fix. If
there is an error, jump to a trap loop. And rearrange the code exception
level switching code to make it smaller and clearer.

This reduces the size of the spin table code section from 696 bytes to
424 bytes. If CONFIG_ARMV8_SWITCH_TO_EL1 the code size reduced from 696
bytes to 632 bytes.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27 14:16:28 +05:30
Michael Walle
16863da82a armv8: layerscape: relocate spin table if EFI_LOADER is enabled
On ARM64, a 64kb region is reserved for the runtime services code.
Unfortunately, this code overlaps with the spin table code, which also
needs to be reserved. Thus now that the code is relocatable, allocate a
new page from EFI, copy the spin table code into it, update any pointers
to the old region and the start the secondary CPUs.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27 14:16:28 +05:30
Michael Walle
308deab9b1 armv8: layerscape: clean exported symbols in spintable.S
Add a new variable secondary_boot_code_start, which holds a pointer to
the start of the spin table code. This will help to relocate the code
section. While at it, move the size variable from the end to the
beginning so there is a common section for the variables. Remove any
other symbols.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27 14:16:28 +05:30
Michael Walle
2e262111ea armv8: layerscape: drop first .ltorg directive in spintable.S
Now that the spin table is in a separate module, this is no longer
necessary. Drop it.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27 14:16:28 +05:30
Michael Walle
86c31dad32 armv8: layerscape: make wake_secondary_core_n() static
This function is not used outside the module. Make it static.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27 14:16:28 +05:30
Michael Walle
dcfbbed570 armv8: layerscape: simplify get_spin_tbl_addr() calls
There is no need to cast around. Assign the address to the local
variable and use it.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27 14:16:27 +05:30
Michael Walle
c31ac97f96 armv8: layerscape: remove determine_mp_bootpg()
Only the PowerPC architecture needs this function. Remove it.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27 14:16:27 +05:30
Michael Walle
b1c41231c4 armv8: layerscape: fix alignment for spin table
Fix the alignment so it will match the comments. The spin table has to
be 8 byte aligned, so ".align 3" is enough.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27 14:16:27 +05:30
Michael Walle
2eca7b9704 armv8: layerscape: load function pointer using ADR
Don't use LDR to load a pointer to a function. This will generate a
literal which cannot be relocated. Use ADR which is PC-relative and
therefore can easily be relocated.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27 14:16:27 +05:30
Michael Walle
f6c62f1c9e armv8: layerscape: move spin table into own module
Move it out of lowlevel.S into spintable.S. On layerscape, the secondary
CPUs are brought up in main u-boot. This will make it possible to only
compile the spin table code for the main u-boot and omit it in SPL.

This saves about 720 bytes in the SPL.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27 14:16:27 +05:30
Michael Walle
3d3fe8b12d armv8: layerscape: properly use CPU_RELEASE_ADDR
The generic armv8 code already has support to bring up the secondary
cores. Thus, don't hardcode the jump in the layerscape lowlevel_init to
the spin table code; instead just return early and let the common armv8
code handle the jump. This way we can actually use the CPU_RELEASE_ADDR
feature.

Signed-off-by: Michael Walle <michael@walle.cc>
[Rebased, Removed kontron_sl28.h change as file does not exist]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27 14:16:27 +05:30
Michael Walle
ae846a6119 armv8: layerscape: pretty print info about SMP cores
Make the print of the starting address a debug output and pretty print
the info about online cores.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27 14:16:27 +05:30
Michael Walle
b27f48540e armv8: layerscape: fix spin-table support
Spin tables are broken with bootefi. This is because - in contrast to
the booti call chain - there is no call to smp_kick_all_cpus(). Due to
this missing call the secondary CPUs are never released from their "wait
for interrupt state", see secondary_boot_func() in lowlevel.S.

Originally, this "wait for interrupt" is there to make sure, the spin
table is cleared before the secondary cores read it for the first time.
But the boot flow for the layerscape architecture is different from
that. The CPUs are release from their BootROM _after_ U-Boot's
spin-table is cleared, see fsl_layerscape_wake_seconday_cores() in mp.c.
Thus, there is no need to wait for this interrupt and no need for
kicking all cores on cpu_release. An atomic 64bit write to the
spin-table and a "sev" is sufficient.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27 14:16:27 +05:30
hui.song
02decd4e0c dm: armv8: gpio: include <asm/arch/gpio.h> for fsl-layerscape
Enable the gpio feature on fsl-layerscape platform.

Signed-off-by: hui.song <hui.song_1@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27 14:16:27 +05:30
hui.song
08333fa50b armv8: gpio: add gpio feature
add one struct mpc8xxx_gpio_plat to enable gpio feature.

Signed-off-by: hui.song <hui.song_1@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27 14:16:26 +05:30
Michael Walle
f8c5815c1b armv8: ls1028a: move FSL_LAYERSCAPE to kconfig
CONFIG_FSL_LAYERSCAPE is available in kconfig. There is no need to
define it per board; the ls1028a_common.h is really board dependent and
only fits to the NXP eval boards. Instead select CONFIG_FSL_LAYERSCAPE
when ARCH_LS1028A is selected.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-07-27 14:16:26 +05:30
Masahiro Yamada
2548493ab4 treewide: convert devfdt_get_addr() to dev_read_addr()
When you enable CONFIG_OF_LIVE, you will end up with a lot of
conversions.

To generate this commit, I used coccinelle excluding drivers/core/,
include/dm/, and test/

The semantic patch that makes this change is as follows:

  <smpl>
  @@
  expression dev;
  @@
  -devfdt_get_addr(dev)
  +dev_read_addr(dev)
  </smpl>

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-25 14:46:57 -06:00
Dave Gerlach
5ab71ea4b1 arm: mach-k3: Use SOC driver for device identification
Make use of UCLASS_SOC to find device family and revision for
print_cpuinfo.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2020-07-25 14:46:57 -06:00
Dave Gerlach
e8918bccd8 arm: dts: k3-j721e-mcu-wakeup: Introduce chipid node
Introduce a chipid node to provide a UCLASS_SOC driver to identify TI K3
SoCs.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2020-07-25 14:46:57 -06:00
Dave Gerlach
bec8b94e08 arm: dts: k3-am65-wakeup: Introduce chipid node
Introduce a chipid node to provide a UCLASS_SOC driver to identify TI K3
SoCs.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2020-07-25 14:46:57 -06:00
Dave Gerlach
21e3c219ae test: Add tests for SOC uclass
Add a sandbox SOC driver, and some tests for the SOC uclass.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2020-07-25 14:46:57 -06:00
Simon Glass
961420fa5f cpu: Convert the methods to use a const udevice *
These functions should not modify the device. Convert them to const so
that callers don't need to cast if they have a const udevice *.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-07-25 14:46:57 -06:00
Adam Ford
59028798ab ARM: rmobile: Add Beacon EmbeddedWorks RZG2M Dev Kit
The Beacon EmbeddedWorks kit is based on the R8A774A1 SoC also
known as the RZ/G2M.

The kit consists of a SOM + Baseboard and supports microSD,
eMMC, Ethernet, a couple celular radios, two CAN interfaces,
Bluetooth and WiFi.

Signed-off-by: Adam Ford <aford173@gmail.com>
2020-07-25 14:19:26 +02:00
Adam Ford
3aabb0c3f1 ARM: dts: r8a774a1: Import DTS from Linux 5.8-rc1
This patch imports the device tree and required bindings to permit
the device tree to build for the R8Z774A1 (RZ/G2M).

Signed-off-by: Adam Ford <aford173@gmail.com>
2020-07-25 11:16:39 +02:00
Adam Ford
dbabfcc873 ARM: renesas: Add basic R8A774A1 Support
In order to build boards based on the R8A774A1, there needs to
be a config option from which to enable other drivers and/or flags
for this SoC.

Signed-off-by: Adam Ford <aford173@gmail.com>
2020-07-25 11:16:39 +02:00
Tom Rini
ada61f1ee2 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscv
- Fix SiFive HiFive Unleashed board booting failure problem.
- Enable SiFive fu540 PWM driver.
- Support SiFive fu540: SPI boot.
- Update OpenSBI used for RISC-V CI testing.
- Revert "riscv: Allow use of reset drivers".
- Revert "Revert "riscv: sifive: fu540: Add gpio-restart support"".
- sysreset: syscon:
        - Don't assume default value for offset and mask property.
        - Support value property.
- qemu: Add syscon reboot and poweroff support.
- Fix SIFIVE debug serial dependency.
- Fix linking error when building u-boot-spl with no SMP support.
- AE350 use fdtdec_get_addr_size_auto_noparent to parse smc reg.
- Make memory node available to SPL in hifive-unleashed-a00-u-boot.dtsi
- SiFive fu540 avoid using hardcoded ram base and size.
2020-07-24 08:43:08 -04:00
Tom Rini
7208396bbf Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm"
This reverts commit 5d3a21df66, reversing
changes made to 56d37f1c56.

Unfortunately this is causing CI failures:
https://travis-ci.org/github/trini/u-boot/jobs/711313649

Signed-off-by: Tom Rini <trini@konsulko.com>
2020-07-24 08:42:06 -04:00
Bin Meng
142dd57c5d riscv: dts: hifive-unleashed-a00: Make memory node available to SPL
Make memory node available to SPL in prepration to updates to SiFive
DDR RAM driver to read memory information from DT.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-07-24 14:56:29 +08:00
Leo Yu-Chi Liang
e491e15a3f riscv: Fix linking error when building u-boot-spl with no SMP support
Switch off SMP support when building u-boot-spl would cause linking error as follow:
undefined reference to 'secondary hart relocate' and 'smp_call_function'.
Add macro to wrap up proper code region that needs SMP configuration on.

Signed-off by: Leo Liang <ycliang@andestech.com>
Cc: rick@andestech.com
Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-07-24 14:56:13 +08:00
Bin Meng
6b62495026 Revert "riscv: Allow use of reset drivers"
This reverts commit 958a3f464c.

A more appropriate change below is already in mainline.
Commit fd31e4fd18 ("riscv: Do not build reset.c if SYSRESET is on")

Revert this patch, so that U-Boot can be built successfully for
SiFive Fu540 board.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Leo Liang <ycliang@andestech.com>
2020-07-24 14:55:31 +08:00
Jagan Teki
ff7d25e8db env: Enable SPI flash env for SiFive FU540
SPI flash device on HiFive Unleashed has 32MiB Size.

This patch adds SPI flash environment after U-Boot proper
partition with a size of 128KiB.

SPI flash partition layout(32MiB):
    0 - 34	: reserved for GPT header
   35 - 39	: unused
   40 - 2087	: loader1 (SPL, FSBL)
 2088 - 10279	: loader2 (U-Boot proper, U-Boot)
10280 - 10535	: environment
10536 - 65494	: rootfs
65528 - 65536	: distro script

Note: the loader1 must start from 40th sector even though
there are 6 free sectors prior since 40th sector is nearest
flash sector boundary. 

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
2020-07-24 14:55:19 +08:00
Jagan Teki
4243ff11fe sifive: fu540: Add Booting from SPI
Add booting from SPI for SiFive Unleashed board.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
2020-07-24 14:55:19 +08:00
Bin Meng
a0018fc820 riscv: Make SiFive HiFive Unleashed board boot again
Commit 40686c394e ("riscv: Clean up IPI initialization code")
caused U-Boot failed to boot on SiFive HiFive Unleashed board.

The codes inside arch_cpu_init_dm() may call U-Boot timer APIs
before the call to riscv_init_ipi(). At that time the timer register
base (e.g.: the SiFive CLINT device in this case) is unknown yet.

It might be the name riscv_init_ipi() that misleads people to only
consider it is related to IPI, but in fact the timer capability is
provided by the same SiFive CLINT device that provides the IPI.
Timer capability is needed for both UP and SMP.

Considering that the original refactor does have benefits, that it
makes the IPI code more similar to U-Boot initialization idioms.
It also removes some quite ugly macros. Let's do the minimal revert
instead of a complete revert, plus a fixes to arch_cpu_init_dm() to
consider the SPL case.

Fixes: 40686c394e ("riscv: Clean up IPI initialization code")
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Tested-by: Leo Liang <ycliang@andestech.com>
2020-07-24 14:55:04 +08:00
Tom Rini
5d3a21df66 binman support for FIT
new UCLASS_SOC
 patman switch 'test' command
 minor fdt fixes
 patman usability improvements
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Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm

binman support for FIT
new UCLASS_SOC
patman switch 'test' command
minor fdt fixes
patman usability improvements
2020-07-23 15:56:06 -04:00
Tom Rini
95fc1f1647 Merge tag 'u-boot-rockchip-20200722' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- New rk3326 board: Hardkernel Odroid Go2;
- Update board config and dts for RockPI 4/N8/N10;
- Update led boot on support for roc-rk3399-pc;
- Enable SPI Flash suppor for rk3328 rock64 board;
- Update rockchip pcie phy to use generic framework;
2020-07-22 11:30:52 -04:00
Jagan Teki
318392a745 arm64: dts: rockchip: Add u-boot, spl-boot-order for ROCKPi N10
Add u-boot,spl-boot-order for ROCKPi N10, so-that it can able
to boot from eMMC and SDMMC in order.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22 20:55:13 +08:00
Jagan Teki
e1e1c3de24 arm64: dts: rockchip: Add PCIe for RockPI N10
This patch adds support to enable PCIe for RockPI N10.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22 20:55:13 +08:00
Jagan Teki
5217f4991e arm: dts: rockchip: Add HDMI out for RockPI N8/N10
This patch adds support to enable HDMI out for
N10 and N8 combinations SBCs.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22 20:55:13 +08:00
Jagan Teki
87027292c1 ARM: dts: rockchip: Add USB for RockPI N8/N10
Radxa dalang carrier board has 2x USB 2.0 and 1x USB 3.0
ports.

This patch adds support to enable all these USB ports for
N10 and N8 combinations SBCs.

Note that the USB 3.0 port on RockPI N8 combination works
as USB 2.0 OTG since it is driven from RK3288.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22 20:55:13 +08:00
Jagan Teki
4b0446d57f ARM: dts: rockchip: Add usb host0 ohci node for rk3288
rk3288 and rk3288w have a usb host0 ohci controller.

Although rk3288 ohci doesn't actually work on hardware, but
rk3288w ohci can work well.

So add usb host0 ohci node in rk3288 dtsi and the quirk in
ohci platform driver will disable ohci on rk3288.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22 20:55:13 +08:00
Suniel Mahesh
e70d826c06 arm: dts: rockchip: Sync rk3288 dtsi from linux
This sync has changes required to use HDMI CEC pin in U-Boot.

Sync dts from linux v5.8-rc5 commit:
	"ARM: dts: rockchip: define the two possible rk3288 CEC pins"
	(sha1: 838980dd04e994bf81cf104fa01ae60802146b39)

Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2020-07-22 20:55:13 +08:00
Jagan Teki
2710779efd ARM: dts: rockchip: Sync ROCKPi N8/N10 dts(i) from Linux
Sync ROCKPi N8/N10 dts(i) changes from Linux.

commit <afd9eb880414> ("ARM: dts: rockchip: Add Radxa Rock Pi N8 initial
support")

Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
2020-07-22 20:55:13 +08:00
Jagan Teki
e230c579a3 rockchip: Separate the reset cause from display cpuinfo
reset cause is a generic functionality based on the soc
cru registers in rockchip. This can be used for printing
the cause of reset in cpuinfo or some other place where
reset cause is needed. 

Other than cpuinfo, reset cause can also be using during
bootcount for checking the specific reset cause and glow
the led based on the reset cause.

So, let's separate the reset cause code from cpuinfo, and
add a check to build it for rk3399, rk3288 since these two
soc are supporting reset cause as of now.

Tested-by: Suniel Mahesh <sunil@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22 20:55:13 +08:00
Jagan Teki
88132e0a28 rockchip: Don't clear the reset status reg
reset reason can be used several stages of U-Boot bootloader
like SPL, U-Boot proper based on the requirements.

Clearing the status register end of get_reset_cause will end
up showing the wrong reset cause when it read the second time.
For example, if board resets, SPL reads the reset status as
RST whereas U-Boot proper reads the status as POR.

However, based on the latest testing clearing reset status
won't be required for determine the last reset cause or
following resets.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22 20:55:13 +08:00
Kever Yang
b24405f39b rockchip: tpl: Remove board_early_init_f()
There is no need for board_early_init_f() in TPL, anything like this
should goes to SPL.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22 20:55:13 +08:00
Jagan Teki
500d1e7749 rockchip: rk3399: Add weak led_setup()
Add weak led_setup() so that board which has an uncommon
led setup code that can make use of custom implementation.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22 20:55:13 +08:00
Jagan Teki
eab5c50a3b rockchip: rk3288: Add OF board setup
The new rk3288 revision rk3288w has some changes with respect
to legacy rk3288 like hclk_vio in cru and usb host0 ohci.

Linux clock driver already handle this via rockchip,rk3288w-cru
compatible.

USB ohci host can enable via dts for rk3288w based boards.

So, add fdt board setup code to update cru compatible with
rk3288w-cru compatible if the SOC revision is RK3288W.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22 20:55:13 +08:00
Jagan Teki
c60d1c4e17 rockchip: Add rk3288 SoC detection helper
Rockchip SoC's has a new revision chip for rk3288 SoCs.

RK3288 has a new revision chip called RK3288W which is similar
but different hclk_vio clock and fixed OHCI host.

Add common Rockchip SoC detection helper to support this rk3288w
detection.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22 20:55:13 +08:00
Jagan Teki
1f1395405f arm64: dts: rockchip: Add Radxa ROCK Pi 4C support
Rock PI 4C has AP6256 Wifi/BT, PoE, miniDP, USB Host enabled
GPIO pin change compared to 4B, 4C.

So, add or enable difference nodes/properties in 4C dts
by including common dtsi.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22 20:55:13 +08:00
Jagan Teki
8d7192cb7f arm64: dts: rockchip: Add ROCKPi 4A/4B support
Rock PI 4 has 3 variants of hardware platforms called
RockPI 4A, 4B, and 4C.

- Rock PI 4A has no Wif/BT.
- Rock PI 4B has AP6256 Wifi/BT, PoE.
- Rock PI 4C has AP6256 Wifi/BT, PoE, miniDP, USB Host enable
  GPIO pin change compared to 4B, 4C

So move common nodes, properties into dtsi file and include
on respective variant dts files.

Use 4B dts into default rock-pi-4 defconfig until we find any
solution for dynamic detection of these variants.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22 20:55:13 +08:00
Alex Bee
90f740a06a rockchip: sdram: fix dram_init_banksize
Currently 2.5 GB is calculated as DRAM size for a 1 GB RK322x board
if CONFIG_SPL_OPTEE is set. This is troublesome when booting a
linux kernel since this size will be injected in FDT of the kernel.

gd->bd->bi_dram[0].start (which is basically CONFIG_SYS_SDRAM_BASE)
must not be taken into consideration for calculation of second bank
size, since this offset is already included in calculation of "top".

After applying this patch 992 MB (1024 MB - 32 MB reserved for
optee-os) is correctly calculated and has also been verified on
2 GB boards.

Signed-off-by: Alex Bee <knaerzche@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22 20:22:52 +08:00
Kever Yang
b32858ca51 rockchip: ram: fix debug funcfion define when RAM_ROCKCHIP_DEBUG not set
The empty function define should not be in the header file, or else the
build will error with function multi definition after CONFIG_RAM_ROCKCHIP_DEBUG
is disabled.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22 20:22:33 +08:00
Johannes Krottmayer
61b229e24c ARM: dts: rk3328-rock64: Add SPI Flash support
Add U-Boot SPI Flash support for the PINE64 Rock64 board

Signed-off-by: Johannes Krottmayer <krjdev@gmail.com>
Cc: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22 20:22:16 +08:00
Johannes Krottmayer
b5716c1325 ARM: dts: rk3328: Add SPI support
Add U-Boot SPI support for the RK3328

Signed-off-by: Johannes Krottmayer <krjdev@gmail.com>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
(fix checkpatch error for code ident)
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22 20:22:07 +08:00
Heiko Stuebner
02ce99ec91 rockchip: board: add Hardkernel Odroid Go2 board
Also known as Odroid Go Advance but named Go2 internally by the
vendor it seems.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22 20:21:23 +08:00
Heiko Stuebner
b75f01a918 rockchip: px30: sync Odroid Go Advance devicetree from Linux
Get the devicetree from mainline Linux and include it for U-Boot uses.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22 20:21:08 +08:00
Heiko Stuebner
014fbd7d36 rockchip: px30: sync the main rk3326 dtsi from mainline
The rk3326 is just a trimmed down px30 from a software perspective,
so the mainline rk3326 dtsi also ist just a tiny addition.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-22 20:21:01 +08:00
Masahiro Yamada
60e7fa8b3b treewide: convert devfdt_get_addr() to dev_read_addr()
When you enable CONFIG_OF_LIVE, you will end up with a lot of
conversions.

To generate this commit, I used coccinelle excluding drivers/core/,
include/dm/, and test/

The semantic patch that makes this change is as follows:

  <smpl>
  @@
  expression dev;
  @@
  -devfdt_get_addr(dev)
  +dev_read_addr(dev)
  </smpl>

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-20 11:37:47 -06:00
Dave Gerlach
469f04e882 arm: mach-k3: Use SOC driver for device identification
Make use of UCLASS_SOC to find device family and revision for
print_cpuinfo.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2020-07-20 11:37:47 -06:00
Dave Gerlach
a1631d51ad arm: dts: k3-j721e-mcu-wakeup: Introduce chipid node
Introduce a chipid node to provide a UCLASS_SOC driver to identify TI K3
SoCs.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2020-07-20 11:37:47 -06:00
Dave Gerlach
30402cadb3 arm: dts: k3-am65-wakeup: Introduce chipid node
Introduce a chipid node to provide a UCLASS_SOC driver to identify TI K3
SoCs.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2020-07-20 11:37:47 -06:00
Dave Gerlach
fbde39f417 test: Add tests for SOC uclass
Add a sandbox SOC driver, and some tests for the SOC uclass.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
2020-07-20 11:37:47 -06:00
Simon Glass
f07e58b878 cpu: Convert the methods to use a const udevice *
These functions should not modify the device. Convert them to const so
that callers don't need to cast if they have a const udevice *.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-07-20 11:37:47 -06:00
Simon Glass
c6efee5031 x86: mp: Add more comments to the module
Add a description of how this module works and also some missing function
comments.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-20 09:46:48 +08:00
Simon Glass
8dda2baa97 x86: mtrr: Add support for writing to MTRRs on any CPU
To enable support for the 'mtrr' command, add a way to perform MTRR
operations on selected CPUs.

This works by setting up a little 'operation' structure and sending it
around the CPUs for action.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-07-20 09:46:47 +08:00
Simon Glass
aa3a4d870e x86: mtrr: Update MTRRs on all CPUs
When the boot CPU MTRRs are updated, perform the same update on all other
CPUs so they are kept in sync.

This avoids kernel warnings about mismatched MTRRs.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-20 09:46:47 +08:00
Simon Glass
3d734b59c7 x86: Don't enable SMP in SPL
SMP should be set up in U-Boot where possible, not SPL. Disable it in SPL.
For 64-bit U-Boot we should find a way to allow SMP operations in U-Boot,
but this is somewhat more complicated. For now that is disabled too.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-07-20 09:46:46 +08:00
Simon Glass
240752c612 x86: mtrr: Use MP calls to list the MTRRs
Update the mtrr command to use mp_run_on_cpus() to obtain its information.
Since the selected CPU is the boot CPU this does not change the result,
but it sets the stage for supporting other CPUs.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-20 09:46:46 +08:00
Simon Glass
0538d6833c x86: mp: Add iterators for CPUs
It is convenient to iterate through the CPUs performing work on each one
and processing the result. Add a few iterator functions which handle this.
These can be used by any client code. It can call mp_run_on_cpus() on
each CPU that is returned, handling them one at a time.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-20 09:46:46 +08:00
Simon Glass
99a573fb32 x86: mp: Park CPUs before running the OS
With the new MP features the CPUs are no-longer parked when the OS is run.
Fix this by calling a special function to park them, just before the OS is
started.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-20 09:46:46 +08:00
Simon Glass
84d3ed125a x86: mp: Allow running functions on multiple CPUs
Add a way to run a function on a selection of CPUs. This supports either
a single CPU, all CPUs, just the main CPU or just the 'APs', in Intel
terminology.

It works by writing into a mailbox and then waiting for the CPUs to notice
it, take action and indicate they are done.

When SMP is not yet enabled, this just calls the function on the main CPU.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-20 09:46:45 +08:00
Simon Glass
db3a37c711 x86: Set the SMP flag when MP init is complete
Set this flag so we can track when it is safe to use CPUs other than the
main one.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-20 09:46:45 +08:00
Simon Glass
c33aa3527d x86: mp: Support APs waiting for instructions
At present the APs (non-boot CPUs) are inited once and then parked ready
for the OS to use them. However in some cases we want to send new requests
through, such as to change MTRRs and keep them consistent across CPUs.

Change the last state of the flight plan to go into a wait loop, accepting
instructions from the main CPU.

Drop cpu_map since it is not used.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-20 09:46:45 +08:00
Simon Glass
8bccbc5ac0 x86: cpu: Remove unnecessary #ifdefs
Drop some #ifdefs that are not needed or can be converted to compile-time
checks.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-20 09:46:44 +08:00
Simon Glass
20b049e885 x86: mp_init: Adjust bsp_init() to return more information
This function is misnamed since it does not actually init the BSP. Also
it is convenient to adjust it to return a little more information.

Rename and update the function, to allow it to return the BSP CPU device
and number, as well as the total number of CPUs.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-20 09:46:44 +08:00
Simon Glass
77a5e2d3bc x86: mp_init: Set up the CPU numbers at the start
At present each CPU is given a number when it starts itself up. While this
saves a tiny amount of time by doing the device-tree read in parallel, it
is confusing that the numbering happens on the fly.

Move this code into mp_init() and do it at the start.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-20 09:46:44 +08:00
Simon Glass
a6c9fd4da0 x86: mp_init: Drop the num_cpus static variable
This does not need to be global across all functions in this file. Pass a
parameter instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-20 09:46:43 +08:00
Simon Glass
3a5752ccff x86: mp_init: Switch parameter names in start_aps()
These parameters are named differently from elsewhere in this file. Switch
them to avoid confusion.

Also add comments to this function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-07-20 09:46:43 +08:00
Simon Glass
e624858407 x86: mp_init: Avoid declarations in header files
The functions used by the flight plan are declared in the header file but
are not used in any other file.

Move the flight plan steps down to just above where it is used so that we
can make these function static.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-20 09:46:43 +08:00
Simon Glass
78d57d63d7 x86: Move MP code into mp_init
At present the 'flight plan' for CPUs is passed into mp_init. But it is
always the same. Move it into the mp_init file so everything is in one
place. Also drop the SMI function since it does nothing. If we implement
SMIs, more refactoring will be needed anyway.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-20 09:46:42 +08:00
Simon Glass
cb1cb7146f x86: mp_init: Switch to livetree
Update this code to use livetree calls instead of flat-tree.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-20 09:46:42 +08:00
Stefan Roese
5fef24c912 mips: octeon: Add minimal Octeon 3 EBB7304 EVK support
This patch adds very basic minimal support for the Marvell Octeon 3
CN73xx based EBB7304 EVK. Please note that the basic Octeon port does
not support DDR3/4 initialization yet. To still use U-Boot on with this
port, the L2 cache (4MiB) is used as RAM. This way, U-Boot can boot
to the prompt on this board.

Supported devices:
- UART
- reset
- CFI parallel NOR flash

Signed-off-by: Stefan Roese <sr@denx.de>
2020-07-18 15:47:50 +02:00
Stefan Roese
e9609dc38b mips: octeon: use mips_mach_early_init() to copy to L2 cache
This patch adds the code to copy itself from bootrom location to a
different location (TEXT_BASE) to the Octeon platform. Its used in
this case to copy the complete U-Boot image into L2 cache, which
greatly improves the bootup time - especially in regard to the
very long and complex DDR4 init code.

The Kconfig symbol CONFIG_MIPS_MACH_EARLY_INIT is enabled with this
patch for Octeon.

Signed-off-by: Stefan Roese <sr@denx.de>
2020-07-18 15:47:50 +02:00
Stefan Roese
ff7e4f030b mips: octeon: dts: Add Octeon 3 cn73xx base dtsi file
This patch adds the base dtsi file for the Octeon 3 cn73xx SoC.

Signed-off-by: Stefan Roese <sr@denx.de>
2020-07-18 15:47:50 +02:00
Aaron Williams
0dc4ab9c43 mips: octeon: Initial minimal support for the Marvell Octeon SoC
This patch adds very basic support for the Octeon III SoCs. Only
CFI parallel NOR flash and UART is supported for now.

Please note that the basic Octeon port does not include the DDR3/4
initialization yet. This will be added in some follow-up patches
later. To still use U-Boot on with this port, the L2 cache (4MiB on
Octeon III CN73xx) is used as RAM. This way, U-Boot can boot to the
prompt on such boards.

Signed-off-by: Aaron Williams <awilliams@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
2020-07-18 15:47:50 +02:00
Stefan Roese
de34a61642 mips: Add CONFIG_MIPS_MACH_EARLY_INIT for very early mach init code
This patch adds the optional call to mips_mach_early_init() to start.S
at a very early stage. Its disabled per default. It can be used for
very early machine / platform specific init code.  Its called very
early and at this stage the PC is allowed to differ from the linking
address (CONFIG_TEXT_BASE) as no absolute jump has been performed until
this call.

It will be used by thje Octeon platform.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2020-07-18 14:23:25 +02:00
Daniel Schwierzeck
81d4b14f7e mips: sync asm/mipsregs.h with Linux 5.7
Sync asm/mipsregs.h with Linux 5.7. Also replace the custom
symbols EBASE_CPUNUM and EBASE_WG with the according symbols
from Linux.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2020-07-18 14:23:25 +02:00
Daniel Schwierzeck
c0f99579fa mips: sync asm/addrspace.h with Linux 5.7
Sync asm/addrspace.h with Linux 5.7

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2020-07-18 14:23:25 +02:00
Daniel Schwierzeck
eac800043f mips: sync asm/asm.h with Linux 5.7
Sync asm/asm.h with Linux 5.7.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2020-07-18 14:23:25 +02:00
Daniel Schwierzeck
dd1bb42305 mips: remove deprecated UNCACHED_SDRAM() macro
This macro only served as a wrapper for CKSEG1ADDR() with an
exception for CONFIG_TB0229. CONFIG_TB0229 doesn't exist, thus
use CKSEG1ADDR() directly.

This also prepares for an upcoming asm header sync with Linux.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2020-07-18 14:23:25 +02:00
Daniel Schwierzeck
57bfb1aed6 mips: add config options for generic cache setup code
Add an own Kconfig symbol for the initial disabling of caches
invoked from generic start code.

Also add an own Kconfig symbols for the initialization of caches
invoked from generic start code.

Until now both code paths could only be disabled with
CONFIG_SKIP_LOWLEVEL_INIT. But this is not flexible enough for
RAM boot scenarios like EJTAG or SPL payload or for machines
which don't require cache initialization or which want to
provide their own cache implementation.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2020-07-18 14:23:25 +02:00
Daniel Schwierzeck
60772433dd mips: refactor disabling of caches
Logically this code belongs to cache_init.S.

If a complex SoC needs to replace the generic cache init,
mips_cache_disable() can now be called from custom start.S files.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2020-07-18 14:23:25 +02:00
Daniel Schwierzeck
b55e07e565 mips: add KSEG1 wrapper for change_k0_cca
change_k0_cca() is called multiple times. Move the code for
changing to KSEG1 to a macro to avoid code duplication.

Also fix missing change to KSEG1 when changing to CONF_CM_CACHABLE_COW.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2020-07-18 14:23:25 +02:00
Daniel Schwierzeck
54e7fbd5ad mips: start.S: remove dead code
Since commit 703ec9ddf9 ("MIPS: Stop building position independent code")
the relocation code was completely reworked and removed from start.S.
Remove some left-overs of the old code.

Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
2020-07-18 14:23:25 +02:00
Stefan Roese
60a0559b7f mips: cache: Make invalidate_dcache_range() weak to enable overwrite
This patch adds __weak to invalidate_dcache_range() in lib/cache.c. This
makes it possible to overwrite this function by a platforms specific
version, which will be done for Octeon.

Signed-off-by: Stefan Roese <sr@denx.de>
2020-07-18 14:23:25 +02:00
Stefan Roese
1d4ba15c6f mips: cache: Make flush_cache() weak to enable overwrite
This patch adds __weak to flush_cache() in lib/cache.c. This makes it
possible to overwrite this function by a platforms specific version,
like done with the Octeon base port.

Signed-off-by: Stefan Roese <sr@denx.de>
2020-07-18 14:23:25 +02:00
Stefan Roese
2eed3dca22 mips: cache: Allow using CONFIG_MIPS_L2_CACHE without CONFIG_MIPS_CM
This patch enables the usage of CONFIG_MIPS_L2_CACHE without
CONFIG_MIPS_CM, which is what is needed for the newly added Octeon
platform.

Signed-off-by: Stefan Roese <sr@denx.de>
2020-07-18 14:23:25 +02:00
Stefan Roese
c372813105 mips: reloc: Change R_MIPS_NONE to catch pre-reloc BSS usage
This patch changes the R_MIPS_NONE define from 0 to a magic value. This
makes it possible to better detect any forbidden pre-relocation usage
of BSS variables, as they are often zero'ed and then relocation is
stopped too early.

Additionally the error message is improved to also print the faulting
address. This helps finding the root-cause for this breakage by
comparing this address with the values in System.map.

This patch helps a lot when working on pre-relocation code, like the
Octeon DDR init code, where such variables have hit me multiple times
now.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
2020-07-18 14:23:25 +02:00
Stefan Roese
a02bc1f992 mips: traps: Set WG bit in EBase register on Octeon
WG (bit 11) needs to be set on Octeon to enable writing bits 63:30 of
the exception base register.

Signed-off-by: Stefan Roese <sr@denx.de>
2020-07-18 14:23:25 +02:00
Stefan Roese
a414281da4 mips: time: Only compile the weak get_tbclk() when needed
This patch opts-out the compilation of get_tbclk() if
CONFIG_SYS_MIPS_TIMER_FREQ is not defined. This is used on the Octeon
platform, where the weak get_tbclk() function is overwritten by its
platform specific one.

Signed-off-by: Stefan Roese <sr@denx.de>
2020-07-18 14:23:24 +02:00
Masahiro Yamada
bb5a2cf9f9 treewide: convert bd_t to struct bd_info manually
Some code was not converted by coccinelle, somehow.

I manually fixed up the remaining, and comments, README docs.

Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
[trini: Add arch/arm/mach-davinci/include/mach/sdmmc_defs.h and
        include/fdt_support.h]
Signed-off-by: Tom Rini <trini@konsulko.com>
2020-07-17 10:46:44 -04:00
Masahiro Yamada
b75d8dc564 treewide: convert bd_t to struct bd_info by coccinelle
The Linux coding style guide (Documentation/process/coding-style.rst)
clearly says:

  It's a **mistake** to use typedef for structures and pointers.

Besides, using typedef for structures is annoying when you try to make
headers self-contained.

Let's say you have the following function declaration in a header:

  void foo(bd_t *bd);

This is not self-contained since bd_t is not defined.

To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h>

  #include <asm/u-boot.h>
  void foo(bd_t *bd);

Then, the include direcective pulls in more bloat needlessly.

If you use 'struct bd_info' instead, it is enough to put a forward
declaration as follows:

  struct bd_info;
  void foo(struct bd_info *bd);

Right, typedef'ing bd_t is a mistake.

I used coccinelle to generate this commit.

The semantic patch that makes this change is as follows:

  <smpl>
  @@
  typedef bd_t;
  @@
  -bd_t
  +struct bd_info
  </smpl>

Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
2020-07-17 09:30:13 -04:00
Patrick Delaunay
b4d14bc81a Convert CONFIG_ARMV7_PSCI_1_0 and CONFIG_ARMV7_PSCI_0_2 to Kconfig
This converts the following to Kconfig:
CONFIG_ARMV7_PSCI_1_0
CONFIG_ARMV7_PSCI_0_2

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-07-17 08:51:29 -04:00
Tom Rini
7c3cc6f106 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86
- New timer API to allow delays with a 32-bit microsecond timer
- Add dynamic ACPI structs (DSDT/SSDT) generations to the DM core
- x86: Enable ACPI table generation by default
- x86: Enable the copy framebuffer on Coral
- x86: A few fixes to FSP2 with ApolloLake
- x86: Drop setup_pcat_compatibility()
- x86: Primary-to-Sideband Bus minor fixes
2020-07-17 08:04:48 -04:00
Tom Rini
42e7659db0 i.MX for 2020.10
----------------
 
 - i.MX DDR driver fix/update for i.MX8M
 - i.MX pinctrl driver fix.
 - Use arm_smccc_smc to remove imx sip function
 - i.MX8M clk update
 - support booting aarch32 kernel on aarch64 hardware
 - fused part support for i.MX8MP
 - imx6: pcm058 to DM
 
 Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/708734785
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Merge tag 'u-boot-imx-20200716' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

i.MX for 2020.10
----------------

- i.MX DDR driver fix/update for i.MX8M
- i.MX pinctrl driver fix.
- Use arm_smccc_smc to remove imx sip function
- i.MX8M clk update
- support booting aarch32 kernel on aarch64 hardware
- fused part support for i.MX8MP
- imx6: pcm058 to DM

Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/708734785
2020-07-17 08:04:28 -04:00
Simon Glass
d40d2c5706 acpi: Enable ACPI table generation by default on x86
This should ideally be used by all x86 boards in U-Boot. Enable it by
default. If some boards don't use it, the cost is small.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-17 14:32:24 +08:00
Simon Glass
4021ee6388 x86: Rename board_final_cleanup() to board_final_init()
This function sounds like something that is called when U-Boot is about to
jump to Linux. In fact it is an init function.

Rename it to reduce confusion.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-07-17 14:32:24 +08:00
Simon Glass
22a7396f7f x86: acpi: Correct the version of the MADT
Currently U-Boot implements version 2 but reports version 4. Correct it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-07-17 14:32:24 +08:00
Simon Glass
a308b1fa39 x86: Drop setup_pcat_compatibility()
This function does not exist anymore. Drop it from the header file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-17 14:32:24 +08:00
Simon Glass
538c9b3d29 x86: Update the comment about booting for FSP2
The comment here applies only to FSP1, so update it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-07-17 14:32:24 +08:00
Simon Glass
9ef168676c x86: Store the coreboot table address in global_data
At present this information is used to locate and parse the tables but is
not stored. Store it so that we can display it to the user, e.g. with the
'bdinfo' command.

Note that now the GD_FLG_SKIP_LL_INIT flag is set in get_coreboot_info(),
so it is always set when booting from coreboot.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-07-17 14:32:24 +08:00
Simon Glass
487852b51b x86: apl: Adjust FSP-M code to avoid hard-coded address
Update this code to calculate the address to use, rather than hard-coding
it. Obtain the requested stack size from the FSP.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-17 14:32:24 +08:00
Simon Glass
efd3132852 x86: apl: Set the correct boot mode in the FSP-M code
If there is MRC information we should run FSP-M with a different
boot_mode flag since it is supposed to do a 'fast path' through the
memory init. Fix this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-17 14:32:24 +08:00
Simon Glass
b336a2b8f6 x86: Add debugging to table writing
Writing tables is currently pretty opaque. Add a bit of debugging to the
process so we can see what tables are written and where they start/end in
memory.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-07-17 14:32:24 +08:00
Simon Glass
b95611f67e x86: apl: Fix save/restore of ITSS priorities
The FSP-S changes the ITSS priorities. The code that tries to save it
before running FSP-S and restore it afterwards does not work as U-Boot
relocates in between the save and restore. This means that the driver
data saved before relocation is lost and the new driver just sees zeroes.

Fix this by allocating space in the relocated memory for the ITSS data.
Save it there and access it from the driver after relocation.

This fixes interrupt handling on coral.

Also drop the log_msg_ret() in irq_first_device_type() since this function
can be called speculatively in places where we are not sure if there is
an interrupt controller of that type. The resulting log errors are
confusing when there is no error.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-07-17 14:32:24 +08:00
Simon Glass
a8c2789c09 x86: irq: Support flags for acpi_gpe
This binding currently has a flags cell but it is not used. Make use of it
to create ACPI tables for interrupts.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-07-17 14:32:24 +08:00
Simon Glass
62fba44d6d x86: apl: Hide the p2sb on exit from U-Boot
This confuses Linux's PCI probing so needs to be hidden when booting
Linux. Add a remove() method to handle this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-07-17 14:32:24 +08:00
Simon Glass
f549d9bbde x86: apl: Support set_hide() in p2sb driver
Add support for this new method in the driver and in the fsp-s setup.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-07-17 14:32:24 +08:00
Simon Glass
eb2ebbcf56 x86: apl: Use memory-mapped access for VBT
Use the new binman memory-mapping function to access the VBT, to simplify
the code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-17 14:32:24 +08:00
Simon Glass
31b410a68c x86: Add error checking for csrt table generation
Generation of this table can fail, so update the function to return an
error code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-07-17 14:32:24 +08:00
Simon Glass
59cf26480b x86: pinctrl: Drop the acpi_path member
This is in the device tree now, so drop the unnecessary field here.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-17 14:32:24 +08:00
Simon Glass
05516e3d47 x86: pinctrl: Update comment for intel_pinctrl_get_pad()
Add information about what is returned on error.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-17 14:32:24 +08:00
Simon Glass
4916f4586e x86: pinctrl: Add a way to get the pinctrl reg address
At present we can query the offset of a pinctrl register within the p2sb.
For ACPI we need to get the actual address of the register. Add a function
to handle this and rename the old one to more accurately reflect its
purpose.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-07-17 14:32:24 +08:00
Simon Glass
7f926c9648 x86: Add support for building up an NHLT structure
The Intel Non-High-Definition-Audio Link Table (NHLT) table describes the
audio codecs and connections in a system. Various devices can contribute
information to produce the table.

Add functions to allow adding to the structure that is eventually written
to the ACPI tables. Also add the device-tree bindings.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-07-17 14:32:24 +08:00
Simon Glass
8d7ff12e63 acpi: Allow creating the GNVS to fail
In some cases an internal error may prevent this from working. Update the
function return value and report the error. At present the API for writing
tables does not easily support reporting errors, but once it is fully
updated to use a context pointer, this will be easier.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-07-17 14:32:24 +08:00
Simon Glass
fefac0b064 dm: acpi: Enhance acpi_get_name()
For many device types it is possible to figure out the name just by
looking at its uclass or parent. Add a function to handle this, since it
allows us to cover the vast majority of cases automatically.

However it is sometimes impossible to figure out an ACPI name for a device
just by looking at its uclass. For example a touch device may have a
vendor-specific name. Add a new "acpi,name" property to allow a custom
name to be created.

With this new feature we can drop the get_name() methods in the sandbox
I2C and SPI drivers. They were only added for testing purposes. Update the
tests to use the new values.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-17 14:32:24 +08:00
Simon Glass
58a6ccd34e x86: Allow devices to write to DSDT
Call the new core function to inject ASL programmatically into the DSDT.
This is made up of fragments generated by devices that have the
inject_dsdt() method. The normal, compiled ASL file is added after this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-17 14:32:24 +08:00
Simon Glass
01694589af acpi: Add support for DSDT generation
Some devices need to inject extra code into the Differentiated System
Descriptor Table (DSDT). Add a method to handle this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: correct one typo in inject_dsdt() comments]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-17 14:32:24 +08:00
Simon Glass
351fef5c57 x86: Allow devices to write an SSDT
Call the new core function to write the SSDT. This is made up of fragments
generated by devices that have the fill_ssdt() method.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-17 14:32:24 +08:00
Simon Glass
0f7b111f70 acpi: Support ordering SSDT data by device
Add a /chosen property to control the order in which the data appears
in the SSDT. This allows matching up U-Boot's output from a dump of the
known-good data obtained from within Linux.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-17 14:32:24 +08:00
Simon Glass
85f2def907 x86: acpi: Move MADT down a bit
Put this table before MCFG so that it matches the order that coreboot uses
when passing tables to Linux. This is a cosmetic change since the order of
the tables does not otherwise matter.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-17 14:32:24 +08:00
Simon Glass
b5183172f0 acpi: Add support for SSDT generation
Some devices need to generate code for the Secondary System Descriptor
Table (SSDT). Add a method to handle this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-17 14:32:24 +08:00
Simon Glass
0667900049 acpi: Support copying properties from device tree to ACPI
Some drivers in Linux support both device tree and ACPI. U-Boot itself
uses Linux device-tree bindings for its own configuration but does not use
ACPI.

It is convenient to copy these values over to the ACPI DP table for
passing to linux. Add some convenience functions to help with this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-17 14:32:24 +08:00
Simon Glass
1361a53c1a acpi: Add a function to get a device path and scope
Add a function to build up the ACPI path for a device and another for its
scope.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-17 14:32:24 +08:00
Simon Glass
0990c894cc x86: fsp: Support a warning message when DRAM init is slow
With DDR4, Intel SOCs take quite a long time to init their memory. During
this time, if the user is watching, it looks like SPL has hung. Add a
message in this case.

This works by adding a return code to fspm_update_config() that indicates
whether MRC data was found and a new property to the device tree.

Also add one more debug message while starting.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-07-17 14:32:24 +08:00
Simon Glass
ef5f5f6ca6 x86: Avoid #ifdef with CONFIG_HAVE_ACPI_RESUME
At present this enables a few arch-specific members of the global_data
struct which are otherwise not part of the struct. As a result we have to
use #ifdef in various places.

The cost of always having these in the struct is small. Adjust things so
that we can use compile-time code instead of #ifdefs.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-17 14:32:24 +08:00
Wolfgang Wallner
ce04a9020c x86: p2sb: make P2SB driver depend on P2SB uclass
Currently it is possible to select the P2SB driver without selecting the
P2SB uclass, which can't work. Fix this by adding a "depends on" in
Kconfig.

Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-17 14:32:24 +08:00
Ilko Iliev
8794cb543f arm: dts: imx7: Fix error in coresight TPIU graph connection
OF graph endpoint connections must be bidirectional and dtc warn if they
are not. i.MX7 based DTs have an error and generate
warnings:

arch/arm/dts/imx7d-sdb.dtb: Warning (graph_endpoint):
/replicator/ports/port@0/endpoint: graph connection to node
'/soc/tpiu@30087000/port/endpoint' is not bidirectional
arch/arm/dts/imx7d-sdb.dtb: Warning (graph_endpoint):
/soc/tpiu@30087000/port/endpoint: graph connection to node
'/replicator/ports/port@1/endpoint' is not bidirectional

Signed-off-by: Ilko Iliev <iliev@ronetix.at>
2020-07-16 11:20:58 +02:00
Heinrich Schuchardt
90865614b4 ARM: mx6: make CAAM usable on the i.MX6 boards
Even if the HAB fuse is not set we want to be able to use the Cryptographic
Accelerator and Assurance Module (CAAM) for generating random numbers. So
SYS_FSL_HAS_SEC should be selected even if IMX_HAB is not set.

arch_misc_init() has to be called to initialize the CAAM.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-07-16 11:20:08 +02:00
Ye Li
dfbdaa66b7 misc: scu_api: Add SCFW API to get the index of boot container set
Add SCFW API sc_misc_get_boot_container to get current boot container
set index.
The index value returns 1 for primary container set, 2 for secondary
container set.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-07-16 11:19:50 +02:00
Niel Fourie
26a6ed1b2e arm: imx6q: pcm058: Convert pcm058 to use DM with DTs
Convert pcm058 support to use device trees and the driver model.
Add rudimentary boot scripts to the environment, expand README.

Signed-off-by: Niel Fourie <lusus@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2020-07-14 11:46:04 +02:00
Niel Fourie
08310cf96e arm: dts: imx6q: Add Linux dts files for Phytec Mira
Add Phytec Mira device tree files, for use with pcm058.
>From Linux 5.6, commit 7111951b8d49 upstream

Signed-off-by: Niel Fourie <lusus@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
2020-07-14 11:46:04 +02:00
Peng Fan
eb3967388e imx8m: implement armv8_el2_to_aarch32
Add iMX8M specific armv8_el2_to_aarch32 to let AArch64 mode U-Boot
could boot aarch32 mode linux with FIT image as below:

/dts-v1/;

/ {
        description = "Configuration to load ARM32 Linux";

        images {
                kernel@1 {
                        description = "ARM32 Linux kernel";
                        data = /incbin/("./Image");
                        type = "kernel";
                        arch = "arm";
                        os = "linux";
                        compression = "none";
                        load = <0x40008000>;
                        entry = <0x40008000>;
                        hash@1 {
                                algo = "md5";
                        };
                };
                fdt@1 {
                        description = "Flattened Device Tree blob";
                        data = /incbin/("./imx8mm-evk.dtb");
                        type = "flat_dt";
                        arch = "arm";
                        compression = "none";
                        load = <0x43000000>;
                        hash@1 {
                                algo = "md5";
                        };
                };
        };
        configurations {
                default = "config@1";

                config@1 {
                        description = "fsl-imx8mm-evk";
                        kernel = "kernel@1";
                        fdt = "fdt@1";
                };
        };
};

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:48 +08:00
Peng Fan
3c41728d80 imx8m: Refactor the OPTEE memory removal
Current codes assume the OPTEE address is at the end of first DRAM bank.
Adjust the process to allow OPTEE in the middle of first bank.

When OPTEE memory is removed from first bank, it may split the first bank
to two banks, adjust the MMU table for the split case,
Since the default CONFIG_NR_DRAM_BANKS is 4, it is enough, just enlarge
i.MX8MP evk to default to avoid issue.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Tested-by: Silvano di Ninno <silvano.dininno@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:48 +08:00
Peng Fan
6036dba1c8 imx8m: disable nodes before kernel/mfgtool boot for fused part
To fused part, we need to disable nodes of dtb to let kernel boot.

To mfgtool, USB issue when using super-speed for mfgtool, temporally
work around the problem to use high-speed only.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:47 +08:00
Ye Li
2707faf01f imx8mn/imx8mp: override env_get_offset and env_get_location
To use one defconfig for all boot device, we have to runtime set
env offset and return env medium according to the boot device.
This patch overrides the env_get_offset and env_get_location to
implement the feature.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:47 +08:00
Peng Fan
7a42bf0489 imx8m: power down fused cores
For non-Quad SoCs, the fused cpu cores could be powered down in SPL
to save power.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:47 +08:00
Ye Li
d1eee7eed9 imx8mp: Add fused parts support
iMX8MP has 6 fused parts in each qualification tier, with core, VPU,
ISP, NPU or DSP fused respectively.

The configuration tables for enabled modules:
MIMX8ML8DVNLZAA          Quad Core, VPU, NPU, ISP, DSP
MIMX8ML7DVNLZAA          Quad Core, NPU, ISP
MIMX8ML6DVNLZAA          Quad Core, VPU, ISP
MIMX8ML5DVNLZAA          Quad Core, VPU
MIMX8ML4DVNLZAA          Quad Lite
MIMX8ML3DVNLZAA          Dual Core, VPU, NPU, ISP, DSP

Add the support in U-Boot

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:47 +08:00
Peng Fan
2f3c92060d imx8m: workaround ROM serror
ROM SError happens on two cases:

1. ERR050342, on iMX8MQ HDCP enabled parts ROM writes to GPV1 register, but
when ROM patch lock is fused, this write will cause SError.

2. ERR050350, on iMX8MQ/MM/MN, when the field return fuse is burned, HAB
is field return mode, but the last 4K of ROM is still protected and cause
SError.

Since ROM mask SError until ATF unmask it, so then ATF always meets the
exception. This patch works around the issue in SPL by enabling SPL
Exception vectors table and the SError exception, take the exception
to eret immediately to clear the SError.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:47 +08:00
Peng Fan
3c9221ad27 imx8m: add eqos clk
Add imx_eqos_txclk_set_rate/imx_get_eqos_csr_clk to override the
weak function in driver

Add set_clk_eqos to configure eQoS clk

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:47 +08:00
Peng Fan
3c1c28d4e0 imx8m: add sdhc/nand/ecspi clk api
Current DM CLK is a bit complicated, for simplity, let DM clk only
support enable/disable/get_rate. For the expected rate settings,
we use non-DM clk to do that. Then we could have simple DM clk for
i.MX and could also share between SPL/U-Boot proper.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:47 +08:00
Peng Fan
14254e646d imx8m: configure NoC clk
Configure NoC clk for better system performance

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:47 +08:00
Peng Fan
46a8a28bf6 imx8m: configure arm clk sources from PLL
A53 CCM root max support 1GHz, to support high freq, we need
to switch ARM clk sources from ARM PLL directly.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:47 +08:00
Peng Fan
d6498bc459 imx: remove imx sip file
We have switch to use arm_smccc_smc, no need to keep i.MX specific
sip wrapper.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:47 +08:00
Peng Fan
bf26b9421e imx: bootaux: use arm_smccc_smc
Use arm_smccc_smc to replace call_imx_sip

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:46 +08:00
Peng Fan
a2f143eaac imx8m: soc: use arm_smccc_smc
Use arm_smccc_smc to replace call_imx_sip

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:46 +08:00
Peng Fan
dc575201c8 imx8: misc: use arm_smccc_smc
Use arm_smccc_smc to replace call_imx_sip

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:46 +08:00
Oliver Chen
b335966958 drivers: ddr: imx Workaround for i.MX8M DDRPHY rank to rank issue
Add logic to automatically update umctl2's setting based
on phy training CDD value for rank to rank space issue

Acked-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Oliver Chen <Oliver.Chen@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:46 +08:00
Sherry Sun
f3acb02386 drivers: ddr: imx8mp: Add inline ECC feature support
the DRAM Controller in i.MX8MP will support a feature called "Inline ECC".
This is supported for all 3 supported DRAM technologies (LPDDR4, DDR4 and
DDR3L). When this feature is enabled by software, the DRAM Controller
reserves 12.5% of DRAM capacity for ECC information, and presents only
the non-ECC portion (lower 87.5% of the installed capacity of DRAM) to
the rest of the SoC.
The DRAM memory can be divided into 8 regions so that if a use case only
requires ECC protection on a subset of memory, then only that subset of
memory need support inline ECC. If this occurs, then there is no
performance penalty accessing the non-ECC-protected memory (no need to
access ECC for this portion of the memory map). This is all configured
with the DRAM Controller.

Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-07-14 15:23:46 +08:00
Patrick Delaunay
865fdfddce arm: k3: use correct weak function name spl_board_prepare_for_linux
Replace the function spl_board_prepare_for_boot_linux by the correct
name of the weak function spl_board_prepare_for_linux defined in spl.h.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-07-13 20:58:34 +05:30
Jan Kiszka
dde9da82d6 arm: k3: Consolidate and silence k3_fit_atf.sh call
Buiding u-boot-spl-k3[_HS].its is currently unconditionally verbose
about what it does. Change that by wrapping the call to k3_fit_atf.sh
into a cmd, also using that chance to reduce duplicate lines of makefile
code - only IS_HS=1 is different when CONFIG_TI_SECURE_DEVICE is on.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-07-13 20:58:34 +05:30
Vignesh Raghavendra
3f09ebfbde arm: dts: k3-am65: Sync CPSW DT node from kernel
Sync CPSW DT node from kernel and move it out of -u-boot.dtsi file.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-07-13 20:58:34 +05:30
Vignesh Raghavendra
aeeca07a80 arm: dts: k3-j721e: Sync CPSW DT node from kernel
Sync CPSW DT node from Kernel and move it out of -u-boot.dtsi file.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2020-07-13 20:58:34 +05:30
Vignesh Raghavendra
99faf0df04 arm: dts: k3-am65/j721e: Sync DMA DT bindings from Kernel DT
Sync DT bindings from kernel DT and move them to out of -u-boot.dtsi
files.

Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
2020-07-13 20:58:34 +05:30
Tom Rini
497c7598c4 Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-spi
- Enable DM_SPI on siemens omap boards (Jagan)
- Dropped some non-dm supported omap3 boards (Jagan)
- Dropped non-dm code in omap3 spi driver (Jagan)
- Dropped non-dm code in kirkwood spi driver (Bhargav)
2020-07-11 17:40:00 -04:00
Tom Rini
610e1487c8 UniPhier SoC updates for v2020.10
- remove workaround for Cortex-A72
 
  - increase U-Boot proper size to 2MB
 
  - sync DT with Linux
 
  - add system bus controller driver
 
  - improve serial driver
 
  - add reset assertion to Denali NAND driver
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Merge tag 'uniphier-v2020.10' of https://gitlab.denx.de/u-boot/custodians/u-boot-uniphier

UniPhier SoC updates for v2020.10

 - remove workaround for Cortex-A72

 - increase U-Boot proper size to 2MB

 - sync DT with Linux

 - add system bus controller driver

 - improve serial driver

 - add reset assertion to Denali NAND driver
2020-07-11 11:50:49 -04:00
Masahiro Yamada
5785950369 ARM: uniphier: remove NAND reset code
Now that commit 3e57f879ee ("mtd: nand: raw: denali: Assert reset
before deassert") added the reset assertion, this code in the board
file is unneeded.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-11 21:56:51 +09:00
Masahiro Yamada
d7877c985b ARM: uniphier: remove sbc/ directory
Now that this directory contains only uniphier_sbc_boot_is_swapped(),
move it to boot-device.c and delete the sbc/ directory entirely.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-11 21:30:21 +09:00
Masahiro Yamada
862274913f bus: uniphier-system-bus: move hardware init from board files
Move the bus initialization code to this driver from board files.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-11 21:30:21 +09:00
Masahiro Yamada
e2bb0be2fc bus: uniphier-system-bus: add UniPhier System Bus driver
Since commit 1517126fda ("ARM: uniphier: select DM_ETH"), DM-based
drivers/net/smc911x.c is compiled, but it is never probed because the
parent node lacks the DM-based driver.

I need a skeleton driver to populate child devices (but the next commit
will move more hardware settings to the this driver).

I put this to drivers/bus/uniphier-system-bus.c because this is the
same path as the driver in Linux kernel.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-11 21:30:21 +09:00
Masahiro Yamada
d69d49d3ec ARM: uniphier: remove support for NOR Flash on support card
I actually do not see this used these days because eMMC or NAND is used
for non-volatile devices. Dump the burden to maintain this crappy code.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-11 21:30:21 +09:00
Masahiro Yamada
f95237bb02 ARM: uniphier: remove unused uniphier_sbc_init_admulti()
This was used by the old sLD3 SoC, the support of which was removed
by commit 00aa453ebf ("ARM: uniphier: remove sLD3 SoC support").

There is no more user of this function.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-11 21:30:21 +09:00
Masahiro Yamada
43db571b2d ARM: uniphier: fix build error when CONFIG_MICRO_SUPPORT_CARD=n
If CONFIG_MICRO_SUPPORT_CARD is unset, the build fails due to
function redefinition.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-11 21:30:21 +09:00
Masahiro Yamada
0852033309 ARM: uniphier: sync with Linux 5.8-rc4
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-11 21:30:21 +09:00
Masahiro Yamada
56d463bdba ARM: uniphier: consolidate SoC select menu
Currently, the supports for the following two ARMv7 SoC groups
are exclusive, because the boot ROM loads the SPL to a different
address:

 - LD4, sLD8                 (SPL is loaded at 0x00040000)
 - Pro4, Pro5, PXs2, LD6b    (SPL is loaded at 0x00100000)

This limitation exists only when CONFIG_SPL=y.

Instead of using crappy CONFIG options, checking SPL and SPL_TEXT_BASE
is cleaner.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-11 21:30:21 +09:00
Masahiro Yamada
1f8e6a670c Revert "ARM: uniphier: add weird workaround code for LD20"
This reverts commit 45f41c134b.

This weird workaround was the best I came up with at that time
to boot U-Boot from TF-A.

I noticed U-Boot successfully boots on LD20 (i.e. CA72 CPU) by using
the latest TF-A.

Specifically, since the following TF-A commit, U-Boot runs at EL2
instead of EL1, and this issue went away as a side-effect.

|commit f998a052fd94ea082833109f25b94ed5bfa24e8b
|Author: Masahiro Yamada <yamada.masahiro@socionext.com>
|Date:   Thu Jul 25 10:57:38 2019 +0900
|
|    uniphier: run BL33 at EL2
|
|    All the SoCs in 64-bit UniPhier SoC family support EL2.
|
|    Just hard-code MODE_EL2 instead of using el_implemented() helper.
|
|    Change-Id: I7ab48002c5205bc8c013e1b46313b57d6c431db0
|    Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

However, if I reverted that, this problem would come back, presumably
because some EL1 code in U-Boot triggers this issue.

Now that commit f8ddd8cbb5 ("arm64: issue ISB after updating system
registers") fixed this issue properly, this weird workaround is no
longer needed irrespective of the exception level at which U-Boot runs.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-11 21:30:21 +09:00
Tom Rini
4a9146c295 of-platdata: better phandle and compatible-string support
patman support for Python3 on Ubuntu 14.04
 new checkpatch check to avoid #ifdefs
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Merge tag 'dm-pull-10jul20' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm

of-platdata: better phandle and compatible-string support
patman support for Python3 on Ubuntu 14.04
new checkpatch check to avoid #ifdefs
2020-07-10 16:22:57 -04:00
Tom Rini
3113c84ba2 - add support for PCI and XHCI for RPi4 (64 bit only)
- optionally reset XHCI device on registration
 - enable USB_KEYBOARD for rpi_4_defconfig
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Merge tag 'rpi-next-2020.10' of https://gitlab.denx.de/u-boot/custodians/u-boot-raspberrypi

- add support for PCI and XHCI for RPi4 (64 bit only)
- optionally reset XHCI device on registration
- enable USB_KEYBOARD for rpi_4_defconfig
2020-07-10 14:31:22 -04:00
Marek Szyprowski
814e1a4b8c rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 32bit)
Create a non-cacheable mapping for the 0x600000000 physical memory region,
where MMIO registers for the PCIe XHCI controller are instantiated by the
PCIe bridge. Due to 32bit limit in the CPU virtual address space in ARM
32bit mode, this region is mapped at 0xff800000 CPU virtual address.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
2020-07-10 14:10:43 -04:00
Marek Szyprowski
d877f8fd0f arm: provide a function for boards init code to modify MMU virtual-physical map
Provide function for setting arbitrary virtual-physical MMU mapping
and cache settings for the given region.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2020-07-10 14:10:43 -04:00
Marek Szyprowski
f5a9fcc602 arm: update comments to the common style
Update the comments in include/asm/system.h to the common style.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2020-07-10 14:10:43 -04:00
Nicolas Saenz Julienne
d774da08dc arm: rpi: Add function to trigger VL805's firmware load
On the Raspberry Pi 4, after a PCI reset, VL805's (a xHCI chip) firmware
may either be loaded directly from an EEPROM or, if not present, by the
SoC's VideCore (the SoC's co-processor). Introduce the function that
informs VideCore that VL805 may need its firmware loaded.

Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2020-07-10 11:49:28 +02:00
Walter Lozano
407009a426 arm: dts: include gpio nodes for card detect
Several MMC drivers use GPIO for card detection with cd-gpios property in
the MMC node pointing to a GPIO node. However, as U-Boot tries to save
space by keeping only required nodes using u-boot* properties, several
devices tree result in having only in the MMC node but not the GPIO node
associated to cd-gpios.

This patch, fixes several ocurrence of this issue.

Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Adam Ford <aford173@gmail.com> #da850-evm
2020-07-09 22:00:29 -06:00
Walter Lozano
df29730410 sandbox: Move section u_boot_list to make it RW
In order to be able to update data in u_boot_list, move this section to
make it RW.

Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-09 22:00:29 -06:00
Walter Lozano
e3e2470fdd drivers: rename drivers to match compatible string
When using OF_PLATDATA, the bind process between devices and drivers
is performed trying to match compatible string with driver names.
However driver names are not strictly defined, and also there are different
names used when declaring a driver with U_BOOT_DRIVER, the name of the
symbol used in the linker list and the used in the struct driver_info.

In order to make things a bit more clear, rename the drivers names. This
will also help for further OF_PLATDATA improvements, such as checking
for valid driver names.

Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Add a fix for sandbox of-platdata to avoid using an invalid ANSI colour:
Signed-off-by: Simon Glass <sjg@chromium.org>
2020-07-09 18:57:22 -06:00
Heinrich Schuchardt
e85497a930 sandbox: make RAM size configurable
Up to now the RAM size of the sandbox is hard coded as 128 MiB. This does
not allow testing the correct handling of addresses outside the 32bit
range. 128 MiB is also rather small when tracing functions where the trace
is written to RAM.

Provide configuration variable CONFIG_SANDBOX_RAM_SIZE_MB to set the RAM
size in MiB. It defaults to 128 MiB with a minimum of 64 MiB.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-09 18:57:22 -06:00
Heinrich Schuchardt
c7e49ddc61 sandbox: handling out of memory
assert() only works in debug mode. So checking a successful memory
allocation should not use assert().

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-09 18:57:21 -06:00
Jagan Teki
f247354708 arm: Remove mx31pdk board
DM, OF_CONTROL, DM_SPI and other driver model migration
deadlines are expired for this board.

Remove it.

Acked-by: Magnus Lilja <lilja.magnus@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-07-09 20:58:06 +05:30
Jagan Teki
bb1cbb2ba6 arm: Remove pengwyn board
OF_CONTROL, DM_SPI and other driver model migration deadlines
are expired for this board.

Remove it.

Cc: Lothar Felten <lothar.felten@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-07-09 20:58:06 +05:30
Jagan Teki
bce26c45e2 arm: Remove pepper board
OF_CONTROL, DM_SPI and other driver model migration deadlines
are expired for this board.

Remove it.

Cc: Ash Charles <ash@gumstix.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-07-09 20:58:05 +05:30
Jagan Teki
37559488a9 arm: Remove bav335x board
OF_CONTROL, DM_SPI and other driver model migration deadlines
are expired for this board.

Remove it.

Cc: Gilles Gameiro <gilles@gigadevices.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-07-09 20:58:05 +05:30
Jagan Teki
45833e25fc arm: Remove cairo board
OF_CONTROL, DM_SPI and other driver model migration deadlines
are expired for this board.

Drop it.

Cc: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-07-09 20:58:05 +05:30
Jagan Teki
d78b9df763 logicpd: Drop omap3 zoom1
OF_CONTROL, DM_SPI and other driver model migration deadlines
are expired for this board.

Drop it.

Cc: Nishanth Menon <nm@ti.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-07-09 20:58:05 +05:30
Jagan Teki
ed3294d6d1 arm: Remove overo board
OF_CONTROL, DM_SPI and other driver model migration deadlines
are expired for this board.

Drop it.

Cc: Ash Charles <ash@gumstix.com>
Cc: Steve Sakoman <sakoman@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-07-09 20:58:05 +05:30
Jagan Teki
76386d6195 arm: Remove cm_t35 board
DM, DM_SPI and other driver model migration deadlines
are expired for this board.

Remove it.

Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-07-09 20:58:05 +05:30
Jagan Teki
a25aea733d arm: Remove cm_t54 board
DM, DM_SPI and other driver model migration deadlines
are expired for this board.

Remove it.

Cc: Dmitry Lifshitz <lifshitz@compulab.co.il>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-07-09 20:58:05 +05:30
Tom Rini
506d52308a Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86
- Add two- and three-argument versions of CONFIG_IS_ENABLED in
  linux/kconfig.h
- Adds a new feature which supports copying modified parts of
  the frame buffer to the uncached hardware buffer
- Enable the copy framebuffer on various x86 targets
2020-07-09 09:54:22 -04:00
Marek Szyprowski
d69ddf2494 rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 64bit)
Create a non-cacheable mapping for the 0x600000000 physical memory region,
where MMIO registers for the PCIe XHCI controller are instantiated by the
PCIe bridge.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2020-07-09 15:46:12 +02:00
Marek Szyprowski
c44b3f523c rpi4: shorten a mapping for the DRAM
Remove the overlap between DRAM and device's IO area.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2020-07-09 15:46:12 +02:00
Tom Rini
d9107930af Merge tag 'for-v2020.10' of https://gitlab.denx.de/u-boot/custodians/u-boot-i2c
i2c changes for v2020.10
- Add support for I2C controllers found on Octeon II/III and Octeon TX
  TX2 SoC platforms.
- Add I2C controller support for Cortina Access CAxxxx SoCs
- new rtc methods, rtc command, and tests
- imx_lpi2c: Improve the codes to use private data
- stm32f7_i2c.c: Add new compatible "st,stm32mp15-i2c"
- stm32f7_i2c.c: Add Fast Mode Plus support
- pwm: Add PWM driver for SiFive SoC
2020-07-09 08:22:44 -04:00
Simon Guinot
ca6f44ec19 arm: kirkwood: add DT spi0 alias to LaCie boards
The spi0 alias is needed by the environment code to retrieve the SPI
flash. This patch adds some -u-boot.dtsi files, providing the spi0
aliases, for all the following Kirkwood-based LaCie boards:

- d2 Network v2
- Internet Space v2
- 2Big Network v2
- Network Space v2
- Network Space Lite v2
- Network Space Max v2
- Network Space Mini v2

Note that this -u-boot.dtsi files will be removed as soon as the spi0
aliases will be available in the upstream Linux dtsi files.

Signed-off-by: Simon Guinot <simon.guinot@sequanux.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-07-09 06:51:20 +02:00
Dennis Gilmore
34fb7df42e arm: mvebu: helios4: sync helios4 config to clearfog and dts to kernel
The helios4 is built on the same microsom as the clearfog, by syncing the config
we enable the same featureset that exists in the som on the helios4. The current
config does not boot as some of the clearfog changes needed to be made on the
helios4 also, generally speaking most changes for the clearfog should also be
made on the helios4.

Signed-off-by: Dennis Gilmore <dennis@ausil.us>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-07-09 06:50:05 +02:00
Chris Packham
4182232158 arm: mvebu: a38x: Adjust UTMI PHY parameters
When running USB compliance tests on our Armada-385 hardware platforms
we have seen some eye mask violations. Marvell's internal documentation
says: Based on silicon test results, it is recommended to change the
impedance calibration threshold setting to 0x6 prior to calibration.

Port changes from Marvell's u-boot fork[1] to address this.

[1] - https://github.com/MarvellEmbeddedProcessors/u-boot-marvell/commit/a6221551

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-07-09 06:49:44 +02:00
Chris Packham
ec9deec400 arm: mvebu: a38x: Fix typo
Fix spelling of Alignment.

Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-07-09 06:49:44 +02:00
Simon Glass
db17e40cca x86: apl: Re-enable loading of SPL
At present the SPL loader is not included in the TPL image so SPL cannot
be loaded. Fix it by including this file for both SPL and TPL.

Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: c87f9ce227 ("x86: Don't build some unused objects in TPL")
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-09 12:33:24 +08:00
Bin Meng
7d5de35b6f arm: cmd_stm32prog: Fix the CONFIG_IS_ENABLED() usage
Add parentheses around CONFIG_IS_ENABLED() in the if statement, to
fix potential build failures.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-07-09 12:33:24 +08:00
Simon Glass
be7418f35e x86: fsp: video: Allocate a frame buffer when needed
When the copy framebuffer is in use, we must also have the standard U-Boot
framebuffer available. Update the FSP driver to support this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-09 12:33:24 +08:00
Simon Glass
3dada5a1a8 x86: fsp: Reinit the FPU after FSP meminit
The APL FSP appears to leave the FPU in a bad state in that it has
registers in use. This causes an error when the next FPU operation is
performed.

Work around this by re-resetting the FPU after calling FSP-M. This allows
the freetype console to work correctly.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-09 12:33:24 +08:00
Rasmus Villemoes
baed779138 test: dm: rtc: add test of dm_rtc_read, dm_rtc_write
Define a few aux registers and check that they can be read/written
individually. Also check that one can access the time-keeping
registers directly and get the expected results.

Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2020-07-09 06:02:45 +02:00
Tom Rini
186529953f - Add proper Odroid-N2 board support code
- Add support for Odroid-C4 single board computer
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Merge tag 'u-boot-amlogic-20200708' of https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic

- Add proper Odroid-N2 board support code
- Add support for Odroid-C4 single board computer
2020-07-08 10:40:32 -04:00
Neil Armstrong
d9c967792b ARM: dts: meson-sm1-odroid-c4: add ethernet PHY reset
The PHY needs a reset in order to be functionnal for U-Boot, add the old
PHY reset bindings for dwmac until we support the new bindings in the PHY node.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Anand Moon <linux.amoon@gmail.com>
2020-07-08 10:52:45 +02:00
Christian Hewitt
8888d83773 boards: amlogic: add Odroid C4 support
Odroid C4 is an Amlogic SM1 device, the board config and board documentation
are adapted from the Odroid-N2 support from the same vendor.

Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
[narmstrong: fix odroid-c4.rst typos and structure]
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Anand Moon <linux.amoon@gmail.com>
2020-07-08 10:52:45 +02:00
Christian Hewitt
da77a787ff ARM: dts: sync amlogic G12A/G12B/SM1 DT from Linux 5.8-rc1
This imports the changes and the new Odroid-C4 board from the Linux
commit b3a9e3b9622a ("Linux 5.8-rc1").

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Anand Moon <linux.amoon@gmail.com>
2020-07-08 10:52:45 +02:00
Tom Rini
526fe06a5d Merge tag 'u-boot-rockchip-20200708' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- dts sync from kernel for rk3399 boards;
- Add Radxa Rock Pi N8, N10;
- Some feature update for Pinebook Pro;
2020-07-07 23:05:57 -04:00
Andre Przywara
cc696e7cae arm: juno: Enable DM_ETH
The smc911X driver is now DM enabled, so we can switch the Juno board
over to use DM_ETH for the on-board Fast Ethernet device.
Works out of the box by using the DT.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
2020-07-07 18:23:48 -04:00
Heinrich Schuchardt
22a4e006be arm: use correct argument size of special registers
Compiling with clang on ARMv8 shows errors like:

./arch/arm/include/asm/system.h:162:32: note: use constraint modifier "w"
                asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc");
                                             ^~
                                             %w0

These errors are due to using an incorrect size for the variables used
for writing to and reading from special registers which have 64 bits on
ARMv8.

Mask off reserved bits when reading the exception level.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-07-07 18:23:48 -04:00
Heinrich Schuchardt
b87d8d6a0e arm: remove outdated comment concerning -ffixed-x18
Clang 9 supports -ffixed-x18.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-07 18:23:48 -04:00
Amit Singh Tomar
cd2baaf777 owl: Kconfig: Enable DM eth for OWL platform
This patch selects CONFIG_DM_ETH (ethernet driver is base on DM model)
for Action semi owl SoC.

Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
2020-07-07 17:12:01 -04:00
Amit Singh Tomar
75523d54ac arm: dts: s700: add node for ethernet controller
This patch adds node for ethernet controller found on Action Semi OWL
S700 SoC.

Since, there is no upstream Linux binding exist for S700 ethernet
controller, Changes are put in u-boot specific dtsi file.

Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
2020-07-07 17:12:01 -04:00
Amit Singh Tomar
3c5c4ee35f net: designware: s700: Add glue code for S700 mac
This patchs adds glue logic to enable designware mac present on
Action Semi based S700 SoC, Configures SoC specific bits.

Undocumented bit that programs the PHY interface select register
comes from vendor source.

It has been tested on Cubieboard7-lite based on S700 SoC.

Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
2020-07-07 17:11:58 -04:00
Amit Singh Tomar
3a21734605 clk: actions: Add Ethernet clocks
This commit adds clocks needed for ethernet operations for
Actions OWL family of SoCs (S700 and S900).

Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
2020-07-07 16:09:22 -04:00
Amit Singh Tomar
3ca564e96e Actions: OWL: Calculate SDRAM size
Calculate the SDRAM size from DDR capacity register registers instead
of using hard-coded value. This is quite useful to get correct size
on differnt boards based on Actions OWL family of SoCs (S700 and S900).

There is no documentation available that talks about DDR registers, and
this is very much taken from vendor source.

This commit lets Linux boot on Cubieboard7-lite(based on S700).

Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2020-07-07 16:09:22 -04:00
Tom Rini
1e88e78177 - arch and board update for stm32mp15:
- use OPP information in device tree for 800MHz/650MHz support
   - ram: inprovments of test command
   - solve boot on closed chip when access to DBGMCU_IDC is protected
   - stm32prog command: Add "device anme" during USB enumeration
   - update configs: activate WATCHDOG and 'env erase' command,
     increase teed partition, support SD card after NOR boot by default and
     use env info in env_check
   - some sboard cleanups: gpio hog in dh board, specific driver for
     type-c stusb1600 controller code in a driver move part of code in spl.c
     and in common directory
 - fix STM32 compatible for dwc_eth_qos driver
 - support of new pinctrl ops get_dir_flags/set_dir_flags in stm32 and stmfx
   drivers
 - vrefbuf: fix a possible overshoot when re-enabling
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Merge tag 'u-boot-stm32-20200707' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm

- arch and board update for stm32mp15:
  - use OPP information in device tree for 800MHz/650MHz support
  - ram: inprovments of test command
  - solve boot on closed chip when access to DBGMCU_IDC is protected
  - stm32prog command: Add "device anme" during USB enumeration
  - update configs: activate WATCHDOG and 'env erase' command,
    increase teed partition, support SD card after NOR boot by default and
    use env info in env_check
  - some sboard cleanups: gpio hog in dh board, specific driver for
    type-c stusb1600 controller code in a driver move part of code in spl.c
    and in common directory
- fix STM32 compatible for dwc_eth_qos driver
- support of new pinctrl ops get_dir_flags/set_dir_flags in stm32 and stmfx
  drivers
- vrefbuf: fix a possible overshoot when re-enabling
2020-07-07 14:00:44 -04:00
Tom Rini
c4df37bfa9 First set of u-boot-atmel features for 2020.10 cycle
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Merge tag 'u-boot-atmel-2020.10-a' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel

First set of u-boot-atmel features for 2020.10 cycle
2020-07-07 12:55:57 -04:00
Volodymyr Babchuk
f8ddd8cbb5 arm64: issue ISB after updating system registers
ARM Architecture reference manual clearly states that PE pipeline
should be flushed after changes to some system registers. Refer to
paragraph "B2.3.5 Memory Barriers" at page B2-92 of "Arm Architecture
Reference Manual ARMv8 for ARMv8-A Architecture Profile" (ARM DDI
0487B.a).

Failing to issue instruction synchronization barrier can lead to
spurious errors, like synchronous exception when accessing FPU
registers. This is very prominent on CPUs with long instruction
pipeline, like ARM Cortex A72.

This change fixes the following U-Boot panic:

 "Synchronous Abort" handler, esr 0x1fe00000
 elr: 00000000800948cc lr : 0000000080091e04
 x0 : 00000000801ffdc8 x1 : 00000000000000c8
 x2 : 00000000800979d4 x3 : 00000000801ffc60
 x4 : 00000000801ffd40 x5 : ffffff80ffffffd8
 x6 : 00000000801ffd70 x7 : 00000000801ffd70
 x8 : 000000000000000a x9 : 0000000000000000
 x10: 0000000000000044 x11: 0000000000000000
 x12: 0000000000000000 x13: 0000000000000000
 x14: 0000000000000000 x15: 0000000000000000
 x16: 000000008008b2e0 x17: 0000000000000000
 x18: 00000000801ffec0 x19: 00000000800957b0
 x20: 00000000000000c8 x21: 00000000801ffdc8
 x22: 000000008009909e x23: 0000000000000000
 x24: 0000000000000000 x25: 0000000000000000
 x26: 0000000000000000 x27: 0000000000000000
 x28: 0000000000000000 x29: 00000000801ffc50

 Code: a94417e4 a90217e4 a9051fe6 a90617e4 (3d801fe0)

While executing instruction

 str     q0, [sp, #112]

in vsnprintf() prologue. This panic was observed only on Cortex A72 so
far.

This patch places ISBs on other strategic places as well.

Also, this probably is the right fix for the issue workarounded in the
commit 45f41c134b ("ARM: uniphier: add weird workaround code for LD20")

Reported-by: Oleksandr Andrushchenko <oleksandr_andrushchenko@epam.com>
Suggested-by: Julien Grall <julien.grall.oss@gmail.com>
Signed-off-by: Volodymyr Babchuk <volodymyr_babchuk@epam.com>
CC: Tom Rini <trini@konsulko.com>
CC: Masahiro Yamada <yamada.masahiro@socionext.com>
CC: Stefano Stabellini <sstabellini@kernel.org>
Reviewed-by: Julien Grall <julien@xen.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-07-07 11:01:52 -04:00
Patrick Delaunay
c16cba88bd stm32mp1: use the command env info in env_check
Activate CMD_NVEDIT_INFO and use the new command "env info -d -p -q"
to automatically save the environment on first boot.

This patch allows to remove the env_default variable.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-07-07 16:01:23 +02:00
Patrick Delaunay
bd3f60d29c arm: stm32mp: protect DBGMCU_IDC access with BSEC
As debugger must be totally closed on Sec closed chip,
the DBGMCU_IDC register is no more accessible (self
hosted debug is disabled with OTP).

This patch adds a function bsec_dbgswenable() to check
if the DBGMCU registers are available before to access them:
BSEC_DENABLE.DBGSWENABLE = self hosted debug status.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-07-07 16:01:23 +02:00
Patrick Delaunay
03c4e6224a arm: stm32mp: stm32prog: add "Device Name" in iproduct during DFU USB enumeration
Add "Device Name" in iproduct during DFU USB enumeration
to have this information in STM32CubeProgrammer trace
(this tools is compatible with @Name since v2.3)

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-07-07 16:01:23 +02:00
Patrick Delaunay
4a87fea6de ARM: dts: stm32mp1: use OPP information for PLL1 settings in SPL
This patch allows to switch the CPU frequency to 800MHz on the
ST Microelectronics board (DK1/DK2 and EV1) or dh electronics SOM
using the STM32MP15x SOC and when it is supported by the HW
(for STM32MP15xD and STM32MP15xF).

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-07-07 16:01:23 +02:00
Patrick Delaunay
d1a4b09de6 board: st: stpmic1: add function stpmic1_init
Add a function stmpic_init to early initialize the PMIC STPMIC1
- keep vdd on during the reset cycle (to avoid issue when backup battery
  is absent)
- Check if debug is enabled to program PMIC according to the bit

This patch allows to remove the compilation of spl.c file from stm32mp1
board in dh_stm32mp1.

CONFIG_SPL_BOARD_INIT is removed as the new function is called earlier
in SPL, in the function board_early_init_f.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-07-07 16:01:23 +02:00
Patrick Delaunay
4e62642aef arm: stm32mp: add weak function to save vddcore
Add a weak functions to save the vddcore voltage value provided
in the OPP node when the clock tree is initialized.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-07-07 16:01:23 +02:00
Patrick Delaunay
6f2e0ad194 ARM: dts: stm32: add cpufreq support on stm32mp15x
This commit adds cpufreq support on stm32mp15x SOC. STM32 cpufreq uses
operating points V2 bindings (no legacy). Nvmem cells have to be used to
know the chip version and then which OPPs are available. Note that STM32
cpufreq driver is mainly based on "cpufreq-dt" driver.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-07-07 16:01:23 +02:00
Patrick Delaunay
95bd49a5aa arm: stm32mp: spl: add bsec driver in SPL
Add the bsec driver in SPL, as it is needed by SOC part number detection
to found the supported OPP.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-07-07 16:01:23 +02:00
Jagan Teki
ad277eb458 ARM: dts: rockchip: Add Radxa Rock Pi N8 initial support
Rock Pi N8 is a Rockchip RK3288 based SBC, which has
- VMARC RK3288 SOM (as per SMARC standard) from Vamrs.
- Compatible carrier board from Radxa.

VAMRC RK3288 SOM need to mount on top of radxa dalang
carrier board for making Rock Pi N8 SBC.

So, add initial support for Rock Pi N8 by including rk3288,
rk3288 vamrc-som and raxda dalang carrier board dtsi files.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-07 19:45:57 +08:00
Jagan Teki
9e7b9d4fc0 ARM: dts: rockchip: Add VMARC RK3288 SOM initial support
VMARC RK3288 SOM is a standard SMARC SOM design with
Rockchip RK3288 SoC, which is designed by Vamrs.

Specification:
- Rockchip RK3288
- PMIC: RK808
- SD slot, 16GiB eMMC
- 2xUSB-2.0, 1xUSB3.0
- USB-C for power supply
- Ethernet, PCIe
- HDMI, MIPI-DSI/CSI, eDP

Add initial support for VMARC RK3288 SOM, this would use
with associated carrier board.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-07 19:45:57 +08:00
Jagan Teki
1a95b1e82c ARM: dts: rockchip: radxa-dalang: Update sdmmc properties
Radxa dalang carrier boards are used to mount vmarc SoM's
of rk3399pro and rk3288 to make complete SBC.

Among these combinations, card detection gpio, max-frequency
properties are used with rk3399pro SoM but not required for
rk3288 SoM based on the hardware schematics.

So, let's move these sdmmc specific properties on associate
vmarc dtsi to make common use of dalang carrier device tree file.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-07 19:45:57 +08:00
Hugh Cole-Baker
46a8606873 rockchip: rk3399: allow deselecting SPL_ATF_NO_PLATFORM_PARAM
SPL_ATF_NO_PLATFORM_PARAM is selected by default for RK3399 configs, to
guard against issues when used with TF-A versions that perform
insufficient validation on the platform parameter. However, since commit
8109f738ffa7 "rockchip: increase FDT buffer size" in TF-A, passing a
device tree as platform parameter no longer causes problems for upstream
TF-A for RK3399.

Since SPL_ATF_NO_PLATFORM_PARAM doesn't need to be selected when using
upstream TF-A, change the Kconfig option from select to imply. It'll
still default to being selected but can be deselected by a user if they
know they will be using a compatible version of TF-A.

Signed-off-by: Hugh Cole-Baker <sigmaris@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Walter Lozano <walter.lozano@collabora.com>
2020-07-07 19:45:57 +08:00
Jagan Teki
b1fccd3c0c arm64: dts: rockchip: Add Radxa Rock Pi N10 initial support
Rock Pi N10 is a Rockchip RK3399Pro based SBC, which has
- VMARC RK3399Pro SOM (as per SMARC standard) from Vamrs.
- Compatible carrier board from Radxa.

VAMRC RK3399Pro SOM need to mount on top of radxa dalang
carrier board for making Rock Pi N10 SBC.

So, add initial support for Rock Pi N10 by including rk3399,
rk3399pro vamrc-som and raxda dalang carrier board dtsi files.

rk3399pro-rock-pi-n10.dts was synced from linux-next v5.7-rc1.

Tested
- ROCK PI N10 Model B
- ROCK PI N10 Model C
- Boot from SD

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-07 19:45:57 +08:00
Jagan Teki
29dac6316a ARM: dts: rockchip: Sync v5.7-rc1 Radxa Dalang Carrier
Carrier board often referred as baseboard. For making
complete SBC or any other industrial boards, these
carrier boards will be used with associated SOMs.

Radxa has Dalang carrier board which supports on-board
peripherals, ports like USB-2.0, USB-3.0, HDMI, MIPI DSI/CSI,
eDP, Ethernet, WiFi, PCIe, USB-C, 40-Pin GPIO header and etc.

Right now Dalang carrier board is used with two SBC-variants:
Rock Pi N10 => VMARC RK3399Por SOM + Dalang carrier board
Rock Pi N8  => VMARC RK3288 SOM + Dalang carrier board(+codec)

So add this carrier board dtsi as a separate file in
ARM directory, so-that the same can reuse it in both
rk3288, rk3399pro variants of Rockchip SOMs.

Sync this dtsi from linux-next v5.7-rc1.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-07 19:45:57 +08:00
Jagan Teki
f18d2663d3 arm64: dts: rockchip: Sync v5.7-rc1 VMARC RK3399Pro SOM
VMARC RK3399Pro SOM is a standard SMARC SOM design with
Rockchip RK3399Pro SoC, which is designed by Vamrs.

Specification:
- Rockchip RK3399Pro
- PMIC: RK809-3
- SD slot, 16GiB eMMC
- 2xUSB-2.0, 1xUSB3.0
- USB-C for power supply
- Ethernet, PCIe
- HDMI, MIPI-DSI/CSI, eDP

Add initial support for VMARC RK3399Pro SOM, this would use
with associated carrier board.

Sync this dtsi from linux-next v5.7-rc1.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-07 19:45:57 +08:00
Jagan Teki
889348593b arm64: dts: rockchip: Sync v5.7-rc1 rk3399pro.dtsi
Sync linux-next v5.7-rc1 rk3399pro.dtsi.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-07 19:45:57 +08:00
Peter Robinson
f9d67436ce rockchip: Pinebook Pro: Fix SPI flash and store env on it
Some minor fixes for SPI flash on the Pinebook Pro and also
default to saving environment to the SPI flash as it's
guaranteed to be on board.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
(applied with make savedefconfig)
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-07 19:45:57 +08:00
Peter Robinson
dc38a58360 rockchip: Pinebook Pro: enable rng to provide an entropy source
Enable the rng so UEFI can provide entropy for KASLR

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-07-07 19:45:56 +08:00
Tom Rini
6e7d7aa2e2 Merge branch 'next'
Merge all outstanding changes from the current next branch in now that
we have released.
2020-07-06 15:46:38 -04:00
Tom Rini
df3d0a3f95 Merge branch '2020-07-01-kconfig-etc-updates' into next
- Resync Kconfiglib with the v14.1.0 release.
- Re-sync our <linux/compiler*h> files with v5.7-rc5 from upstream.
- Fully resync checkpatch.pl with v5.7 release.

To safely to all of the above, we have a few bugfixes about functions
that need a 'static inline' but weren't.  We also stop setting
CROSS_COMPILE in arch/*/config.mk.  Finally, with the above changes
boards can now opt-in to optimizing inlining and we do this for the
socfpga stratix10 platform for space savings.
2020-07-05 18:03:32 -04:00
Heiko Schocher
9ba84329dc sandbox, test: add test for GPIO_HOG function
currently gpio hog function is not tested with "ut dm gpio"
so add some basic tests for gpio hog functionality.

For this enable GPIO_HOG in sandbox_defconfig, add
in DTS some gpio hog entries, and add testcase in
"ut dm gpio" command.

Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-05 08:06:09 -04:00
Heinrich Schuchardt
c5a444270f riscv: use log functions in fdt_fixup
Replace printf() and debug() by log_err() and log_debug().

"No reserved memory region found in source FDT\n" is not an error but a
debug information.

%s/can not/cannot/ - use the more common spelling.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-07-03 15:09:12 +08:00
Pragnesh Patel
5ce50206ed riscv: sifive: fu540: enable all cache ways from U-Boot proper
Add L2 cache node to enable all cache ways from U-Boot proper.

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-03 15:09:06 +08:00
Atish Patra
edf4fc2baf riscv: Use optimized version of fdtdec_get_addr_size_no_parent
fdtdec_get_addr_size_no_parent is not an optimized version if parent
node is already available with the caller.

Use fdtdec_get_addr_size_auto_parent to read the "reg" property

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-07-03 15:09:00 +08:00
Atish Patra
7eb4bcc3f4 riscv: Do not return error if reserved node already exists
Not all errors are fatal. If a reserved memory node already exists in the
destination device tree, we can continue to boot without failing.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-07-03 15:09:00 +08:00
Bin Meng
fd31e4fd18 riscv: Do not build reset.c if SYSRESET is on
SYSRESET uclass driver already provides all the reset APIs, hence
exclude our own ad-hoc reset.c implementation.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Sagar Kadam <sagar.kadam@sifive.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-07-03 15:07:48 +08:00
Bin Meng
1c17e55594 riscv: Enable CONFIG_OF_BOARD_FIXUP by default for OF_SEPARATE
Starting from OpenSBI v0.7, the SBI firmware inserts/fixes up the
reserved memory node for PMP protected memory regions. All RISC-V
boards need to copy the reserved memory node from the device tree
provided by the firmware to the device tree used by U-Boot.

Turn on CONFIG_OF_BOARD_FIXUP by default for OF_SEPARATE.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2020-07-02 10:03:09 +08:00
Bin Meng
a8492e25ac riscv: Expand the DT size before copy reserved memory node
The FDT blob might not have sufficient space to hold a copy of
reserved memory node. Expand it before the copy.

Reported-by: Rick Chen <rick@andestech.com>
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2020-07-02 10:03:09 +08:00
Bin Meng
c4f7c506d9 riscv: Avoid the reserved memory fixup if src and dst point to the same place
The copy of reserved memory node from source dtb to destination dtb
can be avoided if they point to the same place. This is useful when
OF_PRIOR_STAGE is used.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-07-02 10:03:09 +08:00
Bin Meng
76585c9ecc riscv: fu540: dts: Correct reg size of otp and dmc nodes
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-07-02 10:03:03 +08:00
Bin Meng
6c6a29cde4 riscv: fu540: dts: Remove the unnecessary space in the cpu2_intc node
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
2020-07-02 10:03:03 +08:00
Tom Rini
6ca300aec0 socfpga: Mark socfpga_fpga_add() as static inline in the non-FPGA case
Unless we mark the function as 'static inline' it may end up being
non-inlined by the compiled and result in duplicate functions.

Cc: Marek Vasut <marex@denx.de>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Marek Vasut <marex@denx.de>
2020-07-01 10:11:03 -04:00
Tom Rini
897860ebc1 x86: Convert from ACCESS_ONCE to READ/WRITE_ONCE
In order to update our <linux/compiler.h> to a newer version that no
longer provides ACCESS_ONCE() but only READ_ONCE()/WRITE_ONCE() we need
to convert arch/x86/include/asm/atomic.h to the other macros.

Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-01 10:11:03 -04:00
Tom Rini
f2ff327e93 tegra: Convert from ACCESS_ONCE to READ/WRITE_ONCE
In order to update our <linux/compiler.h> to a newer version that no
longer provides ACCESS_ONCE() but only READ_ONCE()/WRITE_ONCE() we need
to convert arch/arm/mach-tegra/ivc.c to the other macros.

Cc: Tom Warren <twarren@nvidia.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
2020-07-01 10:11:03 -04:00
Tom Rini
faf002c0ab Remove CROSS_COMPILE default from arch/*/config.mk
In order to support the compiler providing information used within
Kconfig itself we cannot have the compiler be determined by
arch/*/config.mk as we will not be able to evaluate that yet.  Given
that most documentation tells people to specify CROSS_COMPILE, remove
these references.

Cc: Huan Wang <alison.wang@nxp.com>
Cc: Angelo Dureghello <angelo@sysam.it>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Rick Chen <rick@andestech.com>
Cc: Thomas Chou <thomas@wytron.com.tw>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Michal Simek <michal.simek@xilinx.com>
2020-07-01 10:11:03 -04:00
Sagar Shrikant Kadam
eb75ee4bd6 riscv: dts: hifive-unleashed-a00: add cpu aliases
Add cpu aliases to U-Boot specific dtsi for hifive-unleashed.
Without aliases we see that the CPU device sequence numbers are set
randomly and the cpu list/detail command will show it as follows:
=> cpu list
  1: cpu@1      rv64imafdc
  2: cpu@2      rv64imafdc
  3: cpu@3      rv64imafdc
  0: cpu@4      rv64imafdc

Seems like CPU probing with dm-model also relies on aliases as observed
in case spi. The fu540-c000-u-boot.dtsi has cpu nodes and so adding
corresponding aliases we can ensure that cpu devices are assigned
proper sequence as follows:

=> cpu list
  1: cpu@1      rv64imafdc
  2: cpu@2      rv64imafdc
  3: cpu@3      rv64imafdc
  4: cpu@4      rv64imafdc

Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com>
Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
2020-07-01 15:01:27 +08:00
Sean Anderson
a7c81fc853 riscv: Add Sipeed Maix support
The Sipeed Maix series is a collection of boards built around the RISC-V
Kendryte K210 processor. This processor contains several peripherals to
accelerate neural network processing and other "ai" tasks. This includes a
"KPU" neural network processor, an audio processor supporting beamforming
reception, and a digital video port supporting capture and output at VGA
resolution. Other peripherals include 8M of sram (accessible with and
without caching); remappable pins, including 40 GPIOs; AES, FFT, and SHA256
accelerators; a DMA controller; and I2C, I2S, and SPI controllers. Maix
peripherals vary, but include spi flash; on-board usb-serial bridges; ports
for cameras, displays, and sd cards; and ESP32 chips. Currently, only the
Sipeed Maix Bit V2.0 (bitm) is supported, but the boards are fairly
similar.

Documentation for Maix boards is located at
<http://dl.sipeed.com/MAIX/HDK/>.  Documentation for the Kendryte K210 is
located at <https://kendryte.com/downloads/>. However, hardware details are
rather lacking, so most technical reference has been taken from the
standalone sdk located at
<https://github.com/kendryte/kendryte-standalone-sdk>.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-07-01 15:01:22 +08:00
Sean Anderson
bba8618c8e riscv: Add device tree for K210 and Sipeed Maix BitM
Where possible, I have tried to find compatible drivers based on the layout
of registers. However, many devices remain untested. All untested devices
have been left disabled, but some tentative properties (such as compatible
strings, and clocks, interrupts, and resets properties) have been added.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
2020-07-01 15:01:22 +08:00
Sean Anderson
958a3f464c riscv: Allow use of reset drivers
Currently, one cannot use a reset driver on RISC-V. Follow the MIPS
example, and disable the default reset handler when the sysreset driver is
enabled.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-01 15:01:22 +08:00
Sean Anderson
b8bc120927 riscv: Add option to support RISC-V privileged spec 1.9
Some older processors (notably the Kendryte K210) use an older version of
the RISC-V privileged specification. The primary changes between the old
and new are in virtual memory, and in the merging of three separate counter
enable CSRs.  Using the new CSR on an old processor causes an illegal
instruction exception.  This patch adds an option to use the old CSRs
instead of the new one.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-01 15:01:22 +08:00
Sean Anderson
40686c394e riscv: Clean up IPI initialization code
The previous IPI code initialized the device whenever the first call was
made to a riscv_*_ipi function. This made it difficult to determine when
the IPI device was initialized. This patch introduces a new function
riscv_init_ipi. It is called once during arch_cpu_init_dm. In SPL, it is
called in spl_invoke_opensbi. Before this point, no riscv_*_ipi functions
should be called.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2020-07-01 15:01:22 +08:00
Sean Anderson
9472630337 riscv: Clear pending interrupts before enabling IPIs
On some platforms (k210), the previous stage bootloader may have not
cleared pending IPIs before transferring control to U-Boot. This can cause
race conditions, as multiple harts all attempt to initialize the IPI
controller at once. This patch clears IPIs before enabling them, ensuring
that only one hart modifies shared memory at once.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2020-07-01 15:01:21 +08:00
Sean Anderson
309c79f3de riscv: Add headers for asm/global_data.h
This header depended on bd_t and ulong, but did not include the appropriate
headers.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-07-01 15:01:21 +08:00
Sean Anderson
038b13ee81 reset: Add generic reset driver
This patch adds a generic reset driver. It is designed to be useful when
one has a register in a regmap which contains bits that reset other
devices. I thought this seemed like a very generic use, so here is a
generic driver. The overall structure has been modeled on the syscon-reboot
driver.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-01 15:01:21 +08:00
Sean Anderson
4a3390f1d3 dm: Add support for simple-pm-bus
This type of bus is used in Linux to designate buses which have power
domains and/or clocks which need to be enabled before their child devices
can be used. Because power domains are automatically enabled before probing
in U-Boot, we just need to enable any clocks present.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-07-01 15:01:21 +08:00
Tom Rini
e2a4d24e6b Merge branch '2020-06-30-minor-TI-board-updates' into next
- Minor updates to some platforms I am the listed maintainer of.
  Notably this removes the ti814x_evm which stopped building with the PXA
  MMC migration series (oops) but hasn't been functional in some time.
2020-06-30 15:03:25 -04:00
Tom Rini
50b5326868 ti814x: Remove platform
The TI814x (DM814x) platform is rather old and in need of a lot of
migration work.  As much of that work is well past the deadline, remove
this platform.

Signed-off-by: Tom Rini <trini@konsulko.com>
2020-06-30 15:02:45 -04:00
Tom Rini
5fdb3c0e7e - net: pcnet: cleanup and add DM support
- Makefile: add rule to build an endian-swapped U-Boot image
   used by MIPS Malta EL variants
 - CI: add Qemu tests for MIPS Malta
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Merge tag 'mips-pull-2020-06-29' of https://gitlab.denx.de/u-boot/custodians/u-boot-mips into next

- net: pcnet: cleanup and add DM support
- Makefile: add rule to build an endian-swapped U-Boot image
  used by MIPS Malta EL variants
- CI: add Qemu tests for MIPS Malta
2020-06-30 11:43:18 -04:00
Lukasz Majewski
2896422706 spi: Move DM_SPI_FLASH and SPI_FLASH_DATAFLASH to Kconfig (for ls1021aXXX)
This patch moves the CONFIG_DM_SPI_FLASH and CONFIG_SPI_FLASH_DATAFLASH
to be defined in Kconfig, not in board specific header file
(include/configs/<board>.h).

Before this change the CONFIG_DM_SPI_FLASH was not set in .config (so it
was not possible to use CONFIG_IS_ENABLED(DM_SPI_FLASH) in SPI DM/DTS
converted drivers), but it was set in u-boot.cfg file.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2020-06-29 13:34:43 -04:00
Lukasz Majewski
044a66cb83 spi: Move DM_SPI_FLASH to Kconfig (for NXP's ls1043a)
This patch fixes issue with defining the DM_SPI_FLASH in the
configs/include/<board.h> instead of enabling this option in Kconfig.

The problem is that CONFIG_IS_ENABLED(DM_SPI_FLASH) shows false as there
is no DM_SPI_FLASH=y in .config (but the define is set in u-boot.cfg).

As a result conversion of DM_SPI_FLASH to using CONFIG_IS_ENABLED() is not
working properly.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
2020-06-29 13:34:43 -04:00
Lukasz Majewski
56c4046038 spi: Convert CONFIG_DM_SPI* to CONFIG_$(SPL_TPL_)DM_SPI*
This change allows more fine tuning of driver model based SPI support in
SPL and TPL. It is now possible to explicitly enable/disable the DM_SPI
support in SPL and TPL via Kconfig option.

Before this change it was necessary to use:
    /* SPI Flash Configs */
    #if defined(CONFIG_SPL_BUILD)
    #undef CONFIG_DM_SPI
    #undef CONFIG_DM_SPI_FLASH
    #undef CONFIG_SPI_FLASH_MTD
    #endif

in the ./include/configs/<board>.h, which is error prone and shall be
avoided when we strive to switch to Kconfig.

The goal of this patch:

Provide distinction for DM_SPI support in both U-Boot proper and SPL (TPL).
Valid use case is when U-Boot proper wants to use DM_SPI, but SPL must
still support non DM driver.

Another use case is the conversion of non DM/DTS SPI driver to support
DM/DTS. When such driver needs to work in both SPL and U-Boot proper, the
distinction is needed in Kconfig (also if SPL version of the driver
supports OF_PLATDATA).

In the end of the day one would have to support following use cases (in
single driver file - e.g. mxs_spi.c):

- U-Boot proper driver supporting DT/DTS
- U-Boot proper driver without DT/DTS support (deprecated)
- SPL driver without DT/DTS support
- SPL (and TPL) driver with DT/DTS (when the SoC has enough resources to
  run full blown DT/DTS)
- SPL driver with DT/DTS and SPL_OF_PLATDATA (when one have constrained
  environment with no fitImage and OF_LIBFDT support).

Some boards do require SPI support (with DM) in SPL (TPL) and some only
have DM_SPI{_FLASH} defined to allow compiling SPL.

This patch converts #ifdef CONFIG_DM_SPI* to #if CONFIG_IS_ENABLED(DM_SPI)
and provides corresponding defines in Kconfig.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
Tested-by: Adam Ford <aford173@gmail.com> #da850-evm
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[trini: Fixup a few platforms]
Signed-off-by: Tom Rini <trini@konsulko.com>
2020-06-29 13:34:43 -04:00
Tom Rini
c87f9ce227 x86: Don't build some unused objects in TPL
In the future if we have separate symbols for DM_SPI_FLASH and
SPL_DM_SPI_FLASH we will not always have function declarations available
for some DM calls.  This in turn leads to build warnings but not
failures as the code isn't used and is discarded at link time.
Restructure things to not build code we won't use for TPL anyways.

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
2020-06-29 13:34:43 -04:00
Tom Rini
5f99ba1e24 Merge tag 'u-boot-rockchip-20200628' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- rk3188 cpu init and APLL fix;
- rk3399: Add BOOTENV_SF command;
- rk3288 correct vop0 vop1 setting;
2020-06-28 10:12:07 -04:00
Alexander Kochetkov
a2b1cff8b8 rockchip: rk3188: Fix back to BROM boot
Move the setting for noc remap out of SPL code. Changing
noc remap inside SPL results in breaking back to BROM
boot.

Fixes commit c14fe2a8e1 ("rockchip: rk3188: Move SoC
one time setting into arch_cpu_init()").

Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-06-27 22:12:34 +08:00
Tom Rini
7d80a9cd92 arm: imx: Finish migration of CONFIG_CSF_SIZE to Kconfig
While in most cases CSF_SIZE is handled via Kconfig we have some i.MX8M
platforms that set the size based on the now-renamed CONFIG_SECURE_BOOT
symbol.  Update things so that CSF_SIZE itself depends on IMX_HAB being
enabled and provide the default value for i.MX8M family of parts.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Ye Li <ye.li@nxp.com>
Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
Fixes: d714a75fd4 ("imx: replace CONFIG_SECURE_BOOT with CONFIG_IMX_HAB")
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Ye Li <ye.li@nxp.com>
2020-06-26 10:29:06 -04:00
Tom Rini
0567099bea arm: imx: Finish migration from CONFIG_SECURE_BOOT to CONFIG_IMX_HAB
There are a few remaining places where we say CONFIG_SECURE_BOOT rather
than CONFIG_IMX HAB.  Update these instances.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
Cc: Eddy Petrișor <eddy.petrisor@gmail.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Priyanka Jain <priyanka.jain@nxp.com>
Fixes: d714a75fd4 ("imx: replace CONFIG_SECURE_BOOT with CONFIG_IMX_HAB")
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2020-06-26 10:29:06 -04:00
Tom Rini
348d183e54 Convert CONFIG_AT91_GPIO to Kconfig
This converts the following to Kconfig:
   CONFIG_AT91_GPIO

Signed-off-by: Tom Rini <trini@konsulko.com>
2020-06-26 10:29:04 -04:00
Ley Foon Tan
8a204312ab arm: socfpga: misc_s10: Fix EMAC register address calculation
Fix EMAC register address calculation, address need to multiply
with sizeof(u32) or 4.

This fixes write to invalid address.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-06-26 11:30:24 +08:00
Simon Glass
c68a1ae6ab bdinfo: x86: vesa: Update fb_base to the correct value
Set this value in global_data so that it is reported correctly on x86
boards.

In fact, U-Boot allocates space for the frame buffer even though it is not
used. Then the FSP picks the address itself (e.g. 0xb0000000). So the
value set by U-Boot (high in memory with everything else that is
relocated), is not actually the correct value.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-06-25 13:24:13 -04:00
Simon Glass
64791981eb bdinfo: m68k: ppc: Move arch-specific code from bdinfo
We don't have an easy way to share these three lines of code with two
architectures. We also want to make it clear that this code is actually
arch-specific.

So just duplicate it in each arch-specific file.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-06-25 13:24:13 -04:00
Simon Glass
1a520d949b bdinfo: m68k: Move m68k-specific info into its own file
We don't really want to have m68k-specific code in a generic file. Create
a new arch-specific function to hold it, and move it into that.

Make the function weak so that any arch can implement it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Angelo Dureghello <angelo.dureghello@timesys.com>
Tested-by: Angelo Dureghello <angelo.dureghello@timesys.com>
2020-06-25 13:24:12 -04:00
Simon Glass
79d074d301 bdinfo: ppc: Move PPC-specific info into its own file
We don't really want to have PPC-specific code in a generic file. Create
a new arch-specific function to hold it, and move it into that.

Make the function weak so that any arch can implement it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-06-25 13:24:12 -04:00
Simon Glass
59b0d7d839 bdinfo: arm: Move ARM-specific info into its own file
We don't really want to have ARM-specific code in a generic file. Create
a new arch-specific function to hold it, and move it into that.

Make the function weak so that any arch can implement it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-06-25 13:24:12 -04:00
Simon Glass
b46f989bb7 bdinfo: riscv: Use generic bd_info
At present riscv still uses its own private bd_info struct. Move it over
to use the generic one like other archs.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-06-25 13:24:10 -04:00
Simon Glass
5ffd5e834e bdinfo: nds32: Use generic bd_info
At present nds32 still uses its own private bd_info struct. Move it over
to use the generic one like other archs.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-06-25 13:24:10 -04:00
Fabio Estevam
4b78b5bfda ARM: dts: imx6q-tbs2910: Fix Ethernet regression
Since commit:

commit 6333cbb381
Author: Michael Walle <michael@walle.cc>
Date:   Thu May 7 00:11:58 2020 +0200

    phy: atheros: ar8035: remove static clock config

    We can configure the clock output in the device tree. Disable the
    hardcoded one in here. This is highly board-specific and should have
    never been enabled in the PHY driver.

    If bisecting shows that this commit breaks your board it probably
    depends on the clock output of your Atheros AR8035 PHY. Please have a
    look at doc/device-tree-bindings/net/phy/atheros.txt. You need to set
    "clk-out-frequency = <125000000>" because that value was the hardcoded
    value until this commit.

    Signed-off-by: Michael Walle <michael@walle.cc>
    Acked-by: Joe Hershberger <joe.hershberger@ni.com>

, the clock output setting for the AR803x driver is removed from being
hardcoded in the PHY driver and should be passed via device tree instead.

Update the device tree with the "qca,clk-out-frequency" property so that
Ethernet can work again.

Reported-by: Soeren Moch <smoch@web.de>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Tested-by: Soeren Moch <smoch@web.de>
2020-06-25 10:39:48 -04:00
Tom Rini
f0e236c8d6 Xilinx changes for v2020.10
Versal:
 - xspi bootmode fix
 - Removing one clock from clk driver
 - Align u-boot memory setting with OS by default
 - Map TCM and OCM by default
 
 ZynqMP:
 - Minor DT improvements
 - Reduce console buffer for mini configurations
 - Add fix for AMS
 - Add support for XDP platform
 
 Zynq:
 - Support for AES engine
 - Enable bigger memory test by default
 - Extend documentation for SD preparation
 - Use different freq for Topic miami board
 
 mmc:
 - minor GD pointer removal
 
 net:
 - Support fixed-link cases by zynq gem
 - Fix phy looking loop in axi enet driver
 
 spi:
 - Cleanup global macros for xilinx spi drivers
 
 firmware:
 - Add support for pmufw reloading
 
 fpga:
 - Improve error status reporting
 
 common:
 - Remove 4kB addition space for FDT allocation
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Merge tag 'xilinx-for-v2020.10' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next

Xilinx changes for v2020.10

Versal:
- xspi bootmode fix
- Removing one clock from clk driver
- Align u-boot memory setting with OS by default
- Map TCM and OCM by default

ZynqMP:
- Minor DT improvements
- Reduce console buffer for mini configurations
- Add fix for AMS
- Add support for XDP platform

Zynq:
- Support for AES engine
- Enable bigger memory test by default
- Extend documentation for SD preparation
- Use different freq for Topic miami board

mmc:
- minor GD pointer removal

net:
- Support fixed-link cases by zynq gem
- Fix phy looking loop in axi enet driver

spi:
- Cleanup global macros for xilinx spi drivers

firmware:
- Add support for pmufw reloading

fpga:
- Improve error status reporting

common:
- Remove 4kB addition space for FDT allocation
2020-06-25 09:33:39 -04:00
Mike Looijmans
39c5cf0e70 topic: zynqmp: Add support for zynqmp-xilinx-xdp platform
XDP - Xilinx Drone Platform is a board for drones or other UAV.

Pinmux the SD card by default, and if the SD card detect line is high
(inactive) then pinmux the SD1 interface to EMIO instead. SD is placed on
extension card and shares connection with on board wife. That means that
when SD card is present in the board wifi can't be used.

There seems to be an issue with DDR access from PL at 2400MT/s, after
updating the PMU and ATF firmware this is causing extremely slow DDR
access. Reducing the DDR speed from 2400 to 2133 appears to solve that
issue, even though the hardware has proven to be 2400 capable.

Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-06-24 13:11:08 +02:00
T Karthik Reddy
7831292fc9 arm64: zynqmp: Change spi-max-frequency for qspi mini
Change mini u-boot qspi spi-max-frequency to 108Mhz, make the
frequency similar to full u-boot qspi flash spi-max-frequency.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-06-24 13:07:58 +02:00
Saeed Nowshadi
3ab205c117 arm64: zynqmp: Fix si570 clock output names and references
Align clock output names with node references.

Signed-off-by: Saeed Nowshadi <saeed.nowshadi@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-06-24 13:07:58 +02:00
Walter Lozano
24899e03a5 mx6cuboxi: enable MMC and eMMC in DT for SPL
Signed-off-by: Walter Lozano <walter.lozano@collabora.com>
2020-06-23 00:08:53 +02:00
Ye Li
59a88e0af0 arm: dts: imx: fsl-imx8qm.dtsi: fix gpio aliases
Current aliases missed gpio0 node, and this node shoud be
aliased to gpio index 0 to align with i.MX8QXP. Otherwise, we
will get below message when running "gpio status" command, and
see the reason by "dm uclass".

=> gpio status
Device 'gpio@5d090000': seq 0 is in use by 'gpio@5d080000'
Device 'gpio@5d0a0000': seq 1 is in use by 'gpio@5d090000'
Device 'gpio@5d0b0000': seq 2 is in use by 'gpio@5d0a0000'

=> dm uclass
uclass 36: gpio
0   * gpio@5d080000 @ fbaefb90, seq 0, (req -1)
1   * gpio@5d090000 @ fbaefc70, seq 1, (req 0)
2   * gpio@5d0a0000 @ fbaefd50, seq 2, (req 1)
3   * gpio@5d0b0000 @ fbaefe30, seq 5, (req 2)
4   * gpio@5d0c0000 @ fbaeff10, seq 3, (req 3)
5   * gpio@5d0d0000 @ fbaefff0, seq 4, (req 4)
6   * gpio@5d0e0000 @ fbaf00d0, seq 6, (req 5)
7   * gpio@5d0f0000 @ fbaf01b0, seq 7, (req 6)

Signed-off-by: Ye Li <ye.li@nxp.com>
2020-06-23 00:08:53 +02:00
Marek Vasut
a1f6d04aa1 ARM: imx: soc: Select default TEXT_BASE for MX7
Select default U-Boot and SPL text base for the MX7 SoC. The U-Boot
text base is picked as the one used by various MX7 boards. The SPL
text base however is different.

The SPL text base is set to 0x912000 instead of the usual 0x911000,
that is because the 0x911000 value cannot work. Using 0x911000 as a
SPL text base will result in the DCD header being placed below the
0x911000 address, which is a reserved SRAM area which must not be
used. This will actually trigger eMMC boot failure on MX7D at least.
Hence the increment.

Update all boards affected by this SPL problem to the new SPL_TEXT_BASE.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2020-06-22 17:44:20 +02:00
Marek Vasut
7204160315 ARM: imx: soc: Switch BOARD_EARLY_INIT_F to imply on MX7
There are systems where board_early_init_f() is plain empty. Switch
the config option from "select" to "imply", to permit user to unset
the BOARD_EARLY_INIT_F if it were to be empty.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2020-06-22 17:44:13 +02:00
Marek Vasut
cb82ee25f7 ARM: imx: ddr: Fill in missing DDRC ZQCTLx on i.MX7
The iMX7 defines further DDRC ZQCTLx registers, however those were
thus far missing from the list of registers and not programmed. On
systems with LPDDR2 or DDR3, those registers must be programmed with
correct values, otherwise the DRAM may not work. However, existing
systems which worked without programming these registers before are
now setting those registers to 0, which is the default value, so no
functional change there.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2020-06-22 17:44:06 +02:00
Fabio Estevam
041dd8e9c4 ARM: dts: imx6qdl-sabresd: Fix AR8031 phy-mode
As per kernel commit 0672d22a1924 ("ARM: dts: imx: Fix the AR803X phy-mode)
the correct phy-mode should be "rgmii-id", so fix it accordingly
to fix the Ethernet regression.

This problem has been exposed by commit:

commit 13114f38e2
Author: Vladimir Oltean <vladimir.oltean@nxp.com>
Date:   Thu May 7 00:11:51 2020 +0200

    phy: atheros: Explicitly disable RGMII delays

    To eliminate any doubts about the out-of-reset value of the PHY, that
    the driver previously relied on.

    If bisecting shows that this commit breaks your board you probably have
    a wrong PHY interface mode. You probably want the
    PHY_INTERFACE_MODE_RGMII_RXID or PHY_INTERFACE_MODE_RGMII_ID mode.

    Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
    Acked-by: Joe Hershberger <joe.hershberger@ni.com>

Signed-off-by: Fabio Estevam <festevam@gmail.com>
2020-06-22 17:41:25 +02:00
Fabio Estevam
64e2793f70 ARM: dts: imx6qdl-sabreauto: Fix AR8031 phy-mode
As per kernel commit 0672d22a1924 ("ARM: dts: imx: Fix the AR803X phy-mode)
the correct phy-mode should be "rgmii-id", so fix it accordingly
to fix the Ethernet regression.

This problem has been exposed by commit:

commit 13114f38e2
Author: Vladimir Oltean <vladimir.oltean@nxp.com>
Date:   Thu May 7 00:11:51 2020 +0200

    phy: atheros: Explicitly disable RGMII delays

    To eliminate any doubts about the out-of-reset value of the PHY, that
    the driver previously relied on.

    If bisecting shows that this commit breaks your board you probably have
    a wrong PHY interface mode. You probably want the
    PHY_INTERFACE_MODE_RGMII_RXID or PHY_INTERFACE_MODE_RGMII_ID mode.

    Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
    Acked-by: Joe Hershberger <joe.hershberger@ni.com>

Fix the phy-mode accordingly to fix the regression.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
2020-06-22 17:41:13 +02:00
Fabio Estevam
db86e6c66a ARM: dts: imx6qdl-sr-som: Sync with kernel 5.8-rc1
Sync the device tree with 5.8-rc1.

It basically contains the following extra kernel commit:

commit 86b08bd5b99480b79a25343f24c1b8c4ddcb5c09
Author: Russell King <rmk+kernel@armlinux.org.uk>
Date:   Wed Apr 15 16:44:17 2020 +0100

    ARM: dts: imx6-sr-som: add ethernet PHY configuration

    Add ethernet PHY configuration ahead of removing the quirk that
    configures the clocking mode for the PHY.  The RGMII delay is
    already set correctly.

    Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
    Reviewed-by: Fabio Estevam <festevam@gmail.com>
    Signed-off-by: Shawn Guo <shawnguo@kernel.org>

, which passes the 'qca,clk-out-frequency' property and it is important
to specify the correct frequency generated by the AR8035.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Tested-by: Tom Rini <trini@konsulko.com>
2020-06-22 17:40:56 +02:00
Tom Rini
5575f79bda Merge https://gitlab.denx.de/u-boot/custodians/u-boot-spi into next
- Convert fsl_espi to driver model (Chuanhua)
- Enable am335x baltos to DM_SPI (Jagan)
- Drop few powerpc board which doesn't have DM enabled (Jagan)
2020-06-19 16:25:50 -04:00
Tom Rini
1e389a434a - fix SD card cart detect on DHCOM and ST boards
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Merge tag 'u-boot-stm32-20200619' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm

- fix SD card cart detect on DHCOM and ST boards
2020-06-19 12:41:24 -04:00
Patrick Delaunay
792919241b ARM: dts: stm32: Reinstate card detect behavior on ST boards
The cd-gpios with (GPIO_ACTIVE_LOW | GPIO_PULL_UP) gpio is thus far
unsupported, reinstate the old cd-gpios behavior until this handling
is fully implemented. This avoid potential issue for SDCard boot:
the card detect fails with floating gpio.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-06-19 14:18:36 +02:00
Marek Vasut
3c2e2a1a79 ARM: dts: stm32: Reinstate card detect behavior on DHSOM
The cd-gpios with (GPIO_ACTIVE_LOW | GPIO_PULL_UP) gpio is thus far
unsupported, reinstate the old cd-gpios behavior until this handling
is fully implemented. This permits the DHSOM to boot from SD again,
without this patch the card detect fails.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-06-19 09:43:59 +02:00
Tom Rini
04909251fd - migrate remaining imx5/imx6qd boards to DM_VIDEO
- use 'vidconsole' stdout in nitrogen6x upgrade script
 - add option for selection of the vidconsole commands
   lcdputs and setcurs
 - allow building ipuv3 driver with disabled CONFIG_PANEL
 - make backlight and panel drivers optional
 - remove useless code from ipuv3 driver
 - extend existing DM_VIDEO work-around for console name
   to support 'vga'
 - remove non-DM code in ipuv3
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Merge tag 'video-next' of https://gitlab.denx.de/u-boot/custodians/u-boot-video into next

- migrate remaining imx5/imx6qd boards to DM_VIDEO
- use 'vidconsole' stdout in nitrogen6x upgrade script
- add option for selection of the vidconsole commands
  lcdputs and setcurs
- allow building ipuv3 driver with disabled CONFIG_PANEL
- make backlight and panel drivers optional
- remove useless code from ipuv3 driver
- extend existing DM_VIDEO work-around for console name
  to support 'vga'
- remove non-DM code in ipuv3
2020-06-18 16:59:16 -04:00
Jon Hunter
1ec7453384 ARM: tegra: Enable PSCI support for Tegra210 and Tegra186
The PSCI nodes are currently not populated for the Tegra210 and Tegra186
devices. This prevents the PSCI driver from being able to identify the
PSCI method used by these devices and causes the probe of the PSCI
driver to fail.

Since commit 81ea00838c ("efi_loader: PSCI reset and shutdown") was
added, which moves the PSCI EFI system reset handler into the PSCI
driver, this has prevented the EFI system reset from working for
Tegra210 and Tegra186. Therefore, populating these nodes is necessary
to fix the EFI system reset for Tegra210 and Tegra186.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
2020-06-18 13:14:50 -07:00
Anatolij Gustschin
22b897a123 video: extend stdout video console work-around for 'vga'
cfb_console driver uses 'vga' console name and we still have board
environments defining this name. Re-use existing DM_VIDEO work-
around for console name to support 'vga' name in stdout environment.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
Tested-by: Soeren Moch <smoch@web.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
2020-06-18 19:30:14 +02:00
Jagan Teki
47df4b5f2a powerpc: Remove TWR-P1025_defconfig board
DM_SPI and other driver model migration deadlines
are expired for this board.

Remove it.

Patch-cc: Xiaobo Xie <xiaobo.xie@nxp.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-06-18 21:47:08 +05:30
Jagan Teki
5d226cd013 powerpc: Remove T4160QDS_NAND_defconfig board
DM_SPI and other driver model migration deadlines
are expired for this board.

Remove it.

Patch-cc: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-06-18 21:47:08 +05:30
Jagan Teki
ce17d99d12 powerpc: Remove T1040QDS_DDR4_defconfig board
DM_SPI and other driver model migration deadlines
are expired for this board.

Remove it.

Patch-cc: Poonam Aggrwal <poonam.aggrwal@nxp.com>
Patch-cc: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-06-18 21:47:08 +05:30
Jagan Teki
7723a6deb7 powerpc: Remove T1024QDS_DDR4_SECURE_BOOT_defconfig board
DM_SPI and other driver model migration deadlines
are expired for this board.

Remove it.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-18 21:47:08 +05:30
Jagan Teki
197fc64578 powerpc: Remove P1022DS_36BIT_NAND_defconfig board
DM_SPI and other driver model migration deadlines
are expired for this board.

Remove it.

Patch-cc: Timur Tabi <timur@tabi.org>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-06-18 21:47:08 +05:30
Jagan Teki
8429b95167 powerpc: Remove configs/MPC8536DS_36BIT_defconfig board
DM_SPI and other driver model migration deadlines
are expired for this board.

Remove it.

Patch-cc: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-06-18 21:47:08 +05:30
Jagan Teki
447ec175b2 powerpc: Remove configs/C29XPCIE_NAND_defconfig board
DM_SPI and other driver model migration deadlines
are expired for this board.

Remove it.

Patch-cc: Po Liu <po.liu@nxp.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-06-18 21:47:08 +05:30
Jagan Teki
55bcea4fb4 powerpc: Remove configs/BSC9132QDS_NAND_DDRCLK100_SECURE_defconfig board
DM_SPI and other driver model migration deadlines
are expired for this board.

Remove it.

Patch-cc: Naveen Burmi <naveen.burmi@nxp.com>
Patch-cc: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-06-18 21:47:08 +05:30
Jagan Teki
f178468b5e powerpc: Remove configs/BSC9131RDB_NAND_SYSCLK100_defconfig board
DM_SPI and other driver model migration deadlines
are expired for this board.

Remove it.

Patch-cc: Poonam Aggrwal <poonam.aggrwal@nxp.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-06-18 21:47:08 +05:30
Jagan Teki
e3e6782d47 powerpc: Remove configs/B4420QDS_NAND_defconfig board
DM_SPI and other driver model migration deadlines
are expired for this board.

Remove it.

Patch-cc: Ashish Kumar <ashish.kumar@nxp.com>
Patch-cc: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-06-18 21:47:08 +05:30
Tom Rini
83fdb43882 Merge tag 'ti-v2020.10-next' of https://gitlab.denx.de/u-boot/custodians/u-boot-ti into next
- DM conversion for OMAP4, OMAP5 platforms.
- Other minor fixes for Nokia RX51, am33, am57, am654.
2020-06-18 10:07:49 -04:00
Gregory CLEMENT
c7c120c22b ARM: at91: Enable SPL_SEPARATE_BSS by default
According to the linker script for both armv7 and arm926ejs based SoC,
BSS section was all the time separated for SPL but this symbol was
only enabled on some boards. However, it is necessary to have it
enabled for OF_SEPARATE configuration where DTB is appended to u-boot
with DTB.

Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
2020-06-18 14:28:37 +03:00
Eugen Hristev
c260cb2c8c ARM: dts: sama5d3: fix gadget endpoint address warning
arch/arm/dts/sama5d36ek.dtb: Warning (graph_endpoint): /ahb/gadget@00500000/endpoint@10: graph node unit address error, expected "a"
arch/arm/dts/sama5d36ek.dtb: Warning (graph_endpoint): /ahb/gadget@00500000/endpoint@11: graph node unit address error, expected "b"
arch/arm/dts/sama5d36ek.dtb: Warning (graph_endpoint): /ahb/gadget@00500000/endpoint@12: graph node unit address error, expected "c"
arch/arm/dts/sama5d36ek.dtb: Warning (graph_endpoint): /ahb/gadget@00500000/endpoint@13: graph node unit address error, expected "d"
arch/arm/dts/sama5d36ek.dtb: Warning (graph_endpoint): /ahb/gadget@00500000/endpoint@14: graph node unit address error, expected "e"
arch/arm/dts/sama5d36ek.dtb: Warning (graph_endpoint): /ahb/gadget@00500000/endpoint@15: graph node unit address error, expected "f"

Fixed by changing address in node name to hex.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2020-06-18 14:28:37 +03:00
Eugen Hristev
4675b519c9 ARM: dts: sama5d4: fix gadget endpoint address warning
arch/arm/dts/at91-sama5d4ek.dtb: Warning (graph_endpoint): /ahb/gadget@00400000/endpoint@10: graph node unit address error, expected "a"
arch/arm/dts/at91-sama5d4ek.dtb: Warning (graph_endpoint): /ahb/gadget@00400000/endpoint@11: graph node unit address error, expected "b"
arch/arm/dts/at91-sama5d4ek.dtb: Warning (graph_endpoint): /ahb/gadget@00400000/endpoint@12: graph node unit address error, expected "c"
arch/arm/dts/at91-sama5d4ek.dtb: Warning (graph_endpoint): /ahb/gadget@00400000/endpoint@13: graph node unit address error, expected "d"
arch/arm/dts/at91-sama5d4ek.dtb: Warning (graph_endpoint): /ahb/gadget@00400000/endpoint@14: graph node unit address error, expected "e"
arch/arm/dts/at91-sama5d4ek.dtb: Warning (graph_endpoint): /ahb/gadget@00400000/endpoint@15: graph node unit address error, expected "f"

Fixed by changing address in node name to hex.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
2020-06-18 14:28:37 +03:00
Tero Kristo
803e9a1f28 omap5: uevm: convert to device model
Convert omap5 uevm board to device model.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
2020-06-16 17:00:12 +05:30
Tero Kristo
8f1ed2e4ed omap5: Copy device tree from linux 5.7.y
Copy all the device tree files required for omap5 uevm support from
mainline Linux.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
2020-06-16 17:00:12 +05:30
Peter Ujfalusi
8812ed9725 omap4: sdp: convert to device model
Convert omap4 sdp to device model.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2020-06-16 17:00:12 +05:30
Peter Ujfalusi
e58b697e36 omap4: Copy device tree from Linux 5.7.y for SDP4430
Copy all device tree files required for omap4 sdp4430 support from
mainline Linux.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2020-06-16 17:00:12 +05:30
Tero Kristo
0a45375115 omap4: panda: convert to device model
Convert omap4 panda to device model.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
2020-06-16 17:00:12 +05:30
Tero Kristo
00fde6b873 omap4: Copy device tree from Linux 5.7.y
Copy all device tree files required for omap4 panda support from
mainline Linux.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
2020-06-16 17:00:12 +05:30
Etienne Carriere
9e69696506 dts: ARM: stm32mp15: add OP-TEE node in u-boot DTSI
Add OP-TEE firmware node in stm32mp15 U-Boot DTSI. This node is
needed since commit [1] that changed U-Boot/stm32mp15 to detect
OP-TEE availability by probing the resource instead of relying on
U-Boot configuration. The software sequence implemented by [1] is
fine but U-Boot DTS/DTSI files were not updated accordingly since,
hence OP-TEE presence is never detected by U-Boot, preventing Linux
kernel from using OP-TEE resources.

For consistency and to synchronize stm32mp15 DTSI files (excluding
U-Boot specific DTSI files) with the Linux kernel ones, this change
also moves the OP-TEE reserved memory nodes from board generic DTSI
files to U-Boot specific board DTSI files.

Link: [1] commit 43df0a159d ("stm32mp1: dynamically detect op-tee presence")
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-06-16 10:39:28 +02:00
Etienne Carriere
164873a0c0 board: stm32mp1: fix handling of DT OP-TEE reserved memory nodes
Fix the sequence in stm32mp1 fdt.c that disables OP-TEE resources
defined in FDT when U-boot detects OP-TEE firmware is not present.

Before this change, helper function stm32_fdt_disable_optee()
set property status to "disabled" for the OP-TEE reserved memory
nodes but this has no impact since Linux kernel does not consider
the status property for reserved-memory subnodes. This change
make U-Boot to attempt to delete the node instead.

Fixes: 4a1b975dac ("board: stm32mp1: reserve memory for OP-TEE in device tree")
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-06-16 10:38:09 +02:00
Tom Rini
bb1ff1371e Merge tag 'mmc-2020-6-15' of https://gitlab.denx.de/u-boot/custodians/u-boot-mmc
- fsl_esdhc sdr104 and hs200 fix and error path fix
- fsl_esdhc workaround 3.3v io issue
- ca_dw_mmc cleanup
- presidio-asic emmc DT update.
2020-06-15 10:20:35 -04:00
Alex Nemirovsky
1ac6447644 board: presidio-asic: update eMMC DT information
Change DT compatibility name to match change in driver's name.
Remove unused io_ds and fifo_mode fields from DT.

Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com>
CC: Peng Fan <peng.fan@nxp.com>
CC: Jaehoon Chung <jh80.chung@samsung.com>
CC: Tom Rini <trini@konsulko.com>
2020-06-15 09:45:22 +08:00
Tom Rini
18d8977bdf Merge https://gitlab.denx.de/u-boot/custodians/u-boot-socfpga
- cyclone5 bugfix
2020-06-14 12:00:50 -04:00
Ley Foon Tan
a0bda1dd83 arm: dts: socfpga: cyclone5: Update i2c-scl-falling-time-ns
Commit e71b6f6622 ("i2c: designware_i2c: Rewrite timing calculation")
change the hcnt and lcnt timing calculation. New timing calculation is
based on calculation from Designware i2c databook.

After this new timing calculation, hcnt will have negative value
with i2c-scl-falling-time-ns 5000 that set in socfpga_cyclone5_socdk.dts.

This patch overwrite i2c-scl-falling-time-ns to 300ns (default SCL fall
time used in Designware i2c driver) for Uboot.

Before the fix:
=> i2c dev 0
Setting bus to 0
Failure changing bus number (-22)

After the fix:
=> i2c dev 0
Setting bus to 0
=> i2c probe
Valid chip addresses: 17 51 55 5B 5C 5E 66 68 70

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-06-14 13:37:31 +02:00
Faiz Abbas
c78ae11e07 mmc: davinci_mmc: Cleanup to use dt in U-boot and static platdata in SPL
Cleanup this driver to use dt in U-boot and static platdata in SPL.
This requires the following steps:

1. Move all platdata assignment from probe() to ofdata_to_platdata().
   This function is only called in U-boot.
2. Replicate all the platdata assignment being done in
   ofdata_to_platdata() in the omapl138 board file. This data is used in
   the SPL case where SPL_OF_CONTROL is not enabled.
3. Remove SPL_OF_CONTROL and related configs from omapl138_lcdk_defconfig

This cleanup effectively reverts 3ef94715cc ('mmc: davinci: fix mmc boot in SPL')

Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Tested-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
2020-06-13 23:12:17 +05:30
Michael Walle
be1a6e9425 dm: uclass: don't assign aliased seq numbers
If there are aliases for an uclass, set the base for the "dynamically"
allocated numbers next to the highest alias.

Please note, that this might lead to holes in the sequences, depending
on the device tree. For example if there is only an alias "ethernet1",
the next device seq number would be 2.

In particular this fixes a problem with boards which are using ethernet
aliases but also might have network add-in cards like the E1000. If the
board is started with the add-in card and depending on the order of the
drivers, the E1000 might occupy the first ethernet device and mess up
all the hardware addresses, because the devices are now shifted by one.

Also adapt the test cases to the new handling and add test cases
checking the holes in the seq numbers.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Alex Marginean <alexandru.marginean@nxp.com>
Tested-by: Alex Marginean <alexandru.marginean@nxp.com>
Acked-by: Vladimir Oltean <olteanv@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Michal Simek <michal.simek@xilinx.com> [on zcu102-revA]
2020-06-11 20:52:11 -06:00
Michael Walle
c03b7612ea usb: provide a device tree node to USB devices
It is possible to specify a device tree node for an USB device. This is
useful if you have a static USB setup and want to use aliases which
point to these nodes, like on the Raspberry Pi.
The nodes are matched against their hub port number, the compatible
strings are not matched for now.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-06-11 20:52:11 -06:00
Jagan Teki
64efd11d3b arm: Remove pcm051 board
OF_CONTROL, DM_SPI and other driver model migration deadlines
are expired for this board.

Remove it.

Acked-by: Lars Poeschel <poeschel@lemonage.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-11 15:14:04 +05:30
Jagan Teki
a9c84ffa99 arm: Remove omap3_pandora_defconfig board
OF_CONTROL, DM_SPI and other driver model migration deadlines
are expired for this board.

Remove it.

Acked-by: Grazvydas Ignotas <notasas@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-11 15:14:04 +05:30
Tom Rini
be79009f3b Fixes for 2020.07
-----------------
 
 - mx53: mx53menlo Convert to DM_ETH, fix fail boot
 - imx8mp_evk: fix boot issue
 - MX6, display5: fix environment
 - drop warnings (watchdog) for i.MX8mm i.mx8mp
 - enable bootaux for i.MX8M
 
 Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/695929999
 -----BEGIN PGP SIGNATURE-----
 
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 bnguZGUACgkQ9PVl5Jpo76aLCQCeK7NCaFMWpTtGSwYVDnl5PVCodqkAn2XuBkdu
 NCxgw1UqknHk3GaY0s9u
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Merge tag 'u-boot-imx-20200609' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

Fixes for 2020.07
-----------------

- mx53: mx53menlo Convert to DM_ETH, fix fail boot
- imx8mp_evk: fix boot issue
- MX6, display5: fix environment
- drop warnings (watchdog) for i.MX8mm i.mx8mp
- enable bootaux for i.MX8M

Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/695929999
2020-06-09 09:17:24 -04:00
Stefano Babic
3854296801 Revert "imx: rom api: fix image offset computation"
This reverts commit 1f63ee6566.

As reported by Ye Li on ML:

1. Removing the image_offset will break secondary (redundant) boot support for sd and emmc.
2. When booting from emmc boot partition, the image_offset is 0. But the flash.bin
generated by mkimage with imximage-8mp-lpddr4.cfg is for sd. It expects to be burn at 32KB offset.
The fit offset 0x60000 has already included the 32KB offset.  So when you burn this flash.bin
to emmc boot partition at offset 0, the fit offset should subtract the 32KB (0x60000 - 0x8000).

Signed-off-by: Stefano Babic <sbabic@denx.de>
2020-06-09 11:19:55 +02:00
Tom Rini
08649c3d50 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx
- DM_ETH support for P2041RDB, T1024RDB, P5040DS, P3041DS, P4080DS, bug
  fixes
- Add TBI PHY access through MII
- DDR: Rework errata workaround for A008109, A008378, 009942
2020-06-08 08:51:59 -04:00
Marek Vasut
a13644c065 ARM: dts: imx: m53menlo: Convert to DM_ETH
Convert the board to DM_ETH instead of legacy networking. This requires
a minor addition to the DT to satisfy the requirement for specifying a
PHY node. No functional change from board user perspective.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2020-06-08 10:43:02 +02:00
Marek Vasut
0e06d63d19 ARM: imx: ddr: Add missing PHY reset
The iMX7D RM 9.2.4.9.3 Power removal flow Table 9-11. Re-enabling power
explicitly says both the DDR controller and the PHY must be reset in the
correct sequence. Currently the code only resets the controller. This
leads to a misbehavior where the system brings the DRAM up after reboot,
but the DRAM is unstable. Add the missing reset.

The easiest way to trigger this is by triggering WDT without having the
WDT assert WDOG_B signal, i.e. mw.w 0x30280000 0x25 .

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2020-06-08 10:42:54 +02:00
Sébastien Szymanski
1f63ee6566 imx: rom api: fix image offset computation
When not booting from FlexSPI, the offset computation is:

offset = image_offset + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512 - 0x8000;

When booting from SD card or eMMC user partition, image_offset is
0x8000. It is useless to add and remove 0x8000.
When booting from other device, image_offset is 0 so this computation is wrong.

Simplfy this computation to work on all booting devices.

Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
2020-06-08 10:42:14 +02:00
Patrick Wildt
0e9c045b2b imx: move ATF to the back of the FIT to fix loading over yModem
With yModem the FIT Image is only supplied once, so we can only
seek forward in the yModem supplied image and never backwards.
With the recent changes to the SPL mechanism, including loading
U-Boot first, FDT after, then the loadables, we must also reorder
the FIT image script to make sure that the loadables are last in
the FIT image.

Signed-off-by: Patrick Wildt <patrick@blueri.se>
Tested-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
2020-06-08 10:41:38 +02:00
Peng Fan
f3e1c536a9 imx: Kconfig: enable IMX_BOOTAUX for i.MX8M
i.MX8M could use imx bootaux to boot m4/m7 core, so let's add it
to the dependency list.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-06-08 10:39:24 +02:00
Giulio Benetti
8fde50f702 ARM: dts: imxrt1050: indent lcdif node correctly
Accidentally submitted a patch with indentation not correct, let's fix it
by indenting wrong lines.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
2020-06-08 10:39:07 +02:00
Heiko Stuebner
97fa784725 rockchip: puma: reorganize devicetrees to actually work and match upstream
So far the puma dts files only just included the main puma dtsi without
handling the actual baseboard and rk3399-puma.dtsi was very much
detached from the variant in the mainline Linux kernel.

Recent changes resulted in a strange situation with nonworking puma boards.

Commit ab800e5a6f ("arm: dts: rockchip: puma: move U-Boot specific bits to u-boot.dtsi")
moved the sdram include from rk3399-puma-ddrX.dts to new files
rk3399-puma-ddrx-u-boot.dtsi which were never included anywhere though.

Commit 167efc2c7a ("arm64: dts: rk3399: Sync v5.7-rc1 from Linux")
replaced the rk3399-puma.dtsi nearly completely, but in the kernel
it definitly depends on a baseboard dts to actually enable peripherals
like sd-slot, uarts, etc.

So to untagle this and bring the whole thing more in line with mainline
Linux, bring the rk3399-puma-haikou.dts over as well, drop the separate
DDR-option devicetrees and instead replace them with a puma Kconfig option
to select and include the needed DDR variant.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-06-07 18:57:16 +08:00
Heiko Stuebner
efcb2bd9cb rockchip: puma: fix indentation for -u-boot.dtsi
Tabs not spaces, so transform it to the common styling.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-06-07 18:57:16 +08:00
Heiko Stuebner
e2dd607bce arm64: dts: rk3399-puma: fix gpio levels for vcc5v0-host regulator
The regulator enable-gpio uses opposite values for the declaration
vs. the enable_active_low property, breaking the regulator enablement.

Make the usbhost-supply work again by bringing them in sync again.

This mimics the upstream Linux change found on:
http://lore.kernel.org/r/20200604091239.424318-1-heiko@sntech.de

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
2020-06-07 18:57:16 +08:00
Heiko Stuebner
41c985d5fb arm64: dts: rk3399-puma: fix gpio levels for gmac reset pin
The gmac reset has opposite values for the gpio declaration
and the separate reset-active, bring this in line to make
u-boot also find the ethernet-phy.

This mimics the upstream Linux commit found on
https://lore.kernel.org/r/20200603132836.362519-1-heiko@sntech.de

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-06-07 18:57:16 +08:00
Marcin Juszkiewicz
b587acc6b1 rockchip: rockpro64: add SPI boot
U-Boot TPL 2020.07-rc3-00121-gab88251130 (Jun 03 2020 - 16:43:42)
Channel 0: LPDDR4, 50MHz
BW=32 Col=10 Bk=8 CS0 Row=16/15 CS=1 Die BW=16 Size=2048MB
Channel 1: LPDDR4, 50MHz
BW=32 Col=10 Bk=8 CS0 Row=16/15 CS=1 Die BW=16 Size=2048MB
256B stride
256B stride
lpddr4_set_rate: change freq to 400000000 mhz 0, 1
lpddr4_set_rate: change freq to 800000000 mhz 1, 0
Trying to boot from BOOTROM
Returning to boot ROM...

U-Boot SPL 2020.07-rc3-00121-gab88251130 (Jun 03 2020 - 16:43:42 +0200)
Trying to boot from SPI

U-Boot 2020.07-rc3-00121-gab88251130 (Jun 03 2020 - 16:43:42 +0200)

SoC: Rockchip rk3399
Reset cause: RST
Model: Pine64 RockPro64 v2.1
DRAM:  3.9 GiB
PMIC:  RK808
MMC:   mmc@fe310000: 2, mmc@fe320000: 1, sdhci@fe330000: 0
Loading Environment from SPI Flash... SF: Detected gd25q128 with page size 256 Bytes, erase size 4 KiB, total 16 MiB
*** Warning - bad CRC, using default environment

In:    serial
Out:   vidconsole
Err:   vidconsole
Model: Pine64 RockPro64 v2.1
Net:   eth0: ethernet@fe300000
Hit any key to stop autoboot:  0
=>

Signed-off-by: Marcin Juszkiewicz <marcin@juszkiewicz.com.pl>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-06-07 18:57:16 +08:00
Jagan Teki
1831191b18 roc-rk3399-pc: Add SPI boot
U-Boot TPL 2020.07-rc3-00090-gd4e919f927-dirty (Jun 01 2020 - 23:45:53)
Channel 0: LPDDR4, 50MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
Channel 1: LPDDR4, 50MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
256B stride
256B stride
lpddr4_set_rate: change freq to 400000000 mhz 0, 1
lpddr4_set_rate: change freq to 800000000 mhz 1, 0
Trying to boot from BOOTROM
Returning to boot ROM...

U-Boot SPL 2020.07-rc3-00087-ga21e9fd385 (Jun 02 2020 - 00:09:45 +0530)
Trying to boot from MMC1
NOTICE:  BL31: v2.2(release):
NOTICE:  BL31: Built : 15:05:37, May 12 2020

U-Boot 2020.07-rc3-00087-ga21e9fd385 (Jun 02 2020 - 00:09:45 +0530)

SoC: Rockchip rk3399
Reset cause: POR
Model: Firefly ROC-RK3399-PC Board
DRAM:  3.9 GiB
PMIC:  RK808
MMC:   mmc@fe320000: 1, sdhci@fe330000: 0
Loading Environment from SPI Flash... SF: Detected w25q128 with page size 256 Bytes, erase size 4 KiB, total 16 MiB
*** Warning - bad CRC, using default environment

In:    serial
Out:   serial
Err:   serial
Model: Firefly ROC-RK3399-PC Board

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-06-07 18:57:16 +08:00
Kever Yang
3d82b1b3d3 rockchip: rk3399-evb: add stdout-path for the board
The 'stdout-path' is missing after dts sync.
Fixes: 167efc2c7a ("arm64: dts: rk3399: Sync v5.7-rc1 from Linux")

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2020-06-07 18:57:16 +08:00
b.l.huang
5764911e67 rockchip: rk3328: add rock-pi-e dts file
The ROCK-PI-E is a credit card size SBC based on Rockchip RK3328
Quad-Core ARM Cortex A53.

    Net - Dual ethernet port, 1 X Gbe, 1 X 100M
    USB - USB 3.0
    DC  - USB-Type C, 5V 2A
    Storage - TF card, eMMC

Just build idbloader.img and u-boot.itb for Rockpi E board and
follow the blow steps to replace the relevant partition.

    dd if=idbloader.img of=/dev/sdcard seek=64 conv=notrunc
    dd if=u-boot.itb of=/dev/sdcard seek=16384 conv=notrunc

Signed-off-by: Banglang Huang <banglang.huang@foxmail.com>
2020-06-07 18:57:16 +08:00
Tom Rini
07d90d8bd4 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscv
- Fixes 7e249bc13a: ("riscv: Move all SMP related SBI calls to
  SBI_v01") Move sbi_probe_extension() out of CONFIG_SBI_V01.
- SiFive FU540 support SPL.
2020-06-04 13:50:39 -04:00
Tom Rini
c27178ba36 First set of u-boot-atmel fixes for 2020.07 cycle
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Merge tag 'u-boot-atmel-fixes-2020.07-a' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel

First set of u-boot-atmel fixes for 2020.07 cycle

This set includes just two small commits that fix a build warning and
add a missing serial node.
2020-06-04 10:21:51 -04:00
Jaiprakash Singh
164a5af436 ddr: Rework errata A008109, A008378, 009942 workaround
Move errata A008109, A008378, 009942 workaround implementation from
compute_fsl_memctl_config_regs() to  fsl_ddr_set_memctl_regs()
and add register write after each workaround implementation.

Signed-off-by: Jaiprakash Singh <Jaiprakash.singh@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-06-04 18:53:20 +05:30
Joakim Tjernlund
73af094c84 ddr: fsl: Impl. Erratum A008109
Impl. erratum as descibed in errata doc.
Enable A008109 for T1040 and T1024

Signed-off-by: Joakim Tjernlund <joakim.tjernlund@infinera.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-06-04 18:53:20 +05:30
Madalin Bucur
ffe706d9b8 powerpc: dts: add QorIQ DPAA 1 FMan v3 to T1024RDB
Introduce the QorIQ DPAA 1 Frame Manager nodes in the T1024RDB
device tree. The device tree fragments are copied over with little
modification from the Linux kernel source code.

Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-06-04 18:53:20 +05:30
Madalin Bucur
cdc76f80ac powerpc: dts: add QorIQ DPAA 1 FMan v3 for T102x
Add the QorIQ DPAA 1 Frame Manager v3 device tree nodes for the
T102x SoCs. The device tree fragments are copied over with little
modification from the Linux kernel source code.

Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-06-04 18:53:20 +05:30
Madalin Bucur
28d1d5ec81 powerpc: dts: add QorIQ DPAA 1 FMan to P5040DS
Introduce the QorIQ DPAA 1 Frame Manager nodes in the P5040DS
device tree. The device tree fragments are copied over with little
modification from the Linux kernel source code.

Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-06-04 18:53:20 +05:30
Madalin Bucur
a1ecc56bbf powerpc: dts: add QorIQ DPAA 1 FMan for P5040
The device tree fragments are copied over with little
modification from the Linux kernel source code.

Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-06-04 18:53:20 +05:30
Madalin Bucur
fb1b2e161e powerpc: dts: add QorIQ DPAA 1 FMan to P3041DS
Introduce the QorIQ DPAA 1 Frame Manager nodes in the P3041DS
device tree. The device tree fragments are copied over with little
modification from the Linux kernel source code.

Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-06-04 18:53:20 +05:30
Madalin Bucur
cb78233642 powerpc: dts: add QorIQ DPAA 1 FMan for P3041
The device tree fragments are copied over with little
modification from the Linux kernel source code.

Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-06-04 18:53:20 +05:30
Madalin Bucur
97e692307d powerpc: dts: add QorIQ DPAA 1 FMan to P2041RDB
Introduce the QorIQ DPAA 1 Frame Manager nodes in the P2041RDB
device tree. The device tree fragments are copied over with little
modification from the Linux kernel source code.

Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-06-04 18:53:20 +05:30
Madalin Bucur
44fc26e270 powerpc: dts: add QorIQ DPAA 1 FMan for P2041
The device tree fragments are copied over with little
modification from the Linux kernel source code.

Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-06-04 18:53:20 +05:30
Madalin Bucur
1659ff02cb powerpc: dts: add QorIQ DPAA 1 FMan interfaces to P4080DS
Introduce the QorIQ DPAA 1 Frame Manager interfaces nodes in the
P4080DS device tree.

Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-06-04 18:53:20 +05:30
Madalin Bucur
6e5e123924 powerpc: dts: add QorIQ DPAA 1 FMan for P4080
The device tree fragments are copied over with little
modification from the Linux kernel source code.

Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-06-04 18:53:20 +05:30
Madalin Bucur
eb3c194c40 powerpc: dts: add QorIQ DPAA 1 FMan v3 device tree nodes
Add the QorIQ DPAA Frame Manager version 3 device tree nodes
description. The device tree fragments are copied over with little
modification from the Linux kernel source code.

Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-06-04 18:53:20 +05:30
Madalin Bucur
37fa0b07b4 powerpc: dts: add QorIQ DPAA 1 FMan device tree nodes
Add the QorIQ DPAA Frame Manager device tree nodes description.
The device tree fragments are copied over with little modification
from the Linux kernel source code.

Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-06-04 18:53:20 +05:30
Madalin Bucur
55168c03a5 powerpc: dts: add QorIQ GPIOs
Add the QorIQ GPIO device tree nodes description. The device tree
fragments are copied over with little modification from the Linux
kernel source code.

Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-06-04 18:53:20 +05:30
Madalin Bucur
9485076c86 powerpc: dts: QorIQ: Add node(s) for the platform PLL
Add the QorIQ clock control device nodes include files.

Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-06-04 18:53:20 +05:30
Bin Meng
0a94007e82 riscv: sbi: Move sbi_probe_extension() out of CONFIG_SBI_V01
sbi_probe_extension() is an API defined in SBI v0.2, not v0.1.

Fixes 7e249bc13a: ("riscv: Move all SMP related SBI calls to SBI_v01")
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2020-06-04 09:44:21 +08:00
Bin Meng
fe94355716 riscv: sbi: Remove sbi_spec_version
U-Boot defaults to use SBI v0.2. Howerver there is a global variable
sbi_spec_version that stills refers to v0.1. Since it is not used
anywhere, let's remove it.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Rick Chen <rick@andestech.com>
2020-06-04 09:44:21 +08:00
Pragnesh Patel
01cdef22ee riscv: sifive: fu540: add SPL configuration
Add a support for SPL which will boot from L2 LIM (0x0800_0000) and
then SPL will boot U-Boot FIT image (OpenSBI FW_DYNAMIC + u-boot.bin)
from MMC boot devices.

SPL related code is leveraged from FSBL
(https://github.com/sifive/freedom-u540-c000-bootloader.git)

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-04 09:44:09 +08:00
Pragnesh Patel
7c45fc9870 riscv: cpu: fu540: Add support for cpu fu540
Add SiFive fu540 cpu to support RISC-V arch

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-04 09:44:09 +08:00
Pragnesh Patel
25d0853fcb riscv: dts: sifive: Sync hifive-unleashed-a00 dts from linux
This sync has changes required to use GPIO in U-Boot and
U-Boot SPL.

Sync dts from linux v5.7-rc2 commit:
"riscv: dts: Add GPIO reboot method to HiFive Unleashed DTS file"
(sha1: 0a91330b2af9f71ceeeed483f92774182b58f6d9)

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-04 09:44:09 +08:00
Pragnesh Patel
329e023868 riscv: sifive: dts: fu540: set ethernet clock rate
Set ethernet clock rate to 125 Mhz so that it will work with 1000Mbps,
Earlier this is done by FSBL. With this change We can remove the
ethernet clock rate code from FSBL.

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2020-06-04 09:44:09 +08:00
Pragnesh Patel
fdf5dba1fc riscv: sifive: dts: fu540: add U-Boot dmc node
Add dmc node to enable ddr driver. dmc is used to
initialize the memory controller.

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-04 09:44:08 +08:00
Pragnesh Patel
8a3fd8440f sifive: dts: fu540: Add DDR controller and phy register settings
Add DDR controller and phy register settings, taken from fsbl
(https://github.com/sifive/freedom-u540-c000-bootloader.git)

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-04 09:44:08 +08:00
Pragnesh Patel
0eed87ed90 riscv: sifive: dts: fu540: Add board -u-boot.dtsi files
Devicetree files in FU540 platform is synced from Linux, like other
platforms does. Apart from these U-Boot in FU540 would also require
some U-Boot specific node like clint.

So, create board specific -u-boot.dtsi files. This would help of
maintain U-Boot specific changes separately without touching Linux
dts(i) files which indeed easy for syncing from Linux between
releases.

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-04 09:44:08 +08:00
Pragnesh Patel
bbb94af981 riscv: Add _image_binary_end for SPL
For SPL_SEPARATE_BSS, Device tree will be put at _image_binary_end

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-04 09:44:08 +08:00
Pragnesh Patel
88eec6159a riscv: sifive: fu540: Use OTP DM driver for serial environment variable
Use the OTP DM driver to set the serial environment variable.

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-04 09:44:08 +08:00
Tom Rini
1b6ae82a5a Pull request for UEFI sub-system for efi-2020-07-rc4
This patch series addresses the following issues:
 
 * allow compiling with clang
 * add missing function descriptions to the HTML documentation
 * simplify the validation of UEFI images
 * validate load options in the UEFI boot manager
 
 In a preparatory patch a structure definition is moved.
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Merge tag 'efi-2020-07-rc4' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi

Pull request for UEFI sub-system for efi-2020-07-rc4

This patch series addresses the following issues:

* allow compiling with clang
* add missing function descriptions to the HTML documentation
* simplify the validation of UEFI images
* validate load options in the UEFI boot manager

In a preparatory patch a structure definition is moved.
2020-06-03 14:10:03 -04:00
Tom Rini
f1a69b8c73 Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-sunxi
- H6 emac support
- USB PHY H6 logic alignment
2020-06-03 11:52:13 -04:00
Heinrich Schuchardt
4f7dc5f608 efi_loader: allow compiling with clang
On ARM systems gd is stored in register r9 or x18. When compiling with
clang gd is defined as a macro calling function gd_ptr(). So we can not
make assignments to gd.

In the UEFI sub-system we need to save gd when leaving to UEFI binaries and
have to restore gd when reentering U-Boot.

Define a new function set_gd() for setting gd and use it in the UEFI
sub-system.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tested-by: Tom Rini <trini@konsulko.com>
2020-06-03 17:19:17 +02:00
Madalin Bucur
564637a360 board/freescale: add the DM_ETH changes for the PPC DPAA platforms
Add the required changes for compiling with DM_ETH on the PPC
DPAA platforms.

Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-06-03 12:14:28 +05:30
Madalin Bucur
03fe5d5116 powerpc: mpc85xx: fix unused variable warning
Fix unused variable warning when CONFIG_QE is not set.

Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-06-03 12:14:27 +05:30
Madalin Bucur
9e998d5dc1 powerpc/mpc85xx: Fix compiling error with DM_GPIO
P4080DS compilation fails with DM_GPIO enabled:

drivers/gpio/gpio-uclass.c:355:5: error: redefinition of 'gpio_request'
 int gpio_request(unsigned gpio, const char *label)
     ^~~~~~~~~~~~
In file included from ./arch/powerpc/include/asm/arch/gpio.h:17:0,
                 from ./arch/powerpc/include/asm/gpio.h:1,
                 from drivers/gpio/gpio-uclass.c:16:
./arch/powerpc/include/asm/mpc85xx_gpio.h:68:19: note: previous definition of 'gpio_request' was here
 static inline int gpio_request(unsigned gpio, const char *label)
                   ^~~~~~~~~~~~

Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-06-03 12:14:27 +05:30
Masahiro Yamada
9f8aa0fbee ARM: add psci_arch_init() declaration for CONFIG_ARMV7_PSCI
arch/arm/include/asm/system.h declares psci_arch_init(), but it is
surrounded by #ifdef CONFIG_ARMV8_PSCI.

psci_arch_init() is called for CONFIG_ARMV7_PSCI too. Add the missing
function declaration.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-06-02 17:27:04 -04:00
Tom Rini
ecd4d99f65 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86
- Corrected some FSP-M/FSP-S settings for Chromebook Coral
- ICH SPI driver and mrccache fixes for obtaining the SPI memory map
- Fixed various warnings generated by latest version IASL when compiling
  ACPI tables
2020-06-01 23:34:18 -04:00
Bin Meng
95cfa1d46c x86: quark: acpi: Replace _ADR() by _UID() in description of PCI host bridge
PCI Firmware specification requires _UID() and doesn't require _ADR()
to be set. Replace latter by former. This fixes the following warning
reported by ACPICA 20200430:

  Warning 3073 - Multiple types (Device object requires either a _HID
  or _ADR, but not both)

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2020-06-02 09:16:13 +08:00
Bin Meng
d8b5f5d436 x86: baytrail: acpi: Replace _ADR() by _UID() in description of PCI host bridge
PCI Firmware specification requires _UID() and doesn't require _ADR()
to be set. Replace latter by former. This fixes the following warning
reported by ACPICA 20200430:

  Warning 3073 - Multiple types (Device object requires either a _HID
  or _ADR, but not both)

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2020-06-02 09:16:13 +08:00
Bin Meng
319506c7a9 x86: baytrail: acpi: Create buffers outside of the methods
Create buffers outside of the methods as ACPICA 20200430 complains
about this:

  Remark 2173 - Creation of named objects within a method is highly
  inefficient, use globals or method local variables instead
  (\_SB.PCI0.LPCB.IURT._CRS)

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
2020-06-02 09:16:13 +08:00
Andy Shevchenko
b9ce32ec3a x86: tangier: acpi: Drop _HID() where enumerated by _ADR()
ACPICA complains that either _HID() or _ADR() should be used.
For General Purpose DMA we may not drop the _ADR() because
the device is enumerated by PCI. Thus, simple drop _HID().

Reported-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2020-06-02 09:16:13 +08:00
Andy Shevchenko
10a428ed15 x86: tangier: acpi: Drop _ADR() where _HID() is present
ACPICA complains that either _HID() or _ADR() should be used.
Drop _ADR() where _HID() is present.

Reported-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2020-06-02 09:16:13 +08:00
Andy Shevchenko
55f54538f8 x86: tangier: acpi: Replace _ADR() by _UID() in description of PCI host bridge
PCI Firmware specification requires _UID() and doesn't require _ADR()
to be set. Replace latter by former.

Reported-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2020-06-02 09:16:13 +08:00
Andy Shevchenko
d8177a94ca x86: tangier: acpi: Create buffers outside of the methods
Create buffers outside of the methods as ACPICA 20200214 complains about this:

	Remark 2173 - Creation of named objects within a method is
	highly inefficient, use globals or method local variables
	instead

Reported-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2020-06-02 09:16:13 +08:00
Simon Glass
4711c1f548 x86: apl: Add hex offsets for registers in FSP-S
When comparing hex dumps it is useful to see the offsets of the registers.
Add them in where they correspond to a multiple of 16.

Possibly it would be useful to have a a command to output the FSP values
in human-readable form, making use of the fsp_bindings implementation.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-06-02 09:16:13 +08:00
Simon Glass
501ba58ae6 x86: coral: Correct some FSP-S settings
Some settings were modified slightly in the device-tree conversion. Return
these to their original values. This includes some audio settings and a
few others that have changed.

Note that we still rely on the FSP defaults for most values, so there is
no need to specify a value if the FSP default is suitable.

This makes WiFi work again.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
2020-06-02 09:16:13 +08:00
Simon Glass
6e5ac59ec3 x86: apl: Add hex offsets for registers in FSP-M
When comparing hex dumps it is useful to see the offsets of the registers.
Add them in where they correspond to a multiple of 16.

Possibly it would be useful to have a a command to output the FSP values
in human-readable form, making use of the fsp_bindings implementation.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-06-02 09:16:13 +08:00
Simon Glass
537558b226 x86: coral: Correct some FSP-M settings
Some settings were modified slightly in the device-tree conversion. Return
these to their original values.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>
2020-06-02 09:16:13 +08:00
Simon Glass
70c3c911cc x86: mrccache: Allow use before driver model is active
The change to avoid searching the device tree does not work on boards
wich don't have driver model set up this early, for example minnowmax.
Put back the old code (converted to livetree) as a fallback for these
devices. Also update the documentation.

This is tested on minnowmax, link, samus and coral.

Fixes: 87f1084a63 (x86: Adjust mrccache_get_region() to use livetree)
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com> (on Intel minnowmax)
2020-06-02 09:16:13 +08:00
Simon Glass
d7413deadd x86: spl: Print the error on SPL failure
The error code is often useful to figure out what is going on. Printing it
does not increase code size much, so print out the error and then hang.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-06-02 09:16:13 +08:00
Simon Glass
8e2922e357 x86: spi: Add a way to access the SPI mapping via registers
At present the PCI BDF (bus/device/function) is needed to access the SPI
mapping, since the registers are at BAR0. This doesn't work when PCI
auto-config has not been done yet, since BARs are unassigned.

Add another way to find the mapping, using the MMIO base, if the caller
knows this.

Also add a missing function comment.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-06-02 09:16:13 +08:00
Samuel Holland
5cfeeacaea sunxi: Silence warning about non-static inline function
When compiling with CONFIG_SPL_SERIAL=n, gcc warns about
mbus_configure_port not being marked as static:

In file included from include/common.h:34,
                 from arch/arm/mach-sunxi/dram_sunxi_dw.c:11:
include/log.h:185:4: warning: 'printf' is static but used in inline function 'mbus_configure_port' which is not static
  185 |    printf(pr_fmt(fmt), ##args); \
      |    ^~~~~~
include/log.h:192:2: note: in expansion of macro 'debug_cond'
  192 |  debug_cond(_DEBUG, fmt, ##args)
      |  ^~~~~~~~~~
arch/arm/mach-sunxi/dram_sunxi_dw.c💯2: note: in expansion of macro 'debug'
  100 |  debug("MBUS port %d cfg0 %08x cfg1 %08x\n", port, cfg0, cfg1);
      |  ^~~~~

Fix this by updating the function accordingly.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-06-01 22:38:08 +05:30
Tom Rini
42c8a112d2 - stm32mp15: fix DT on DHCOR SOM and avenger96 board
- stm32mp15: re-enable KS8851 on DHCOM
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Merge tag 'u-boot-stm32-20200528' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm

- stm32mp15: fix DT on DHCOR SOM and avenger96 board
- stm32mp15: re-enable KS8851 on DHCOM
2020-06-01 11:42:22 -04:00
Tom Rini
9452b7496f Merge tag 'u-boot-rockchip-20200531' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- Fix mmc of path after syncfrom kernel dts;
- Add dwc3 host support with DM for rk3399;
- Add usb2phy and typec phy for rockchip platform;
- Migrate board list doc to rockchip.rst;
- Add rk3399 Pinebook Pro board support;
- Update dram_init in board_init and add memory node in SPL;
2020-05-31 20:07:39 -04:00
Heiko Stuebner
b6740fb116 rockchip: spl: do full dram_init instead of only probing
Parts of later SPL may need RAM information as well, so do full
dram_init() call, which includes the existing dram probing but also
initializes the ram information in gd.

dram_init() from sdram.c does the following steps:
- uclass_get_device(UCLASS_RAM, ...) like the current code
- ret = ram_get_info(dev, &ram);
- gd->ram_size = ram.size;

CONFIG_SPL_RAM already makes sure that sdram.c gets compiled
and thus no other variant of dram_init() can exist.

So it's the same functionality as before and only adds that the
SPL now aquires knowledge about the amount of available ram,
which it didn't know about before.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-31 22:22:07 +08:00
Peter Robinson
9fb8e24804 rockchip: Add initial support for the Pinebook Pro laptop from Pine64.
Specification:
- Rockchip RK3399
- 4GB Dual-Channel LPDDR4
- eMMC socket
- mSD card slot
- 128Mbit (16Mb) SPI Flash
- AP6256 for 11AC WiFi + BT5
- 14 inch 1920*1080 eDP MiPi display
- Camera
- USB 3.0, 2.0 ports
- Type-C port with alt-mode display (DP 1.2) and 15W charge
- DC 5V/3A
- optional PCIe slot for NVMe SSD drive

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Tested-by: Vagrant Cascadian <vagrant@debian.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-31 22:22:07 +08:00
Peter Robinson
7390fb9999 arm: dts: rockchip: Add initial DT for Pinebook Pro
Sync initial support for Pinebook Pro device tree from Linux 5.7-rc1.

Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-31 20:46:08 +08:00
Frank Wang
86554ab10a ARM: dts: rk3399-evb: usb3.0 host support
Configure 'tcphy1' and 'usbdrd_dwc3_1' nodes to support USB3.0 host
for Rockchip RK3399 Evaluation Board.

Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-30 07:38:50 +08:00
Frank Wang
c28ef1bcc8 arm: mach-rockchip: bind sub-nodes for rk3399_syscon
There are some sub-nodes under the grf DT, so add bind callback
function in rk3399 syscon driver to scan them recursively.

Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # roc-rk3399-pc
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-29 18:13:19 +08:00
Jagan Teki
20dcee45cb arm64: dts: rk3399-nanopi4: Add u-boot,spl-boot-order
Add u-boot,spl-boot-order as sdhci and sdmmc for booting
from eMMC and SD card.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-29 17:58:55 +08:00
Jagan Teki
97de3935aa rockchip: Fix spl mmc boot device ofpath
Linux v5.7-rc1 dts(i) sync has changed the sdmmc node from
dwmmc@fe320000 to mmc@fe320000 and this ofpath is being
used in rockchip spl bootdevice code.

So, update the ofpath with a new node name and prefix "same-as-spl"
to missing u-boot,spl-boot-order.

Bug log:
U-Boot SPL 2020.07-rc2-00256-g9c5fef5774 (May 24 2020 - 20:20:43 +0530)
Trying to boot from MMC2
mmc_load_image_raw_sector: mmc block read error
Trying to boot from MMC1
mmc_load_image_raw_sector: mmc block read error
SPL: failed to boot from all boot devices

Fixes: 167efc2c7a ("arm64: dts: rk3399: Sync v5.7-rc1 from Linux"
Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-29 17:58:21 +08:00
Neil Armstrong
3678a5f059 arm: dts: meson-gxl: fix USB gadget by adding missing nodes for U-Boot
The khadas-vim, khadas-vim2, libretech-ac & libretech-*-pc boards were missing
DT tweak to enable USB gadget.
Add them to their -u-boot.dtsi files and include the right gxl-u-boot.dtsi.

Fixes: a19e8a0f03 ("arm: dts: meson-gxl: Add USB Gadget nodes for U-Boot")
Reported-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-05-29 10:20:34 +02:00
Neil Armstrong
21981c1059 arm: dts: khadas-vim3: include meson-g12-common-u-boot.dtsi to enable HDMI output
Include the common g12 u-boot tweaks to permit enabling video output tweaks
on Khadas VIM3 boards.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-05-29 10:20:34 +02:00
Marek Vasut
08f372ac2a ARM: dts: stm32: Disable SDR104 mode on AV96
Disable SDR104 mode until we know it is really stable.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-05-28 08:52:04 +02:00
Marek Vasut
39a18aaa33 ARM: dts: stm32: Repair I2C2 operation on AV96
The I2C2 uses different pinmux on AV96, use correct pinmux and
also add comments about the I2C being present on the "low-speed"
expansion connector X6.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-05-28 08:52:04 +02:00
Marek Vasut
b1ebcd27ee ARM: dts: stm32: Add alternate pinmux for I2C2 pins
Add another mux option for I2C2 pins, this is used on AV96 board.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-05-28 08:52:04 +02:00
Marek Vasut
8b4101d0f9 ARM: stm32: Hog GPIO PF7 high on DHCOR to unlock SPI NOR nWP
The SPI NOR nWP line is connected to GPIO PF7 on the SoM,
pull the GPIO line high by default to clear SPI NOR WP.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-05-28 08:52:04 +02:00
Tom Rini
ab80137cc4 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell
- Fix SPI boot on ds414 (Ezra)
- Fix PHY mode definition on armada-3720-uDPU (Jakov)
- Convert CRS305-1G-4S to generic version (Luka)
2020-05-27 10:56:25 -04:00
Simon Glass
0621b5e1ee cbfs: Don't require the CBFS size with cbfs_init_mem()
The size is not actually used since it is present in the header. Drop this
parameter. Also tidy up error handling while we are here.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-05-27 14:40:09 +08:00
Christian Gmeiner
53942b9658 x86: coreboot: add SMBIOS cbmem entry parsing
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-05-27 14:40:09 +08:00
Bernhard Messerklinger
d9e7efe10a x86: apl: Use devicetree for FSP-S configuration
A the moment the FSP-S configuration is a mix of hard coded values and
devicetree properties.

This patch makes FSP-S full configurable from devicetree by
adding binding properties for all FSP-S parameters.

Co-developed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org> (Tested on coral)
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-05-27 14:40:09 +08:00
Bernhard Messerklinger
1fa6305fd6 x86: apl: Use devicetree for FSP-M configuration
A the moment the FSP-M configuration is a mix of hard coded values and
devicetree properties.

This patch makes FSP-M full configurable from devicetree by adding
binding properties for all FSP-M parameters.

Co-developed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org> (Tested on coral)
[sjg: Fix a build error for coral]
Signed-off-by: Simon Glass <sjg@chromium.org>
[bmeng: Add __maybe_unused to fsp_update_config_from_dtb()]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-05-27 14:40:09 +08:00
Bernhard Messerklinger
832fee864c x86: apl: Only load VBT if CONFIG_HAVE_VBT is enabled
Only load VBT if it's present in the u-boot.rom.

Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org> (Tested on coral)
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-05-27 14:40:09 +08:00
Luka Kovacic
df9ebbe17e arm: mvebu: Convert CRS305-1G-4S board to CRS3xx-98DX3236
Convert the CRS305-1G-4S board to CRS3xx-98DX3236 to enable easier
implementation of new CRS3xx series boards, based on Marvell Prestera
98DX3236.

Signed-off-by: Luka Kovacic <luka.kovacic@sartura.hr>
Reviewed-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Jakov Petrina <jakov.petrina@sartura.hr>
2020-05-27 07:03:17 +02:00
Jakov Petrina
8678776df6 arm: mvebu: armada-3720-uDPU: fix PHY mode definition to sgmii-2500
Commit f49ac7e1c4 switched the default PHY speed to 3.125Gbit to resolve
issues with SFP modules. However, U-Boot does not have a "2500base-x"
phy-mode.

Resolve this by using "sgmii-2500" instead.

Signed-off-by: Jakov Petrina <jakov.petrina@sartura.hr>
Signed-off-by: Vladimir Vid <vladimir.vid@sartura.hr>
Reviewed-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Stefan Roese <sr@denx.de>
2020-05-27 07:03:01 +02:00
Ezra Buehler
a1a61b0672 arm: mvebu: ds414: add u-boot,dm-pre-reloc to spi0
Without this U-Boot-specific property, booting on the Synology DS414
(or DS214+) fails in SPL. The spi0 DT node is not scanned, as a result
the SPI flash cannot be found.

Signed-off-by: Ezra Buehler <ezra@easyb.ch>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-05-27 07:02:24 +02:00
Atish Patra
7e249bc13a riscv: Move all SMP related SBI calls to SBI_v01
SMP support for S-mode U-Boot is enabled only if SBI_V01 is enabled.
There is no point in supporting SMP related (IPI and fences) SBI calls
when SBI_V02 is enabled.

Modify all the SMP related SBI calls to be defined only for SBI_V01.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-05-26 15:50:08 +08:00
Tom Rini
60c7facfc9 Merge tag 'ti-v2020.07-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-ti
- Enable DM_ETH on omap3_logic board
- Enable Caches in SPL for K3 platforms
- Enable backup boot mode support for J721E
- Update the DDR timings for AM654 EVM
- Add automated tests for RX-51
2020-05-25 14:09:42 -04:00
Michael Walle
efc0644802 sandbox: move compression option to Kconfig
CONFIG_BZIP2 and CONFIG_GZIP_COMPRESSED are Kconfig options. Select them
by CONFIG_SANDBOX instead of setting them in configs/sandbox.h.

Signed-off-by: Michael Walle <michael@walle.cc>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-05-25 11:54:53 -04:00
Peng Fan
b4b2619211 armv8: cache_v8: fix mmu_set_region_dcache_behaviour
The enum dcache_optoion contains a shift left 2 bits in the armv8 case
already.  The PMD_ATTRINDX(option) macro will perform a left shift of 2
bits.  Perform a right shift so that in the end we get the correct
value.

[trini: Reword the commit message]
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-25 11:54:53 -04:00
Tom Rini
9c5fef5774 Merge git://git.denx.de/u-boot-usb
- DM support for OMAP
- DWC3 fix
- Typo fix in eth/r8152
2020-05-22 22:58:50 -04:00
Tom Rini
f53c2dc162 Merge tag 'u-boot-rockchip-20200522' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- Fix rk3288 chromebook veyron support;
- Add pcie driver support for rk3399;
- other fixes for rk3399 boards
2020-05-22 10:28:38 -04:00
Adam Ford
94ed66194f usb: ehci-omap: Add Support for DM_USB and OF_CONTROL
The omap3.dtsi file shows the usbhshost node with two sub-nodes
for ohci and ehci.  This patch file creates the usbhshost, and
pulls the portX-mode information.  It then locates the EHCI
sub-node, and initializes the EHCI controller with the info
pulled from the usbhshost node.

There is still more to do since there isn't an actual link
between the 'phys' reference and the corresponding phy driver,
and there is no nop-xceiv driver yet.

In the meantime, the older style reference to
CONFIG_OMAP_EHCI_PHYx_RESET_GPIO is still needed to pull
the phy out of reset until the phy driver is completed and the
phandle reference is made.

Signed-off-by: Adam Ford <aford173@gmail.com>
2020-05-22 15:22:35 +02:00
Kurt Miller
33863f744d rockchip: rk3328: rock64 - fix gen3 SPL hang
Use the same approach as ROC-RK3328-CC which enables SPL GPIO,
pinctl and regulator support. This allows the gen3 board to
boot through SPL and does not break gen2 in the process.

Signed-off-by: Kurt Miller <kurt@intricatesoftware.com>
Acked-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-22 20:53:20 +08:00
Urja Rannikko
e68a843601 rockchip: spl-boot-order: do not attempt to access fdt if OF_PLATDATA
gd->fdt_blob is null if using OF_PLATDATA in SPL, which causes a hang
after f0921f5098 ("fdt: Sync up to the latest libfdt").
We use the same test that is used in spl_common_init on whether to call
fdtdec_setup to unconditionally avoid linking in the fdt-using code
when not necessary and thus reduce SPL size.

Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-22 20:53:20 +08:00
Urja Rannikko
353ad95aa6 rockchip: spl: veyron speedy boots from SPI
Apparently speedy was forgotten from this list of veyron devices.

Fixes: 49105fb7ed ("rockchip: add common spl board file")
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-22 20:53:20 +08:00
Jagan Teki
765a12d6a3 rockchip: Enable PCIe/M.2 on rk3399 board w/ M.2
Enable PCIe/M.2 support on
- NanoPC-T4
- ROC-RK3399-PC Mezzanine boards.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Suniel Mahesh <sunil@amarulasolutions.com> #roc-rk3399-pc
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-22 20:53:20 +08:00
Deepak Das
5c606ca35c rockchip: rk3399: enable spl-fifo-mode for sdmmc
adapting commit fa2047c473 ("rockchip: rk3328: enable spl-fifo-mode
for emmc and sdmmc") for rk3399.
Since mmc to sram can't do dma, add patch to prevent aborts transferring
TF-A parts.

Signed-off-by: Deepak Das <deepakdas.linux@gmail.com>
2020-05-22 17:24:30 +08:00
Masahiro Yamada
6cbe90486c ARM: uniphier: remove board_eth_init()
This platform completely migrated to CONFIG_DM_ETH.

board_eth_init() is only called from net/eth_legacy.c

Remove the legacy hook.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-05-22 11:21:06 +09:00
Masahiro Yamada
6717e15447 ARM: uniphier: delete or replace <common.h> includes
<common.h> pulls in a lot of bloat. <common.h> is unneeded in most of
places.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-05-22 11:21:06 +09:00
Masahiro Yamada
1e1518866f ARM: uniphier: drop #include <log.h> again
I do not understand the changes made to these files by
commit f7ae49fc4f ("common: Drop log.h from common header").

  git show f7ae49fc4f -- arch/arm/mach-uniphier/

None of them uses the log function feature.

Simply revert the changes made to these files.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-05-22 11:21:06 +09:00
Masahiro Yamada
e9d3b23505 ARM: uniphier: drop #include <init.h> again from umc-pxs2.c
I do not understand the change made to this file by
commit 691d719db7 ("common: Drop init.h from common header").

  git show 691d719db7 -- arch/arm/mach-uniphier/dram/umc-pxs2.c

This file does not call or define any functions declared in <init.h>

Simply revert the change made to this file.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-05-22 11:21:06 +09:00
Masahiro Yamada
e6396fcab2 ARM: uniphier: remove #include <net.h> again from micro-support-card.c
I do not understand the changes made to this file by
commit 90526e9fba ("common: Drop net.h from common header").

  git show 90526e9fba -- arch/arm/mach-uniphier/micro-support-card.c

The necessary declaration is already included by <netdev.h> at line 112.
It also moved the <dm/of.h> inclusion, but I do not understand the
motivation of doing so, either.

Simply revert the changes made to this file.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-05-22 11:21:06 +09:00
Masahiro Yamada
f49049a8ec ARM: uniphier: include <asm/system.h> instead of <asm/cache.h> from psci.c
I do not understand the change made to this file by
commit 90526e9fba ("common: Drop net.h from common header").

  git show 90526e9fba -- arch/arm/mach-uniphier/arm32/psci.c

It added <asm/cache.h> while this file does not call the standard cache
functions at all.

All the uniphier-specific cache functions, uniphier_cache_*() are
declared in cache-uniphier.h, which is already included from this file.

Including <asm/system.h> is sensible to fix the -Wmissing-prototypes
warnings because this file defines psci_cpu_on and psci_system_reset().

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-05-22 11:21:06 +09:00
Masahiro Yamada
1517126fda ARM: uniphier: select DM_ETH
drivers/net/smc911x.c has been converted to DM.

select DM_ETH to enable it for all the UniPhier platform boards.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2020-05-22 11:21:06 +09:00
Tom Rini
2fa581ba91 Merge git://git.denx.de/u-boot-sh
- Enable -ffunction-sections / -fdata-sections --gc-sections to SH
- RCar Gen3 updates
2020-05-21 08:26:40 -04:00
Tom Rini
b0b13f4114 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq
- Add DM_ETH support for lx2160aqds, ls2080aqds, ls1088aqds
- QSI related fixes on ls1012a, ls2080a, ls1046a, ls1088a, ls1043a based
  platforms
- Bug-fixes/updtaes related to ls1046afrwy, fsl-mc, msi-map property
2020-05-20 08:46:56 -04:00
Marek Vasut
56f01746ab sh: Enable ffunction-sections and fdata-sections
Enable these two options to let compiler eliminate unused code.
On R2Dplus, this results in considerable amount of saved space:

      text    data     bss     dec     hex filename
  - 266580   13196   39076  318852   4dd84 u-boot
  + 220214   12797   38745  271756   4258c u-boot

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Tom Rini <trini@konsulko.com>
2020-05-20 13:20:25 +02:00
Marek Vasut
03578d940d ARM: dts: rmobile: Enable eMMC DDR52 modes on Gen3 Salvator-X(S),ULCB,Ebisu
Enable DDR52 modes, since the SD core supports correct switching now.
For completeness, list HS200 modes, however those were already enabled.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2020-05-20 13:20:25 +02:00
Marek Vasut
5d17a1691b ARM: dts: rmobile: Reserve space in R-Car Gen3 DTs
Reserve 4 kiB of space in R-Car Gen3 DTs when those DTs are compiled
to permit patching in OpTee-OS /firmware node, /reserved-memory node
and possibly also additional /memory@ nodes.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
2020-05-20 13:20:19 +02:00
Heiko Schocher
d934b43a02 mpc83xx, abb: remove suvd3 board
the mpc83xxx suvd3 variant is not longer used, so
remove it.

Signed-off-by: Holger Brunck <holger.brunck@ch.abb.com>
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-05-19 14:01:47 -04:00
Rasmus Villemoes
e2e3ea8916 mpc83xx: remove redundant MPC83xx_RESET #define
This macro is only used (tested for existence) in mpc83xx.c, which
unconditionally includes mpc83xx.h where it is unconditionally
defined. Removing it makes the remaining code easier to read.

Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
2020-05-19 14:01:47 -04:00
Jan Kiszka
c02712a748 arm: mach-k3: Enable dcache in SPL
Add support for enabling dcache already in SPL. It accelerates the boot
and resolves the risk to run into unaligned 64-bit accesses.

Based on original patch by Lokesh Vulta.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-05-19 14:41:13 +05:30
Andreas Dannenberg
7bf82cc1f8 arm: mach-k3: j721e_init: Add support for backup boot modes
When the boot of J721E devices using the primary bootmode (configured
via device pins) fails a boot using the configured backup bootmode is
attempted. To take advantage of the backup boot mode feature go ahead
and add support to the J721E init code to determine whether the ROM code
performed the boot using the primary or backup boot mode, and if booted
from the backup boot mode, decode the bootmode settings into the
appropriate U-Boot mode accordingly so that the boot can proceed.

Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
2020-05-19 14:40:54 +05:30
Adam Ford
62ca4aa16f ARM: omap3_logic boards: Convert to DM_ETH
With the converstion of SMC911x to DM, this can facilitate the omap3
boards from LogicPD (now called Beacon EmbeddedWorks) to be converted.
There isn't a clean solution to doing this in phases, so the boards are
all being done together to avoid breaking functionality.

Because the GPMC bus hasn't been converted, the -u-boot.dtsi node needs
to show the address of the ethernet controller for each board.

The board file, which is common betwen the OMAP35 and DM37 SOM LV and
Torpedo boards, can remove the manual ethernet initialization, but it
still needs to register the address and GPMC configuration for the Ethernet
controller which is now being moved around to board_late_init().

Lastly, this patch updates the various config files to add the reference
for DM_ETH and remove the SMC address, which is now fetched from the
newly created device tree nodes.

Signed-off-by: Adam Ford <aford173@gmail.com>
2020-05-19 14:40:42 +05:30
Praneeth Bajjuri
a665cb13dc ddr: k3-am654: EMIF Tool update to 2.02 for IO optimizations and fixes
EMIF tool for AM65x [1] is now updated from rev 1.98 to 2.02

This update includes
* Optimizations in IO configuration.
* Fix for byte enablement in GCR registers.
* Fixes for PG2.0 including ZQ control.

[1]: http://www.ti.com/lit/zip/sprcah7

Acked-by: James Doublesin <doublesin@ti.com>
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
2020-05-19 14:40:27 +05:30
Ioana Ciornei
020ed9c666 arm: dts: ls2080aqds: add CONFIG_MULTI_DTB_FIT support
Add support for selecting the appropriate DTS file depending on the
SERDES protocol used.

The fsl-ls2080a-qds DTS will be used by default if there isn't a DTS
file specifically made for the current SERDES protocol.

This patch adds the necessary DPMAC nodes (DPMAC 1-8) for
protocol 42 (0x2A) on SD#1.

Also, in case CONFIG_DM_ETH and CONFIG_MULTI_DTB_FIT are enabled
implement the board_fit_config_name_match() function in order to choose
the appropriate DTS.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-05-19 09:22:08 +05:30
Ioana Ciornei
b62526282a arm: dts: ls1088aqds: add CONFIG_MULTI_DTB_FIT support
Add support for selecting the appropriate DTS file depending on the
SERDES protocol used. The fsl-ls2088a-qds DTS will be used by default if
there isn't a DTS file specifically made for the current SERDES
protocol.

This patch adds support for the on-board ports (DPMAC 1,2 and 4,5) found
on the SERDES protocols 21(0x15) and 29(0x1d) for SD#1.

On the LS1088AQDS board EMDIO1 is used with two onboard RGMII PHYs
(Realtek RTL8211FD-CG), as well as 2 input/output connectors for
mezzanine cards. Configuration signals from the Qixis FPGA control the
routing of the external MDIOs.

Register 0x54 of the Qixis FPGA controls the routing of the EMDIO1 one
of the 2 IO slots. As a consequence, a new node is added to
describe register 0x54 as a MDIO mux controlled with child nodes
describing all the IO slots as MDIO buses.

Also, in case CONFIG_DM_ETH and CONFIG_MULTI_DTB_FIT are enabled
implement the board_fit_config_name_match() function in order to choose
the appropriate DTS.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-05-19 09:22:08 +05:30
Ioana Ciornei
74f04490f2 arm: dts: lx2160aqds: add nodes describing possible mezzanine cards
Add device trees describing possible uses of mezzanine cards depending
on the SERDES protocol employed.

This patch adds DPAA2 networking support for the following protocols on
each SERDES block:
 * SD #1: 3, 7, 19, 20
 * SD #2: 11

Each SERDES block has a different device tree file per protocol
supported, where the IO SLOTs used are enabled and PHYs located on the
mezzanine cards are described. Also, dpmac nodes are edited and their
associated phy-connection-type and phy-handle are added.

Top DTS files are also added for each combination of protocol on the 3
SERDES blocks.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-05-19 09:22:07 +05:30
Ioana Ciornei
3695e4ccfd arm: dts: lx2160aqds: add MDIO slots
The LX2160A processor has two external MDIO interfaces, described in the
DTS as emdio1 and emdio2.

On the LX2160AQDS board EMDIO1 is used with two onboard RGMII PHYs
(Realtek RTL8211FD-CG), as well as eight input/output connectors for
mezzanine cards. Configuration signals from the Qixis FPGA control the
routing of the external MDIOs.

Register 0x54 of the Qixis FPGA controls the routing of the EMDIO1 one
of the 8 IO slots. As a consequence, a new node is added to
describe register 0x54 as a MDIO mux controlled with child nodes
describing all the IO slots as MDIO buses.

Also, DPMAC 17 and 18 are updated to reference the on-board PHYs.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-05-19 09:22:07 +05:30
Ioana Ciornei
237b262009 arm: dts: lx2160a: add noted for dpmacs 1, 2, 5-6
Add nodes for DPMACs 1, 2 and 5-6 which were missing from the
description. These will be later used on the LX2160AQDS specific DTS.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-05-19 09:22:07 +05:30
Kuldeep Singh
b480bcca80 treewide: Update fsl qspi node dt properties as per spi-mem driver
According to new qspi driver, some properties like "bus-num, num-cs,
big-endian" are no longer used. Device endiannes can be determined from
device-type data in driver.

Now use board specific compatibles, generic node names and specific
labels to align with linux device-tree properties.

Also consolidate spi-max-frequency to 50Mhz treewide.

Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-05-19 09:22:05 +05:30
Kuldeep Singh
c93ad777b8 treewide: Remove unused FSL QSPI config options for Layerscape platforms
Some of these options are not used by the driver anymore and some of
them are obsolete as the information is gathered from the dt. Also
consolidating defines in common headers.

Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-05-19 09:22:05 +05:30
Simon Glass
cd93d625fd common: Drop linux/bitops.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:23 -04:00
Simon Glass
f09f1ecbe7 Use __ASSEMBLY__ as the assembly macros
Some places use __ASSEMBLER__ instead which does not work since the
Makefile does not define it. Fix them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:23 -04:00
Simon Glass
c05ed00afb common: Drop linux/delay.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:23 -04:00
Simon Glass
07e1114671 Fix some checkpatch warnings in calls to udelay()
Fix up some incorrect code style in calls to functions in the linux/time.h
header, mostly udelay().

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:23 -04:00
Simon Glass
1af3c7f422 common: Drop linux/stringify.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:23 -04:00
Simon Glass
eb41d8a1be common: Drop linux/bug.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:23 -04:00
Simon Glass
8ad92118dc common: Drop asm_offsets.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:23 -04:00
Simon Glass
25a5818ff8 common: Drop asm/ptrace.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:23 -04:00
Simon Glass
f7ae49fc4f common: Drop log.h from common header
Move this header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 21:19:18 -04:00
Simon Glass
3c7dded8e1 Fix some checkpatch warnings in calls to debug()
Fix up some incorrect code style in calls to functions in the log.h
header, mostly debug().

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 18:36:57 -04:00
Simon Glass
0914011310 command: Remove the cmd_tbl_t typedef
We should not use typedefs in U-Boot. They cannot be used as forward
declarations which means that header files must include the full header to
access them.

Drop the typedef and rename the struct to remove the _s suffix which is
now not useful.

This requires quite a few header-file additions.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 18:36:55 -04:00
Simon Glass
691d719db7 common: Drop init.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 17:33:33 -04:00
Simon Glass
4d72caa5b9 common: Drop image.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 17:33:33 -04:00
Simon Glass
52f2423804 common: Drop bootstage.h from common header
Move this fairly uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 17:33:33 -04:00
Simon Glass
b67eefdb6e bootstage: Use BOOTSTAGE instead of BOOTSTATE
Some of the enum members are wrong. Fix them.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 17:33:33 -04:00
Simon Glass
e6f6f9e648 common: Drop part.h from common header
Move this uncommon header out of the common header.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 17:33:33 -04:00
Simon Glass
0528979fa7 part: Drop disk_partition_t typedef
We should not be using typedefs and these make it harder to use
forward declarations (to reduce header file inclusions). Drop the typedef.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 17:33:33 -04:00
Simon Glass
90526e9fba common: Drop net.h from common header
Move this header out of the common header. Network support is used in
quite a few places but it still does not warrant blanket inclusion.

Note that this net.h header itself has quite a lot in it. It could be
split into the driver-mode support, functions, structures, checksumming,
etc.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 17:33:31 -04:00
Simon Glass
c3dc39a2f8 arm: Don't include common.h in header files
It is bad practice to include common.h in other header files since it can
bring in any number of superfluous definitions. It implies that some C
files don't include it and thus may be missing CONFIG options that are set
up by that file. The C files should include these themselves.

Update some header files in arch/arm to drop this.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 14:54:24 -04:00
Simon Glass
b79fdc7697 common: Drop flash.h from common header
Move this uncommon header out of the common header.

Fix up some style problems in flash.h while we are here.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 14:53:28 -04:00
Simon Glass
a595a0e910 flash: Tidy up coding style for flash functions
Some functions use the wrong code style and generate checkpatch errors.
Fix these.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-05-18 14:53:28 -04:00
Tiaki Rice
d32cbefc8a ARM: dts: sama5d2: Add uart4 definition
This patch adds support for uart4 to the
processor level device tree include file.

Signed-off-by: Tiaki Rice <tiakirice@hotmail.com>
Cc: Eugen Hristev <Eugen.Hristev@microchip.com>
2020-05-18 15:00:20 +03:00
Ilias Apalodimas
7f44c7e281 dts: nxp2160ardb: add op-tee node
A defconfig is added on lx2160ardb which allows UEFI variable management
via OP-TEE. Enable the the node in the relevant DTS file.

Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
2020-05-17 21:59:53 +02:00
Michael Walle
714497e327 efi_loader: round the memory area in efi_add_memory_map()
Virtually all callers of this function do the rounding on their own.
Some do it right, some don't. Instead of doing this in each caller,
do the rounding in efi_add_memory_map(). Change the size parameter
to bytes instead of pages and remove aligning and size calculation in
all callers.

There is no more need to make the original efi_add_memory_map() (which
takes pages as size) available outside the module. Thus rename it to
efi_add_memory_map_pg() and make it static to prevent further misuse
outside the module.

Signed-off-by: Michael Walle <michael@walle.cc>
Add missing comma in sunxi_display.c.
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-05-17 21:59:53 +02:00
Samuel Holland
3988be5fd4 spl: Always define preloader_console_init
A large number of boards call preloader_console_init unconditionally.
Currently, they fail to build with CONFIG_SPL_SERIAL=n, because the
function is undefined in that case. To fix the build, always define
preloader_console_init, but make it no-op when CONFIG_SPL_SERIAL=n.

For the few boards that did check for CONFIG_SPL_SERIAL before calling
preloader_console_init, remove the checks, since the function can now
be called unconditionally.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-05-15 14:47:35 -04:00
Trevor Woerner
71f6354b0e rename symbol: CONFIG_STM32 -> CONFIG_ARCH_STM32
Have this symbol follow the pattern of all other such symbols.

Signed-off-by: Trevor Woerner <twoerner@gmail.com>
2020-05-15 14:47:35 -04:00
Trevor Woerner
18138ab203 rename symbol: CONFIG_TEGRA -> CONFIG_ARCH_TEGRA
Have this symbol follow the pattern of all other such symbols.

Signed-off-by: Trevor Woerner <twoerner@gmail.com>
2020-05-15 14:47:35 -04:00
Trevor Woerner
bb0fb4c0f4 rename symbol: CONFIG_KIRKWOOD -> CONFIG_ARCH_KIRKWOOD
Have this symbol follow the pattern of all other such symbols.
This patch also removes a TODO from the code.

Reviewed-by: Chris Packham <judge.packham@gmail.com>
Signed-off-by: Trevor Woerner <twoerner@gmail.com>
2020-05-15 14:47:35 -04:00
Trevor Woerner
b48f72a86b arm: orion5x: finish moving SoC to mach-orion5x
The SPL linker script had been left in arch/$(ARCH)/cpu/$(CPU)/$(SOC);
therefore move it to the already-established arch/$(ARCH)/mach-$(SOC)
location.

Signed-off-by: Trevor Woerner <twoerner@gmail.com>
2020-05-15 14:47:35 -04:00
Trevor Woerner
b16a331697 rename symbol: CONFIG_ORION5X -> CONFIG_ARCH_ORION5X
Have this symbol follow the pattern of all other such symbols.
This patch removes a TODO from the code.

Signed-off-by: Trevor Woerner <twoerner@gmail.com>
2020-05-15 14:47:35 -04:00
Trevor Woerner
9bffc54996 arch/arm/Makefile: sort machine names
The comment immediately above the block of machine directory names implored
users to keep the macro names sorted, but, alas, this is no longer the case.

Put the list of machine directory names back in alphanumerical order by
CONFIG_* macro name, as the comment asks. Sort all the symbols as though they
all followed the convention of having the string "ARCH_" in the middle of
their definitions.

Signed-off-by: Trevor Woerner <twoerner@gmail.com>
2020-05-15 14:47:35 -04:00
Trevor Woerner
b3d9a8b185 arm: lpc32xx: move SoC to mach-lpc32xx
Following the example of most other SoCs in arch/$(ARCH)/cpu/$(CPU)/$(SOC)
move the lpc32xx code from arch/arm/cpu/arm926ejs/lpc32xx to
arch/arm/mach-lpc32xx.

Following the checklist from
commit 01f1445630 ("ARM: prepare for moving SoC sources into mach-*"):

    [1] move files from arch/arm/cpu/arm926ejs/lpc32xx to arch/arm/mach-lpx32xx
    [2] add machine entry to arch/arm/Makefile
    [3] remove "obj-y += ..." from arch/arm/cpu/arm926ejs/Makefile
    [4] fix the Kconfig file path in arch/arm/Kconfig
    [5] (no MAINTAINERS update)

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Trevor Woerner <twoerner@gmail.com>
2020-05-15 14:47:35 -04:00
Tom Rini
e2b86e23ce - stm32mp1: migrate MTD and DFU configuration in Kconfig
- stm32mp1: add command stm32prog
 - stm32mp1: several board and arch updates
 - stm32mp1: activate data cache in SPL and before relocation
 - Many improvment for AV96 board and DHCOR SoM
   (add new defconfig, DDR3 coding on DHCOR SoM, split between board and SOM
    Synchronize DDR setttings on DH SoMs, setting for I2C EEPROM)
 - clk: stm32mp1: fix CK_MPU calculation
 - DT alignment of stm32mp1 device tree with Linux 5.7-rc2
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Merge tag 'u-boot-stm32-20200514' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm

- stm32mp1: migrate MTD and DFU configuration in Kconfig
- stm32mp1: add command stm32prog
- stm32mp1: several board and arch updates
- stm32mp1: activate data cache in SPL and before relocation
- Many improvment for AV96 board and DHCOR SoM
  (add new defconfig, DDR3 coding on DHCOR SoM, split between board and SOM
   Synchronize DDR setttings on DH SoMs, setting for I2C EEPROM)
- clk: stm32mp1: fix CK_MPU calculation
- DT alignment of stm32mp1 device tree with Linux 5.7-rc2
2020-05-14 08:44:06 -04:00
Tom Rini
fe16786149 - fix phy configuration for RPi4's bcmgenet
- sync RPi4's env size with other RPi configs
 - add kconfig option to reserver more pages in the EFI mem map
 - add support for SDMA which is used by RPi4
 - fix corner case boot bug for RPi3 32-bit
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Merge tag 'rpi-next-2020.07' of https://gitlab.denx.de/u-boot/custodians/u-boot-raspberrypi

- fix phy configuration for RPi4's bcmgenet
- sync RPi4's env size with other RPi configs
- add kconfig option to reserver more pages in the EFI mem map
- add support for SDMA which is used by RPi4
- fix corner case boot bug for RPi3 32-bit
2020-05-14 08:43:33 -04:00
Patrick Delaunay
1b28a5e2b0 ARM: dts: stm32mp1: DT alignment with Linux 5.7-rc2
DT alignment with Linux 5.7-rc2, including the kernel commits

431c89e6f323 ARM: dts: stm32: use correct vqmmc regu for eMMC on stm32mp1 ED1/EV1 boards
79e965053872 ARM: dts: stm32: add disable-wp property for SD-card on STM32MP1 boards
877db62ea516 ARM: dts: stm32: add cd-gpios properties for SD-cards on STM32MP1 boards
7519e95ba5f8 ARM: dts: stm32: Do clean up in stmpic nodes on stm32mp15 boards
f68e2dbc591a ARM: dts: stm32: Rename stmfx joystick pins on stm32mp157c-ev1
d6210da4f8bf ARM: dts: stm32: add cpu clock-frequency property on stm32mp15x
b65b6fc56925 ARM: dts: stm32: add wakeup-source in all I2C nodes of stm32mp157c
1c1cf5996cfb ARM: dts: stm32: add i2c4 sleep pinctrl on stm32mp157c-ed1
bef15fc0fad9 ARM: dts: stm32: add i2c2/i2c5 sleep pinctrl on stm32mp157c-ev1
b7fc0a87b9ac ARM: dts: stm32: add i2c4 sleep pinctrl on stm32mp15xx-dkx
a5e557655285 ARM: dts: stm32: set i2c4 bus freq to 400KHz on stm32mp15 DK boards
8bc631b650a6 ARM: dts: stm32: set i2c4 bus freq to 400KHz on stm32mp157c-ed1
fccd6a577bb3 ARM: dts: stm32: Correct stmfx node name on stm32mp157c-ev1 board
cc775a83db65 ARM: dts: stm32: add resets property on all DMA nodes on stm32mp151
c5fae093511b ARM: dts: stm32: enable USB OTG Dual Role on stm32mp157c-ev1
9879e2165758 ARM: dts: stm32: add USB OTG pinctrl to stm32mp15
82ac8a81f985 ARM: dts: stm32: add USB OTG full support on stm32mp151
8714b26e2863 ARM: dts: stm32: remove useless properties in stm32mp157a-avenger96 stmpic node
a7959919709e ARM: dts: stm32: Add UART8 pins A pinmux entry on stm32mp1
4d7c53a684da ARM: dts: stm32: Add USART3 pins A pinmux entry on stm32mp1
80ab128332ee ARM: dts: stm32: Add SAI2A pins B pinmux entry on stm32mp1
ab7f98c0c546 ARM: dts: stm32: Add Ethernet0 RMII pins A pinmux entry on stm32mp1

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-05-14 09:02:12 +02:00
Patrick Delaunay
dc7e5f190d arm: stm32mp: activate data cache on DDR in SPL
Activate cache on DDR to improve the accesses to DDR used by SPL:
- CONFIG_SPL_BSS_START_ADDR
- CONFIG_SYS_SPL_MALLOC_START

Cache is configured only when DDR is fully initialized,
to avoid speculative access and issue in get_ram_size().
Data cache is deactivated at the end of SPL, to flush the data cache
and the TLB.

Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-05-14 09:02:12 +02:00
Patrick Delaunay
7e8471cae5 arm: stm32mp: activate data cache in SPL and before relocation
Activate the data cache in SPL and in U-Boot before relocation.

In arch_cpu_init(), the function early_enable_caches() sets the early
TLB, early_tlb[] located .init section, and set cacheable:
- for SPL, all the SYSRAM
- for U-Boot, all the DDR

After relocation, the function enable_caches() (called by board_r)
reconfigures the MMU with new TLB location (reserved in
board_f.c::reserve_mmu) and re-enable the data cache.

This patch allows to reduce the execution time, particularly
- for the device tree parsing in U-Boot pre-reloc stage
  (dm_extended_scan_fd =>dm_scan_fdt)
- in I2C timing computation in SPL (stm32_i2c_choose_solution())

For example, the result on STM32MP157C-DK2 board is:
   1,6s gain for trusted boot chain with TF-A
   2,2s gain for basic boot chain with SPL

For information, as TLB is added in .data section, the binary size
increased and the SPL load time by ROM code increased (30ms on DK2).

But early malloc can't be used for TLB because arch_cpu_init()
is executed before the early poll initialization done in spl_common_init()
called by spl_early_init() So it too late for this use case.
And if I initialize the MMU and the cache after this function it is
too late, as dm_init_and_scan and fdt parsing is also called in
spl_common_init().

And .BSS can be used in board_init_f(): only stack and global can use
before BSS init done in board_init_r().

So .data is the better solution without hardcoded location but if you
have size issue for SPL you can deactivate cache for SPL only
(with CONFIG_SPL_SYS_DCACHE_OFF).

Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-05-14 09:02:12 +02:00
Marek Vasut
1e444bdc98 ARM: stm32: Hog GPIO PF7 high on DHCOM to unlock SPI NOR nWP
The SPI NOR nWP line is connected to GPIO PF7 on the SoM,
pull the GPIO line high by default to clear SPI NOR WP.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-05-14 09:02:12 +02:00
Marek Vasut
92ca0f7446 ARM: dts: stm32: Synchronize DDR setttings on DH SoMs
Add custom DDR DRAM settings for the DHCOR and DHCOM SoMs and put them
into use by the board file instead of the default ones. These new DRAM
settings are a better fit for the SoMs.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-05-14 09:02:12 +02:00
Marek Vasut
1ca5017418 ARM: dts: stm32: Fix AV96 and DHCOR split
The commit 132e5b6898 ("ARM: dts: stm32: Split AV96 into DHCOR SoM
and AV96 board") was not applied correctly and in full, and omitted
an important split of the SoM into 3V3 and 1V8 options. The Avenger96
board is based on the 1V8 IO option of the DHCOR SoM, however this is
an optional modification of the 3V3 IO DHCOR SoM with extra on-SoM
regulator to cater for the 96boards 1V8 IO requirements.

Reinstate the split between the 1V8 and 3V3 IO variants.

Fixes: 132e5b6898 ("ARM: dts: stm32: Split AV96 into DHCOR SoM and AV96 board")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-05-14 09:02:12 +02:00
Patrick Delaunay
414315bcdf ARM: dts: stm32mp15: use DDR3 files generated by STM32CubeMX
Use the DDR3 dtsi files generated by STM32CubeMX 5.6.0
Speed Bin Grade = using DDR3-1066G / 8-8-8 and all others
parameters at default value.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-05-14 09:02:12 +02:00
Patrick Delaunay
0c95295e17 board: stm32mp1: update management of boot-led
Force boot-led ON and no more rely on default-state.
This patch avoid device-tree modification for U-Boot.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-05-14 09:02:12 +02:00
Patrick Delaunay
eaec1f9e90 arm: stm32mp: spl: update error management in board_init_f
Call hang when an error is detected for probe of any driver
needed for console or DDR init: clk, reset and pincontrol

NB: previous behavior with a return in board_init_f() was not correct;
    DDR is not initialized and SPL execution can't continue

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-05-14 09:02:12 +02:00
Patrick Delaunay
586117ce80 arm: stm32mp: remove dependency for STM32KEY
This command is not more depending on fuse command, but have
direct access to BSEC misc driver, so the dependency with
can be removed CMD_FUSE

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-05-14 09:02:12 +02:00
Patrick Delaunay
306a5cf24f stm32mp: stm32prog: add support of RAM target
Add support of RAM target in flashlayout to load kernel image
("system") and device tree ("filesystem") in DDR with DFU and
start these images.

The flashlayout.tsv is:

-	0x01	fsbl		Binary		none	0x00000000	tf-a.stm32
-	0x03	ssbl		Binary		none	0x00000000	u-boot.stm32
P	0x10	kernel		System		ram0	0xC2000000	uImage.bin
P	0x11	dtb		FileSystem	ram0	0xC4000000	dtb.bin

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-05-14 09:02:12 +02:00
Patrick Delaunay
d0686c69ff stm32mp: stm32prog: support for script
Support an U-Boot script included in uimage instead of flashlayout file
(text file in tsv format).

This feature is used to execute this script directly when U-Boot is
loaded in DDR (for update without STM32CubeProgrammer for example).

A simple example with dfu-util only is:

$> echo "dfu 0" > script.cmd
$> mkimage -C none -A arm -T script -d script.cmd script.uimg
$> mkimage -T stm32image -a 0xC0000000 -e 0xC0000000 -d script.uimg \
  script.stm32

$> dfu-util -d 0483:df11 -a 1 -D tf-a.stm32
$> dfu-util -d 0483:df11 -a 0 -D script.stm32
$> dfu-util -d 0483:df11 -a 0 -D u-boot.stm32
$> dfu-util -d 0483:df11 -a 0 -e

Then you can used dfu-utils to update your device

To increase speed, you can also switch to fastboot protocol with:
  echo "fastboot 0" > script.cmd

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-05-14 09:02:12 +02:00
Patrick Delaunay
99d643cb41 stm32mp: stm32prog: enable videoconsole
Enable the videoconsole during the stm32prog command execution
to have information without UART.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-05-14 09:02:12 +02:00
Patrick Delaunay
468f0508b5 stm32mp: stm32prog: add serial link support
Add a support of UART, using the same protocol than MCU STM32.

See "AN5275: USB DFU/USART protocols used in STM32MP1 Series
bootloaders" for details.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-05-14 09:02:12 +02:00
Patrick Delaunay
6ce1f4ad8d stm32mp: stm32prog: add pmic NVM update support
Add a virtual partition to update the pmic non volatile memory.
(on ST board, STPMIC1).

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-05-14 09:02:12 +02:00
Patrick Delaunay
936f1aea80 stm32mp: stm32prog: add otp update support
Add a virtual partition to update the STM32MP15x OTP based
on SMC service provided by TF-A.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-05-14 09:02:12 +02:00
Patrick Delaunay
2bad5d082d stm32mp: stm32prog: add support for delete option in flashlayout
Add support for delete option 'D' in flashlayout for
full device or for partitions

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-05-14 09:02:12 +02:00
Patrick Delaunay
b83caf9fcb stm32mp: stm32prog: add support of ssbl copy
For reliability of boot from NAND/SPI-NAND (with read-disturb issue)
the SSBL can be present several time, when it is indicated in the
flashlayout with "Binary(X)".
The received binary is copied X times by U-Boot on the target.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-05-14 09:02:12 +02:00
Patrick Delaunay
8f035f7b48 stm32mp: stm32prog: adapt the MTD partitions
Dynamically adapt the MTD partitions in NOR/NAND/SPI-NAND when stm32prog
command detects in the parsed flash layout files:
- a fsbl partition in NOR.
- a tee partition in NOR/NAND/SPI-NAND

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-05-14 09:02:12 +02:00
Patrick Delaunay
eb845d6f8b stm32mp: stm32prog: add MTD devices support
Add support of MTD device (DFU_MTD backend) for
NOR, NAND or SPI-NAND target.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-05-14 09:02:12 +02:00
Patrick Delaunay
ffc405e63b stm32mp: stm32prog: add upport of partial update
Add support of partial update, update only some partitions,
and check the coherence of the layout with the existing GPT
partitions (offset and size).

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-05-14 09:02:12 +02:00
Patrick Delaunay
878f7542f1 stm32mp: stm32prog: add support of boot partition for eMMC device
Add support of eMMC device boot partition with
part_id = -1 for offset="boot1"
     or = -2 for offset="boot2"

The stm32prog command configures the MMC DFU backend with "mmcpart"
and configure the eMMC (command "mmc bootbus" and "mmc partconf")
when the update is done.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-05-14 09:02:12 +02:00
Patrick Delaunay
aff4c5dd82 stm32mp: stm32prog: add MMC device
Add support of MMC device (based on DFU_MMC backend)
for SD card and eMMC update.

Create a GPT partitioning on the device.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-05-14 09:02:12 +02:00
Patrick Delaunay
6ee6839183 stm32mp: stm32prog: add flash layout parsing
Build the list of device and of partition with
a tab separated value file with a stm32 header: the FlashLayout.tsv
(https://wiki.st.com/stm32mpu/wiki/STM32CubeProgrammer_flashlayout)

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-05-14 09:02:12 +02:00
Patrick Delaunay
954bd1a923 stm32mp: add the command stm32prog
Add a specific command stm32prog for STM32MP soc family
witch allows to program the boot devices with the tool
STM32CubeProgrammer (http://www.st.com/STM32CubeProg).

This command uses the same UART STM32 protocol than MCU
STM32 with or USB with DFU protocol v1.1 (ithe MCU ST
extension are no supported).

The executed actions are based on a tab separated value file
with a stm32 header, the FlashLayout file
(https://wiki.st.com/stm32mpu/wiki/STM32CubeProgrammer_flashlayout).

This file is parsed by the U-Boot command to:
- initialize the devices
- create the partition table on each device
- initialize the DFU backend to access to not volatile memory
  (NOR/NAND/SD/eMMC) or to virtual device (OTP/PMIC)

Up to STM32PROG_MAX_DEV (5) devices can be updated with a FlashLayout.

The communication between U-Boot and STM32CubeProgrammer is done with
the specific alternate configuration (see "AN5275: USB DFU/USART protocols
used in STM32MP1 Series bootloaders" for details).

The command stm32prog is executed when a boot from USB is detected
(selected with bootpins) and we can program the boot devices with
a simple command (on Windows or Linux):

PC $>  STM32_Programmer_CLI -c port=usb1 -w flaslayout.tsv

1/ the ROM code loads TF-A in embedded RAM (DFU or uart)
2/ TF-A loads flashlayout file and U-Boot in DDR (DFU or uart)
3/ U-Boot executes the stm32prog command (DFU or uart)

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-05-14 09:02:12 +02:00
Patrick Delaunay
7802a4495f stm32mp: add function get_cpu_dev
Add a function get_cpu_dev to get the DEV_ID present
in DBGMCU_IDC register.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-05-14 09:02:12 +02:00
Patrick Delaunay
b664a74537 board: stm32mp1: support boot from spi-nand
Manage BOOT_FLASH_SPINAND, with boot_device="spi-nand"
and treat this value in bootcmd_stm32mp.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-05-14 09:02:12 +02:00
Patrick Delaunay
4ac345220a board: stm32mp1: use FDT address provided by TF-A at boot time
Save and use the FDT address provided by TF-A in r2 at boot time
(it is NT_FW_CONFIG = Non Trusted Firmware configuration file)

Address is saved in save_boot_params(), called by start.S
and the used DTB is gd->fdt_blob = board_fdt_blob_setup().

If dtb is not provided or invalid, U-Boot use as fallback
the builtin DTB.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-05-14 09:02:12 +02:00
Patrick Delaunay
43df0a159d stm32mp1: dynamically detect op-tee presence
Activate OP-TEE driver for trusted and optee defconfig.

This driver allows detection of TEE presence for boot from flash;
CONFIG_STM32MP1_OPTEE is also removed.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-05-14 09:02:12 +02:00
Patrick Delaunay
4a1b975dac board: stm32mp1: reserve memory for OP-TEE in device tree
Add reserve memory for OP-TEE in U-Boot and in kernel device tree:
- no more reduce the DDR size in "memory" node:
  CONFIG_SYS_MEM_TOP_HIDE is no more used
- U-Boot device-tree defines the needed "reserved-memory" for OP-TEE
  and U-Boot should not use this reserved memory: board_get_usable_ram_top
  use lmb lib to found the first free region, the not reserved
  memory, enough to relocate U-Boot: the needed size of U-Boot
  is estimated with gd->mon_len + CONFIG_SYS_MALLOC_LEN.
- the optee node ("optee@...": firmware with compatible "linaro,optee-tz")
  and the associated "reserved-memory" are deactivated in kernel device
  tree when OP-TEE is not detected by U-Boot to prevent kernel issue
  (memory is reserved but not used, optee driver probe failed).

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-05-14 09:02:12 +02:00
Marek Vasut
2d68365da1 ARM: stm32: Implement DDR3 coding on DHCOR SoM
The DHCOR board does exist in multiple variants with different DDR3
DRAM sizes. To cater for all of them, implement DDR3 code handling.
There are two GPIOs which code the DRAM size populated on the SoM,
read them out and use the value to pick the correct DDR3 config.

Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
2020-05-14 09:02:12 +02:00
Marek Vasut
a8c97f4a00 ARM: dts: stm32: Rework DDR DT inclusion
Adjust the DDR configuration dtsi such that they only generate the
DRAM configuration node, the DDR controller node is moved into the
stm32mp157-u-boot.dtsi itself. This permits including multiple DDR
configuration dtsi files in board DT.

Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
2020-05-14 09:02:12 +02:00
Marek Vasut
731fd50e27 ARM: stm32: Implement board coding on AV96
The AV96 board does exist in multiple variants. To cater for all of
them, implement board code handling. There are two GPIOs which code
the type of the board, read them out and use the value to pick the
correct device tree from an fitImage.

Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Change-Id: Iddb330b9a66500495885457cbe17edc0eacaaf43
2020-05-14 09:02:12 +02:00
Marek Vasut
65e38e81ac ARM: stm32: Add board_early_init_f() to SPL
Add weak implementation of board_early_init_f() hook into the
STM32MP1 SPL. This can be used to read out e.g. configuration
straps before initializing the DRAM.

Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
2020-05-14 09:02:12 +02:00
Eugeniy Paltsev
bed6481940 ARC: HSDK: add reset for EHCI
Add reset phandle to EHCI device tree node to make on-chip reset
controller usable with EHCI.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2020-05-13 18:18:09 +03:00
Eugeniy Paltsev
d82ed6788e ARC: DTS: cleanup USB node names
Remove redundant '0x' from node names.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2020-05-13 18:15:12 +03:00
Kyle Evans
c6badda85c rpi: Kconfig option for initial page reservation
While the nearly-universal default for the Raspberry Pi family is to use
spin tables and the spin table implementation provided by the Raspberry Pi
Foundation, FreeBSD and others may use a PSCI implementation instead.

Accommodate these setups by allowing them to configure for more than one
page to be reserved in the initial reservation.  The default reservation
remains as one page.

Signed-off-by: Kyle Evans <kevans@FreeBSD.org>
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2020-05-13 14:04:49 +02:00
Tom Rini
1e6d9f515d - Enable USB Host for Odroid-C2 board
- Add Open-Drain/Open-Source emulation in GPIO uclass
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Merge tag 'u-boot-amlogic-20200511' of https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic

- Enable USB Host for Odroid-C2 board
- Add Open-Drain/Open-Source emulation in GPIO uclass
2020-05-12 09:23:15 -04:00
Simon Glass
6cbb41432d arm: dts: bcm283x: Allow UARTs to work before relocation
At present the pinctrl nodes are not enabled in pre-relocation U-Boot so
the UARTs do not correctly select the pinconfig to enable the UART pins.
Fix this so that the U-Boot banner is printed.

This fixes serial output on rpi_3b_32b with the following config.txt
options:

   enable_uart=1
   gpu_freq=250

Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes: 9821636b64 (bcm2835_pinctrl: Probe pre-reloc)
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
2020-05-12 10:59:12 +02:00
Tom Rini
bb488ac34d Merge tag 'ti-v2020.07-rc2' of https://gitlab.denx.de/u-boot/custodians/u-boot-ti
- Fix boot issues on Nokia RX-51
- Configure AM6 CPSW for 10Mbps in rgmii mode.
- Minor changes for J721e
2020-05-11 12:04:54 -04:00
Tom Rini
1bccb23b7b i.MX for 2020.07
----------------
 
 - i.MX NAND and nandbxb for i.MX8M
 - imx8MM : new beacon devkit
 - imx8MQ : new pico-imx8MQ
 - imx8QXP : extend to enable M4, fixes
 - add thermal support
 - caches in SPL (missing board)
 - Fixes
 
 Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/685391011
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Merge tag 'u-boot-imx-20200511' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

i.MX for 2020.07
----------------

- i.MX NAND and nandbxb for i.MX8M
- imx8MM : new beacon devkit
- imx8MQ : new pico-imx8MQ
- imx8QXP : extend to enable M4, fixes
- add thermal support
- caches in SPL (missing board)
- Fixes

Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/685391011
2020-05-11 09:46:43 -04:00
Neil Armstrong
9bf87e256c test: dm: update test for open-drain/open-source emulation in gpio-uclass
Add tests for testing open-drain/open-source emulation in gpio-uclass.
It also adds two test3-gpios configured as GPIO_ACTIVE_LOW.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-05-11 15:12:56 +02:00
Beniamino Galvani
375d79cdbb odroid-c2: enable USB host controller
Enable the second USB controller, which is connected to a hub with 4
ports. The first controller is for the OTG port and is currently not
supported.

Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
[narmstrong: removed useless DWC2_UTMI_WIDTH in meson64.h]
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-05-11 10:07:57 +02:00
Andrew F. Davis
b76bea1205 arm: K3: Increase default SYSFW image size allocation
The memory allocated to store the FIT image containing SYSFW and board
configuration data is statically defined to the largest size expected.
Some additions to the board configuration data has pushed us slightly
over the current defined size on some HS devices, expand to 278000.

Signed-off-by: Andrew F. Davis <afd@ti.com>
2020-05-11 10:16:49 +05:30
Jagan Teki
5a2b6778fa phy: Use _nodev naming convention if non-device clients
Clients that are requesting some of uclass API's
without a device (with ofnode) usually have _nodev
naming convention.

- clk_get_by_index_nodev
- clk_get_by_name_nodev
- reset_get_by_index_nodev
- gpio_request_by_name_nodev

So, update the same naming convention PHY framework.

This doesn't change the existing functionality.

Cc: Neil Armstrong <narmstrong@baylibre.com>
Cc: Tom Rini <trini@konsulko.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
2020-05-11 01:30:49 +05:30
Peng Fan
d52a03b130 imx8: cpu: check resource owned after sid fail
When we create software partition, we still need let parent
partition to configure sid, so move the check after sid failed.

Acked-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10 20:55:21 +02:00
Peng Fan
ed5b253d0e imx: imx8qm/qxp: check whether m4 partition booted
Add code to check m4 partition booted or not, we will use this
to runtime set device tree file that passed to Linux Kernel.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10 20:55:20 +02:00
Ye Li
42b26ddc80 imx8: Select boot device dynamically
For fspi build, we will enable both SPL NOR support and SPL SPI
support. SPL will dynamically check the resource owner then
select corresponding boot device.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10 20:55:20 +02:00
Peng Fan
6aead23323 imx: imx8qm/qxp: Recover SPL data section for partition reboot
When doing partition reboot, the boot image won't be reloaded by ROM,
it is just CPU reset to boot entry. The SW has to keep the boot image
inside the RAM unchanged. It includes both the TEXT section and DATA
section.

For SPL, the problem is DATA section will be updated at runtime, so in
next partition reboot the data is not same as the initial value from
cold boot. If any code depends on the initial value, then it will have
problem.

This patch introduces a mechanism to recover the data section
for partition reboot. It adds a new section in image for saving
data section. When from cold boot, the data section will be saved
to that new section at SPL early phase. When from partition reboot,
the data section will be restored from the new section.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10 20:55:20 +02:00
Peng Fan
231401de2e imx: imx8qm/imx8qxp: Power down the resources before SPL jump to u-boot
Make sure that all devices that are powered up by SPL are powered down
before entering into the u-boot. Otherwise the subsystem/device will
never be powered down by SCFW, due to SPL and u-boot are in different
partitions.

Benefiting from power domain driver, this patch implements the function
"imx8_power_off_pd_devices" to power off all active devices.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10 20:55:20 +02:00
Peng Fan
8103767256 imx: imx8qm/qxp: add get_board_serial
Add get_board_serial support, the info could be got from fuse.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10 20:55:20 +02:00
Ye Li
7c351ff5e0 imx: imx8qm/qxp: Fix issue in get_effective_memsize
When Trusty OS allocates the mem region from 0xfe0000000-0xffffffff,
the get_effective_memsize does not return correct memory size.
There is a check in get_effective_memsize to find the memreg where
the u-boot is running, and return the size of that memreg as the result
of get_effective_memsize. When using aligned start, the value is
0x80200000 since it is 2MB aligned. Thus the finding of memreg will
fail and return the PHYS_SDRAM_1_SIZE because u-boot text base is
0x80020000. This cause u-boot is relocated to the high memory where has
been occupied by Trusty OS.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10 20:55:20 +02:00
Peng Fan
f44afd546f imx: imx8qm/qxp: reserving DDR memory for M4
The DDR memory from 0x88000000 to 0x8FFFFFFF is assigned to M4 on
QM and QXP. The M4 can allocate this memory by two ways,
in SCD or u-boot.

In this patch, u-boot addes the memory reserve node to DTB to pass
the info to kernel, no matter the M4 memory is reserved in SCD
or u-boot. So kernel won't access M4 reserved memory.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10 20:55:20 +02:00
Han Xu
f797fe84fc nandbcb: read boot search count from fuse for imx8qxp
add support for imx8qxp to read boot search count from fuse in nandbcb

Signed-off-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10 20:55:20 +02:00
Han Xu
214b7d534d cmd: nandbcb: Reconstruct the nandbcb tool for all platforms
The original nandbcb tool was designed for imx6 only, when trying to
leverage it to replace the kobs-ng tool, we found the design is not
friendly for supporting all platforms. To support all iMX6/7/8 platforms
and for easy further maintain, I reconstruct the structure of the tool.

The main changes including:

1. Use platform_data to determine the logic branches rather than simply
   use SOC name.
2. More data structures as parameter for functions.
3. Global variables to define the FCB/DBBT/FW locations.
4. Implement the kobs-ng default 4 FCB/4 DBBT/2 FW layout.
5. Support Hamming coding/ 40bit BCH/ 62bit BCH coding FCB.
6. Dump and compare all written FCB/DBBT to verify data integrity.

The tool has been verified on iMX6Q/DL, 6SX, 7D, 6ULL, iMX8QX, iMX8MM.

Signed-off-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10 20:55:20 +02:00
Alice Guo
49f8454705 nandbcb: add nandbcb dump command for i.MX6
Verify/dump boot structures.

Signed-off-by: Alice Guo <alice.guo@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10 20:55:20 +02:00
Alice Guo
0b10337b21 nandbcb: add nandbcb dump command for i.MX8MM
Verify/dump boot structures written to NAND Flash chip.

Signed-off-by: Alice Guo <alice.guo@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10 20:55:20 +02:00
Alice Guo
66dbd9c9ed nandbcb: support i.MX8M
Tested on i.MX8MM EVK, imx8mm evk uses BCH
encoding and randomizer
modify macro and print size_t with %zx
use CONFIG_IMX8M because it should apply to imx8mq/mm/mn

Signed-off-by: Alice Guo <alice.guo@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10 20:55:20 +02:00
Han Xu
c6ed3508bd nandbcb: fix the issue cannot support gf_14 NAND boot
bchtype in FCB should be associated to the gf_13/14 settings in BCH, fix
the issue and test on Micron 29F64G08CBABB, it can boot after the
change.

Signed-off-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10 20:55:20 +02:00
Leonard Crestez
6fcb2ee783 imx8: Replace SC_R_LAST with SC_R_NONE in DTB
We are currently using SC_R_LAST as a marker for imx8 power domain tree
nodes without a resource attached. This value is compiled into dtb as
part of the linux build and used by uboot.

The SC_R_LAST constant changes frequently as SCFW resources are added
(by design) and every time we need to update linux and uboot headers
together or boot can fail.

Fix this by replacing SC_R_LAST usage with a new constant SC_R_NONE
defined to be 0xFFF0.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10 20:55:20 +02:00
Peng Fan
8c0a1c6de8 imx8: power: Add PD device lookup interface to power domain uclass
Add power_domain_lookup_name interface to power domain uclass to find
a power domain device by its DTB node name, not using its associated
client device.

Through this interface, we can operate the power domain devices directly.
This is needed for non-DM drivers.

Modified from Ye's NXP downstream patch

only for legacy imx8 power domain driver, since we have not migrated
to use new power domain driver.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10 20:55:20 +02:00
Adam Ford
f36f8bc627 imx: Add support for i.MX8MM Beacon EmbeddedWorks devkit.
Beacon EmbeddedWorks, formerly known as Logic PD, is releasing
a devkit based on the i.MX8M Mini SoC consisting of baseboard +
SOM.

It supports eMMC on the SOM, microSD on the baseboard, various
GPIO, the PINCTRL, and UART.

Signed-off-by: Adam Ford <aford173@gmail.com>
2020-05-10 20:55:20 +02:00
Peng Fan
39320e7256 mtd: nand: support GPMI NAND driver for i.MX8
enable the GPMI NAND driver for i.MX8, i.MX8 use similar controller as
i.MX8M

- register definition for i.mx8
- DMA structure must be 32bit address

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10 20:55:20 +02:00
Han Xu
17282f45ab mtd: mxs_nand: fix the gf_13/14 definition issue
gf_13/14 mask was not set correctly in register definition.

Signed-off-by: Han Xu <han.xu@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10 20:55:20 +02:00
Ye Li
ff99041b3b mxs_nand: Add support for i.MX8M
Update the gpmi/apbh_dma/bch drivers and relevant registers for i.MX8M.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10 20:55:20 +02:00
Peng Fan
29f40c07e7 nand: mxs: correct bitflip for erased NAND page
This patch is a porting of
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/
commit/?h=imx_4.1.15_1.0.0_ga&id=e4dacc44d22e9474ec456cb330df525cd805ea38
"
i.MX6QP and i.MX7D BCH module integrated a new feature to detect the
bitflip number for erased NAND page. So for these two platform, set the
erase threshold to gf/2 and if bitflip detected, GPMI driver will
correct the data to all 0xFF.

Also updated the imx6qp dts file to ditinguish the GPMI module for i.MX6Q
with the one for i.MX6QP.
"

In this patch, i.MX6UL is added and threshold changed to use ecc_strength.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10 20:55:20 +02:00
Peng Fan
dc597d1d40 imx: cpu: support tmu
Support tmu when print cpu info

Signed-off-by: peng Fan <peng.fan@nxp.com>
2020-05-10 20:55:20 +02:00
Peng Fan
ef56281cf3 imx: regs: add more fuse bank structure
Add more fuse bank structure for use.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10 20:55:20 +02:00
Ye Li
3462b55d17 imx8mp: Set default SNSR25C for TMU probe1
So far u-boot only load SNSR25C for TMU main probe (probe 0). However,
kernel enables two probes. So it also needs to set default SNSR25C of
TCALIV1 for blank samples.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10 20:55:20 +02:00
Ye Li
ebb9aab318 imx: load calibration parameters from fuse for i.MX8MP
i.MX8MP thermal which has two probes and supports temperature range
from -40 to 125.  The driver still uses default 1p HW
calibration at 25C and loads calibration parameters from fuse.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10 20:55:20 +02:00
Ye Li
94c693d782 imx: i.MX8MN: Enable loading TASR and TCALIV from fuse
Like iMX8MM, iMX8MN also needs SW to load TMU TASR and TCALIV registers
value from fuse before enabling TMU calibration. Otherwise the calibration
is not exact.

Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10 20:55:20 +02:00
Ye Li
70487ff386 imx8mm: Load fuse for TMU TCALIV and TASR
On iMX8MM, the default value of TMU registers TCALIV and TASR need
be loaded from fuse. HW won't do this, it expect SW loads them before
using TMU.

Reviewed-by: Bai Ping <ping.bai@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10 20:55:20 +02:00
Ye Li
9d4194f179 fec: Move imx_get_mac_from_fuse declare to imx file
imx_get_mac_from_fuse is used to load MAC address from fuse. On imx8mp,
we have two different ENET controllers and both need to call this
function. So decouple its declare from fec driver.

Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10 20:55:20 +02:00
Peng Fan
3c42c0f673 imx: add module fuse support
There are different parts from one SoC. Take i.MX6ULL for example,
some part might not have ENET, some might have; some might not have
USB, some might have. The information could be got from OCOTP,
to make one image support the different parts, we need runtime
disable linux kernel dts node and uboot driver probe if the
corresponding module not exists in the part.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-10 13:21:13 +02:00
Marek Vasut
b52fb0b0b5 ARM: imx: pico-imx8mq: Add support for Technexion Pico-iMX8MQ
Add initial support for Technexion Pico-iMX8MQ SoM on PicoPI carrier
board. Currently working is ethernet, serial, eMMC. DT is imported
from Linux 5.4.28 ("462afcd6e7ea") .

Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: "NXP i.MX U-Boot Team" <uboot-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
2020-05-10 13:19:39 +02:00
Stefano Babic
b77d0292ca Merge branch 'master' of git://git.denx.de/u-boot 2020-05-10 13:03:56 +02:00
Patrice Chotard
c2a2123e33 cmd: cache: Fix non-cached memory cachability
If dcache is switched OFF to ON state and if non-cached memory is
used, this non-cached memory must be re-declared as uncached to mmu
each time dcache is set ON.

Introduce noncached_set_region() to set this non-cached region's mmu
settings. Let architecture override it by defining it as a weak
function.

For ARM architecture, noncached_set_region() defines all noncached
region as non-cacheable.

Issue found on STM32MP1 platform using dwc_eth_qos ethernet driver,
when going from dcache OFF to dcache ON state, ethernet driver issued
TX timeout errors when performing dhcp or ping.

It can be reproduced with the following sequence:

dhcp
while true ; do
  ping 192.168.1.300 ;
  dcache off ;
  ping 192.168.1.300 ;
  dcache on ;
done

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Marek Vasut <marex@denx.de>
2020-05-07 09:01:42 -04:00
Andre Przywara
56e403d95f arm: juno: enable USB
The Juno board features a standard compliant EHCI/OHCI USB host
controller pair, which we can just enable.
The platform data is taken from the device tree.

This allows to use USB mass storage (the only storage on a Juno r0)
for loading.

At least on my board USB seems a bit flaky, I need two "usb reset"
sequences after the "usb start" to detect an USB hard drive.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Liviu Dudau <liviu.dudau@arm.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-05-07 09:01:42 -04:00
Andre Przywara
be0d09695d arm: juno: Use PSCI based reset
So far the Juno board wasn't implementing reset. Let's just use the
already existing PSCI_RESET based method to avoid any extra code.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Liviu Dudau <liviu.dudau@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-05-07 09:01:42 -04:00
Andre Przywara
b3270e9138 arm: juno: Enable OF_CONTROL
The Arm Juno board was still somewhat stuck in "hardcoded land", even
though there are stable DTs around, and one happens to actually be on
the memory mapped NOR flash.

Enable the configuration options to let the board use OF_CONTROL, and
add a routine to find the address of the DTB partition in NOR
flash, to use that for U-Boot's own purposes.
This can also passed on via $fdtcontroladdr to any kernel or EFI
application, removing the need to actually load a device tree.

Since the existing "afs" command and its flash routines require
flash_init() to be called before being usable, and this is done much
later in the boot process, we introduce a stripped-down partition finder
routine in vexpress64.c, to scan the NOR flash partitions for the
DT partition. This location is then used for U-Boot to find and probe
devices.

The name of the partition can be configured, if needed, but defaults
to "board.dtb", which is used by Linaro's firmware image provided.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-05-07 09:01:42 -04:00
Tom Rini
1259567ae3 Merge git://git.denx.de/u-boot-usb
- MediaTek USB host support
2020-05-05 14:53:51 -04:00
Tom Rini
191ee8aac6 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx
- Add DM model for P1010RDB
- Add I2C DM Model support for P1010RDB, T1042RDB, T2080, T4240RDB,
  MPC8548CDS, T1024RDB, P4080, P3041DS, P2041RDB, P2020RDB, P1020RDB,
  P5040DS
- Fix reference to READM.qe_firmware
2020-05-05 09:08:53 -04:00
Tom Rini
425fefa9a3 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86
- Support 64-bit U-Boot as the payload for coreboot x86
2020-05-04 11:06:14 -04:00
Tom Rini
a1f5f4ac20 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell
- 2 MVEBU related fixes
2020-05-04 11:05:48 -04:00
Tom Rini
143414c03f i.MX for 2020.07
----------------
 
 - imxrt: fix LCD clock, fix doc
 - new board: Coral Dev
 - imx8: enable Cache in SPL. SNVS, update SCFW API
 - imx8MM: fix reset, 8MQ quand and QuadLite, CPU speed grading
 - MX6ULL : is_imx6ull to include i.MX6ULZ
 - Net: add config to enable TXC delay
 
 Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/682033914
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Merge tag 'u-boot-imx-20200502' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

i.MX for 2020.07
----------------

- imxrt: fix LCD clock, fix doc
- new board: Coral Dev
- imx8: enable Cache in SPL. SNVS, update SCFW API
- imx8MM: fix reset, 8MQ quand and QuadLite, CPU speed grading
- MX6ULL : is_imx6ull to include i.MX6ULZ
- Net: add config to enable TXC delay

Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/682033914
2020-05-04 09:29:42 -04:00
Tom Rini
04da42770b Merge tag 'u-boot-rockchip-20200501' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- dts clean up to use -u-boot for px30, rk3399 boards
- dts sycn from upstream kernel for rk3328, rk3399
- add rockchip rng driver
- new board support: rk3328-roc-cc, rk3399-roc-pc,Nanopi M4 2GB
2020-05-04 07:28:14 -04:00
Simon Glass
b4d4f592b2 x86: coreboot: Allow building an SPL image
Make a few adjustments to allow us to build an SPL image for coreboot.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2020-05-04 15:28:28 +08:00
Simon Glass
fc486371c3 x86: Update SPL for coreboot
At present SPL only works on bare-metal builds. With a few tweaks it can
be used for coreboot also.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2020-05-04 15:28:28 +08:00
Simon Glass
37897c4073 x86: Move work-around out of cpu_jump_to_64bit_uboot()
At present this function copies U-Boot from the last 1MB of ROM. This is
not the right way to do it. Instead, the binman symbol should provide the
location.

But in any case the code should live in the caller,
spl_board_load_image(), so that the 64-bit jump function can be used
elsewhere. Move it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2020-05-04 15:28:28 +08:00
Simon Glass
c2018cdd71 x86: Allow building an SPL image for coreboot
Coreboot runs in 32-bit mode and cannot run a 64-bit U-Boot. To get around
this we can build a combined image with 32-bit SPL and 64-bit U-Boot. Add
a build rule and binman definition for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2020-05-04 15:28:28 +08:00
Simon Glass
7ec0e7b635 x86: Move coreboot-table detection to common 32/64-bit code
At present this function is only available in 32-bit code. Move it to the
common cpu file so it can be used by 64-bit U-Boot too.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2020-05-04 15:28:28 +08:00
Jakov Petrina
f49ac7e1c4 arm: dts: uDPU: switch default PHY speed to 3.125Gbit
This resolves issues with certain SFP modules.

Signed-off-by: Jakov Petrina <jakov.petrina@sartura.hr>
Signed-off-by: Vladimir Vid <vladimir.vid@sartura.hr>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-05-04 07:04:04 +02:00
Biwen Li
9e36eae124 powerpc: dts: p1010: add i2c node
Add i2c node of p1010

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-05-04 09:12:37 +05:30
Hou Zhiqiang
d2d019b7c3 powerpc: Enable device tree support for P1010RDB
Add device tree for P1010RDB boards and enable CONFIG_OF_CONTROL
so that device tree can be compiled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-05-04 09:12:37 +05:30
Biwen Li
d2e3f7c608 dm: powerpc: T1040/T1042: add i2c DM support
This supports i2c DM for SoC T1040/T1042

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-05-04 09:12:36 +05:30
Biwen Li
8e4be6dfb7 dm: powerpc: T2080/T2081: add i2c DM support
This supports i2c DM for SoC T2080/T2081

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-05-04 09:12:36 +05:30
Biwen Li
e6bd72f880 dm: ppc: T4240: add i2c DM support
This supports i2c DM for SoC T4240

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-05-04 09:12:36 +05:30
Biwen Li
9e9771a610 dm: powerpc: T1023/T1024: add i2c DM support
This supports i2c DM for SoC T1023/T1024

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-05-04 09:12:36 +05:30
Biwen Li
369cb88505 powerpc: dts: P4080: add i2c node
This adds i2c node for SoC P4080

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-05-04 09:12:36 +05:30
Biwen Li
0a98d5b02d powerpc: dts: P3041: add i2c node
This adds i2c node for SoC P3041

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-05-04 09:12:36 +05:30
Biwen Li
2f3bb4ab3e dm: powerpc: P2041RDB: add i2c DM support
This supports i2c DM for board P2041RDB

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-05-04 09:12:36 +05:30
Biwen Li
2563aea1ea dts: powerpc: P2020RDB: add i2c node
This adds i2c node for board P2020RDB

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-05-04 09:12:36 +05:30
Biwen Li
74014dfcd8 dm: powerpc: P1020: add i2c DM support
This supports i2c DM for SoC P1020

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-05-04 09:12:36 +05:30
Biwen Li
9919e7ea0e dm: powerpc: P5040DS: add i2c DM support
This supports i2c DM for board P5040DS

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-05-04 09:12:36 +05:30
Biwen Li
213b19054c powerpc: create dts component of i2c to build up an SoC
Provide a common i2c components that we can utilize to
build up the various device tree.

Signed-off-by: Biwen Li <biwen.li@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-05-04 09:12:36 +05:30
Frank Li
8142a97d54 cpu: imx8: show RevC instead of Rev? at boot log
Add REVC informaiton.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-03 15:45:49 +02:00
Chunfeng Yun
ba42c286f6 arm: dts: mt7629: add usb related nodes
Add usb, phy and clock nodes

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
2020-05-02 12:32:28 +02:00
Chunfeng Yun
00c82acfe9 test: dm: phy: add a test item for the phy_bulk API
Add a test item for the phy_bulk API

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
2020-05-02 12:32:28 +02:00
Chunfeng Yun
bf6ad91629 test: dm: add test item for ofnode_get_child_count()
Add a test item for ofnode_get_child_count()

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
2020-05-02 12:32:28 +02:00
Tom Rini
36c2f020f2 actions: Fix syntax for enabling SYS_RELOC_GD_ENV_ADDR
The correct syntax is 'select SYS_...' and not 'select CONFIG_SYS...'

Fixes: d5c819b885 ("actions: Move defconfig options to Kconfig")
Signed-off-by: Tom Rini <trini@konsulko.com>
2020-05-01 13:30:52 -04:00
Harald Seiler
d81a68957f imx: spl: Fix use of removed SPL_FAT_SUPPORT config
CONFIG_SPL_FAT_SUPPORT was removed in commit 0c3a9ed409
("spl: Kconfig: Replace CONFIG_SPL_FAT_SUPPORT with CONFIG_SPL_FS_FAT").
Fixup a leftover use of the symbol.

Fixes: 9d86dbd9cf ("imx: spl: implement spl_boot_mode for i.MX7/8/8M")
Signed-off-by: Harald Seiler <hws@denx.de>
2020-05-01 18:48:48 +02:00
Harald Seiler
5fc5bac67b imx: spl: Remove ifdefs in spl_mmc_boot_mode()
It is hard to read code which contains nested ifdef blocks.  Replace
them with normal if-blocks and the IS_ENABLED() macro.  This is not only
more readable but also helps as both arms are validated by the compiler
in all cases.

Signed-off-by: Harald Seiler <hws@denx.de>
2020-05-01 18:48:36 +02:00
Harald Seiler
15aec318ef Revert "imx: Introduce CONFIG_SPL_FORCE_MMC_BOOT to force MMC boot on falcon mode"
The CONFIG_SPL_FORCE_MMC_BOOT config flag is not needed as its behavior
is the correct one in all cases;  using spl_boot_device() instead of the
boot_device parameter will lead to inconsistency issues, for example,
when a board_boot_order() is defined.  In fact, this is the reason the
parameter was introduced in the first place, in commit 2b1cdafa9f
("common: Pass the boot device into spl_boot_mode()").

This reverts commit 772b55723b.

Link: https://lists.denx.de/pipermail/u-boot/2020-April/405979.html
Signed-off-by: Harald Seiler <hws@denx.de>
2020-05-01 18:47:07 +02:00
Anatolij Gustschin
a15d0aa680 imx: spl: return boot mode for asked MMC device in spl_mmc_boot_mode()
Boards may extend or re-define the boot list in their board_boot_order()
function by modifying spl_boot_list. E.g. a board might boot SPL from a
slow SPI NOR flash and then load the U-Boot from an eMMC or SD-card.
Or it might use additional MMC boot device in spl_boot_list for cases
when the image in SPI NOR flash is not found, so it could fall back to
eMMC, SD-card or another boot device.

Getting the MMC boot mode in spl_mmc will fail when we are trying to
boot from an MMC device in the spl_boot_list and the original board
boot mode (as returned by spl_boot_device()) is not an MMC boot mode.
Fix it by checking the asked MMC boot device from the spl_mmc_boot_mode()
argument.

Signed-off-by: Anatolij Gustschin <agust@denx.de>
2020-05-01 18:46:55 +02:00
Ovidiu Panait
5cf9e3b237 common/board_r: arm: Merge initr_enable_interrupts into interrupts_init
initr_enable_interrupts() is an ARM-specific wrapper over
enable_interrupts(), which is run during the common init sequence. It can
be eliminated by moving the enable_interrupts() call to the end of
interrupt_init() function, in arch/arm/lib/interrupts*.c.

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-05-01 11:34:01 -04:00
Patrick Delaunay
54be09cd8f arm: caches: manage phys_addr_t overflow in mmu_set_region_dcache_behaviour
Solved the overflow on phys_addr_t type for start + size in
mmu_set_region_dcache_behaviour() function.

This overflow is avoided by dividing start and end by 2 before addition,
and we only expecting that start and size are even.

This patch doesn't change the current function behavior if the
parameters (start or size) are not aligned on MMU_SECTION_SIZE.

For example, this overflow occurs on ARM32 with:
start = 0xC0000000 and size = 0x40000000
then start + size = 0x100000000 and end = 0x0.

For information the function behavior change with risk of regression,
if we just shift start and size before the addition.
Example with 2MB section size:
  MMU_SECTION_SIZE 0x200000 and MMU_SECTION_SHIFT = 21
  with start = 0x1000000, size = 0x1000000,
  - with the proposed patch, start = 0 and end = 0x1 as previously
  - with the more simple patch:
    end = (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT)
    the value of end change:
    start >> 21 = 0, size >> 21 = 0 and end = 0x0 !!!

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-05-01 11:34:01 -04:00
Patrick Delaunay
2e8d68e241 arm: caches: add DCACHE_DEFAULT_OPTION
Add the new flags DCACHE_DEFAULT_OPTION to define the default
option to use according the compilation flags
CONFIG_SYS_ARM_CACHE_*.

This new compilation flag allows to simplify dram_bank_mmu_setup()
and can be used as third parameter (option=dcache option to select)
of mmu_set_region_dcache_behaviour function.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-05-01 11:34:01 -04:00
Patrick Delaunay
c8ec1e3ff5 arm: caches: protect dram_bank_mmu_setup access to bi_dram
Add protection in dram_bank_mmu_setup() to avoid access to bd->bi_dram
before relocation.

This patch allow to use the generic weak function dram_bank_mmu_setup
to activate the MMU and the data cache in SPL or in U-Boot before
relocation, when bd->bi_dram is not yet initialized.

In this cases, the MMU must be initialized explicitly with
mmu_set_region_dcache_behaviour function.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-05-01 11:34:01 -04:00
Patrick Delaunay
f8dc7f2f18 configs: migrate CONFIG_SYS_ARM_CACHE_* in Kconfig
Move CONFIG_SYS_ARM_CACHE_WRITETHROUGH and
CONFIG_SYS_ARM_CACHE_WRITEALLOC into Kconfig done by moveconfig.py.

Kconfig uses a choice between the 3 values supported in U-Boot,
including the new configuration CONFIG_SYS_ARM_CACHE_WRITEBACK
(the default configuration).

The patch also avoids to select simultaneously 2 configurations.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-05-01 11:34:01 -04:00
Alifer Moraes
ef99f3d9e8 arm: imx: Add support for Google's Coral Dev Board
Add initial support for Google's Coral Dev Board based on i.MX8MQ.

https://coral.ai/products/dev-board

The Phanbell naming has been used here to match the naming convention
used in Google's U-Boot source tree:

https://coral.googlesource.com/uboot-imx/

Co-developed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Alifer Moraes <alifer.wsdm@gmail.com>
Tested-by: Marco Franchi <marcofrk@gmail.com>
2020-05-01 13:49:15 +02:00
Marek Vasut
d304e7ace3 ARM: imx8m: Fix reset in SPL on Toradex iMX8MM Verdin
Board files should not re-implement do_reset() to work around this
function not being defined in for specific configurations. Rather,
the fix is to compile in drivers which implement this properly.
This patch enables sysreset and watchdog drivers in SPL and ties
them together to implement the same as the do_reset() hack in the
board file, except correctly in the DM/DT framework.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Flavio Suligoi <f.suligoi@asem.it>
Cc: Harald Seiler <hws@denx.de>
Cc: Igor Opaniuk <igor.opaniuk@toradex.com>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Acked-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Acked-by: Igor Opaniuk <igor.opaniuk@toradex.com>
2020-05-01 13:46:22 +02:00
Marek Vasut
f24dea4e1b ARM: imx8m: Fix reset in SPL on NXP iMX8MP EVK
Board files should not re-implement do_reset() to work around this
function not being defined in for specific configurations. Rather,
the fix is to compile in drivers which implement this properly.
This patch enables sysreset and watchdog drivers in SPL and ties
them together to implement the same as the do_reset() hack in the
board file, except correctly in the DM/DT framework.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Flavio Suligoi <f.suligoi@asem.it>
Cc: Harald Seiler <hws@denx.de>
Cc: Igor Opaniuk <igor.opaniuk@toradex.com>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2020-05-01 13:46:22 +02:00
Marek Vasut
2455f91833 ARM: imx8m: Fix reset in SPL on NXP iMX8MN EVK
Board files should not re-implement do_reset() to work around this
function not being defined in for specific configurations. Rather,
the fix is to compile in drivers which implement this properly.
This patch enables sysreset and watchdog drivers in SPL and ties
them together to implement the same as the do_reset() hack in the
board file, except correctly in the DM/DT framework.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Flavio Suligoi <f.suligoi@asem.it>
Cc: Harald Seiler <hws@denx.de>
Cc: Igor Opaniuk <igor.opaniuk@toradex.com>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2020-05-01 13:46:22 +02:00
Marek Vasut
77cfd0d2b6 ARM: imx8m: Fix reset in SPL on NXP iMX8MM EVK
Board files should not re-implement do_reset() to work around this
function not being defined in for specific configurations. Rather,
the fix is to compile in drivers which implement this properly.
This patch enables sysreset and watchdog drivers in SPL and ties
them together to implement the same as the do_reset() hack in the
board file, except correctly in the DM/DT framework.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Flavio Suligoi <f.suligoi@asem.it>
Cc: Harald Seiler <hws@denx.de>
Cc: Igor Opaniuk <igor.opaniuk@toradex.com>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2020-05-01 13:46:22 +02:00
Claudius Heine
c5635a032a ARM: imx8m: Don't use the addr parameter of reset_cpu()
imx8m has the only implementation of reset_cpu() which does not ignore
the addr parameter and instead gives it some meaning as the base address
of watchdog registers.  This breaks convention with the rest of U-Boot
where the parameter is ignored and callers are passing in 0.

Fixes: d2041725e8 ("imx8m: restrict reset_cpu")
Co-developed-by: Harald Seiler <hws@denx.de>
Signed-off-by: Harald Seiler <hws@denx.de>
Signed-off-by: Claudius Heine <ch@denx.de>
2020-05-01 13:46:22 +02:00
Harald Seiler
568af92679 ARM: imx8m: Fix indentation of reset_cpu() function
Use proper code-style, tabs instead of spaces for indentation.

Signed-off-by: Harald Seiler <hws@denx.de>
2020-05-01 13:46:22 +02:00
Marek Vasut
efa1a62ad2 ARM: imx8m: Do not define do_reset() if sysreset is enabled
The SPL can also be compiled with sysreset drivers just fine, so
update the condition to cater for that option.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Flavio Suligoi <f.suligoi@asem.it>
Cc: Harald Seiler <hws@denx.de>
Cc: Igor Opaniuk <igor.opaniuk@toradex.com>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
2020-05-01 13:46:22 +02:00
Marek Vasut
dabaabd3f1 ARM: imx: imx8m: Do not warn about cpu-idle-states if missing
If the cpu-idle-states is missing from the DT in the first place, do
not fail on removing in. Just move on and do not even print an error,
since not being able to remove something which is not there in the
first place is not an error and surely does not justify failing to
boot.

Turn the surrounding prints into debugs to reduce the useless noise.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Frieder Schrempf <frieder.schrempf@kontron.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2020-05-01 13:46:22 +02:00
Adam Ford
87372fed19 arm: dts: imx8mm: sync dts from Linux Kernel 5.6.7
This patch synchronizes the device tree with that from 5.6.7.

This also adds nodes for crypto and ddrc, which makes keeping
the device tree files from individual boards in sync with the
Linux kernel.  This is helpful when boads reference those nodes.

Signed-off-by: Adam Ford <aford173@gmail.com>
2020-05-01 13:46:22 +02:00
Claudius Heine
3675d93875 imx: imx8m: Don't use the addr parameter of reset_cpu
imx8m has the only implementation of `reset_cpu` which does not ignore
the addr parameter and instead gives it some meaning as the base address
of watchdog registers.  This breaks convention with the rest of U-Boot
where the parameter is ignored and callers are passing in 0.

Fixes: d2041725e8 ("imx8m: restrict reset_cpu")
Co-Authored-by: Harald Seiler <hws@denx.de>
Signed-off-by: Claudius Heine <ch@denx.de>
Signed-off-by: Harald Seiler <hws@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
2020-05-01 13:46:22 +02:00
Claudius Heine
b46e6cc581 ARM: reset: use do_reset in SPL/TPL if SYSRESET was not enabled for them
In case CONFIG_SYSRESET is set, do_reset from reset.c will not be available
anywere, even if SYSRESET is disabled for SPL/TPL.

'do_reset' is called from SPL for instance from the panic handler and
PANIC_HANG is not set

Signed-off-by: Claudius Heine <ch@denx.de>
Reviewed-by: Marek Vasut <marex@denx.de>
2020-05-01 13:46:22 +02:00
Franck LENORMAND
242d1cd69b imx8: Configure SNVS
Add a module to configure the tamper and secure violation of
the SNVS using the SCU API.

The module also adds some commands:
 - snvs_cfg: Configure the SNVS HP and LP registers
 - snvs_dgo_cfg: Configure the SNVS DGO bloc if present (8QXP)
 - tamper_pin_cfg: Change the configuration of the tamper pins
 - snvs_clear_status: Allow to write to LPSR and LPTDSR to clear
   status bits

Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01 13:46:22 +02:00
Ye Li
73d769d8af imx8: Update SCFW API to version 1.5
Sync the latest SCFW API with below commit
6dcd0242ae7a53ac ("SCF-105: Revert accidental change") to add
interfaces for PM resource reset and read/write SNVS security
violation and tamper DGO registers.

Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01 13:46:22 +02:00
Breno Lima
f959594db2 imx8: scu api: Add support for SECO manufacturing protection APIs
SECO provides APIs to support CAAM manufacturing protection:

- sc_seco_get_mp_key()
- sc_seco_get_mp_sign()
- sc_seco_update_mpmr()

Add SCFW APIs support.

Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01 13:46:22 +02:00
Ye Li
7247974643 imx8m: Enable WDOG_B for timeout
When doing reset_cpu, in normal case the WDOG_B outputs immediately
after we clean WDA bit. But on mscale, the WDOG_B may be later than
internal reset, and cause PMIC not reset. As we enabled the SD3.0
support, the PMIC must be reset to reset SD card.

Change the reset_cpu to enable the WDOG_B for timeout as well, and set
WDOG timeout to 1s.

Reviewed-by: Fabio Estevam <festevam@gmail.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01 13:46:22 +02:00
Ye Li
1c97fcda7f imx8mm: clock: fix fracpll decode issue
The fracpll decoding is using the bit definitions for int pll. Most of
them are same, but the CLKE bit is different. Fix the wrong CLKE_MASK
for fracpll and correct all bit definitions in fracpll decoding.

Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01 13:46:22 +02:00
Peng Fan
828ad358a5 imx8: parser: fix some bad debug message formating
In SPL build, the formatting '%llx' in debug() is not supported.
Also, fix some misplaced parameters in printf.

Modified from Seb Fagard's downstream patch

Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01 13:46:22 +02:00
Seb Fagard
0e248b5f02 imx8: ahab: fix some bad debug message formating
In SPL build, the formatting '%llx' in debug() is not supported.
Also, fix some misplaced parameters in printf.

Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Seb Fagard <sebastien.fagard@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01 13:46:22 +02:00
Peng Fan
abf7752c40 imx8: ahab: fix 'end address' parameter of rm_find_memreg
parameter 'end address' must be inclusive of address range.

Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01 13:46:21 +02:00
Ye Li
a903e13f97 imx8: Change to use new SECO API commands
Latest SCFW has removed old MISC SECO commands. So update the codes
to use new SECO commands.

Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-05-01 13:46:21 +02:00
Peng Fan
b7328de6cd imx8: parser: fix 'end address' parameter of rm_find_memreg
parameter 'end address' must be inclusive of address range.

Modified from Seb's downstream patch.

Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01 13:46:21 +02:00
Ye Li
6fcd0b2388 imx8m: Dump DRAM PLL rate by clocks command
Add the dump of DRAM PLL into "clocks" command

Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
2020-05-01 13:46:21 +02:00
Peng Fan
712a341c76 imx8mq: Set ARM core clock directly from ARM PLL
For ARM core clock, there are two input branches, and can select via mux:
one from ARM PLL directly, second from CCM A53 clock root.

Currently we are using second branch. But IC confirmed the CCM A53 root
signoff timing is 1Ghz, so we should switch to input from ARM PLL directly.

This patch fixes the CORE SEL slice configuration and switch ARM clock
to ARM PLL.

Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01 13:46:21 +02:00
Ye Li
15a7426045 imx8mq: Enable eMMC HS400 and SD UHS mode on EVK
iMX8MQ EVK board has a eMMC5.0 chip and supports SD3.0, so enable the UHS
and HS400 configs to enhance the eMMC/SD access.

The change also needs to set usdhc clock to 400Mhz, and add the
off-on-delay-us to SD reset pin, otherwise some SD cards will
fail to select UHS mode in re-initialization.

Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01 13:46:21 +02:00
Peng Fan
6b87b3f4dc imx8m: update clock root and fix core_sel
Update clock root table to let it be easy to configure clock at
very early stage. Also the core_sel mux parent should be A53 CLK
root and ARM PLL.

Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01 13:46:21 +02:00
Peng Fan
a07bcec403 imx8m: acquire ATF commit hash
Acquire ATF commit hash when booting U-Boot to make user easy
to know the ATF version.

Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01 13:46:21 +02:00
Peng Fan
3f49742801 imx8: move SIP macro to common header
Move the SIP macro to common header and unify the name to
make others could reuse them.

Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01 13:46:21 +02:00
Peng Fan
9b4e197d4b imx: update is_imx6ull to include i.MX6ULZ
Update is_imx6ull helper to include i.MX6ULZ SoC. i.MX6ULZ could
share same macro, then we no need to add is_imx6ulz in various drivers.

Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01 13:46:21 +02:00
Peng Fan
c915403218 imx: imx8m: add i.MX8MN variants support
Add i.MX8MN variants support

Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01 13:46:21 +02:00
Peng Fan
cb1a1de6a0 imx: imx8m: add i.MX8MQ Dual and QuadLite support
Add i.MX8MQ Dual and QuadLite variants.

Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01 13:46:21 +02:00
Peng Fan
354dcce682 imx: cpu: support speed grade for i.MX8MP
i.MX8MP speed grade use same layout as i.MX8MN, so reuse it for i.MX8MP

Reviewed-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01 13:46:21 +02:00
Peng Fan
47586a4a55 imx8mn: Update speed grade
imx8mn speed grade fuse uses new definitions as below. So have
to update get_cpu_speed_grade_hz function to match it.

SPEED_GRADE[5:4]    SPEED_GRADE[3:0]    MHz
      xx                0000            2300
      xx                0001            2200
      xx                0010            2100
      xx                0011            2000
      xx                0100            1900
      xx                0101            1800
      xx                0110            1700
      xx                0111            1600
      xx                1000            1500
      xx                1001            1400
      xx                1010            1300
      xx                1011            1200
      xx                1100            1100
      xx                1101            1000
      xx                1110             900
      xx                1111             800

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2020-05-01 13:46:21 +02:00
Ye Li
c9a1a24be5 imx8mm: Update CPU speed grading
According to iMX8MM datasheet (IMX8MMIEC_Rev_D and IMX8MMCEC_Rev_D),
the speed grading for imx8mm is 800Mhz, 1.2Ghz, 1.6Ghz and 1.8Ghz.
Update them to get_cpu_speed_grade_hz function.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-05-01 13:46:21 +02:00
Peng Fan
499c94975e imx: fix cpu_type helper
i.MX8MP use 0x182 as its ID, so 0xff is not valid to get the cpu type,
extend it to 0x1ff.

Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-05-01 13:46:21 +02:00
Marek Vasut
126dcc925d ARM: imx: imx8mm: Add missing clock entries for FEC clock
All the FEC ethernet clock entries for iMX8MM are missing, while they
are already present on iMX8MQ. Fill in the nodes on iMX8MM, as the FEC
ethernet gets bogus clock information otherwise which makes ethernet
inoperable.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
2020-05-01 13:46:21 +02:00
Deepak Das
d597e61374 rockchip: rk3399: Add Nanopi M4 2GB board support
commit b2f5da9dd0 ("rockchip: rk3399: Add Nanopi M4 board support") added
support for Nanopi M4 board with Dual-Channel 4GB LPDDR3-1866 RAM.
This patch adds another variant of NanoPi M4 board with Dual-Channel
2GB DDR3-1866 RAM.

Signed-off-by: Deepak Das <deepakdas.linux@gmail.com>
2020-05-01 18:32:56 +08:00
Suniel Mahesh
f417d71ea7 rk3399: Add ROC-RK3399-PC Mezzanine board
Add Firefly ROC-RK3399-PC Mezzanine board which is an
extension board on top of roc-rk3399-pc.

Will drop the separate defconfig file, once we support
the board detection at runtime.

Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-01 18:32:56 +08:00
Jagan Teki
fb3f5cdbf1 arm: dts: rk3399: Sync roc-pc-mezzanine from v5.7-rc1
Sync Firefly ROC-RK3399-PC Mezzanine Board dts file
from Linux v5.7-rc1.

Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-01 18:32:56 +08:00
Jagan Teki
167efc2c7a arm64: dts: rk3399: Sync v5.7-rc1 from Linux
Sync rk3399 dts(i) files from v5.7-rc1 linux-next.

Reason:
To get updated PCIe nodes and properties on respective
dts(i) files.

Summary:
- sync won't include new board dts(i)
- sync will add required files used on respective dts(i)
- rk3399-puma-u-boot.dtsi spiflash label changed to norflash
- move puma.dtsi bios_enable into rk3399-puma-u-boot.dtsi
- move legacy max-frequency of sdhci into rk3399-u-boot.dtsi
- update cross-ec-[keyboard|sbs].dtsi path as per U-Boot
- keep roc-rk3399-pc dc_12v changes to -u-boot.dtsi

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-01 18:32:56 +08:00
Jagan Teki
f44bf1b5b1 arm64: dts: rk3399-evb: Move u-boot properties into -u-boot.dtsi
Move U-Boot specific properties into rk3399-evb u-boot
specific dtsi file.

This would help to sync the devicetrees from Linux whenever
required instead of adding specific nodes.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-01 18:32:56 +08:00
Jagan Teki
4888fbe935 arm64: dts: rk3399-puma: Move u-boot properties into -u-boot.dtsi
Move U-Boot specific properties into rk3399-puma u-boot
specific dtsi file.

This would help to sync the devicetrees from Linux whenever
required instead of adding specific nodes.

Cc: Peter Robinson <pbrobinson@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-01 18:32:56 +08:00
Chen-Yu Tsai
062baa2566 rockchip: dts: rock64: Fix XHCI usage
If the VBUS regulator is always-on, XHCI will fail to detect USB 3.0
devices; USB 2.0 devices will work however.

Make the VBUS regulator controllable and tie it to only the XHCI. This
makes all three USB ports usable.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-01 18:32:56 +08:00
Chen-Yu Tsai
bab972948e rockchip: rk3328: Add support for ROC-RK3328-CC board
The ROC-RK3328-CC from Firefly and Libre Computer Project is a credit
card size development board based on the Rockchip RK3328 SoC, with:

  - 1/2/4 GB DDR4 DRAM
  - eMMC connector for optional module
  - micro SD card slot
  - 1 x USB 3.0 host port
  - 2 x USB 2.0 host port
  - 1 x USB 2.0 OTG port
  - HDMI video output
  - TRRS connector with audio and composite video output
  - gigabit Ethernet
  - consumer IR receiver
  - debug UART pins

The ROC-RK3328-CC has the enable pin of the SD card power switch tied
to GPIO_0_D6. This pin also has the function SDMMC0_PWREN, which is
muxed by default. SDMMC0_PWREN is an active high signal controlled by
the MMC controller, however the switch enable is active low, and
pulled low (enabled) by default to make things work on boot.

As such, we need to mux away from SDMMC0_PWREN and use GPIO to enable
power to the card. The default GPIO state for the pin is pull-down and
input, which doesn't require extra configuration when paired with the
external pull-down and active low switch.

Deal with this by enabling regulator support in SPL, and setting
"u-boot,dm-spl" for the regulator and other device nodes needed for
muxing the pin.

The device tree file is synced from the Linux kernel next-20200324.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-01 18:32:56 +08:00
Chen-Yu Tsai
50cbff7cf3 rockchip: dts: rk3328: Sync device tree files from Linux
This syncs rk3328 device tree files from the Linux kernel next-20200324.
The last commit to touch these files is:

    b2411befed60 ("arm64: dts: add bus to rockchip amba nodenames")

Additional changes not yet in the Linux kernel include:

    arm64: dts: rockchip: rk3328: drop #address-cells, #size-cells from grf node
    arm64: dts: rockchip: rk3328: drop non-existent gmac2phy pinmux options
    arm64: dts: rockchip: rk3328: Replace RK805 PMIC node name with "pmic"

Changes include:

  - conversion of raw pin numbers to macros
  - removal of deprecated RK_FUNC_* macros
  - update of device tree binding headers
  - new devices
  - device tree cleanups
  - gmac2phy disabled in -u-boot.dtsi as it is not supported in U-boot

This includes a re-ordering of the USB device nodes compared to upstream
Linux, moving the dwc2 OTG controller after the EHCI/OHCI nodes. This is
currently required as otherwise the dwc2 controller would not be able to
detect devices in some cases. This may be due to lack of USB PHY support
in U-boot.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2020-05-01 18:32:56 +08:00
Chen-Yu Tsai
32fd6169a1 rockchip: dts: rk3328: Move OTG node's hnp-srp-disable to rk3328-u-boot.dtsi
The "hnp-srp-disable" property for dwc2 is specific to U-boot, not part
of upstream Linux's device tree bindings.

Move it to rk3328-u-boot.dtsi to avoid losing it when syncing device
tree files.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-05-01 18:32:56 +08:00
Chen-Yu Tsai
032ca153e2 rockchip: dts: rk3328-evb: Move gmac2io related nodes to -u-boot.dtsi
The device tree file for rk3328-evb in the Linux kernel does not have
gmac2io enabled. Instead, gmac2phy is enabled, but that is not supported
in U-boot.

Move the gmac2io related nodes to rk3328-evb-u-boot.dtsi to preserve the
current functionality. When the device tree files are synced, gmac2phy
should be marked as "broken" in -u-boot.dtsi files.

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Loic Devulder <ldevulder@suse.com>
Tested-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2020-05-01 18:32:56 +08:00
Chen-Yu Tsai
9a03177378 rockchip: dts: rk3328-evb: Move vcc5v0-host-xhci-drv to -u-boot.dtsi
USB 3.0 is only supported in U-boot, not in the Linux kernel where the
device tree files are ultimately synced from. While the xhci node was
moved, the external vbus regulator was not.

Move it as well.

Fixes: 2e91e2025c ("rockchip: rk3328: migrate u-boot node to -u-boot.dtsi")
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Loic Devulder <ldevulder@suse.com>
Tested-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2020-05-01 18:32:56 +08:00
Tom Rini
b641dd3ec8 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-spi
- distro boot support for SPI flash
- sifive spi flash driver
2020-04-30 18:05:15 -04:00
Jagan Teki
286bcdb40f sifive: fu540: Enable spi-nor flash support
HiFive Unleashed A00 support is25wp256 spi-nor flash,
So enable the same and add test result log for future
reference.

Tested on SiFive FU540 board.

Thanks to Sagar for various use cases and tests.

[QUAD mode in dt with spi-tx-bus-width: <4>]
 pp opcode      = 0x34 [QUAD MODE]
 read opcode  = 0x6c  [QUAD MODE]
 erase opcode = 0x21

SPI-NOR:
1. erase entire flash: Pass
2. write entire flash: Pass
3. read entire flash: Pass
4. cmp 32MiB read back data: Pass
5. MMC: Booted Linux and dtb from mmc

[SPI MODE in dt with spi-tx-bus-width: <1>]
pp opcode     = 0x12 [SPI MODE]
read opcode  = 0xc   [SPI MODE]
erase opcode = 0x21

SPI-NOR:
1. erase entire flash: Pass
2. write entire flash: Pass
3. read entire flash: Pass
4. cmp 32MiB read back data: Pass
5. MMC: Booted Linux and dtb from mmc

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Sagar Kadam <sagar.kadam@sifive.com>
2020-04-30 22:34:20 +05:30
Jagan Teki
0edb066ce5 riscv: dts: hifive-unleashed-a00: Add -u-boot.dtsi
Add U-Boot specific dts file for hifive-unleashed-a00, this
would help to add u-boot specific properties and other node
changes without touching the base dts(i) files which are easy
to sync from Linux.

Added spi2 alias for qspi2 as an initial u-boot specific
property change.

spi probing in current dm model is very much rely on aliases
numbering. Even though the qspi2 can't come under any associated
spi nor flash it would require to specify the same to make proper
binding happen for other spi slaves.

Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Sagar Kadam <sagar.kadam@sifive.com>
2020-04-30 22:34:20 +05:30
Tom Rini
9f0a6df3a5 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86
- DM ACPI support (Part A)
- Improve support for chain-loading x86 U-Boot
2020-04-30 13:00:20 -04:00
Tom Rini
6d7dacf726 Xilinx changes for v2020.07-rc2
mmc:
 - Fix dt property handling via generic function
 
 clk:
 - Fix versal watchdog clock setting
 
 nand:
 - Fix zynq nand command comparison
 
 xilinx:
 - Enable ubifs
 - Sync board_late_init configurations with initrd_high setup
 - Make custom distro boot more verbose
 
 zynq:
 - Kconfig alignments
 - Fix nand cse configuration
 
 zynqmp:
 - Fix zcu104 low level qspi configuration
 - Small DT updates
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Merge tag 'xilinx-for-v2020.07-rc2' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2020.07-rc2

mmc:
- Fix dt property handling via generic function

clk:
- Fix versal watchdog clock setting

nand:
- Fix zynq nand command comparison

xilinx:
- Enable ubifs
- Sync board_late_init configurations with initrd_high setup
- Make custom distro boot more verbose

zynq:
- Kconfig alignments
- Fix nand cse configuration

zynqmp:
- Fix zcu104 low level qspi configuration
- Small DT updates

Signed-off-by: Tom Rini <trini@konsulko.com>
2020-04-30 11:34:01 -04:00
Tom Rini
b9da77f195 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq
- Add DM_ETH support for DPAA1, DPAA2 based RDB platforms: ls1046ardb,
  ls1043ardb, lx2160ardb, ls2088ardb, ls1088ardb.
- Add GICv3 support for ls1028a, ls2088a, ls1088a.
- Add lpuart support on ls1028aqds.
- Few bug fixes and updates on ls2088a, ls1012a, ls1046a, ls1021a based
  platforms.
2020-04-30 10:06:54 -04:00
Simon Glass
86ee14f58b x86: Use the existing stack when chain-loading
With chromebook_coral we normally run TPL->SPL->U-Boot. This is the
'bare metal' case.

When running from coreboot we put u-boot.bin in the RW_LEGACY portion
of the image, e.g. with:

   cbfstool image-coral.serial.bin add-flat-binary -r RW_LEGACY \
	-f /tmp/b/chromebook_coral/u-boot.bin -n altfw/u-boot \
	-c lzma -l 0x1110000 -e 0x1110000

In this case U-Boot is run from coreboot (actually Depthcharge, its
payload) so we cannot access CAR. Use the existing stack instead.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-30 17:48:17 +08:00
Simon Glass
cfe7a1068b x86: Add a way to detect running from coreboot
If U-Boot is running from coreboot we need to skip low-level init. Add
an way to detect this and to set the gd flag.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-30 17:48:16 +08:00
Simon Glass
33139a0bc7 x86: Move coreboot-table detection into common code
To support detecting booting from coreboot, move the code which locates
the coreboot tables into a common place. Adjust the algorithm slightly to
use a word comparison instead of string, since it is faster.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: correct the comments to 960KB]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-30 17:47:06 +08:00
Simon Glass
526aabec24 x86: cpu: Skip init code when chain loading
When U-Boot is not the first-stage bootloader the interrupt and cache init
must be skipped, as well as init for various peripherals. Update the code
to add checks for this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-30 17:40:16 +08:00
Simon Glass
52b9beb527 x86: apl: Skip init code when chain loading
When U-Boot is not the first-stage bootloader the FSP-S init must be
skipped. Update it to add a check.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-30 17:40:16 +08:00
Simon Glass
c793dbdb90 x86: fsp: Allow skipping init code when chain loading
It is useful to be able to boot the same x86 image on a device with or
without a first-stage bootloader. For example, with chromebook_coral, it
is helpful for testing to be able to boot the same U-Boot (complete with
FSP) on bare metal and from coreboot. It allows checking of things like
CPU speed, comparing registers, ACPI tables and the like.

When U-Boot is not the first-stage bootloader much of this code is not
needed and can break booting. Add checks for this to the FSP code.

Rather than checking for the amount of available SDRAM, just use 1GB in
this situation, which should be safe. Using 2GB may run into a memory
hole on some SoCs.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-30 17:40:16 +08:00
Simon Glass
0b885bcfd9 acpi: Add an acpi command
It is useful to dump ACPI tables in U-Boot to see what has been generated.
Add a command to handle this.

To allow the command to find the tables, add a position into the global
data.

Support subcommands to list and dump the tables.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-04-30 17:16:12 +08:00
Simon Glass
7e586f6907 acpi: Put table-setup code in its own function
We always write three basic tables to ACPI at the start. Move this into
its own function, along with acpi_fill_header(), so we can write a test
for this code.

Signed-off-by: Simon Glass <sjg@chromium.org>
2020-04-30 17:16:12 +08:00
Simon Glass
29b351122e acpi: Move acpi_add_table() to generic code
Move this code to a generic location so that we can test it with sandbox.
This requires adding a few new fields to acpi_ctx, so drop the local
variables used in the original code.

Also use mapmem to avoid pointer-to-address casts which don't work on
sandbox.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-04-30 17:16:12 +08:00
Simon Glass
288edc7821 acpi: Drop code for missing XSDT from acpi_write_rsdp()
We don't actually support tables without an XSDT so we can drop this dead
code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-04-30 17:16:12 +08:00
Simon Glass
5f5ab0d3bf x86: Allow devices to write ACPI tables
Call the new core function to permit devices to write their own ACPI
tables. These tables will appear after all other tables.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-04-30 17:16:12 +08:00
Simon Glass
86e1778ded acpi: Convert part of acpi_table to use acpi_ctx
The current code uses an address but a pointer would result in fewer
casts. Also it repeats the alignment code in a lot of places so this would
be better done in a helper function.

Update write_acpi_tables() to make use of the new acpi_ctx structure,
adding a few helpers to clean things up.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-04-30 17:16:12 +08:00
Simon Glass
93f7f82782 acpi: Add a method to write tables for a device
A device may want to write out ACPI tables to describe itself to Linux.
Add a method to permit this.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
2020-04-30 17:16:12 +08:00
Tom Rini
6864fc8704 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-sh
- rmobile gen2/gen3 DTS sync and defconfig consolidation
2020-04-29 10:39:18 -04:00
Madalin Bucur
6eb32a03e0 driver: net: fm: add DM ETH support
Probe the FMan MACs based on the device tree while
retaining the legacy code/functionality.
One notable change introduced here is that, for DM_ETH,
the name of the interfaces is corrected to the fmX-macY
format, that avoids the referral to the MAC block names
which were incorrect for FMan v3 devices (i.e. DTSEC,
TGEC) and had weird formatting (i.e. FM1@DTSEC6, FM1@TGEC1).
The legacy code is left unchanged in this respect.

Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-04-29 11:10:54 +05:30
Madalin Bucur
8de6301dd8 ARM: dts: add QorIQ DPAA 1 FMan v3 to LS1046ARDB
Introduce the QorIQ DPAA 1 Frame Manager nodes in the LS1046ARDB
device tree. The device tree fragments are copied over with little
modification from the Linux kernel source code.

Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-04-29 11:10:54 +05:30
Madalin Bucur
acbb98c062 ARM: dts: add QorIQ DPAA 1 FMan v3 for LS1046A
Add the QorIQ DPAA 1 Frame Manager v3 device tree nodes for the
LS1046A SoC. The device tree fragments are copied over with little
modification from the Linux kernel source code.

Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-04-29 11:10:54 +05:30
Madalin Bucur
be1d758969 ARM: dts: add QorIQ DPAA 1 FMan v3 to LS1043ARDB
Introduce the QorIQ DPAA 1 Frame Manager nodes in the LS1043ARDB
device tree. The device tree fragments are copied over with little
modification from the Linux kernel source code.

Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-04-29 11:10:54 +05:30
Madalin Bucur
cd64b0a6d9 ARM: dts: add QorIQ DPAA 1 FMan v3 for LS1043A
Add the QorIQ DPAA 1 Frame Manager v3 device tree nodes for the
LS1043A SoC. The device tree fragments are copied over with little
modification from the Linux kernel source code.

Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-04-29 11:10:54 +05:30
Madalin Bucur
d86ab1bc05 ARM: dts: add QorIQ DPAA 1 FMan v3 device tree nodes
Add the QorIQ DPAA Frame Manager v3 device tree nodes description.
The device tree fragments are copied over with little modification
from the Linux kernel source code.

Signed-off-by: Madalin Bucur <madalin.bucur@oss.nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-04-29 11:10:54 +05:30
Yuantian Tang
e88cfb07eb armv8: ls1028aqds: add lpuart dts support
Rename fsl-ls1028a-qds.dts to fsl-ls1028a-qds.dtsi so that
it can be used as common device tree for lpuart and duart.
Add lpuart device tree and duart device tree respectively
for qds which are used with duart and lpuart console.

Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-04-29 11:10:54 +05:30
Yuantian Tang
4659eb24f1 arm: dts: ls1028a: add lpuart nodes
Add lpuart nodes to enable lpuart feature

Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-04-29 11:10:54 +05:30
Ioana Ciornei
68c7c008e8 arm: dts: ls1088ardb: add DPMAC and PHY nodes
In order to maintain compatibility with the Linux DTS, the entire fsl-mc
node is added but instead of being probed by a dedicated bus driver it
will be a simple-mfd.

Also, annotate the external MDIO nodes and describe the PHYs (8 x
VSC8514, AQR105). Also, add phy-handles for the dpmacs to their
associated PHY.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-04-29 11:10:54 +05:30
Ioana Ciornei
87274918f2 arm: dts: ls2088ardb: add DPMAC and PHY nodes
In order to maintain compatibility with the Linux DTS, the entire fsl-mc
node is added but instead of being probed by a dedicated bus driver it
will be a simple-mfd.

Also, annotate the external MDIO nodes and describe the PHYs (4 x AQR405
and 4 x CS4340). Also, add phy-handles for the dpmacs to their
associated PHY.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-04-29 11:10:54 +05:30
Ioana Ciornei
f660f7af1d arm: dts: lx2160ardb: add DPMAC and PHY nodes
In order to maintain compatibility with the Linux DTS, the entire fsl-mc
node is added but instead of being probed by a dedicated bus driver it
will be a simple-mfd.

Also, annotate the EMDIO1 node and describe the 2 AR8035 RGMII PHYs and
the 2 AQR107 PHYs. Also, add phy-handles for the dpmacs to their
associated PHY.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-04-29 11:10:54 +05:30
Ioana Ciornei
a369ee3364 arm: dts: ls1088a: add external MDIO nodes
Add the External MDIO1 device node found in the WRIOP global memory
region. This is needed for management of external PHYs.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-04-29 11:10:54 +05:30
Ioana Ciornei
0952d7cd9b arm: dts: ls2088a: add external MDIO nodes
Add the External MDIO1 device node found in the WRIOP global memory
region. This is needed for management of external PHYs.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-04-29 11:10:54 +05:30
Ioana Ciornei
8d34950238 arm: dts: lx2160a: add external MDIO nodes
Add the External MDIO device nodes found in the WRIOP global memory
region. This is needed for management of external PHYs.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-04-29 11:10:54 +05:30
Lin Jinhan
fb9230c53b arm: dts: rockchip: px30: add and enable rng node
Add enable rng node in px30-evb-u-boot.dtsi.

Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-04-29 10:30:55 +08:00
Lin Jinhan
91e858dcf6 arm: dts: rockchip: rk3399: add and enable rng node
Add rng node in rk3399-u-boot.dtsi and enable it in
rk3399-evb-u-boot.dtsi.

Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
Reviewed-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-04-29 10:30:40 +08:00
Marek Vasut
836f1ce6c7 ARM: dts: rmobile: Scrub unused DT nodes
Remove DT nodes which are not used by U-Boot, like audio and video in/out
nodes. This saves about 35 kiB on the resulting U-Boot binary without any
impact on functionality.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2020-04-29 00:28:34 +02:00
Tom Rini
306881a0bf Convert CONFIG_PHYLIB et al to Kconfig
This converts the following to Kconfig:
   CONFIG_PHYLIB
   CONFIG_BITBANGMII
   CONFIG_MV88E6352_SWITCH
   CONFIG_MV88E61XX_SWITCH
   CONFIG_PHYLIB_10G
   CONFIG_PHY_AQUANTIA
   CONFIG_PHY_ATHEROS
   CONFIG_PHY_BROADCOM
   CONFIG_PHY_CORTINA
   CONFIG_PHY_DAVICOM
   CONFIG_PHY_ET1011C
   CONFIG_PHY_LXT
   CONFIG_PHY_MARVELL
   CONFIG_PHY_MICREL
   CONFIG_PHY_NATSEMI
   CONFIG_PHY_REALTEK
   CONFIG_RTL8211X_PHY_FORCE_MASTER
   CONFIG_PHY_SMSC
   CONFIG_PHY_TERANETICS
   CONFIG_PHY_TI
   CONFIG_PHY_VITESSE
   CONFIG_PHY_XILINX

Signed-off-by: Tom Rini <trini@konsulko.com>
2020-04-28 15:57:58 -04:00
Marek Vasut
c7d681207d ARM: dts: rmobile: Synchronize Gen3 DTs with Linux 5.6.2
Synchronize R-Car Gen3 device trees with Linux 5.6.2,
commit 9fbe5c87eaa9b72db08425c52c373eb5f6537a0a .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2020-04-28 21:34:51 +02:00
Marek Vasut
329267fad2 ARM: dts: rmobile: Synchronize Gen2 DTs with Linux 5.6.2
Synchronize R-Car Gen2 device trees with Linux 5.6.2,
commit 9fbe5c87eaa9b72db08425c52c373eb5f6537a0a .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
2020-04-28 21:34:51 +02:00
Tom Rini
221c4d9826 - fix sd-emmc controller A init on G12A/G12B/SM1 SoCs
- add GXBB USB PHY driver
 - enable access to SPI NOR Flash on VIM2 and VIM3/VIM3L boards
 - fix USB PHYs Power-Up on on VIM3/VIM3L boards
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Merge tag 'u-boot-amlogic-20200428' of https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic

- fix sd-emmc controller A init on G12A/G12B/SM1 SoCs
- add GXBB USB PHY driver
- enable access to SPI NOR Flash on VIM2 and VIM3/VIM3L boards
- fix USB PHYs Power-Up on on VIM3/VIM3L boards
2020-04-28 10:09:16 -04:00
Tom Rini
b4778ae94a Merge branch 'master' of git://git.denx.de/u-boot-socfpga 2020-04-28 10:08:20 -04:00
Kever Yang
2bffb72883 rockchip: px30-evb: remove redundant include file
The file <board name>-u-boot.dtsi inculde automatically by the build
system, no need to add this to dts file.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2020-04-28 20:47:44 +08:00
Kever Yang
1e1cb9539f rockchip: px30: add -u-boot dtsi for soc
Add soc level -u-boot.dtst so that boards can share the common nodes.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
2020-04-28 20:47:44 +08:00
Hou Zhiqiang
f40b120e93 fsl-layerscape: Move GIC RD tables init to soc.c
Move GIC redistributor tables initialization to CPU setup function.

This patch introduces a GIC redistributor tables init function, and
moves the function of reserving memory for GIC redistributor tables
to soc.c and adds a argument for the memory size to reserve, BTW
rename the function so that it is more readable.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Wasim Khan <wasim.khan@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-04-28 17:46:46 +05:30
Hou Zhiqiang
0d5b0711e9 fsl-layerscape: Kconfig: Select RESV_RAM if GIC_V3_ITS
The GIC redistributor tables initialization depends on RESV_RAM config,
so select RESV_RAM if GIC_V3_ITS is enabled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Wasim Khan <wasim.khan@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-04-28 17:46:46 +05:30
Hou Zhiqiang
6ebd48835f fsl-layerscape: Add RESV_RAM check in resv_ram addr
The initialization of gd->arch.resv_ram pointer should depend on if the
RESV_RAM config is enabled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Wasim Khan <wasim.khan@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-04-28 17:46:46 +05:30
Suniel Mahesh
f9e2d9e889 arm: dts: rockchip: rk3399-roc-pc: Enable FE1.1 USB 2.0 HUB on roc-rk3399-pc
roc-rk3399-pc has an FE1.1 USB 2.0 HUB which connects two USB ports
(HOST1 and HOST2). For end devices to work we need to enable USB hub
so that HOST detects there presence and enumerates them accordingly.
This requires explicit pinctrl within gpio enablement.

Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
2020-04-28 19:39:32 +08:00
Neil Armstrong
5110963c4b arm: dts: meson-khadas-vim3: enable SPI NOR flash
Enable the SPI flash controller and reduce the usable eMMC data pins to 4
to permit using the on-board SPI NOR Flash.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-04-28 10:23:10 +02:00
Neil Armstrong
b31950743a arm: dts: meson-gxm-khadas-vim2-u-boot: enable SPI NOR flash
Activate the on-board SPI NOR Flash by enabling the SPI controller and
disabling the DS eMMC pin in the VIM2 u-boot.dtsi file.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-04-28 10:23:10 +02:00
Neil Armstrong
3a7d6a9c8f arm64: dts: meson: sync dt and bindings from v5.7-rc1
Sync the device tree and dt-bindings from Linux v5.7-rc1 8f3d9f354286
("Linux 5.7-rc1").

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-04-28 10:23:10 +02:00
Tom Rini
9b20a794a7 - brcmnand: fix missing code path from Linux driver
- bmips: fix build error when disabling USB
 - mips: add option to restore original exception vector base
 - mips: fix off-by-one error when clearing gd_data
 - mips: minor fixes for compatibility with generic SPL framework
 - spl: refactor legacy image loading
 - spl: add LZMA decompression support for legacy images
 - Makefile: add target to build LZMA compressed U-Boot images
 - mtmips: refactor and rewrite low-level init code
 - mtmips: add and enable SPL support with LZMA
 - mtmips: add support for MT7628 reference board
 - mtmips: add support for VoCore/VoCore2 board
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Merge tag 'mips-pull-2020-04-27' of https://gitlab.denx.de/u-boot/custodians/u-boot-mips

- brcmnand: fix missing code path from Linux driver
- bmips: fix build error when disabling USB
- mips: add option to restore original exception vector base
- mips: fix off-by-one error when clearing gd_data
- mips: minor fixes for compatibility with generic SPL framework
- spl: refactor legacy image loading
- spl: add LZMA decompression support for legacy images
- Makefile: add target to build LZMA compressed U-Boot images
- mtmips: refactor and rewrite low-level init code
- mtmips: add and enable SPL support with LZMA
- mtmips: add support for MT7628 reference board
- mtmips: add support for VoCore/VoCore2 board
2020-04-27 17:50:35 -04:00
Mauro Condarelli
3fd0231432 mips: Add support for SoM "VoCore2".
Small patch to add support for VoCore/VoCore2 board.

VoCore is open hardware and runs OpenWrt/LEDE.
It has WIFI, USB, UART, 20+ GPIOs but is only one inch square.
It will help you to make a smart house, study embedded system
or even make the tiniest router in the world.

Details about this SoM can be found at "https://vocore.io/v2.html".

Signed-off-by: Mauro Condarelli <mc5686@mclink.it>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-27 20:30:14 +02:00
Stefan Roese
04d21a93fa mips: mt76x8: ddr_cal: Correct dqs_find_min/max implementations
The current implementations have some issues detecting the correct
values:

dqs_find_max() will return "last passing fieldval + 1" instead of
"last passing fieldval". Also it will return "maxval + 1" in the
case that all fieldvals are tested valid (without error).

dqs_find_min() will not test the "lowest" value because of using ">"
instead of ">=".

This patch now rewrites these functions to fix those issues. Also,
this patch uses the same approach of a for loop in both functions making
it easier to read and maintain.

Since the variables are integers now, we can use min()/max(), which
handles the wrap around case for fieldval=0: return (0 - 1).

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Weijie Gao <weijie.gao@mediatek.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
2020-04-27 20:30:13 +02:00
Stefan Roese
112add362b mips: mt76x8: ddr_cal: Change types from u32 to int in dqs_find_min/max
This change is made to enable comparison of integer variables, which
might be negative in the next patch. No functional change is intended
in this patch.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Weijie Gao <weijie.gao@mediatek.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
2020-04-27 20:30:13 +02:00
Stefan Roese
896449fa29 mips: mt76x8: ddr_cal: Rename dqs_test_valid() to dqs_test_error()
This function returns "-1" (true) upon error. So the function name does
not match its implementation which is confusing. This patch renames the
function to dqs_test_error() which makes the code easier to read.

Also change the return type to bool and return "true" or "false".

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Weijie Gao <weijie.gao@mediatek.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Weijie Gao <weijie.gao@mediatek.com>
2020-04-27 20:30:13 +02:00
Weijie Gao
6bd888b63b mips: mtmips: add support for mt7628-rfb
This patch adds support for mt7628 reference board. SPL_DM and DT are not
enabled for SPL to save about 17KiB for u-boot-spl.bin.

Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2020-04-27 20:30:13 +02:00
Weijie Gao
757cbbe956 mips: mtmips: enable SPL for all boards
This patch enables SPL for all mtmips boards. And also remove defconfig
files which are intend to build ram bootable u-boot files.

SPL_DM and OF_CONTROL are enabled for both boards.

Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2020-04-27 20:30:13 +02:00
Weijie Gao
7a4b6964b5 mips: mtmips: add SPL support
This patch adds SPL support for mtmips platform. The lowlevel architecture
is split into SPL and the rest parts are built into a memory loadable
u-boot image. Optional SPL_DM and OF_CONTROL are also supported.

The increment of size is very small (< 10 KiB) if SPL_DM and OF_CONTROL are
not enabled and the memory bootable u-boot (u-boot.img) is generated
automatically so there is not need to add a separate config for it.

A lzma compressed payload (u-boot-lzma.img) is also generated and it will
be combined with u-boot-spl.bin to form the unified ROM bootable binary
u-boot-mtmips.bin.

A spl loader is added to support uncompress the payload.

Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2020-04-27 20:30:12 +02:00
Weijie Gao
02cd449f0b mips: mtmips: rewrite lowlevel codes of mt7628
This patch rewrites the mtmips architecture with the following changes:

1. Move MT7628 soc parts into a subfolder.
2. Lock parts of D-Cache as temporary stack.
3. Reimplement DDR initialization in C language.
4. Reimplement DDR calibration in a clear logic.
5. Add full support for auto size detection for DDR1 and DDR2.
6. Use accurate CPU clock depending on the input xtal frequency for timer
   and delay functions.

Note:

print_cpuinfo() has incompatible parts with MT7620 so it's moved into
mt7628 subfolder.

Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2020-04-27 20:29:33 +02:00
Weijie Gao
c95c3ec025 mips: add a option to support not reserving malloc space on initial stack
The initial stack on some platforms is too small to hold a large malloc
space. This patch adds a option to allow these platforms not reserving the
malloc space on initial stack. These platforms should set the malloc base
after DRAM is usable.

Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2020-04-27 20:29:33 +02:00
Weijie Gao
2434f58c78 mips: add an option to support initialize SRAM for initial stack
Currently CONFIG_MIPS_INIT_STACK_IN_SRAM assumes the memory space for the
initial stack can be used directly. However on some platform the SRAM needs
initialization, e.g. lock cache.

This patch adds an option to allow a new function mips_sram_init() being
called before setup_stack_gd.

Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2020-04-27 20:29:33 +02:00
Weijie Gao
df3bad96f3 dts: mtmips: add alternative pinmux node for uart2
This patch adds a new pinmux for UART2, which shares the pins with SPIS.

Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2020-04-27 20:29:33 +02:00
Weijie Gao
a60c1e6d6b mips: add a mtmips-specific field to architecture-specific global data
SoCs of mtmips can use different CPU frequencies depending on the HW/SW
configurations. For example mt7628 uses 580MHz clock if the input xtal
frequency is 40MHz, and 575MHz clock if the xtal is 25MHz. Upon cold boot
the CPU uses the xtal frequency directly.

So hardcoding the timer frequency (half of the CPU frequency) in
CONFIG_SYS_MIPS_TIMER_FREQ is not a good idea for this case.

This patch adds a mtmips-specific field timer_freq to arch_global_data.
This field will be used later in mtmips-specific get_tbclk() to provide
accurate timer frequency in different boot stage.

Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2020-04-27 20:29:33 +02:00
Weijie Gao
c366a45649 mips: mtmips: make use of sysreset-resetctrl for mt7628 soc
This patch replaces sysreset-syscon with sysreset-resetctrl for mt7628 soc.

Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2020-04-27 20:29:33 +02:00
Stefan Roese
2a9d68e41f mips: spl: Flush cache before jumping to U-Boot proper
This patch adds a MIPS specific jump_to_image_no_args() implementation,
which flushes the U-Boot proper image loaded from the boot device in
SPL before jumping to it.

It has been noticed on MT76x8, that this cache flush is needed. Other
MIPS platforms might need it as well.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Weijie Gao <weijie.gao@mediatek.com>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
2020-04-27 20:29:33 +02:00
Weijie Gao
814a8916a9 mips: add an option to enable u_boot_list section for SPL loaders in u-boot-spl.lds
u_boot_list is not only used by DM, but also by some SPL image load methods
such as spl_nor.c.

This patch adds an option CONFIG_SPL_LOADER_SUPPORT in conjunction with
CONFIG_SPL_DM surrounding the u_boot_list section to make sure SPL image
loaders can be correctly built into u-boot SPL without DM enabled.

Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2020-04-27 20:29:33 +02:00
Weijie Gao
e9511193fa mips: enable support for appending dtb to spl binary
If CONFIG_SPL_OF_CONTROL is enabled for SPL and CONFIG_OF_SEPARATE is also
enabled, the dtb will be appended to the u-boot-spl.bin.

When calling dm_init_and_scan() in SPL, fdtdec_setup() will try to locate
dtb at the end of u-boot-spl.bin, by referencing to _image_binary_end.

However _image_binary_end is currently missing in u-boot-spl.lds.
This patch adds _image_binary_end to u-boot-spl.lds to make sure linking
u-boot-spl will not fail.

Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2020-04-27 20:29:33 +02:00
Weijie Gao
6e9281b559 mips: start.S: avoid overwriting outside gd when clearing global data in stack
When setting up initial stack, global data will also be put in the stack,
and being cleared.

The assembler instructions for clearing gd is as follows:

	move	t0, k0
1:
	PTR_S	zero, 0(t0)
	blt	t0, t1, 1b
	 PTR_ADDIU t0, PTRSIZE

t0 is the start address of gd, t1 is the end address of gd (t0 + GD_SIZE).

[PTR_ADDIU t0, PTRSIZE] is in the delay slot of [blt t0, t1, 1b], so it
will be executed before the branch operation.

However the comparison for the BLT instruction is done before executing the
delay slot. This means when the last word just before k1 is cleared, the
loop will continue to run once. This will clear an extra word at k1, which
is outside the global data.

Global data is placed at the top of the stack. If the initial stack is a
SRAM or locked cache, the area outside them may be inaccessible. A write
operation performed in this area may cause an exception.

To solve this, [PTR_ADDIU t0, PTRSIZE] should be placed before the BLT
instruction.

Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2020-04-27 20:29:33 +02:00
Weijie Gao
79765201ca mips: mtmips: add predefined i-cache/d-cache size and linesize
Both mt7620 and mt7628 has the same cache configuration. There is no need
to use CONFIG_SYS_CACHE_SIZE_AUTO to probe it at runtime.

Add them into Kconfig to reduce some code size.

Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2020-04-27 20:29:33 +02:00
Weijie Gao
71059736b8 mips: add support to restore exception vector base before booting linux
In U-Boot the exception vector base will be moved to top of memory, to be
used to display register dump when exception occurs.

But some old linux kernel does not honor the base set in CP0_EBASE. A
modified exception vector base will cause kernel crash.

This patch adds an option to enable reset exception vector base to its
previous value, or a user configured value before booting linux kernel.

Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2020-04-27 20:29:33 +02:00
T Karthik Reddy
e86dce1c0c ARM: zynq: Add nand controller node in zynq-ces-nand dt
Add memory-controller@e000e000 node in zynq-ces-nand.dts as
zynq_nand driver utilizes flash@e1000000 node. Without this
dt node mini nand u-boot does not probe.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-27 14:21:18 +02:00
Michal Simek
14c0fbbc94 arm64: zynqmp: Fix irps5401 device nodes
- Do not use irps54012 as device node which is not correct.
- Fix addresses of irps5401/u180 on zcu104 revisions.
- Remove clock-cells property. It is PMIC without any clock output.
- Define irps5401 nodes in zynqmp-e-a2197

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-27 14:21:18 +02:00
Eugeniy Paltsev
73b3c23e48 ARC: AXS10x: cleanup kconfig
As we've dropped NAND support for AXS101 and AXS103
see commit 4f5e552d95 ("ARC: AXS10x: drop NAND support")
we don't need bounce buffer anymore.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2020-04-27 15:04:42 +03:00
Saeed Nowshadi
783814288b arm64: zynqmp: Add label to GPIO lines for boot mode and POR
Add label to GPIO lines controlling boot mode and POR EMIO pins so System
Controller can assert those lines on Versal.

Signed-off-by: Saeed Nowshadi <saeed.nowshadi@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-27 13:57:18 +02:00
Michal Simek
b72f450527 ARM: zynq: Setup stack size via Kconfig
Stack size has been introduced by commit a69814c815 ("arm64: zynqmp:
Set initrd_high to as high as possible") and commit 085201c246 ("arm64:
versal: Set initrd_high to as high as possible")
to support setting up initrd_high as high as possible.
The same change should happen for Zynq because the code is moved to xilinx
common location.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2020-04-27 13:53:13 +02:00
Eugeniy Paltsev
6917a9dbaf ARC: HSDK-4xD: add CSM configuration support
Add support for CSM enable/disable and CSM relocation via
hsdk_init command. We allow to relocate CSM to the beginning of
any aperture even if HW support finer granularity.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2020-04-27 11:20:27 +03:00
Eugeniy Paltsev
d4ee5c39ba ARC: HSDK-4xD: print timer clock value
Print timer clock value in hsdk_clock print_all command.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2020-04-27 11:20:26 +03:00
Eugeniy Paltsev
28db0d693f ARC: HSDK: split HSDK and HSDK-4xD DTS
Split HSDK and HSDK-4xD device tree files so they can have
different model names.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2020-04-27 11:20:26 +03:00
Eugeniy Paltsev
f0f84efe45 ARC: HSDK-4xD: add initial board support
Add initial HSDK-4xD board support.
The ARC HS4x/HS4xD Development Kit includes a multicore ARC HS4xD-based
chip that integrates a wide range of interfaces including Ethernet,
HDMI, WiFi, Bluetooth, USB, SDIO, I2C, SPI, UART, I2S, ADC, PWM and
GPIO, as well as a Think Silicon GPU.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2020-04-27 11:20:25 +03:00
Eugeniy Paltsev
61c151693b ARC: ARCv2: handle DSP presence in HW
In case of DSP extension presence in HW some instructions
(related to integer multiply, multiply-accumulate, and divide
operation) executes on this DSP execution unit. So their
execution will depend on dsp configuration register (DSP_CTRL)
As we want these instructions to execute the same way regardless
of DSP presence we need to set DSP_CTRL properly.

NOTE:
we do the same adjustments in Linux kernel, see in kernel tree:
commit 4827d0cf744e ("ARC: handle DSP presence in HW")

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2020-04-27 11:20:25 +03:00
Ley Foon Tan
b9d1671829 arm: socfpga: stratix10: Fix incorrect CLKMGR_S10_PERPLL_BYPASS offset
Offset value for CLKMGR_S10_PERPLL_BYPASS should be 0xb0, fix it.

Reported-by: Chee Hong Ang <chee.hong.ang@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-04-27 09:14:52 +02:00
Amit Singh Tomar
99d5ac6f15 arm: add Cubieboard7 board support
The Cubieboard is a single board computer containing a
Actions S700 SoC(with 4 ARMv8 Cortex-A53 cores).

This patch adds respective defconfig alongwith .dts(copied
from Linux v5.5-rc6 with hash "b3a987b0264d").

Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
2020-04-24 16:40:09 -04:00
Amit Singh Tomar
d5c819b885 actions: Move defconfig options to Kconfig
This patch moves some of the config options from bubblegum_96_defconfig
to respective Kconfig files.

Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
2020-04-24 16:40:09 -04:00
Amit Singh Tomar
78e4f4594d arm: add support Actions Semi S700
This patch adds basic support for Actions Semi based S700
SoC, which is driven by common owl framework.

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
2020-04-24 16:40:09 -04:00
Amit Singh Tomar
ea6314a797 arm: dts: actions: s700: add u-boot specific dtsi file
Devices like uart and clk are needed to be enabled before relocation.
this patch adds u-boot.dtsi file that mark these device as dm-pre-reloc.

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
2020-04-24 16:40:09 -04:00
Amit Singh Tomar
1050eaa082 arm: actions: add S700 SoC device tree
This patch adds .dtsi file(sync with Linux 5.5-rc6 with hash "b3a987b0264d")
and required binding for S700 SoC that is a 64-bit Quad-core ARM
Cortex-A53 cores.

It also provisions dts file to be built based on selected
platform(CONFIG_MACH_S900/S700).

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
2020-04-24 16:40:09 -04:00
Amit Singh Tomar
8b520ac153 clk: actions: Add common clock driver
This patch converts S900 clock driver to something common that can
be used for other SoCs, for instance S700(few of clk registers are same).

Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
2020-04-24 16:40:09 -04:00
Amit Singh Tomar
5bc4c0bccc arm: dts: actions: s900: add u-boot specific dtsi file
Devices like uart and clk are needed to be enabled before relocation.
This patch adds u-boot.dtsi file that mark these device as dm-pre-reloc.

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
2020-04-24 16:40:09 -04:00
Amit Singh Tomar
4939beea8e arm: dts: sync dts for Action Semi S900
Synchronize device tree bindings with v5.5-rc6 tag with commit id
"b3a987b0264d".

Also, it removes older clock binding defined for S900 along with undocumented
compatible string "actions,s900-serial" from serial driver and adapts clock
driver to cater to new bindings.

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
2020-04-24 16:40:09 -04:00
Amit Singh Tomar
d996f35403 arm: actions: rename sysmap-s900 to sysmap-owl
Now that memory maps(for both S700 and S900 SoCs) can be managed using
a common file, rename sysmap-s900 to sysmap-owl to reflect the same.

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
2020-04-24 16:40:09 -04:00
Amit Singh Tomar
b1a6bb3b59 arm: actions: Add common framework for Actions Owl Semi SoCs
This commit adds common arch support for Actions Semi Owl
series SoCs and removes the Bubblegum96 board files.

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
2020-04-24 16:40:09 -04:00
Ovidiu Panait
79926e4f2f common/board_f: Make reserve_mmu generic
Introduce arch_reserve_mmu to allow for architecture-specific reserve_mmu
routines. Also, define a weak nop stub for it.

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-04-24 15:17:14 -04:00
Ovidiu Panait
6184858b85 arm: asm/cache.c: Introduce arm_reserve_mmu
As a preparation for turning reserve_mmu into an arch-specific variant,
introduce arm_reserve_mmu on ARM. It implements the default routine for
reserving memory for MMU TLB and needs to be weakly defined in order to allow
for machines to override it.

Without this decoupling, after introducing arch_reserve_mmu, there would be two
weak definitions for it, one in common/board_f.c and one in
arch/arm/lib/cache.c.

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-04-24 15:17:14 -04:00
Ovidiu Panait
586b15bce8 common/board_f: Move arm-specific reserve_mmu to arch/arm/lib/cache.c
Move the ARM-specific reserve_mmu definition from common/board_f.c
to arch/arm/lib/cache.c.

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-04-24 15:17:14 -04:00
Tom Rini
4d131cdb67 - Solve stm32mp15 pinctrl dts issue (patch conflict in branches master and next)
- Split device tree for DHCOR Som and AV 96 board
 - Update PLL4 setting in AV96 board
 - Enable bootd, iminfo, imxtract on DHCOM
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Merge tag 'u-boot-stm32-20200424' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm

- Solve stm32mp15 pinctrl dts issue (patch conflict in branches master and next)
- Split device tree for DHCOR Som and AV 96 board
- Update PLL4 setting in AV96 board
- Enable bootd, iminfo, imxtract on DHCOM
2020-04-24 14:07:59 -04:00
Heinrich Schuchardt
a555557ddc qemu: don't allow to select 32- and 64-bit
TARGET_QEMU_ARM_64BIT and TARGET_QEMU_ARM_32BIT should be mutually
exclusive.

Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
2020-04-24 10:51:32 -04:00
Marek Vasut
132e5b6898 ARM: dts: stm32: Split AV96 into DHCOR SoM and AV96 board
The AV96 is in fact an assembly of DH Electronics DHCOR SoM on top
of an AV96 reference board. Split the DTs to reflect that and make
sure to DHCOR SoM can be reused on other boards easily.

It is also highly recommended to configure the board for the DHCOM
make stm32mp15_dhcom_basic_defconfig
make DEVICE_TREE=stm32mp15xx-dhcor-avenger96
as that permits reusing the board code for the DH components, like
accessing and reading out the ethernet MAC from EEPROM.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Change-Id: I7db47280d4eb0d668eb4e006355240271154f97f
2020-04-24 15:52:48 +02:00
Marek Vasut
e5899099ab ARM: dts: stm32: Adjust PLL4 settings on AV96
The PLL4 is supplying SDMMC12, SDMMC3 and SPDIF with 120 MHz and
FDCAN with 96 MHz. This isn't good for the SDMMC interfaces, which
can not easily divide the clock down to e.g. 50 MHz for high speed
SD and eMMC devices, so those devices end up running at 30 MHz as
that is 120 MHz / 4. Adjust the PLL4 settings such that both PLL4P
and PLL4R run at 100 MHz instead, which is easy to divide to 50MHz
for optimal operation of both SD and eMMC, SPDIF clock are not that
much slower and FDCAN is also unaffected.

Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-04-24 15:50:40 +02:00
Patrick Delaunay
e7a0251d50 ARM: dts: stm32mp1: remove file stm32mp157-pinctrl.dtsi
Remove the unnecessary file stm32mp157-pinctrl.dtsi and
solve all issues introduced by the commit 8914831860 ("Merge branch
 'next'") after a conflict on the patch applied in the next branch in
commit 1a4f57c895 ("ARM: dts: stm32mp1: DT alignment with Linux 5.6-rc1")

Need to reapplied on stm32mp15-pinctrl.dtsi the the 3 patches
applied previously on file "stm32mp157-pinctrl.dtsi" in v2020.04
- commit 4fdbe6487d ("ARM: dts: stm32: Add alternate pinmux for SDMMC1
 direction pins")'
- commit 5fdcba6402 ("ARM: dts: stm32: Add alternate pinmux for SDMMC2
 pins 4-7")'
- commit 955de51111 ("ARM: dts: stm32: Add alternate pinmux for ethernet
 RGMII")'

Cc: Marek Vasut <marex@denx.de>

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
2020-04-24 15:50:15 +02:00
Atish Patra
177c53fe6c riscv: Move all fdt fixups together
Keep all the fdt fixups together for better code management.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-23 10:14:16 +08:00
Atish Patra
73d756fd22 riscv: Copy the reserved-memory nodes to final DT
The DT used by U-Boot may be different from the DT being passed to
the OS if the DT is loaded from external media such as network or
mmc. In that case, the reserved-memory node needs to be copied to
the DT passed to the OS.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-23 10:14:16 +08:00
Atish Patra
0cb27856d1 riscv: Setup reserved-memory node for FU540
FU540 uses OF_SEPARATE instead of OF_PRIOR_STAGE.

Enable OF_BOARD_FIXUP to update the DT with reserved-memory node.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-23 10:14:16 +08:00
Atish Patra
d4ea649f17 riscv: Provide a mechanism to fix DT for reserved memory
In RISC-V, M-mode software can reserve physical memory regions
by setting appropriate physical memory protection (PMP) csr. As the
PMP csr are accessible only in M-mode, S-mode U-Boot can not read
this configuration directly. However, M-mode software can pass this
information via reserved-memory node in device tree so that S-mode
software can access this information.

This patch provides a framework to copy to the reserved-memory node
from one DT to another. This will be used to update the DT used by
U-Boot and the DT passed to the next stage OS.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-23 10:14:16 +08:00
Atish Patra
5370478d1c riscv: Add boot hartid to device tree
Linux booting protocol mandates that register "a0" contains the hartid.
However, U-Boot can not pass the hartid via a0 during standard UEFI
protocol. DT nodes are commonly used to pass such information to the OS.

Add a DT node under chosen node to indicate the boot hartid. EFI stub
in Linux kernel will parse this node and pass it to the real kernel
in "a0" before jumping to it.

Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-23 10:14:16 +08:00
Bin Meng
fa16ec23bc riscv: Make SBI v0.2 the default SBI version
To work with latest OpenSBI release (v0.7 or above) that has the HSM
extension support, select the SBI v0.2 support by default.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-04-23 10:14:06 +08:00
Bin Meng
ff0fa6c1b3 riscv: Add Kconfig option for SBI v0.2
SBI v0.2 is more scalable and extendable to handle future needs
for RISC-V supervisor interfaces. For example, with SBI v0.2 HSM
extension, only a single hart need to boot and enter operating
system. The booting hart can bring up secondary harts one by one
afterwards.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-04-23 10:14:06 +08:00
Bin Meng
6fa022e8fc riscv: Add SMP Kconfig option dependency for U-Boot proper
U-Boot proper running in S-mode only need SMP support when using
SBI v0.1. With SBI v0.2 HSM extension, it does not need implement
multicore boot in U-Boot proper.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-04-23 10:14:06 +08:00
Bin Meng
191636e448 riscv: Introduce SPL_SMP Kconfig option for U-Boot SPL
With SBI v0.2 HSM extension, only a single hart need to boot and
enter operating system. The booting hart can bring up secondary
harts one by one afterwards.

For U-Boot running in SPL, SMP can be turned on, while in U-Boot
proper, SMP can be optionally turned off if using SBI v0.2 HSM.

Introduce a new SPL_SMP Kconfig option to support this.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-04-23 10:14:06 +08:00
Bin Meng
84dc9d2690 riscv: Merge unnecessary SMP ifdefs in start.S
Two consecutive SMP ifdefs blocks can be combined into one.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
2020-04-23 10:14:06 +08:00
Bin Meng
ed1475e2f4 riscv: qemu: Remove the simple-bus driver for the SoC node
Prior to QEMU v3.1.0, QEMU generated the 'virt' SoC node with a
"riscv-virtio-soc" compatible string, and a "simple-bus" driver
was created to accommodate that special case in U-Boot.

Starting from QEMU v3.1.0, the SoC node was set as a "simple-bus",
hence the special simple-bus driver is no longer needed.

Update the doc to mention the latest tested QEMU version 4.2.0.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-23 10:14:06 +08:00
Pragnesh Patel
5988bb9dbf riscv: ax25: cache: Remove SPL_RISCV_MMODE config check
CONFIG_IS_ENABLED(FOO) will check FOO config option for U-Boot,
SPL and TPL, so remove unnecessary CONFIG_IS_ENABLED()

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2020-04-23 10:13:23 +08:00
Tom Rini
caad316b31 Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell
- mvebu bubt cmd: Add A38x support (Joel)
- Clearfog: Fix SCSI boot duplication (Joel)
- Armada-37xx: Fix DDR PHY clock divider values (Marek)
2020-04-22 13:00:21 -04:00
Tom Rini
2b63959e30 Merge tag 'mmc-2020-4-22' of https://gitlab.denx.de/u-boot/custodians/u-boot-mmc
- iproc_sdhci memory leak fix and enable R1B resp quirk
- more mmc cmds and several mmc updates from Heinirich
- Use bounce buffer for tmio sdhci
- Alignment check for tmio sdhci
2020-04-22 08:58:41 -04:00
Harald Seiler
c51b751893 spl: mmc: Rename spl_boot_partition() to spl_mmc_boot_partition()
This function is only relevant to the MMC driver so calling it
spl_boot_partition() might be confusing.  Rename it to
spl_mmc_boot_partition() to make its purpose more clear (and bring
it in line with spl_mmc_boot_mode()).

Signed-off-by: Harald Seiler <hws@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-04-22 20:41:57 +08:00
Harald Seiler
e97590654a spl: mmc: Rename spl_boot_mode() to spl_mmc_boot_mode()
The function's name is misleading as one might think it is used
generally to select the boot-mode when in reality it is only used by the
MMC driver to find out in what way it should try reading U-Boot Proper
from a device (either using a filesystem, a raw sector/partition, or an
eMMC boot partition).

Rename it to spl_mmc_boot_mode() to make it more obvious what this
function is about.

Link: https://lists.denx.de/pipermail/u-boot/2020-April/405979.html
Signed-off-by: Harald Seiler <hws@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
2020-04-22 20:41:57 +08:00
Joel Johnson
ab2f757eb0 arm: mvebu: correct SPL boot configs for SPI/MMC
Update mvebu SPL boot selection mechanism for the move to driver model
usage by ensuring that the required driver support for SPI and MMC
booting is available in SPL when the respective boot method is
selected.

Previously, all mvebu boards selected a boot method (implicitly
MVEBU_SPL_BOOT_DEVICE_SPI for many) even if SPL booting wasn't used.
This changes mvebu boot method selection to depend on SPL usage which
resolves the issue with aarch64 boards which don't use SPL getting an
implicit boot device selection resulting in unmet dependencies. The
32-bit arm boards do use SPL, but I'm led to conclude that most aren't
intentionally using the MVEBU_SPL_BOOT_DEVICE selection since none have
SPL_DM_SPI enabled in their defconfig even though they still implicitly
select the SPI boot method.

This also results in the new addition of SPL_GPIO_SUPPORT to helios4.
The mainline dts for helios4 includes the cd-gpios entry for sdhci with
identical addresses as the clearfog dts. I don't have a helios4 board
to confirm, but based on the current source conclude that the board
itself is either wired to pull the signal low for eMMC, or the default
MMC boot isn't fully functional in mainline. In either case, as far as
I can tell, including the GPIO support will at least cause no
regression.

Tested on SolidRun ClearFog devices.

Signed-off-by: Joel Johnson <mrjoel@lixil.net>
Reviewed-by: Stefan Roese <sr@denx.de>
2020-04-22 14:28:15 +02:00
Tom Rini
bdcb29960e Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriq
- Backplane support and bug fixes
2020-04-21 15:20:42 -04:00
Tom Rini
a063758059 Merge branch '2020-04-17-master-imports'
- Further cleanups for 'make refcheckdocs'
- Another BTRFS fix.
- Support for automatic decompression of images with booti as well as
  unlz4 command for manual decompression.
2020-04-20 17:22:47 -04:00
Tom Rini
e4837da782 - enable DM_RNG on meson boards
- fix SMBIOS info on Odroid-C2
 - Fix video output on GXBB/GXL/GXM boards
 - add USB gadget support for GXL/GXM boards
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Merge tag 'u-boot-amlogic-20200420' of https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic

- enable DM_RNG on meson boards
- fix SMBIOS info on Odroid-C2
- Fix video output on GXBB/GXL/GXM boards
- add USB gadget support for GXL/GXM boards
2020-04-20 13:44:27 -04:00
Tom Rini
62c59545ba Merge tag 'ti-v2020.07-rc1' of https://gitlab.denx.de/u-boot/custodians/u-boot-ti
- Fix boot on am335x guardian board
- Increase OPSI speed on AM65x and J721E devices
- Use JTAD register for identifying K3 devices.
- Update TI entry in MAINTAINERS file.
2020-04-20 11:14:22 -04:00
Tom Rini
d1bbf833aa Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx 2020-04-20 08:45:27 -04:00
Neil Armstrong
a19e8a0f03 arm: dts: meson-gxl: Add USB Gadget nodes for U-Boot
Add the USB DWC2 node to u-boot specific dtsi files since Gadget
support is not (yet) available in upstream Linux yet.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-04-20 14:19:10 +02:00
Neil Armstrong
dc999e5759 arm: meson-gx: add board_usb_init()/cleanup() for USB gadget
Add arch code to initialize USB Gadget mode using the DWC2 controller,
and using the previously added set_mode() phy functions.

[narmstrong: fixup board_usb_cleanup call to phy_meson_gxl_usb2_set_mode]
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-04-20 14:19:10 +02:00
Neil Armstrong
838c0af9d2 phy: meson-gxl-usb: add set_mode call to force switch to peripheral mode
Add set_mode function in the Amlogic GXL PHYs that will be called by
the arch code to switch PHYs from/to gadget mode.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2020-04-20 14:19:10 +02:00
Florinel Iordache
5d3bcdb12f phy: add support for backplane kr mode
Add generic support for backplane kr modes currently available:
10gbase-kr, 40gbase-kr4. Remove platform generic fixups
(armv8/layerscape and powerpc) for ethernet interfaces specified
in device tree as supported backplane modes.

Signed-off-by: Florinel Iordache <florinel.iordache@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-04-20 13:35:11 +05:30
Yinbo Zhu
316fc6ff76 armv8: ls1028a: define esdhc_status_fixup
This patch is to define esdhc_status_fixup function for ls1028a to disable
SDHC1/SDHC2 status in device tree node if not selected.

Signed-off-by: Yinbo Zhu <yinbo.zhu@nxp.com>
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-04-20 13:35:11 +05:30
Lokesh Vutla
e7510d443d arm: mach-k3: Use JTAD_ID register for device identification
JTAG ID register is defined by IEEE 1149.1 for device identification.
Use this JTAG ID register for identifying AM65x[0] and J721E[1] devices
instead of using SoC specific registers.

[0] http://www.ti.com/lit/ug/spruid7e/spruid7e.pdf
[1] http://www.ti.com/lit/ug/spruil1a/spruil1a.pdf

Reported-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
2020-04-19 16:20:53 +05:30
Giulio Benetti
931edc6efb Add support for i.MXRT1020-EVK board
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2020-04-18 14:55:00 +02:00
Giulio Benetti
63d4dc5846 ARM: dts: imxrt1020: add dtsi file
Add dtsi file for i.MXRT1020.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2020-04-18 14:54:44 +02:00
Giulio Benetti
07cae0d147 Add i.MXRT1020 support
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
2020-04-18 14:54:36 +02:00
Lukasz Majewski
4a45f4046b dts: imx: Add fixed-link property to HSC and DDC (imx53) devices
Those two boards are supposed to be run with a single u-boot binary.
There are notable differences though - HSC uses DSA switch (which
phy_id == 0x0) and DCC (DP83848C).

After the commit 3bf135b6c3
("drivers: net: phy: Ignore PHY ID 0 during PHY probing") the PHY devices
with phy_id == 0 are not created in U-Boot anymore. This caused regression
on HSC.

To fix this problem - the fec's 'fixed-link' node has been introduced and
the phy_id is not assessed anymore. This approach works on both boards.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
2020-04-18 13:08:18 +02:00
Harald Seiler
2c8627110e ARM: imx6: DHCOM i.MX6 PDK: Fix usb-otg VBUS regulator
During the conversion of this board to DM_REGULATOR, usb-mass-storage
was broken and started failing with the following error:

        => ums 0 mmc 2
        UMS: LUN 0, dev 2, hwpart 0, sector 0x0, count 0xe90000
        Error enabling VBUS supply
        g_dnl_register: failed!, error: -38
        g_dnl_register failed

Fix this by adding the relevant GPIO to the regulator node.

Fixes: 4ca99fe81a ("ARM: imx: dh-imx6: Enable DM regulator")
Signed-off-by: Harald Seiler <hws@denx.de>
2020-04-18 13:00:35 +02:00
Harald Seiler
15df6b31b6 ARM: imx6: DHCOM i.MX6 PDK: Convert to DM_ETH
Use DM_ETH instead of legacy networking.  Add VIO as a fixed regulator
to the relevant device-trees and augment the FEC node with properties
for the reset GPIO.

It should be noted that the relevant properties for the reset GPIO
already exist in the PHY node (reset-gpios, reset-delay-us,
reset-post-delay-us) but U-Boot currently ignores those and only
supports the bus-level reset properties in the FEC node
(phy-reset-gpios, phy-reset-duration, phy-reset-post-delay).

Signed-off-by: Harald Seiler <hws@denx.de>
2020-04-18 13:00:07 +02:00
Fabio Estevam
4c13a4db60 wandboard: Fix version detection for mx6q/mx6dl revD1
The detection of the revD1 version is based on the presence of the PMIC.

Currently revb1 device trees are used for mx6q/mx6dl variants, which
do not have the PMIC nodes.

This causes revD1 boards to be incorrectly be detected as revB1.

Fix this issue by using the revd1 device trees, so that the PMIC node can be
found and then the PMIC can be detected by reading its register ID.

Imported the revd1 device trees from mainline kernel version 5.7-rc1.

Reported-by: Heiko Schocher <hs@denx.de>
Reported-by: Derek Atkins <derek@ihtfp.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Tested-by: Derek Atkins <derek@ihtfp.com>
Tested-by: Heiko Schocher <hs@denx.de>
Tested-by: Peter Robinson <pbrobinson@gmail.com>
2020-04-18 12:59:23 +02:00
Giulio Benetti
587e09800c arch: arm: dts: imxrt1050-evk: add lcdif node
Add lcdif node and its pinctrl.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
2020-04-18 12:54:43 +02:00
Giulio Benetti
22aa286ef4 ARM: dts: imxrt1050: allow this dtsi file to be compiled in Linux
Linux doesn't provide skeleton.dtsi file so let's remove its include and
provide #address-cells/size-cells = <1> that were defined in
skeleton.dtsi before.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
2020-04-18 12:54:43 +02:00
Giulio Benetti
bb8af5fb6a ARM: dts: i.mxrt1050: add lcdif node
Add lcdif node to SoC.

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
2020-04-18 12:54:43 +02:00
Giulio Benetti
aa045701c2 video: mxsfb: add support for i.MXRT
Add support for i.MXRT by adding CONFIG_IMXRT in register structure and
adding .compatible = "fsl,imxrt-lcdif".

Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Anatolij Gustschin <agust@denx.de>
2020-04-18 12:54:43 +02:00
Michael Krummsdorf
41231dac21 arch: arm: tqma6: apply default Kconfig for device model
Signed-off-by: Michael Krummsdorf <michael.krummsdorf@ew.tq-group.com>
2020-04-17 18:58:03 +02:00
Michael Krummsdorf
acdbe52674 arm: dt: imx6qdl: add tqma6[qdl] som on mba6 mainboard
The device trees for TQMa6x SOM support variations in
- CPU type: imx6dl- or imx6q-
- MBa6 I2C bus access: -mba6a (i2c1) or -mba6b (i2c3)
  (plus the respective common/module include trees)

- USBH1 is directly connected to a hub
- USBOTG is connected to a separate connector
  and can act as host/device or full OTG port.

Signed-off-by: Michael Krummsdorf <michael.krummsdorf@ew.tq-group.com>
2020-04-17 18:57:55 +02:00
Bernhard Messerklinger
7794d889d3 arm: imx6: configure NoC on i.MX6DQP
The i.MX6DP and i.MX6QP incorporate NoC interconnect logic
which needs to be configured in order to use external DDR memory.

This patch enables the SPL to configure the necessary registers
in accordance with the NXP engineering bulletin EB828.

Co-developed-by: Filip Brozović <fbrozovic@gmail.com>

Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
Signed-off-by: Filip Brozovic <fbrozovic@gmail.com>
2020-04-17 18:56:19 +02:00
Fabio Estevam
cbc81b735e mx7ulp: Only enable LDO if it is not already enabled
LDO mode may be already enabled by the ROM and enabling it again
can cause U-Boot to hang.

Avoid this problem by only enabling LDO mode if it is initially disabled.

Reported-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Tested-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-04-17 18:54:14 +02:00
Fabio Estevam
2cfdb3bca7 mx7ulp: Remove duplicated definitions
These PMC0 definitions are already defined in the beginning
of the file, so remove the duplication.

Reported-by: Stefano Babic <sbabic@denx.de>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-04-17 18:54:04 +02:00
Sam Shih
25a1b5efb3 arm: dts: add pwm support for MediaTek SoCs
This patch add pwm support for mt7622, mt7623 and mt7629 SoCs

Signed-off-by: Sam Shih <sam.shih@mediatek.com>
2020-04-17 12:32:36 -04:00
Patrice Chotard
8ce1f10cf2 ARM: bootm: take into account gd->ram_top
If gd->ram_top has been tuned using board_get_usable_ram_top(),
it must be taken into account when reserving arch lmb.

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-04-17 12:29:43 -04:00
Patrick Delaunay
6de299230f arm: set the relocated gd with gd->new_gd
Simplify the arm relocation behavior and get gd directly form new_gd,
as it is already done in crt0_64.S:

	ldr	x18, [x18, #GD_NEW_GD]		/* x18 <- gd->new_gd */

This patch avoid assumption on new GD location (new GD is below bd -
with #GD_SIZE offset).

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-04-16 23:06:54 -04:00
Patrick Delaunay
15ac0c7500 Revert "stm32mp1: remove the imply BOOTSTAGE"
This reverts the workaround introduced by the
commit 16fec9b0bc ("stm32mp1: remove the imply BOOTSTAGE")
As the bootstage alignment issue is now solved.

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-04-16 23:06:54 -04:00
Patrick Delaunay
9d82cbd39a arm: imx: update reference to README.mxc_hab
Update reference in files detected by
scripts/documentation-file-ref-check

doc/README.mxc_hab  => doc/imx/habv4/*

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-04-16 23:06:54 -04:00
Patrick Delaunay
e5301bac5d test: pinmux: add pincontrol-gpio for pin configuration
Add a simple pincontrol associated to the sandbox gpio driver,
that allows to check pin configuration with the command pinmux.

The pinmux test is also updated to test behavior with 2 pincontrols.

Example to check LED pin configuration:

=> pinmux list
| Device                        | Driver                        | Parent
| pinctrl-gpio                  | sandbox_pinctrl_gpio          | root_driver
| pinctrl                       | sandbox_pinctrl               | root_driver

=> pinmux dev pinctrl-gpio

=> pinmux status

a0        : gpio input .
a1        : gpio input .
a2        : gpio input .
a3        : gpio input .
a4        : gpio input .
a5        : gpio output .
a6        : gpio output .
...

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-04-16 23:06:54 -04:00
Patrick Delaunay
ff52665d03 test: dm: update test for pins configuration in gpio
Add tests for new API set_dir_flags and set_dir_flags and associated
code in gpio uclass.

Test support for new flags GPIO_OPEN_DRAIN, GPIO_OPEN_SOURCE
GPIO_PULL_UP and GPIO_PULL_DOWN.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
2020-04-16 23:06:54 -04:00