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mips: reloc: Change R_MIPS_NONE to catch pre-reloc BSS usage

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This patch changes the R_MIPS_NONE define from 0 to a magic value. This
makes it possible to better detect any forbidden pre-relocation usage
of BSS variables, as they are often zero'ed and then relocation is
stopped too early.

Additionally the error message is improved to also print the faulting
address. This helps finding the root-cause for this breakage by
comparing this address with the values in System.map.

This patch helps a lot when working on pre-relocation code, like the
Octeon DDR init code, where such variables have hit me multiple times
now.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Cc: Aaron Williams <awilliams@marvell.com>
Cc: Chandrakala Chavva <cchavva@marvell.com>
This commit is contained in:
Stefan Roese 2020-06-05 10:29:25 +02:00 committed by Daniel Schwierzeck
parent a02bc1f992
commit c372813105
2 changed files with 5 additions and 4 deletions
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2
arch/mips/include/asm/relocs.h
View file

@ -8,7 +8,7 @@
#ifndef __ASM_MIPS_RELOCS_H__
#define __ASM_MIPS_RELOCS_H__
#define R_MIPS_NONE 0
#define R_MIPS_NONE 0xbeef7531
#define R_MIPS_32 2
#define R_MIPS_26 4
#define R_MIPS_HI16 5

7
arch/mips/lib/reloc.c
View file

@ -67,7 +67,7 @@ static unsigned long read_uint(uint8_t **buf)
* intentionally simple, and does the bare minimum needed to fixup the
* relocated U-Boot - in particular, it does not check for overflows.
*/
static void apply_reloc(unsigned int type, void *addr, long off)
static void apply_reloc(unsigned int type, void *addr, long off, uint8_t *buf)
{
uint32_t u32;
@ -92,7 +92,8 @@ static void apply_reloc(unsigned int type, void *addr, long off)
break;
default:
panic("Unhandled reloc type %u\n", type);
panic("Unhandled reloc type %u (@ %p), bss used before relocation?\n",
type, buf);
}
}
@ -137,7 +138,7 @@ void relocate_code(ulong start_addr_sp, gd_t *new_gd, ulong relocaddr)
break;
addr += read_uint(&buf) << 2;
apply_reloc(type, (void *)addr, off);
apply_reloc(type, (void *)addr, off, buf);
}
/* Ensure the icache is coherent */