riscv: sifive: dts: fu540: set ethernet clock rate

Set ethernet clock rate to 125 Mhz so that it will work with 1000Mbps,
Earlier this is done by FSBL. With this change We can remove the
ethernet clock rate code from FSBL.

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Pragnesh Patel 2020-05-29 11:33:32 +05:30 committed by Andes
parent 1ba43d29eb
commit 329e023868

View file

@ -82,3 +82,8 @@
&qspi2 {
u-boot,dm-spl;
};
&eth0 {
assigned-clocks = <&prci PRCI_CLK_GEMGXLPLL>;
assigned-clock-rates = <125000000>;
};