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rpi4: add a mapping for the PCIe XHCI controller MMIO registers (ARM 32bit)

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Create a non-cacheable mapping for the 0x600000000 physical memory region,
where MMIO registers for the PCIe XHCI controller are instantiated by the
PCIe bridge. Due to 32bit limit in the CPU virtual address space in ARM
32bit mode, this region is mapped at 0xff800000 CPU virtual address.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
This commit is contained in:
Marek Szyprowski 2020-06-03 14:43:44 +02:00 committed by Tom Rini
parent 221c5e42a6
commit 814e1a4b8c
3 changed files with 30 additions and 0 deletions
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1
arch/arm/mach-bcm283x/Kconfig
View file

@ -36,6 +36,7 @@ config BCM2711_32B
select BCM2711
select ARMV7_LPAE
select CPU_V7A
select PHYS_64BIT
config BCM2711_64B
bool "Broadcom BCM2711 SoC 64-bit support"

8
arch/arm/mach-bcm283x/include/mach/base.h
View file

@ -8,4 +8,12 @@
extern unsigned long rpi_bcm283x_base;
#ifdef CONFIG_ARMV7_LPAE
#ifdef CONFIG_TARGET_RPI_4_32B
#include <addr_map.h>
#define phys_to_virt addrmap_phys_to_virt
#define virt_to_phys addrmap_virt_to_phys
#endif
#endif
#endif

21
arch/arm/mach-bcm283x/init.c
View file

@ -134,6 +134,27 @@ int mach_cpu_init(void)
}
#ifdef CONFIG_ARMV7_LPAE
#ifdef CONFIG_TARGET_RPI_4_32B
#define BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT 0xff800000UL
#include <addr_map.h>
#include <asm/system.h>
void init_addr_map(void)
{
mmu_set_region_dcache_behaviour_phys(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT,
BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE,
DCACHE_OFF);
/* identity mapping for 0..BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT */
addrmap_set_entry(0, 0, BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT, 0);
/* XHCI MMIO on PCIe at BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT */
addrmap_set_entry(BCM2711_RPI4_PCIE_XHCI_MMIO_VIRT,
BCM2711_RPI4_PCIE_XHCI_MMIO_PHYS,
BCM2711_RPI4_PCIE_XHCI_MMIO_SIZE, 1);
}
#endif
void enable_caches(void)
{
dcache_enable();