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powerpc: Remove T1040QDS_DDR4_defconfig board
DM_SPI and other driver model migration deadlines are expired for this board. Remove it. Patch-cc: Poonam Aggrwal <poonam.aggrwal@nxp.com> Patch-cc: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
This commit is contained in:
Jagan Teki
parent
7723a6deb7
commit
ce17d99d12
21 changed files with 0 additions and 2540 deletions
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@ -225,16 +225,6 @@ config TARGET_T1024RDB
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imply CMD_EEPROM
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imply PANIC_HANG
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config TARGET_T1040QDS
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bool "Support T1040QDS"
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select ARCH_T1040
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select BOARD_LATE_INIT if CHAIN_OF_TRUST
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select PHYS_64BIT
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select FSL_DDR_INTERACTIVE
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imply CMD_EEPROM
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imply CMD_SATA
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imply PANIC_HANG
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config TARGET_T1040RDB
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bool "Support T1040RDB"
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select ARCH_T1040
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@ -1545,7 +1535,6 @@ source "board/freescale/p1_twr/Kconfig"
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source "board/freescale/p2041rdb/Kconfig"
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source "board/freescale/qemu-ppce500/Kconfig"
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source "board/freescale/t102xrdb/Kconfig"
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source "board/freescale/t1040qds/Kconfig"
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source "board/freescale/t104xrdb/Kconfig"
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source "board/freescale/t208xqds/Kconfig"
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source "board/freescale/t208xrdb/Kconfig"
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@ -1,14 +0,0 @@
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if TARGET_T1040QDS
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config SYS_BOARD
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default "t1040qds"
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config SYS_VENDOR
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default "freescale"
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config SYS_CONFIG_NAME
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default "T1040QDS"
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source "board/freescale/common/Kconfig"
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endif
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@ -1,12 +0,0 @@
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T1040QDS BOARD
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M: Poonam Aggrwal <poonam.aggrwal@nxp.com>
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S: Maintained
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F: board/freescale/t1040qds/
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F: include/configs/T1040QDS.h
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F: configs/T1040QDS_defconfig
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F: configs/T1040QDS_DDR4_defconfig
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T1040QDS_SECURE_BOOT BOARD
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M: Ruchika Gupta <ruchika.gupta@nxp.com>
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S: Maintained
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F: configs/T1040QDS_SECURE_BOOT_defconfig
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@ -1,11 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright 2013 Freescale Semiconductor, Inc.
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obj-y += t1040qds.o
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obj-y += ddr.o
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obj-$(CONFIG_PCI) += pci.o
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obj-y += law.o
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obj-y += tlb.o
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obj-y += eth.o
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obj-y += diu.o
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@ -1,169 +0,0 @@
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Overview
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--------
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The T1040QDS is a Freescale reference board that hosts the T1040 SoC
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(and variants).
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T1040 SoC Overview
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------------------
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The QorIQ T1040/T1042 processor support four integrated 64-bit e5500 PA
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processor cores with high-performance data path acceleration architecture
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and network peripheral interfaces required for networking & telecommunications.
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The T1040/T1042 SoC includes the following function and features:
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- Four e5500 cores, each with a private 256 KB L2 cache
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- 256 KB shared L3 CoreNet platform cache (CPC)
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- Interconnect CoreNet platform
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- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
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support
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- Data Path Acceleration Architecture (DPAA) incorporating acceleration
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for the following functions:
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- Packet parsing, classification, and distribution
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- Queue management for scheduling, packet sequencing, and congestion
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management
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- Cryptography Acceleration (SEC 5.0)
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- RegEx Pattern Matching Acceleration (PME 2.2)
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- IEEE Std 1588 support
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- Hardware buffer management for buffer allocation and deallocation
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- Ethernet interfaces
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- Integrated 8-port Gigabit Ethernet switch (T1040 only)
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- Four 1 Gbps Ethernet controllers
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- Two RGMII interfaces or one RGMII and one MII interfaces
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- High speed peripheral interfaces
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- Four PCI Express 2.0 controllers running at up to 5 GHz
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- Two SATA controllers supporting 1.5 and 3.0 Gb/s operation
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- Upto two QSGMII interface
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- Upto six SGMII interface supporting 1000 Mbps
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- One SGMII interface supporting upto 2500 Mbps
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- Additional peripheral interfaces
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- Two USB 2.0 controllers with integrated PHY
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- SD/eSDHC/eMMC
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- eSPI controller
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- Four I2C controllers
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- Four UARTs
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- Four GPIO controllers
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- Integrated flash controller (IFC)
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- LCD and HDMI interface (DIU) with 12 bit dual data rate
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- TDM interface
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- Multicore programmable interrupt controller (PIC)
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- Two 8-channel DMA engines
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- Single source clocking implementation
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- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
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T1040QDS board Overview
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-----------------------
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- SERDES Connections, 8 lanes supporting:
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— PCI Express: supporting Gen 1 and Gen 2;
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— SGMII
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— QSGMII
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— SATA 2.0
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— Aurora debug with dedicated connectors (T1040 only)
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- DDR Controller
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- Supports rates of up to 1600 MHz data-rate
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- Supports one DDR3LP UDIMM/RDIMMs, of single-, dual- or quad-rank types.
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-IFC/Local Bus
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- NAND flash: 8-bit, async, up to 2GB.
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- NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB
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- GASIC: Simple (minimal) target within Qixis FPGA
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- PromJET rapid memory download support
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- Ethernet
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- Two on-board RGMII 10/100/1G ethernet ports.
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- PHY #0 remains powered up during deep-sleep (T1040 only)
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- QIXIS System Logic FPGA
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- Clocks
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- System and DDR clock (SYSCLK, “DDRCLK”)
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- SERDES clocks
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- Power Supplies
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- Video
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- DIU supports video at up to 1280x1024x32bpp
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- USB
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- Supports two USB 2.0 ports with integrated PHYs
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— Two type A ports with 5V@1.5A per port.
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— Second port can be converted to OTG mini-AB
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- SDHC
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- SDHC port connects directly to an adapter card slot, featuring:
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- Supporting SD slots for: SD, SDHC (1x, 4x, 8x) and/or MMC
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— Supporting eMMC memory devices
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- SPI
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- On-board support of 3 different devices and sizes
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- Other IO
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- Two Serial ports
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- ProfiBus port
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- Four I2C ports
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Memory map on T1040QDS
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----------------------
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The addresses in brackets are physical addresses.
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Start Address End Address Description Size
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0xF_FFDF_0000 0xF_FFDF_0FFF IFC - FPGA 4KB
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0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
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0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
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0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB
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0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
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0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
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0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
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0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
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0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
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0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
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0xF_E000_0000 0xF_E7FF_FFFF Promjet 128MB
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0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
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0xC_3000_0000 0xC_3FFF_FFFF PCI Express 4 Mem Space 256MB
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0xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB
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0xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB
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0xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space 256MB
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0x0_0000_0000 0x0_ffff_ffff DDR 2GB
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NOR Flash memory Map on T1040QDS
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--------------------------------
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Start End Definition Size
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0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB
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0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB
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0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
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0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB
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0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB
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0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB
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0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
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0xEBF40000 0xEBFFFFFF U-Boot (alt bank) 768KB
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0xEBF20000 0xEBF3FFFF U-Boot env (alt bank) 128KB
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0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
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0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB
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0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 11MB + 512KB
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0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
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0xE8000000 0xE801FFFF RCW (current bank) 128KB
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Various Software configurations/environment variables/commands
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--------------------------------------------------------------
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The below commands apply to T1040QDS
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1. U-Boot environment variable hwconfig
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The default hwconfig is:
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hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;usb1:
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dr_mode=host,phy_type=utmi
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Note: For USB gadget set "dr_mode=peripheral"
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2. FMAN Ucode versions
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fsl_fman_ucode_t1040.bin
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3. Switching to alternate bank
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Commands for switching to alternate bank.
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1. To change from vbank0 to vbank4
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=> qixis_reset altbank (it will boot using vbank4)
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2.To change from vbank4 to vbank0
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=> qixis reset (it will boot using vbank0)
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T1040 Personality
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--------------------
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T1022 Personality
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--------------------
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T1022 is a reduced personality of T1040 with less core/clusters.
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T1042 Personality
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--------------------
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T1042 is a reduced personality of T1040 without Integrated 8-port Gigabit
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Ethernet switch. Rest of the blocks are same as T1040
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@ -1,142 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2013-2014 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <i2c.h>
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#include <hwconfig.h>
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#include <init.h>
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#include <log.h>
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#include <asm/mmu.h>
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#include <fsl_ddr_sdram.h>
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#include <fsl_ddr_dimm_params.h>
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#include <asm/fsl_law.h>
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#include <asm/mpc85xx_gpio.h>
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#include <linux/delay.h>
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#include "ddr.h"
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DECLARE_GLOBAL_DATA_PTR;
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void fsl_ddr_board_options(memctl_options_t *popts,
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dimm_params_t *pdimm,
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unsigned int ctrl_num)
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{
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const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
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ulong ddr_freq;
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if (ctrl_num > 2) {
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printf("Not supported controller number %d\n", ctrl_num);
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return;
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}
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if (!pdimm->n_ranks)
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return;
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pbsp = udimms[0];
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/* Get clk_adjust, cpo, write_data_delay,2t, according to the board ddr
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* freqency and n_banks specified in board_specific_parameters table.
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*/
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ddr_freq = get_ddr_freq(0) / 1000000;
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while (pbsp->datarate_mhz_high) {
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if (pbsp->n_ranks == pdimm->n_ranks &&
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(pdimm->rank_density >> 30) >= pbsp->rank_gb) {
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if (ddr_freq <= pbsp->datarate_mhz_high) {
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popts->clk_adjust = pbsp->clk_adjust;
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popts->wrlvl_start = pbsp->wrlvl_start;
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popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
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popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
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goto found;
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}
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pbsp_highest = pbsp;
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}
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pbsp++;
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}
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if (pbsp_highest) {
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printf("Error: board specific timing not found\n");
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printf("for data rate %lu MT/s\n", ddr_freq);
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printf("Trying to use the highest speed (%u) parameters\n",
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pbsp_highest->datarate_mhz_high);
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popts->clk_adjust = pbsp_highest->clk_adjust;
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popts->wrlvl_start = pbsp_highest->wrlvl_start;
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popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
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popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
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} else {
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panic("DIMM is not supported by this board");
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}
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found:
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debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
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"\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, "
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"wrlvl_ctrl_3 0x%x\n",
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pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
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pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
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pbsp->wrlvl_ctl_3);
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/*
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* Factors to consider for half-strength driver enable:
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* - number of DIMMs installed
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*/
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popts->half_strength_driver_enable = 1;
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/*
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* Write leveling override
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*/
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popts->wrlvl_override = 1;
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popts->wrlvl_sample = 0xf;
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/*
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* rtt and rtt_wr override
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*/
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popts->rtt_override = 0;
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/* Enable ZQ calibration */
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popts->zq_en = 1;
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/* DHC_EN =1, ODT = 75 Ohm */
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#ifdef CONFIG_SYS_FSL_DDR4
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popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
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popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
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DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
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/* optimize cpo for erratum A-009942 */
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popts->cpo_sample = 0x69;
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#else
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popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
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popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
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#endif
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}
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#if defined(CONFIG_DEEP_SLEEP)
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void board_mem_sleep_setup(void)
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{
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void __iomem *qixis_base = (void *)QIXIS_BASE;
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/* does not provide HW signals for power management */
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clrbits_8(qixis_base + 0x21, 0x2);
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/* Disable MCKE isolation */
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gpio_set_value(2, 0);
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udelay(1);
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}
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#endif
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int dram_init(void)
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{
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phys_size_t dram_size;
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puts("Initializing....using SPD\n");
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dram_size = fsl_ddr_sdram();
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dram_size = setup_ddr_tlbs(dram_size / 0x100000);
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dram_size *= 0x100000;
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puts(" DDR: ");
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#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
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fsl_dp_resume();
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#endif
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gd->ram_size = dram_size;
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return 0;
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}
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@ -1,52 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2013-2014 Freescale Semiconductor, Inc.
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*/
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#ifndef __DDR_H__
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#define __DDR_H__
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struct board_specific_parameters {
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u32 n_ranks;
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u32 datarate_mhz_high;
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u32 rank_gb;
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u32 clk_adjust;
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u32 wrlvl_start;
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u32 wrlvl_ctl_2;
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u32 wrlvl_ctl_3;
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};
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/*
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* These tables contain all valid speeds we want to override with board
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* specific parameters. datarate_mhz_high values need to be in ascending order
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* for each n_ranks group.
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*/
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static const struct board_specific_parameters udimm0[] = {
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/*
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* memory controller 0
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* num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
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* ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
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*/
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#ifdef CONFIG_SYS_FSL_DDR4
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{2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
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{2, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,},
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{1, 1666, 0, 8, 6, 0x0708090B, 0x0C0D0E09,},
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{1, 1900, 0, 8, 6, 0x08080A0C, 0x0D0E0F0A,},
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{1, 2200, 0, 8, 7, 0x08090A0D, 0x0F0F100C,},
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#elif defined(CONFIG_SYS_FSL_DDR3)
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{2, 833, 0, 8, 6, 0x06060607, 0x08080807,},
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{2, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,},
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||||
{2, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
|
||||
{1, 833, 0, 8, 6, 0x06060607, 0x08080807,},
|
||||
{1, 1350, 0, 8, 7, 0x0708080A, 0x0A0B0C09,},
|
||||
{1, 1666, 0, 8, 7, 0x0808090B, 0x0C0D0E0A,},
|
||||
#else
|
||||
#error DDR type not defined
|
||||
#endif
|
||||
{}
|
||||
};
|
||||
|
||||
static const struct board_specific_parameters *udimms[] = {
|
||||
udimm0,
|
||||
};
|
||||
#endif
|
||||
|
|
@ -1,98 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2014 Freescale Semiconductor, Inc.
|
||||
* Copyright 2020 NXP
|
||||
* Author: Priyanka Jain <Priyanka.Jain@freescale.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <clock_legacy.h>
|
||||
#include <command.h>
|
||||
#include <linux/ctype.h>
|
||||
#include <asm/io.h>
|
||||
#include <stdio_dev.h>
|
||||
#include <video_fb.h>
|
||||
#include <fsl_diu_fb.h>
|
||||
#include "../common/qixis.h"
|
||||
#include "../common/diu_ch7301.h"
|
||||
#include "t1040qds.h"
|
||||
#include "t1040qds_qixis.h"
|
||||
|
||||
/*
|
||||
* DIU Area Descriptor
|
||||
*
|
||||
* Note that we need to byte-swap the value before it's written to the AD
|
||||
* register. So even though the registers don't look like they're in the same
|
||||
* bit positions as they are on the MPC8610, the same value is written to the
|
||||
* AD register on the MPC8610 and on the P1022.
|
||||
*/
|
||||
#define AD_BYTE_F 0x10000000
|
||||
#define AD_ALPHA_C_SHIFT 25
|
||||
#define AD_BLUE_C_SHIFT 23
|
||||
#define AD_GREEN_C_SHIFT 21
|
||||
#define AD_RED_C_SHIFT 19
|
||||
#define AD_PIXEL_S_SHIFT 16
|
||||
#define AD_COMP_3_SHIFT 12
|
||||
#define AD_COMP_2_SHIFT 8
|
||||
#define AD_COMP_1_SHIFT 4
|
||||
#define AD_COMP_0_SHIFT 0
|
||||
|
||||
void diu_set_pixel_clock(unsigned int pixclock)
|
||||
{
|
||||
unsigned long speed_ccb, temp;
|
||||
u32 pixval;
|
||||
int ret = 0;
|
||||
speed_ccb = get_bus_freq(0);
|
||||
temp = 1000000000 / pixclock;
|
||||
temp *= 1000;
|
||||
pixval = speed_ccb / temp;
|
||||
|
||||
/* Program HDMI encoder */
|
||||
/* Switch channel to DIU */
|
||||
select_i2c_ch_pca9547(I2C_MUX_CH_DIU, 0);
|
||||
|
||||
/* Set dispaly encoder */
|
||||
ret = diu_set_dvi_encoder(temp);
|
||||
if (ret) {
|
||||
puts("Failed to set DVI encoder\n");
|
||||
return;
|
||||
}
|
||||
|
||||
/* Switch channel to default */
|
||||
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
|
||||
|
||||
/* Program pixel clock */
|
||||
out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR,
|
||||
((pixval << PXCK_BITS_START) & PXCK_MASK));
|
||||
/* enable clock*/
|
||||
out_be32((unsigned *)CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR, PXCKEN_MASK |
|
||||
((pixval << PXCK_BITS_START) & PXCK_MASK));
|
||||
}
|
||||
|
||||
int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
|
||||
{
|
||||
u32 pixel_format;
|
||||
u8 sw;
|
||||
|
||||
/*Route I2C4 to DIU system as HSYNC/VSYNC*/
|
||||
sw = QIXIS_READ(brdcfg[5]);
|
||||
QIXIS_WRITE(brdcfg[5],
|
||||
((sw & ~(BRDCFG5_IMX_MASK)) | (BRDCFG5_IMX_DIU)));
|
||||
|
||||
/*Configure Display ouput port as HDMI*/
|
||||
sw = QIXIS_READ(brdcfg[15]);
|
||||
QIXIS_WRITE(brdcfg[15],
|
||||
((sw & ~(BRDCFG15_LCDPD_MASK | BRDCFG15_DIUSEL_MASK))
|
||||
| (BRDCFG15_LCDPD_ENABLED | BRDCFG15_DIUSEL_HDMI)));
|
||||
|
||||
pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
|
||||
(0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
|
||||
(2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
|
||||
(8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
|
||||
(8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
|
||||
|
||||
printf("DIU: Switching to monitor @ %ux%u\n", xres, yres);
|
||||
|
||||
|
||||
return fsl_diu_init(xres, yres, pixel_format, 0);
|
||||
}
|
||||
|
|
@ -1,592 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The RGMII PHYs are provided by the two on-board PHY connected to
|
||||
* dTSEC instances 4 and 5. The SGMII PHYs are provided by one on-board
|
||||
* PHY or by the standard four-port SGMII riser card (VSC).
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <fdt_support.h>
|
||||
#include <net.h>
|
||||
#include <netdev.h>
|
||||
#include <asm/fsl_serdes.h>
|
||||
#include <asm/immap_85xx.h>
|
||||
#include <fm_eth.h>
|
||||
#include <fsl_mdio.h>
|
||||
#include <malloc.h>
|
||||
#include <fsl_dtsec.h>
|
||||
#include <vsc9953.h>
|
||||
|
||||
#include "../common/fman.h"
|
||||
#include "../common/qixis.h"
|
||||
|
||||
#include "t1040qds_qixis.h"
|
||||
|
||||
#ifdef CONFIG_FMAN_ENET
|
||||
/* - In T1040 there are only 8 SERDES lanes, spread across 2 SERDES banks.
|
||||
* Bank 1 -> Lanes A, B, C, D
|
||||
* Bank 2 -> Lanes E, F, G, H
|
||||
*/
|
||||
|
||||
/* Mapping of 8 SERDES lanes to T1040 QDS board slots. A value of '0' here
|
||||
* means that the mapping must be determined dynamically, or that the lane
|
||||
* maps to something other than a board slot.
|
||||
*/
|
||||
static u8 lane_to_slot[] = {
|
||||
0, 0, 0, 0, 0, 0, 0, 0
|
||||
};
|
||||
|
||||
/* On the Vitesse VSC8234XHG SGMII riser card there are 4 SGMII PHYs
|
||||
* housed.
|
||||
*/
|
||||
static int riser_phy_addr[] = {
|
||||
CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR,
|
||||
CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR,
|
||||
CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR,
|
||||
CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR,
|
||||
};
|
||||
|
||||
/* Slot2 does not have EMI connections */
|
||||
#define EMI_NONE 0xFFFFFFFF
|
||||
#define EMI1_RGMII0 0
|
||||
#define EMI1_RGMII1 1
|
||||
#define EMI1_SLOT1 2
|
||||
#define EMI1_SLOT3 3
|
||||
#define EMI1_SLOT4 4
|
||||
#define EMI1_SLOT5 5
|
||||
#define EMI1_SLOT6 6
|
||||
#define EMI1_SLOT7 7
|
||||
#define EMI2 8
|
||||
|
||||
static int mdio_mux[NUM_FM_PORTS];
|
||||
|
||||
static const char * const mdio_names[] = {
|
||||
"T1040_QDS_MDIO0",
|
||||
"T1040_QDS_MDIO1",
|
||||
"T1040_QDS_MDIO2",
|
||||
"T1040_QDS_MDIO3",
|
||||
"T1040_QDS_MDIO4",
|
||||
"T1040_QDS_MDIO5",
|
||||
"T1040_QDS_MDIO6",
|
||||
"T1040_QDS_MDIO7",
|
||||
};
|
||||
|
||||
struct t1040_qds_mdio {
|
||||
u8 muxval;
|
||||
struct mii_dev *realbus;
|
||||
};
|
||||
|
||||
static const char *t1040_qds_mdio_name_for_muxval(u8 muxval)
|
||||
{
|
||||
return mdio_names[muxval];
|
||||
}
|
||||
|
||||
struct mii_dev *mii_dev_for_muxval(u8 muxval)
|
||||
{
|
||||
struct mii_dev *bus;
|
||||
const char *name = t1040_qds_mdio_name_for_muxval(muxval);
|
||||
|
||||
if (!name) {
|
||||
printf("No bus for muxval %x\n", muxval);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
bus = miiphy_get_dev_by_name(name);
|
||||
|
||||
if (!bus) {
|
||||
printf("No bus by name %s\n", name);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return bus;
|
||||
}
|
||||
|
||||
static void t1040_qds_mux_mdio(u8 muxval)
|
||||
{
|
||||
u8 brdcfg4;
|
||||
if (muxval <= 7) {
|
||||
brdcfg4 = QIXIS_READ(brdcfg[4]);
|
||||
brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
|
||||
brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
|
||||
QIXIS_WRITE(brdcfg[4], brdcfg4);
|
||||
}
|
||||
}
|
||||
|
||||
static int t1040_qds_mdio_read(struct mii_dev *bus, int addr, int devad,
|
||||
int regnum)
|
||||
{
|
||||
struct t1040_qds_mdio *priv = bus->priv;
|
||||
|
||||
t1040_qds_mux_mdio(priv->muxval);
|
||||
|
||||
return priv->realbus->read(priv->realbus, addr, devad, regnum);
|
||||
}
|
||||
|
||||
static int t1040_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
|
||||
int regnum, u16 value)
|
||||
{
|
||||
struct t1040_qds_mdio *priv = bus->priv;
|
||||
|
||||
t1040_qds_mux_mdio(priv->muxval);
|
||||
|
||||
return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
|
||||
}
|
||||
|
||||
static int t1040_qds_mdio_reset(struct mii_dev *bus)
|
||||
{
|
||||
struct t1040_qds_mdio *priv = bus->priv;
|
||||
|
||||
return priv->realbus->reset(priv->realbus);
|
||||
}
|
||||
|
||||
static int t1040_qds_mdio_init(char *realbusname, u8 muxval)
|
||||
{
|
||||
struct t1040_qds_mdio *pmdio;
|
||||
struct mii_dev *bus = mdio_alloc();
|
||||
|
||||
if (!bus) {
|
||||
printf("Failed to allocate t1040_qds MDIO bus\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
pmdio = malloc(sizeof(*pmdio));
|
||||
if (!pmdio) {
|
||||
printf("Failed to allocate t1040_qds private data\n");
|
||||
free(bus);
|
||||
return -1;
|
||||
}
|
||||
|
||||
bus->read = t1040_qds_mdio_read;
|
||||
bus->write = t1040_qds_mdio_write;
|
||||
bus->reset = t1040_qds_mdio_reset;
|
||||
strcpy(bus->name, t1040_qds_mdio_name_for_muxval(muxval));
|
||||
|
||||
pmdio->realbus = miiphy_get_dev_by_name(realbusname);
|
||||
|
||||
if (!pmdio->realbus) {
|
||||
printf("No bus with name %s\n", realbusname);
|
||||
free(bus);
|
||||
free(pmdio);
|
||||
return -1;
|
||||
}
|
||||
|
||||
pmdio->muxval = muxval;
|
||||
bus->priv = pmdio;
|
||||
|
||||
return mdio_register(bus);
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize the lane_to_slot[] array.
|
||||
*
|
||||
* On the T1040QDS board the mapping is controlled by ?? register.
|
||||
*/
|
||||
static void initialize_lane_to_slot(void)
|
||||
{
|
||||
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
|
||||
int serdes1_prtcl = (in_be32(&gur->rcwsr[4]) &
|
||||
FSL_CORENET2_RCWSR4_SRDS1_PRTCL)
|
||||
>> FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
|
||||
|
||||
QIXIS_WRITE(cms[0], 0x07);
|
||||
|
||||
switch (serdes1_prtcl) {
|
||||
case 0x60:
|
||||
case 0x66:
|
||||
case 0x67:
|
||||
case 0x69:
|
||||
lane_to_slot[1] = 7;
|
||||
lane_to_slot[2] = 6;
|
||||
lane_to_slot[3] = 5;
|
||||
break;
|
||||
case 0x86:
|
||||
lane_to_slot[1] = 7;
|
||||
lane_to_slot[2] = 7;
|
||||
lane_to_slot[3] = 7;
|
||||
break;
|
||||
case 0x87:
|
||||
lane_to_slot[1] = 7;
|
||||
lane_to_slot[2] = 7;
|
||||
lane_to_slot[3] = 7;
|
||||
lane_to_slot[7] = 7;
|
||||
break;
|
||||
case 0x89:
|
||||
lane_to_slot[1] = 7;
|
||||
lane_to_slot[2] = 7;
|
||||
lane_to_slot[3] = 7;
|
||||
lane_to_slot[6] = 7;
|
||||
lane_to_slot[7] = 7;
|
||||
break;
|
||||
case 0x8d:
|
||||
lane_to_slot[1] = 7;
|
||||
lane_to_slot[2] = 7;
|
||||
lane_to_slot[3] = 7;
|
||||
lane_to_slot[5] = 3;
|
||||
lane_to_slot[6] = 3;
|
||||
lane_to_slot[7] = 3;
|
||||
break;
|
||||
case 0x8F:
|
||||
case 0x85:
|
||||
lane_to_slot[1] = 7;
|
||||
lane_to_slot[2] = 6;
|
||||
lane_to_slot[3] = 5;
|
||||
lane_to_slot[6] = 3;
|
||||
lane_to_slot[7] = 3;
|
||||
break;
|
||||
case 0xA5:
|
||||
lane_to_slot[1] = 7;
|
||||
lane_to_slot[6] = 3;
|
||||
lane_to_slot[7] = 3;
|
||||
break;
|
||||
case 0xA7:
|
||||
lane_to_slot[1] = 7;
|
||||
lane_to_slot[2] = 6;
|
||||
lane_to_slot[3] = 5;
|
||||
lane_to_slot[7] = 7;
|
||||
break;
|
||||
case 0xAA:
|
||||
lane_to_slot[1] = 7;
|
||||
lane_to_slot[6] = 7;
|
||||
lane_to_slot[7] = 7;
|
||||
break;
|
||||
case 0x40:
|
||||
lane_to_slot[2] = 7;
|
||||
lane_to_slot[3] = 7;
|
||||
break;
|
||||
default:
|
||||
printf("qds: Fman: Unsupported SerDes Protocol 0x%02x\n",
|
||||
serdes1_prtcl);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Given the following ...
|
||||
*
|
||||
* 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
|
||||
* compatible string and 'addr' physical address)
|
||||
*
|
||||
* 2) An Fman port
|
||||
*
|
||||
* ... update the phy-handle property of the Ethernet node to point to the
|
||||
* right PHY. This assumes that we already know the PHY for each port.
|
||||
*
|
||||
* The offset of the Fman Ethernet node is also passed in for convenience, but
|
||||
* it is not used, and we recalculate the offset anyway.
|
||||
*
|
||||
* Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC.
|
||||
* Inside the Fman, "ports" are things that connect to MACs. We only call them
|
||||
* ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs
|
||||
* and ports are the same thing.
|
||||
*
|
||||
*/
|
||||
void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
|
||||
enum fm_port port, int offset)
|
||||
{
|
||||
phy_interface_t intf = fm_info_get_enet_if(port);
|
||||
char phy[16];
|
||||
|
||||
/* The RGMII PHY is identified by the MAC connected to it */
|
||||
if (intf == PHY_INTERFACE_MODE_RGMII) {
|
||||
sprintf(phy, "rgmii_phy%u", port == FM1_DTSEC4 ? 1 : 2);
|
||||
fdt_set_phy_handle(fdt, compat, addr, phy);
|
||||
}
|
||||
|
||||
/* The SGMII PHY is identified by the MAC connected to it */
|
||||
if (intf == PHY_INTERFACE_MODE_SGMII) {
|
||||
int lane = serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC1
|
||||
+ port);
|
||||
u8 slot;
|
||||
if (lane < 0)
|
||||
return;
|
||||
slot = lane_to_slot[lane];
|
||||
if (slot) {
|
||||
/* Slot housing a SGMII riser card */
|
||||
sprintf(phy, "phy_s%x_%02x", slot,
|
||||
(fm_info_get_phy_address(port - FM1_DTSEC1)-
|
||||
CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR + 1));
|
||||
fdt_set_phy_handle(fdt, compat, addr, phy);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void fdt_fixup_board_enet(void *fdt)
|
||||
{
|
||||
int i, lane, idx;
|
||||
|
||||
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
|
||||
idx = i - FM1_DTSEC1;
|
||||
switch (fm_info_get_enet_if(i)) {
|
||||
case PHY_INTERFACE_MODE_SGMII:
|
||||
lane = serdes_get_first_lane(FSL_SRDS_1,
|
||||
SGMII_FM1_DTSEC1 + idx);
|
||||
if (lane < 0)
|
||||
break;
|
||||
|
||||
switch (mdio_mux[i]) {
|
||||
case EMI1_SLOT3:
|
||||
fdt_status_okay_by_alias(fdt, "emi1_slot3");
|
||||
break;
|
||||
case EMI1_SLOT5:
|
||||
fdt_status_okay_by_alias(fdt, "emi1_slot5");
|
||||
break;
|
||||
case EMI1_SLOT6:
|
||||
fdt_status_okay_by_alias(fdt, "emi1_slot6");
|
||||
break;
|
||||
case EMI1_SLOT7:
|
||||
fdt_status_okay_by_alias(fdt, "emi1_slot7");
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case PHY_INTERFACE_MODE_RGMII:
|
||||
if (i == FM1_DTSEC4)
|
||||
fdt_status_okay_by_alias(fdt, "emi1_rgmii0");
|
||||
|
||||
if (i == FM1_DTSEC5)
|
||||
fdt_status_okay_by_alias(fdt, "emi1_rgmii1");
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif /* #ifdef CONFIG_FMAN_ENET */
|
||||
|
||||
static void set_brdcfg9_for_gtx_clk(void)
|
||||
{
|
||||
u8 brdcfg9;
|
||||
brdcfg9 = QIXIS_READ(brdcfg[9]);
|
||||
/* Initializing EPHY2 clock to RGMII mode */
|
||||
brdcfg9 &= ~(BRDCFG9_EPHY2_MASK);
|
||||
brdcfg9 |= (BRDCFG9_EPHY2_VAL);
|
||||
QIXIS_WRITE(brdcfg[9], brdcfg9);
|
||||
}
|
||||
|
||||
void t1040_handle_phy_interface_sgmii(int i)
|
||||
{
|
||||
int lane, idx, slot;
|
||||
idx = i - FM1_DTSEC1;
|
||||
lane = serdes_get_first_lane(FSL_SRDS_1,
|
||||
SGMII_FM1_DTSEC1 + idx);
|
||||
|
||||
if (lane < 0)
|
||||
return;
|
||||
slot = lane_to_slot[lane];
|
||||
|
||||
switch (slot) {
|
||||
case 1:
|
||||
mdio_mux[i] = EMI1_SLOT1;
|
||||
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
|
||||
break;
|
||||
case 3:
|
||||
if (FM1_DTSEC4 == i)
|
||||
fm_info_set_phy_address(i, riser_phy_addr[0]);
|
||||
if (FM1_DTSEC5 == i)
|
||||
fm_info_set_phy_address(i, riser_phy_addr[1]);
|
||||
|
||||
mdio_mux[i] = EMI1_SLOT3;
|
||||
|
||||
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
|
||||
break;
|
||||
case 4:
|
||||
mdio_mux[i] = EMI1_SLOT4;
|
||||
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
|
||||
break;
|
||||
case 5:
|
||||
/* Slot housing a SGMII riser card? */
|
||||
fm_info_set_phy_address(i, riser_phy_addr[0]);
|
||||
mdio_mux[i] = EMI1_SLOT5;
|
||||
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
|
||||
break;
|
||||
case 6:
|
||||
/* Slot housing a SGMII riser card? */
|
||||
fm_info_set_phy_address(i, riser_phy_addr[0]);
|
||||
mdio_mux[i] = EMI1_SLOT6;
|
||||
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
|
||||
break;
|
||||
case 7:
|
||||
if (FM1_DTSEC1 == i)
|
||||
fm_info_set_phy_address(i, riser_phy_addr[0]);
|
||||
if (FM1_DTSEC2 == i)
|
||||
fm_info_set_phy_address(i, riser_phy_addr[1]);
|
||||
if (FM1_DTSEC3 == i)
|
||||
fm_info_set_phy_address(i, riser_phy_addr[2]);
|
||||
if (FM1_DTSEC5 == i)
|
||||
fm_info_set_phy_address(i, riser_phy_addr[3]);
|
||||
|
||||
mdio_mux[i] = EMI1_SLOT7;
|
||||
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
|
||||
}
|
||||
void t1040_handle_phy_interface_rgmii(int i)
|
||||
{
|
||||
fm_info_set_phy_address(i, i == FM1_DTSEC5 ?
|
||||
CONFIG_SYS_FM1_DTSEC5_PHY_ADDR :
|
||||
CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
|
||||
mdio_mux[i] = (i == FM1_DTSEC5) ? EMI1_RGMII1 :
|
||||
EMI1_RGMII0;
|
||||
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
|
||||
}
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
#ifdef CONFIG_FMAN_ENET
|
||||
struct memac_mdio_info memac_mdio_info;
|
||||
unsigned int i;
|
||||
#ifdef CONFIG_VSC9953
|
||||
int lane;
|
||||
int phy_addr;
|
||||
phy_interface_t phy_int;
|
||||
struct mii_dev *bus;
|
||||
#endif
|
||||
|
||||
printf("Initializing Fman\n");
|
||||
set_brdcfg9_for_gtx_clk();
|
||||
|
||||
initialize_lane_to_slot();
|
||||
|
||||
/* Initialize the mdio_mux array so we can recognize empty elements */
|
||||
for (i = 0; i < NUM_FM_PORTS; i++)
|
||||
mdio_mux[i] = EMI_NONE;
|
||||
|
||||
memac_mdio_info.regs =
|
||||
(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
|
||||
memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
|
||||
|
||||
/* Register the real 1G MDIO bus */
|
||||
fm_memac_mdio_init(bis, &memac_mdio_info);
|
||||
|
||||
/* Register the muxing front-ends to the MDIO buses */
|
||||
t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII0);
|
||||
t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
|
||||
t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
|
||||
t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
|
||||
t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
|
||||
t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
|
||||
t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT6);
|
||||
t1040_qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT7);
|
||||
|
||||
/*
|
||||
* Program on board RGMII PHY addresses. If the SGMII Riser
|
||||
* card used, we'll override the PHY address later. For any DTSEC that
|
||||
* is RGMII, we'll also override its PHY address later. We assume that
|
||||
* DTSEC4 and DTSEC5 are used for RGMII.
|
||||
*/
|
||||
fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
|
||||
fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
|
||||
|
||||
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
|
||||
switch (fm_info_get_enet_if(i)) {
|
||||
case PHY_INTERFACE_MODE_QSGMII:
|
||||
fm_info_set_mdio(i, NULL);
|
||||
break;
|
||||
case PHY_INTERFACE_MODE_SGMII:
|
||||
t1040_handle_phy_interface_sgmii(i);
|
||||
break;
|
||||
|
||||
case PHY_INTERFACE_MODE_RGMII:
|
||||
/* Only DTSEC4 and DTSEC5 can be routed to RGMII */
|
||||
t1040_handle_phy_interface_rgmii(i);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_VSC9953
|
||||
for (i = 0; i < VSC9953_MAX_PORTS; i++) {
|
||||
lane = -1;
|
||||
phy_addr = 0;
|
||||
phy_int = PHY_INTERFACE_MODE_NONE;
|
||||
switch (i) {
|
||||
case 0:
|
||||
case 1:
|
||||
case 2:
|
||||
case 3:
|
||||
lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_A);
|
||||
/* PHYs connected over QSGMII */
|
||||
if (lane >= 0) {
|
||||
phy_addr = CONFIG_SYS_FM1_QSGMII21_PHY_ADDR +
|
||||
i;
|
||||
phy_int = PHY_INTERFACE_MODE_QSGMII;
|
||||
break;
|
||||
}
|
||||
lane = serdes_get_first_lane(FSL_SRDS_1,
|
||||
SGMII_SW1_MAC1 + i);
|
||||
|
||||
if (lane < 0)
|
||||
break;
|
||||
|
||||
/* PHYs connected over QSGMII */
|
||||
if (i != 3 || lane_to_slot[lane] == 7)
|
||||
phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
|
||||
+ i;
|
||||
else
|
||||
phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR;
|
||||
phy_int = PHY_INTERFACE_MODE_SGMII;
|
||||
break;
|
||||
case 4:
|
||||
case 5:
|
||||
case 6:
|
||||
case 7:
|
||||
lane = serdes_get_first_lane(FSL_SRDS_1, QSGMII_SW1_B);
|
||||
/* PHYs connected over QSGMII */
|
||||
if (lane >= 0) {
|
||||
phy_addr = CONFIG_SYS_FM1_QSGMII11_PHY_ADDR +
|
||||
i - 4;
|
||||
phy_int = PHY_INTERFACE_MODE_QSGMII;
|
||||
break;
|
||||
}
|
||||
lane = serdes_get_first_lane(FSL_SRDS_1,
|
||||
SGMII_SW1_MAC1 + i);
|
||||
/* PHYs connected over SGMII */
|
||||
if (lane >= 0) {
|
||||
phy_addr = CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR
|
||||
+ i - 3;
|
||||
phy_int = PHY_INTERFACE_MODE_SGMII;
|
||||
}
|
||||
break;
|
||||
case 8:
|
||||
if (serdes_get_first_lane(FSL_SRDS_1,
|
||||
SGMII_FM1_DTSEC1) < 0)
|
||||
/* FM1@DTSEC1 is connected to SW1@PORT8 */
|
||||
vsc9953_port_enable(i);
|
||||
break;
|
||||
case 9:
|
||||
if (serdes_get_first_lane(FSL_SRDS_1,
|
||||
SGMII_FM1_DTSEC2) < 0) {
|
||||
/* Enable L2 On MAC2 using SCFG */
|
||||
struct ccsr_scfg *scfg = (struct ccsr_scfg *)
|
||||
CONFIG_SYS_MPC85xx_SCFG;
|
||||
|
||||
out_be32(&scfg->esgmiiselcr,
|
||||
in_be32(&scfg->esgmiiselcr) |
|
||||
(0x80000000));
|
||||
vsc9953_port_enable(i);
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
if (lane >= 0) {
|
||||
bus = mii_dev_for_muxval(lane_to_slot[lane]);
|
||||
vsc9953_port_info_set_mdio(i, bus);
|
||||
vsc9953_port_enable(i);
|
||||
}
|
||||
vsc9953_port_info_set_phy_address(i, phy_addr);
|
||||
vsc9953_port_info_set_phy_int(i, phy_int);
|
||||
}
|
||||
|
||||
#endif
|
||||
cpu_eth_init(bis);
|
||||
#endif
|
||||
|
||||
return pci_eth_init(bis);
|
||||
}
|
||||
|
|
@ -1,31 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/fsl_law.h>
|
||||
#include <asm/mmu.h>
|
||||
|
||||
struct law_entry law_table[] = {
|
||||
#ifdef CONFIG_MTD_NOR_FLASH
|
||||
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_BMAN_MEM_PHYS
|
||||
SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_QMAN_MEM_PHYS
|
||||
SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
|
||||
#endif
|
||||
#ifdef QIXIS_BASE_PHYS
|
||||
SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_DCSRBAR_PHYS
|
||||
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_NAND_BASE_PHYS
|
||||
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
|
||||
#endif
|
||||
};
|
||||
|
||||
int num_law_entries = ARRAY_SIZE(law_table);
|
||||
|
|
@ -1,23 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <init.h>
|
||||
#include <pci.h>
|
||||
#include <asm/fsl_pci.h>
|
||||
#include <linux/libfdt.h>
|
||||
#include <fdt_support.h>
|
||||
#include <asm/fsl_serdes.h>
|
||||
|
||||
void pci_init_board(void)
|
||||
{
|
||||
fsl_pcie_init_board(0);
|
||||
}
|
||||
|
||||
void pci_of_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
FT_FSL_PCI_SETUP;
|
||||
}
|
||||
|
|
@ -1,27 +0,0 @@
|
|||
#PBI commands
|
||||
#Initialize CPC1
|
||||
09010000 00200400
|
||||
09138000 00000000
|
||||
091380c0 00000100
|
||||
#Configure CPC1 as 256KB SRAM
|
||||
09010100 00000000
|
||||
09010104 fffc0007
|
||||
09010f00 081e000d
|
||||
09010000 80000000
|
||||
#Configure LAW for CPC1
|
||||
09000cf0 00000000
|
||||
09000cf4 fffc0000
|
||||
09000cf8 81000011
|
||||
#Configure alternate space
|
||||
09000010 00000000
|
||||
09000014 ff000000
|
||||
09000018 81000000
|
||||
#Configure SPI controller
|
||||
09110000 80000403
|
||||
09110020 2d170008
|
||||
09110024 00100008
|
||||
09110028 00100008
|
||||
0911002c 00100008
|
||||
#Flush PBL data
|
||||
09138000 00000000
|
||||
091380c0 00000000
|
||||
|
|
@ -1,7 +0,0 @@
|
|||
#PBL preamble and RCW header
|
||||
aa55aa55 010e0100
|
||||
# serdes protocol 0x66
|
||||
0a10000c 0c000000 00000000 00000000
|
||||
66000002 00000000 fc027000 01000000
|
||||
00000000 00000000 00000000 00030810
|
||||
00000000 03fc500f 00000000 00000000
|
||||
|
|
@ -1,307 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
* Copyright 2020 NXP
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <env.h>
|
||||
#include <fdt_support.h>
|
||||
#include <i2c.h>
|
||||
#include <image.h>
|
||||
#include <init.h>
|
||||
#include <netdev.h>
|
||||
#include <linux/compiler.h>
|
||||
#include <asm/mmu.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/cache.h>
|
||||
#include <asm/immap_85xx.h>
|
||||
#include <asm/fsl_law.h>
|
||||
#include <asm/fsl_serdes.h>
|
||||
#include <asm/fsl_liodn.h>
|
||||
#include <fm_eth.h>
|
||||
#include <hwconfig.h>
|
||||
|
||||
#include "../common/sleep.h"
|
||||
#include "../common/qixis.h"
|
||||
#include "t1040qds.h"
|
||||
#include "t1040qds_qixis.h"
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
char buf[64];
|
||||
u8 sw;
|
||||
struct cpu_type *cpu = gd->arch.cpu;
|
||||
static const char *const freq[] = {"100", "125", "156.25", "161.13",
|
||||
"122.88", "122.88", "122.88"};
|
||||
int clock;
|
||||
|
||||
printf("Board: %sQDS, ", cpu->name);
|
||||
printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
|
||||
QIXIS_READ(id), QIXIS_READ(arch));
|
||||
|
||||
sw = QIXIS_READ(brdcfg[0]);
|
||||
sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
|
||||
|
||||
if (sw < 0x8)
|
||||
printf("vBank: %d\n", sw);
|
||||
else if (sw == 0x8)
|
||||
puts("PromJet\n");
|
||||
else if (sw == 0x9)
|
||||
puts("NAND\n");
|
||||
else if (sw == 0x15)
|
||||
printf("IFCCard\n");
|
||||
else
|
||||
printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
|
||||
|
||||
printf("FPGA: v%d (%s), build %d",
|
||||
(int)QIXIS_READ(scver), qixis_read_tag(buf),
|
||||
(int)qixis_read_minor());
|
||||
/* the timestamp string contains "\n" at the end */
|
||||
printf(" on %s", qixis_read_time(buf));
|
||||
|
||||
/*
|
||||
* Display the actual SERDES reference clocks as configured by the
|
||||
* dip switches on the board. Note that the SWx registers could
|
||||
* technically be set to force the reference clocks to match the
|
||||
* values that the SERDES expects (or vice versa). For now, however,
|
||||
* we just display both values and hope the user notices when they
|
||||
* don't match.
|
||||
*/
|
||||
puts("SERDES Reference: ");
|
||||
sw = QIXIS_READ(brdcfg[2]);
|
||||
clock = (sw >> 6) & 3;
|
||||
printf("Clock1=%sMHz ", freq[clock]);
|
||||
clock = (sw >> 4) & 3;
|
||||
printf("Clock2=%sMHz\n", freq[clock]);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int select_i2c_ch_pca9547(u8 ch, int bus_num)
|
||||
{
|
||||
int ret;
|
||||
|
||||
#ifdef CONFIG_DM_I2C
|
||||
struct udevice *dev;
|
||||
|
||||
ret = i2c_get_chip_for_busnum(bus_num, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
|
||||
if (ret) {
|
||||
printf("%s: Cannot find udev for a bus %d\n", __func__,
|
||||
bus_num);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = dm_i2c_write(dev, 0, &ch, 1);
|
||||
#else
|
||||
ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
|
||||
#endif
|
||||
if (ret) {
|
||||
puts("PCA: failed to select proper channel\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void qe_board_setup(void)
|
||||
{
|
||||
u8 brdcfg15, brdcfg9;
|
||||
|
||||
if (hwconfig("qe") && hwconfig("tdm")) {
|
||||
brdcfg15 = QIXIS_READ(brdcfg[15]);
|
||||
/*
|
||||
* TDMRiser uses QE-TDM
|
||||
* Route QE_TDM signals to TDM Riser slot
|
||||
*/
|
||||
QIXIS_WRITE(brdcfg[15], brdcfg15 | 7);
|
||||
} else if (hwconfig("qe") && hwconfig("uart")) {
|
||||
brdcfg15 = QIXIS_READ(brdcfg[15]);
|
||||
brdcfg9 = QIXIS_READ(brdcfg[9]);
|
||||
/*
|
||||
* Route QE_TDM signals to UCC
|
||||
* ProfiBus controlled by UCC3
|
||||
*/
|
||||
brdcfg15 &= 0xfc;
|
||||
QIXIS_WRITE(brdcfg[15], brdcfg15 | 2);
|
||||
QIXIS_WRITE(brdcfg[9], brdcfg9 | 4);
|
||||
}
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
#if defined(CONFIG_DEEP_SLEEP)
|
||||
if (is_warm_boot())
|
||||
fsl_dp_disable_console();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_early_init_r(void)
|
||||
{
|
||||
#ifdef CONFIG_SYS_FLASH_BASE
|
||||
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
|
||||
int flash_esel = find_tlb_idx((void *)flashbase, 1);
|
||||
|
||||
/*
|
||||
* Remap Boot flash + PROMJET region to caching-inhibited
|
||||
* so that flash can be erased properly.
|
||||
*/
|
||||
|
||||
/* Flush d-cache and invalidate i-cache of any FLASH data */
|
||||
flush_dcache();
|
||||
invalidate_icache();
|
||||
|
||||
if (flash_esel == -1) {
|
||||
/* very unlikely unless something is messed up */
|
||||
puts("Error: Could not find TLB for FLASH BASE\n");
|
||||
flash_esel = 2; /* give our best effort to continue */
|
||||
} else {
|
||||
/* invalidate existing TLB entry for flash + promjet */
|
||||
disable_tlb(flash_esel);
|
||||
}
|
||||
|
||||
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, flash_esel, BOOKE_PAGESZ_256M, 1);
|
||||
#endif
|
||||
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned long get_board_sys_clk(void)
|
||||
{
|
||||
u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
|
||||
|
||||
switch (sysclk_conf & 0x0F) {
|
||||
case QIXIS_SYSCLK_64:
|
||||
return 64000000;
|
||||
case QIXIS_SYSCLK_83:
|
||||
return 83333333;
|
||||
case QIXIS_SYSCLK_100:
|
||||
return 100000000;
|
||||
case QIXIS_SYSCLK_125:
|
||||
return 125000000;
|
||||
case QIXIS_SYSCLK_133:
|
||||
return 133333333;
|
||||
case QIXIS_SYSCLK_150:
|
||||
return 150000000;
|
||||
case QIXIS_SYSCLK_160:
|
||||
return 160000000;
|
||||
case QIXIS_SYSCLK_166:
|
||||
return 166666666;
|
||||
}
|
||||
return 66666666;
|
||||
}
|
||||
|
||||
unsigned long get_board_ddr_clk(void)
|
||||
{
|
||||
u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
|
||||
|
||||
switch ((ddrclk_conf & 0x30) >> 4) {
|
||||
case QIXIS_DDRCLK_100:
|
||||
return 100000000;
|
||||
case QIXIS_DDRCLK_125:
|
||||
return 125000000;
|
||||
case QIXIS_DDRCLK_133:
|
||||
return 133333333;
|
||||
}
|
||||
return 66666666;
|
||||
}
|
||||
|
||||
#define NUM_SRDS_BANKS 2
|
||||
int misc_init_r(void)
|
||||
{
|
||||
u8 sw;
|
||||
serdes_corenet_t *srds_regs =
|
||||
(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
|
||||
u32 actual[NUM_SRDS_BANKS] = { 0 };
|
||||
int i;
|
||||
|
||||
sw = QIXIS_READ(brdcfg[2]);
|
||||
for (i = 0; i < NUM_SRDS_BANKS; i++) {
|
||||
unsigned int clock = (sw >> (6 - 2 * i)) & 3;
|
||||
switch (clock) {
|
||||
case 0:
|
||||
actual[i] = SRDS_PLLCR0_RFCK_SEL_100;
|
||||
break;
|
||||
case 1:
|
||||
actual[i] = SRDS_PLLCR0_RFCK_SEL_125;
|
||||
break;
|
||||
case 2:
|
||||
actual[i] = SRDS_PLLCR0_RFCK_SEL_156_25;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
puts("SerDes1");
|
||||
for (i = 0; i < NUM_SRDS_BANKS; i++) {
|
||||
u32 pllcr0 = srds_regs->bank[i].pllcr0;
|
||||
u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
|
||||
if (expected != actual[i]) {
|
||||
printf("expects ref clk%d %sMHz, but actual is %sMHz\n",
|
||||
i + 1, serdes_clock_to_string(expected),
|
||||
serdes_clock_to_string(actual[i]));
|
||||
}
|
||||
}
|
||||
|
||||
qe_board_setup();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
phys_addr_t base;
|
||||
phys_size_t size;
|
||||
|
||||
ft_cpu_setup(blob, bd);
|
||||
|
||||
base = env_get_bootm_low();
|
||||
size = env_get_bootm_size();
|
||||
|
||||
fdt_fixup_memory(blob, (u64)base, (u64)size);
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
pci_of_setup(blob, bd);
|
||||
#endif
|
||||
|
||||
fdt_fixup_liodn(blob);
|
||||
|
||||
#ifdef CONFIG_HAS_FSL_DR_USB
|
||||
fsl_fdt_fixup_dr_usb(blob, bd);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_DPAA_FMAN
|
||||
#ifndef CONFIG_DM_ETH
|
||||
fdt_fixup_fman_ethernet(blob);
|
||||
#endif
|
||||
fdt_fixup_board_enet(blob);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void qixis_dump_switch(void)
|
||||
{
|
||||
int i, nr_of_cfgsw;
|
||||
|
||||
QIXIS_WRITE(cms[0], 0x00);
|
||||
nr_of_cfgsw = QIXIS_READ(cms[1]);
|
||||
|
||||
puts("DIP switch settings dump:\n");
|
||||
for (i = 1; i <= nr_of_cfgsw; i++) {
|
||||
QIXIS_WRITE(cms[0], i);
|
||||
printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
|
||||
}
|
||||
}
|
||||
|
||||
int board_need_mem_reset(void)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
|
|
@ -1,14 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
* Copyright 2020 NXP
|
||||
*/
|
||||
|
||||
#ifndef __T1040_QDS_H__
|
||||
#define __T1040_QDS_H__
|
||||
|
||||
void fdt_fixup_board_enet(void *blob);
|
||||
void pci_of_setup(void *blob, bd_t *bd);
|
||||
int select_i2c_ch_pca9547(u8 ch, int bus_bum);
|
||||
|
||||
#endif
|
||||
|
|
@ -1,51 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#ifndef __T1040QDS_QIXIS_H__
|
||||
#define __T1040QDS_QIXIS_H__
|
||||
|
||||
/* Definitions of QIXIS Registers for T1040QDS */
|
||||
|
||||
/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
|
||||
#define BRDCFG4_EMISEL_MASK 0xE0
|
||||
#define BRDCFG4_EMISEL_SHIFT 5
|
||||
|
||||
/* BRDCFG5[0:1] controls routing and use of I2C3 & I2C4 ports*/
|
||||
#define BRDCFG5_IMX_MASK 0xC0
|
||||
#define BRDCFG5_IMX_DIU 0x80
|
||||
|
||||
/* BRDCFG9[2] controls EPHY2 Clock */
|
||||
#define BRDCFG9_EPHY2_MASK 0x20
|
||||
#define BRDCFG9_EPHY2_VAL 0x00
|
||||
|
||||
/* BRDCFG15[3] controls LCD Panel Powerdown*/
|
||||
#define BRDCFG15_LCDPD_MASK 0x10
|
||||
#define BRDCFG15_LCDPD_ENABLED 0x00
|
||||
|
||||
/* BRDCFG15[6:7] controls DIU MUX selction*/
|
||||
#define BRDCFG15_DIUSEL_MASK 0x03
|
||||
#define BRDCFG15_DIUSEL_HDMI 0x00
|
||||
|
||||
/* SYSCLK */
|
||||
#define QIXIS_SYSCLK_66 0x0
|
||||
#define QIXIS_SYSCLK_83 0x1
|
||||
#define QIXIS_SYSCLK_100 0x2
|
||||
#define QIXIS_SYSCLK_125 0x3
|
||||
#define QIXIS_SYSCLK_133 0x4
|
||||
#define QIXIS_SYSCLK_150 0x5
|
||||
#define QIXIS_SYSCLK_160 0x6
|
||||
#define QIXIS_SYSCLK_166 0x7
|
||||
#define QIXIS_SYSCLK_64 0x8
|
||||
|
||||
/* DDRCLK */
|
||||
#define QIXIS_DDRCLK_66 0x0
|
||||
#define QIXIS_DDRCLK_100 0x1
|
||||
#define QIXIS_DDRCLK_125 0x2
|
||||
#define QIXIS_DDRCLK_133 0x3
|
||||
|
||||
|
||||
#define QIXIS_SRDS1CLK_122 0x5a
|
||||
#define QIXIS_SRDS1CLK_125 0x5e
|
||||
#endif
|
||||
|
|
@ -1,107 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/mmu.h>
|
||||
|
||||
struct fsl_e_tlb_entry tlb_table[] = {
|
||||
/* TLB 0 - for temp stack in cache */
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
|
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
|
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
|
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
|
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
|
||||
/* TLB 1 */
|
||||
/* *I*** - Covers boot page */
|
||||
#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
|
||||
/*
|
||||
* *I*G - L3SRAM. When L3 is used as 256K SRAM, the address of the
|
||||
* SRAM is at 0xfffc0000, it covered the 0xfffff000.
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 0, BOOKE_PAGESZ_256K, 1),
|
||||
#else
|
||||
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 0, BOOKE_PAGESZ_4K, 1),
|
||||
#endif
|
||||
|
||||
/* *I*G* - CCSRBAR */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 1, BOOKE_PAGESZ_16M, 1),
|
||||
|
||||
/* *I*G* - Flash, localbus */
|
||||
/* This will be changed to *I*G* after relocation to RAM. */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
|
||||
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
|
||||
0, 2, BOOKE_PAGESZ_256M, 1),
|
||||
|
||||
/* *I*G* - PCI */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 3, BOOKE_PAGESZ_1G, 1),
|
||||
|
||||
/* *I*G* - PCI I/O */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 4, BOOKE_PAGESZ_256K, 1),
|
||||
|
||||
/* Bman/Qman */
|
||||
#ifdef CONFIG_SYS_BMAN_MEM_PHYS
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 5, BOOKE_PAGESZ_16M, 1),
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
|
||||
CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 6, BOOKE_PAGESZ_16M, 1),
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_QMAN_MEM_PHYS
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 7, BOOKE_PAGESZ_16M, 1),
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
|
||||
CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 8, BOOKE_PAGESZ_16M, 1),
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_DCSRBAR_PHYS
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 9, BOOKE_PAGESZ_4M, 1),
|
||||
#endif
|
||||
#ifdef CONFIG_SYS_NAND_BASE
|
||||
/*
|
||||
* *I*G - NAND
|
||||
* entry 14 and 15 has been used hard coded, they will be disabled
|
||||
* in cpu_init_f, so we use entry 16 for nand.
|
||||
*/
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 10, BOOKE_PAGESZ_64K, 1),
|
||||
#endif
|
||||
#ifdef QIXIS_BASE
|
||||
SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 11, BOOKE_PAGESZ_4K, 1),
|
||||
#endif
|
||||
|
||||
};
|
||||
|
||||
int num_tlb_entries = ARRAY_SIZE(tlb_table);
|
||||
|
|
@ -1,67 +0,0 @@
|
|||
CONFIG_PPC=y
|
||||
CONFIG_SYS_TEXT_BASE=0xEFF40000
|
||||
CONFIG_ENV_SIZE=0x2000
|
||||
CONFIG_ENV_SECT_SIZE=0x20000
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_T1040QDS=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SILENT_CONSOLE=y
|
||||
# CONFIG_CONSOLE_MUX is not set
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_BOARD_EARLY_INIT_F=y
|
||||
CONFIG_BOARD_EARLY_INIT_R=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_IMLS=y
|
||||
CONFIG_CMD_GREPENV=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_ETHSW=y
|
||||
CONFIG_CMD_BMP=y
|
||||
CONFIG_CMD_DATE=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
|
||||
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
|
||||
CONFIG_ENV_IS_IN_FLASH=y
|
||||
CONFIG_ENV_ADDR=0xEFF20000
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_FLASH_CFI_MTD=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHYLIB_10G=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_PHY_TERANETICS=y
|
||||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_FMAN_ENET=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_FSL_ESPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_VIDEO=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
|
|
@ -1,70 +0,0 @@
|
|||
CONFIG_PPC=y
|
||||
CONFIG_SYS_TEXT_BASE=0xEFF40000
|
||||
CONFIG_ENV_SIZE=0x2000
|
||||
CONFIG_NXP_ESBC=y
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_T1040QDS=y
|
||||
# CONFIG_SYS_MALLOC_F is not set
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SILENT_CONSOLE=y
|
||||
# CONFIG_CONSOLE_MUX is not set
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_BOARD_EARLY_INIT_F=y
|
||||
CONFIG_BOARD_EARLY_INIT_R=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_IMLS=y
|
||||
CONFIG_CMD_GREPENV=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_ETHSW=y
|
||||
CONFIG_CMD_BMP=y
|
||||
CONFIG_CMD_DATE=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
|
||||
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
|
||||
CONFIG_DM=y
|
||||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_FLASH_CFI_MTD=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHYLIB_10G=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_PHY_TERANETICS=y
|
||||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_FMAN_ENET=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_FSL_ESPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_VIDEO=y
|
||||
CONFIG_RSA=y
|
||||
CONFIG_SPL_RSA=y
|
||||
CONFIG_RSA_SOFTWARE_EXP=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
|
|
@ -1,68 +0,0 @@
|
|||
CONFIG_PPC=y
|
||||
CONFIG_SYS_TEXT_BASE=0xEFF40000
|
||||
CONFIG_ENV_SIZE=0x2000
|
||||
CONFIG_ENV_SECT_SIZE=0x20000
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_T1040QDS=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SILENT_CONSOLE=y
|
||||
# CONFIG_CONSOLE_MUX is not set
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
CONFIG_BOARD_EARLY_INIT_F=y
|
||||
CONFIG_BOARD_EARLY_INIT_R=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_IMLS=y
|
||||
CONFIG_CMD_GREPENV=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_ETHSW=y
|
||||
CONFIG_CMD_BMP=y
|
||||
CONFIG_CMD_DATE=y
|
||||
CONFIG_MP=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.0"
|
||||
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:2m(uboot),9m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:2m(uboot),9m(kernel),128k(dtb),-(user)"
|
||||
CONFIG_ENV_IS_IN_FLASH=y
|
||||
CONFIG_ENV_ADDR=0xEFF20000
|
||||
CONFIG_FSL_CAAM=y
|
||||
CONFIG_SYS_FSL_DDR3=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
|
||||
CONFIG_FLASH_CFI_MTD=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_PHYLIB=y
|
||||
CONFIG_PHYLIB_10G=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_PHY_TERANETICS=y
|
||||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_FMAN_ENET=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_FSL_ESPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_VIDEO=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
|
|
@ -1,667 +0,0 @@
|
|||
/*
|
||||
* Copyright 2013-2014 Freescale Semiconductor, Inc.
|
||||
* Copyright 2020 NXP
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#include <linux/stringify.h>
|
||||
|
||||
/*
|
||||
* T1040 QDS board configuration file
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_RAMBOOT_PBL
|
||||
#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
|
||||
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
|
||||
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg
|
||||
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg
|
||||
#endif
|
||||
|
||||
/* High Level Configuration Options */
|
||||
#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
|
||||
|
||||
/* support deep sleep */
|
||||
#define CONFIG_DEEP_SLEEP
|
||||
|
||||
#ifndef CONFIG_RESET_VECTOR_ADDRESS
|
||||
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
|
||||
#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
|
||||
#define CONFIG_PCI_INDIRECT_BRIDGE
|
||||
#define CONFIG_PCIE1 /* PCIE controller 1 */
|
||||
#define CONFIG_PCIE2 /* PCIE controller 2 */
|
||||
#define CONFIG_PCIE3 /* PCIE controller 3 */
|
||||
#define CONFIG_PCIE4 /* PCIE controller 4 */
|
||||
|
||||
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
|
||||
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
|
||||
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
#ifdef CONFIG_MTD_NOR_FLASH
|
||||
#if defined(CONFIG_SPIFLASH)
|
||||
#elif defined(CONFIG_SDCARD)
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 0
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
unsigned long get_board_sys_clk(void);
|
||||
unsigned long get_board_ddr_clk(void);
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
|
||||
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
|
||||
|
||||
/*
|
||||
* These can be toggled for performance analysis, otherwise use default.
|
||||
*/
|
||||
#define CONFIG_SYS_CACHE_STASHING
|
||||
#define CONFIG_BACKSIDE_L2_CACHE
|
||||
#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
|
||||
#define CONFIG_BTB /* toggle branch predition */
|
||||
#define CONFIG_DDR_ECC
|
||||
#ifdef CONFIG_DDR_ECC
|
||||
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
|
||||
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
|
||||
#endif
|
||||
|
||||
#define CONFIG_ENABLE_36BIT_PHYS
|
||||
|
||||
#define CONFIG_ADDR_MAP
|
||||
#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
|
||||
|
||||
/*
|
||||
* Config the L3 Cache as L3 SRAM
|
||||
*/
|
||||
#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
|
||||
|
||||
#define CONFIG_SYS_DCSRBAR 0xf0000000
|
||||
#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
|
||||
|
||||
/* EEPROM */
|
||||
#define CONFIG_ID_EEPROM
|
||||
#define CONFIG_SYS_I2C_EEPROM_NXID
|
||||
#define CONFIG_SYS_EEPROM_BUS_NUM 0
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
|
||||
|
||||
/*
|
||||
* DDR Setup
|
||||
*/
|
||||
#define CONFIG_VERY_BIG_RAM
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
|
||||
|
||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
|
||||
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
|
||||
|
||||
#define CONFIG_DDR_SPD
|
||||
|
||||
#define CONFIG_SYS_SPD_BUS_NUM 0
|
||||
#define SPD_EEPROM_ADDRESS 0x51
|
||||
|
||||
#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
|
||||
|
||||
/*
|
||||
* IFC Definitions
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_BASE 0xe0000000
|
||||
#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
|
||||
|
||||
#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
|
||||
#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
|
||||
+ 0x8000000) | \
|
||||
CSPR_PORT_SIZE_16 | \
|
||||
CSPR_MSEL_NOR | \
|
||||
CSPR_V)
|
||||
#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
|
||||
#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
|
||||
CSPR_PORT_SIZE_16 | \
|
||||
CSPR_MSEL_NOR | \
|
||||
CSPR_V)
|
||||
#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
|
||||
|
||||
/*
|
||||
* TDM Definition
|
||||
*/
|
||||
#define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
|
||||
|
||||
/* NOR Flash Timing Params */
|
||||
#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
|
||||
#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
|
||||
FTIM0_NOR_TEADC(0x5) | \
|
||||
FTIM0_NOR_TEAHC(0x5))
|
||||
#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
|
||||
FTIM1_NOR_TRAD_NOR(0x1A) |\
|
||||
FTIM1_NOR_TSEQRAD_NOR(0x13))
|
||||
#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
|
||||
FTIM2_NOR_TCH(0x4) | \
|
||||
FTIM2_NOR_TWPH(0x0E) | \
|
||||
FTIM2_NOR_TWP(0x1c))
|
||||
#define CONFIG_SYS_NOR_FTIM3 0x0
|
||||
|
||||
#define CONFIG_SYS_FLASH_QUIET_TEST
|
||||
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
|
||||
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
|
||||
+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
|
||||
#define CONFIG_FSL_QIXIS /* use common QIXIS code */
|
||||
#define QIXIS_BASE 0xffdf0000
|
||||
#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
|
||||
#define QIXIS_LBMAP_SWITCH 0x06
|
||||
#define QIXIS_LBMAP_MASK 0x0f
|
||||
#define QIXIS_LBMAP_SHIFT 0
|
||||
#define QIXIS_LBMAP_DFLTBANK 0x00
|
||||
#define QIXIS_LBMAP_ALTBANK 0x04
|
||||
#define QIXIS_RST_CTL_RESET 0x31
|
||||
#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
|
||||
#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
|
||||
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
|
||||
#define QIXIS_RST_FORCE_MEM 0x01
|
||||
|
||||
#define CONFIG_SYS_CSPR3_EXT (0xf)
|
||||
#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
|
||||
| CSPR_PORT_SIZE_8 \
|
||||
| CSPR_MSEL_GPCM \
|
||||
| CSPR_V)
|
||||
#define CONFIG_SYS_AMASK3 IFC_AMASK(64 * 1024)
|
||||
#define CONFIG_SYS_CSOR3 0x0
|
||||
/* QIXIS Timing parameters for IFC CS3 */
|
||||
#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
|
||||
FTIM0_GPCM_TEADC(0x0e) | \
|
||||
FTIM0_GPCM_TEAHC(0x0e))
|
||||
#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
|
||||
FTIM1_GPCM_TRAD(0x3f))
|
||||
#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
|
||||
FTIM2_GPCM_TCH(0x8) | \
|
||||
FTIM2_GPCM_TWP(0x1f))
|
||||
#define CONFIG_SYS_CS3_FTIM3 0x0
|
||||
|
||||
#define CONFIG_NAND_FSL_IFC
|
||||
#define CONFIG_SYS_NAND_BASE 0xff800000
|
||||
#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
|
||||
|
||||
#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
|
||||
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
|
||||
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
|
||||
| CSPR_MSEL_NAND /* MSEL = NAND */ \
|
||||
| CSPR_V)
|
||||
#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
|
||||
|
||||
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
|
||||
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
|
||||
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
|
||||
| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
|
||||
| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
|
||||
| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
|
||||
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
|
||||
|
||||
#define CONFIG_SYS_NAND_ONFI_DETECTION
|
||||
|
||||
/* ONFI NAND Flash mode0 Timing Params */
|
||||
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
|
||||
FTIM0_NAND_TWP(0x18) | \
|
||||
FTIM0_NAND_TWCHT(0x07) | \
|
||||
FTIM0_NAND_TWH(0x0a))
|
||||
#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
|
||||
FTIM1_NAND_TWBE(0x39) | \
|
||||
FTIM1_NAND_TRR(0x0e) | \
|
||||
FTIM1_NAND_TRP(0x18))
|
||||
#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
|
||||
FTIM2_NAND_TREH(0x0a) | \
|
||||
FTIM2_NAND_TWHRE(0x1e))
|
||||
#define CONFIG_SYS_NAND_FTIM3 0x0
|
||||
|
||||
#define CONFIG_SYS_NAND_DDR_LAW 11
|
||||
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
|
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
|
||||
|
||||
#if defined(CONFIG_MTD_RAW_NAND)
|
||||
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
|
||||
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
|
||||
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
|
||||
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
|
||||
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
|
||||
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
|
||||
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
|
||||
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
|
||||
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
|
||||
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
|
||||
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
|
||||
#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
|
||||
#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
|
||||
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
|
||||
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
|
||||
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
|
||||
#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
|
||||
#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
|
||||
#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
|
||||
#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
|
||||
#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
|
||||
#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
|
||||
#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
|
||||
#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
|
||||
#else
|
||||
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
|
||||
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
|
||||
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
|
||||
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
|
||||
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
|
||||
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
|
||||
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
|
||||
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
|
||||
#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
|
||||
#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
|
||||
#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
|
||||
#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
|
||||
#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
|
||||
#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
|
||||
#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
|
||||
#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
|
||||
#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
|
||||
#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
|
||||
#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
|
||||
#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
|
||||
#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
|
||||
#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
|
||||
#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
|
||||
#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
|
||||
|
||||
#if defined(CONFIG_RAMBOOT_PBL)
|
||||
#define CONFIG_SYS_RAMBOOT
|
||||
#endif
|
||||
|
||||
#define CONFIG_HWCONFIG
|
||||
|
||||
/* define to use L1 as initial stack */
|
||||
#define CONFIG_L1_INIT_RAM
|
||||
#define CONFIG_SYS_INIT_RAM_LOCK
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
|
||||
/* The assembler doesn't like typecast */
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
|
||||
((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
|
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
|
||||
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
|
||||
GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
|
||||
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
|
||||
|
||||
/* Serial Port - controlled on board with jumper J8
|
||||
* open - index 2
|
||||
* shorted - index 1
|
||||
*/
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
|
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
|
||||
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
|
||||
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
|
||||
#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
|
||||
|
||||
/* Video */
|
||||
#define CONFIG_FSL_DIU_FB
|
||||
#ifdef CONFIG_FSL_DIU_FB
|
||||
#define CONFIG_FSL_DIU_CH7301
|
||||
#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
|
||||
#define CONFIG_VIDEO_LOGO
|
||||
#define CONFIG_VIDEO_BMP_LOGO
|
||||
#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
|
||||
/*
|
||||
* With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
|
||||
* disable empty flash sector detection, which is I/O-intensive.
|
||||
*/
|
||||
#undef CONFIG_SYS_FLASH_EMPTY_INFO
|
||||
#endif
|
||||
|
||||
/* I2C */
|
||||
|
||||
#ifndef CONFIG_DM_I2C
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
|
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 50000
|
||||
#define CONFIG_SYS_FSL_I2C3_SPEED 50000
|
||||
#define CONFIG_SYS_FSL_I2C4_SPEED 50000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
|
||||
#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
|
||||
#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
|
||||
|
||||
#define I2C_MUX_PCA_ADDR 0x77
|
||||
#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
|
||||
|
||||
/* I2C bus multiplexer */
|
||||
#define I2C_MUX_CH_DEFAULT 0x8
|
||||
#define I2C_MUX_CH_DIU 0xC
|
||||
|
||||
/* LDI/DVI Encoder for display */
|
||||
#define CONFIG_SYS_I2C_LDI_ADDR 0x38
|
||||
#define CONFIG_SYS_I2C_DVI_ADDR 0x75
|
||||
#define CONFIG_SYS_I2C_DVI_BUS_NUM 0
|
||||
|
||||
/*
|
||||
* RTC configuration
|
||||
*/
|
||||
#define RTC
|
||||
#define CONFIG_RTC_DS3231 1
|
||||
#define CONFIG_SYS_I2C_RTC_ADDR 0x68
|
||||
|
||||
/*
|
||||
* eSPI - Enhanced SPI
|
||||
*/
|
||||
|
||||
/*
|
||||
* General PCI
|
||||
* Memory space is mapped 1-1, but I/O space must start from 0.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
/* controller 1, direct to uli, tgtid 3, Base address 20000 */
|
||||
#ifdef CONFIG_PCIE1
|
||||
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
|
||||
#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
|
||||
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
|
||||
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
|
||||
#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
|
||||
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
|
||||
#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
|
||||
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
|
||||
#endif
|
||||
|
||||
/* controller 2, Slot 2, tgtid 2, Base address 201000 */
|
||||
#ifdef CONFIG_PCIE2
|
||||
#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
|
||||
#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
|
||||
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
|
||||
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
|
||||
#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
|
||||
#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
|
||||
#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
|
||||
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
|
||||
#endif
|
||||
|
||||
/* controller 3, Slot 1, tgtid 1, Base address 202000 */
|
||||
#ifdef CONFIG_PCIE3
|
||||
#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
|
||||
#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
|
||||
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
|
||||
#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
|
||||
#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
|
||||
#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
|
||||
#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
|
||||
#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
|
||||
#endif
|
||||
|
||||
/* controller 4, Base address 203000 */
|
||||
#ifdef CONFIG_PCIE4
|
||||
#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
|
||||
#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
|
||||
#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
|
||||
#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
|
||||
#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
|
||||
#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
|
||||
#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
|
||||
#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
|
||||
#endif
|
||||
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
/* SATA */
|
||||
#define CONFIG_FSL_SATA_V2
|
||||
#ifdef CONFIG_FSL_SATA_V2
|
||||
#define CONFIG_SYS_SATA_MAX_DEVICE 2
|
||||
#define CONFIG_SATA1
|
||||
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
|
||||
#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
|
||||
#define CONFIG_SATA2
|
||||
#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
|
||||
#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
|
||||
|
||||
#define CONFIG_LBA48
|
||||
#endif
|
||||
|
||||
/*
|
||||
* USB
|
||||
*/
|
||||
#define CONFIG_HAS_FSL_DR_USB
|
||||
|
||||
#ifdef CONFIG_HAS_FSL_DR_USB
|
||||
#ifdef CONFIG_USB_EHCI_HCD
|
||||
#define CONFIG_USB_EHCI_FSL
|
||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MMC
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
|
||||
#define CONFIG_FSL_ESDHC_ADAPTER_IDENT
|
||||
#endif
|
||||
|
||||
/* Qman/Bman */
|
||||
#ifndef CONFIG_NOBQFMAN
|
||||
#define CONFIG_SYS_BMAN_NUM_PORTALS 10
|
||||
#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
|
||||
#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
|
||||
#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
|
||||
#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
|
||||
#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
|
||||
#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
|
||||
#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
|
||||
CONFIG_SYS_BMAN_CENA_SIZE)
|
||||
#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
|
||||
#define CONFIG_SYS_QMAN_NUM_PORTALS 10
|
||||
#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
|
||||
#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
|
||||
#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
|
||||
#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
|
||||
#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
|
||||
#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
|
||||
#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
|
||||
CONFIG_SYS_QMAN_CENA_SIZE)
|
||||
#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
|
||||
#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
|
||||
|
||||
#define CONFIG_SYS_DPAA_FMAN
|
||||
#define CONFIG_SYS_DPAA_PME
|
||||
|
||||
/* Default address of microcode for the Linux Fman driver */
|
||||
#if defined(CONFIG_SPIFLASH)
|
||||
/*
|
||||
* env is stored at 0x100000, sector size is 0x10000, ucode is stored after
|
||||
* env, so we got 0x110000.
|
||||
*/
|
||||
#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
|
||||
#elif defined(CONFIG_SDCARD)
|
||||
/*
|
||||
* PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
|
||||
* about 825KB (1650 blocks), Env is stored after the image, and the env size is
|
||||
* 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
|
||||
*/
|
||||
#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
|
||||
#elif defined(CONFIG_MTD_RAW_NAND)
|
||||
#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
|
||||
#else
|
||||
#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
|
||||
#define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
|
||||
#endif
|
||||
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
|
||||
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
|
||||
#endif /* CONFIG_NOBQFMAN */
|
||||
|
||||
#ifdef CONFIG_SYS_DPAA_FMAN
|
||||
#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
|
||||
#define SGMII_CARD_PORT2_PHY_ADDR 0x10
|
||||
#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
|
||||
#define SGMII_CARD_PORT4_PHY_ADDR 0x11
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FMAN_ENET
|
||||
#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01
|
||||
#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02
|
||||
|
||||
#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
|
||||
#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
|
||||
#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
|
||||
#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
|
||||
|
||||
#define CONFIG_ETHPRIME "FM1@DTSEC1"
|
||||
#endif
|
||||
|
||||
/* Enable VSC9953 L2 Switch driver */
|
||||
#define CONFIG_VSC9953
|
||||
#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x14
|
||||
#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x18
|
||||
|
||||
/*
|
||||
* Dynamic MTD Partition support with mtdparts
|
||||
*/
|
||||
|
||||
/*
|
||||
* Environment
|
||||
*/
|
||||
#define CONFIG_LOADS_ECHO /* echo on for serial download */
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 64 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
|
||||
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
|
||||
|
||||
#ifdef CONFIG_CMD_KGDB
|
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Environment Configuration
|
||||
*/
|
||||
#define CONFIG_ROOTPATH "/opt/nfsroot"
|
||||
#define CONFIG_BOOTFILE "uImage"
|
||||
#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
|
||||
|
||||
/* default location for tftp and bootm */
|
||||
#define CONFIG_LOADADDR 1000000
|
||||
|
||||
#define __USB_PHY_TYPE utmi
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"hwconfig=fsl_ddr:bank_intlv=auto;" \
|
||||
"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
|
||||
"netdev=eth0\0" \
|
||||
"video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \
|
||||
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
|
||||
"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
|
||||
"tftpflash=tftpboot $loadaddr $uboot && " \
|
||||
"protect off $ubootaddr +$filesize && " \
|
||||
"erase $ubootaddr +$filesize && " \
|
||||
"cp.b $loadaddr $ubootaddr $filesize && " \
|
||||
"protect on $ubootaddr +$filesize && " \
|
||||
"cmp.b $loadaddr $ubootaddr $filesize\0" \
|
||||
"consoledev=ttyS0\0" \
|
||||
"ramdiskaddr=2000000\0" \
|
||||
"ramdiskfile=t1040qds/ramdisk.uboot\0" \
|
||||
"fdtaddr=1e00000\0" \
|
||||
"fdtfile=t1040qds/t1040qds.dtb\0" \
|
||||
"bdev=sda3\0"
|
||||
|
||||
#define CONFIG_LINUX \
|
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"setenv ramdiskaddr 0x02000000;" \
|
||||
"setenv fdtaddr 0x00c00000;" \
|
||||
"setenv loadaddr 0x1000000;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr"
|
||||
|
||||
#define CONFIG_HDBOOT \
|
||||
"setenv bootargs root=/dev/$bdev rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr"
|
||||
|
||||
#define CONFIG_NFSBOOTCOMMAND \
|
||||
"setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$serverip:$rootpath " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr"
|
||||
|
||||
#define CONFIG_RAMBOOTCOMMAND \
|
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND CONFIG_LINUX
|
||||
|
||||
#include <asm/fsl_secure_boot.h>
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in a new issue