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https://github.com/AsahiLinux/u-boot
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mips: octeon: Add minimal Octeon 3 EBB7304 EVK support
This patch adds very basic minimal support for the Marvell Octeon 3 CN73xx based EBB7304 EVK. Please note that the basic Octeon port does not support DDR3/4 initialization yet. To still use U-Boot on with this port, the L2 cache (4MiB) is used as RAM. This way, U-Boot can boot to the prompt on this board. Supported devices: - UART - reset - CFI parallel NOR flash Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese
Daniel Schwierzeck
parent
e9609dc38b
commit
5fef24c912
10 changed files with 231 additions and 0 deletions
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@ -18,6 +18,7 @@ dtb-$(CONFIG_BOARD_COMTREND_VR3032U) += comtrend,vr-3032u.dtb
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dtb-$(CONFIG_BOARD_COMTREND_WAP5813N) += comtrend,wap-5813n.dtb
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dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb
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dtb-$(CONFIG_BOARD_MT7628_RFB) += mediatek,mt7628-rfb.dtb
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dtb-$(CONFIG_TARGET_OCTEON_EBB7304) += mrvl,octeon-ebb7304.dtb
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dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb
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dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb
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dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f@st1704.dtb
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96
arch/mips/dts/mrvl,octeon-ebb7304.dts
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96
arch/mips/dts/mrvl,octeon-ebb7304.dts
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@ -0,0 +1,96 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Marvell / Cavium Inc. EVB CN7300
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*/
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/dts-v1/;
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/include/ "mrvl,cn73xx.dtsi"
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/ {
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model = "cavium,ebb7304";
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compatible = "cavium,ebb7304";
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aliases {
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serial0 = &uart0;
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};
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chosen {
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stdout-path = &uart0;
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};
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};
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&bootbus {
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/*
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* bootbus CS0 for CFI flash is remapped (0x1fc0.0000 -> 1f40.0000)
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* as the initial size is too small for the 8MiB flash device
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*/
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ranges = <0 0 0 0x1f400000 0xc00000>,
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<1 0 0x10000 0x10000000 0>,
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<2 0 0x10000 0x20000000 0>,
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<3 0 0x10000 0x30000000 0>,
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<4 0 0 0x1d020000 0x10000>,
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<5 0 0x10000 0x50000000 0>,
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<6 0 0x10000 0x60000000 0>,
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<7 0 0x10000 0x70000000 0>;
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cavium,cs-config@0 {
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compatible = "cavium,octeon-3860-bootbus-config";
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cavium,cs-index = <0>;
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cavium,t-adr = <10>;
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cavium,t-ce = <50>;
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cavium,t-oe = <50>;
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cavium,t-we = <35>;
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cavium,t-rd-hld = <25>;
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cavium,t-wr-hld = <35>;
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cavium,t-pause = <0>;
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cavium,t-wait = <50>;
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cavium,t-page = <30>;
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cavium,t-rd-dly = <0>;
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cavium,page-mode = <1>;
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cavium,pages = <8>;
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cavium,bus-width = <8>;
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};
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cavium,cs-config@4 {
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compatible = "cavium,octeon-3860-bootbus-config";
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cavium,cs-index = <4>;
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cavium,t-adr = <10>;
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cavium,t-ce = <10>;
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cavium,t-oe = <160>;
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cavium,t-we = <100>;
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cavium,t-rd-hld = <10>;
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cavium,t-wr-hld = <0>;
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cavium,t-pause = <50>;
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cavium,t-wait = <50>;
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cavium,t-page = <10>;
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cavium,t-rd-dly = <10>;
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cavium,pages = <0>;
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cavium,bus-width = <8>;
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};
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flash0: nor@0,0 {
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compatible = "cfi-flash";
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reg = <0 0 0x800000>;
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "bootloader";
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reg = <0 0x340000>;
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read-only;
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};
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partition@300000 {
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label = "storage";
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reg = <0x340000 0x4be000>;
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};
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partition@7fe000 {
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label = "environment";
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reg = <0x7fe000 0x2000>;
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read-only;
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};
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};
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};
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&uart0 {
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clock-frequency = <1200000000>;
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};
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@ -31,6 +31,18 @@ config SOC_OCTEON3
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endchoice
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choice
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prompt "Octeon 3 board select"
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default TARGET_OCTEON_EBB7304
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config TARGET_OCTEON_EBB7304
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bool "Marvell Octeon EBB7304"
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select OCTEON_CN73XX
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help
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Choose this for the Octeon EBB7304 board
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endchoice
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config SYS_DCACHE_SIZE
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default 32768
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@ -43,4 +55,6 @@ config SYS_ICACHE_SIZE
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config SYS_ICACHE_LINE_SIZE
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default 128
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source "board/Marvell/octeon_ebb7304/Kconfig"
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endmenu
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19
board/Marvell/octeon_ebb7304/Kconfig
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19
board/Marvell/octeon_ebb7304/Kconfig
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@ -0,0 +1,19 @@
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if TARGET_OCTEON_EBB7304
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config SYS_BOARD
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string
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default "octeon_ebb7304"
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config SYS_VENDOR
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string
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default "Marvell"
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config SYS_CONFIG_NAME
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string
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default "octeon_ebb7304"
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config DEFAULT_DEVICE_TREE
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string
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default "mrvl,octeon-ebb7304"
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endif
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7
board/Marvell/octeon_ebb7304/MAINTAINERS
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7
board/Marvell/octeon_ebb7304/MAINTAINERS
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@ -0,0 +1,7 @@
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OCTEON_EBB7304 BOARD
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M: Aaron Williams <awilliams@marvell.com>
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S: Maintained
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F: board/Marvell/octeon_ebb7304/*
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F: configs/octeon_ebb7304_defconfig
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F: include/configs/octeon_ebb7304.h
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F: arch/mips/dts/mrvl,octeon-ebb7304.dts
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8
board/Marvell/octeon_ebb7304/Makefile
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8
board/Marvell/octeon_ebb7304/Makefile
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@ -0,0 +1,8 @@
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#
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# Copyright (C) 2020 Stefan Roese <sr@denx.de>
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# Copyright (C) 2019-2020 Marvell International Ltd.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y := board.o
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9
board/Marvell/octeon_ebb7304/board.c
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9
board/Marvell/octeon_ebb7304/board.c
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@ -0,0 +1,9 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2020 Stefan Roese <sr@denx.de>
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*/
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/*
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* Nothing included right now. Code will be added in follow-up
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* patches.
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*/
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38
configs/octeon_ebb7304_defconfig
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38
configs/octeon_ebb7304_defconfig
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@ -0,0 +1,38 @@
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CONFIG_MIPS=y
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CONFIG_SYS_TEXT_BASE=0xffffffff80000000
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CONFIG_SYS_MALLOC_F_LEN=0x4000
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CONFIG_ENV_SIZE=0x2000
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CONFIG_ENV_SECT_SIZE=0x10000
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CONFIG_NR_DRAM_BANKS=2
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CONFIG_DEBUG_UART_BASE=0x8001180000000800
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CONFIG_DEBUG_UART_CLOCK=1200000000
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CONFIG_ARCH_OCTEON=y
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# CONFIG_MIPS_CACHE_SETUP is not set
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# CONFIG_MIPS_CACHE_DISABLE is not set
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CONFIG_DEBUG_UART=y
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CONFIG_SYS_CONSOLE_INFO_QUIET=y
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CONFIG_HUSH_PARSER=y
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CONFIG_CMD_MTD=y
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CONFIG_CMD_PCI=y
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CONFIG_CMD_DHCP=y
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CONFIG_CMD_PING=y
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CONFIG_CMD_TIME=y
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CONFIG_ENV_IS_IN_FLASH=y
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CONFIG_ENV_ADDR=0x1FBFE000
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CONFIG_CLK=y
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# CONFIG_INPUT is not set
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CONFIG_MTD=y
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CONFIG_DM_MTD=y
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CONFIG_MTD_NOR_FLASH=y
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CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_CFI_FLASH=y
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CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_FLASH_CFI_MTD=y
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CONFIG_SYS_FLASH_CFI=y
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# CONFIG_NETDEVICES is not set
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CONFIG_DEBUG_UART_SHIFT=3
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CONFIG_DEBUG_UART_ANNOUNCE=y
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CONFIG_SYS_NS16550=y
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CONFIG_SYSRESET=y
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CONFIG_SYSRESET_OCTEON=y
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CONFIG_HEXDUMP=y
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19
include/configs/octeon_common.h
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19
include/configs/octeon_common.h
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@ -0,0 +1,19 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2019-2020
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* Marvell <www.marvell.com>
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*/
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#ifndef __OCTEON_COMMON_H__
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#define __OCTEON_COMMON_H__
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/* No DDR init yet -> run in L2 cache with limited resources */
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#define CONFIG_SYS_MALLOC_LEN (256 << 10)
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#define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + (1 << 20))
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#define CONFIG_SYS_INIT_SP_OFFSET 0x180000
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#endif /* __OCTEON_COMMON_H__ */
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20
include/configs/octeon_ebb7304.h
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20
include/configs/octeon_ebb7304.h
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@ -0,0 +1,20 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2019-2020
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* Marvell <www.marvell.com>
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*/
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#ifndef __CONFIG_H__
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#define __CONFIG_H__
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#include "octeon_common.h"
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/*
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* CFI flash
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*/
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#define CONFIG_SYS_MAX_FLASH_BANKS 1
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#define CONFIG_SYS_MAX_FLASH_SECT 256
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
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#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */
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#endif /* __CONFIG_H__ */
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