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x86: irq: Fix some typos
Fix some typos in arch/x86/include/asm/irq.h. Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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1 changed files with 3 additions and 3 deletions
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@ -12,8 +12,8 @@
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* Intel interrupt router configuration mechanism
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*
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* There are two known ways of Intel interrupt router configuration mechanism
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* so far. On most cases, the IRQ routing configuraiton is controlled by PCI
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* configuraiton registers on the legacy bridge, normally PCI BDF(0, 31, 0).
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* so far. On most cases, the IRQ routing configuration is controlled by PCI
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* configuration registers on the legacy bridge, normally PCI BDF(0, 31, 0).
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* On some newer platforms like BayTrail and Braswell, the IRQ routing is now
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* in the IBASE register block where IBASE is memory-mapped.
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*/
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@ -36,7 +36,7 @@ struct pirq_regmap {
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* @link_base: link value base number
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* @link_num: number of PIRQ links supported
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* @has_regmap: has mapping table between PIRQ link and routing register offset
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* @irq_mask: IRQ mask reprenting the 16 IRQs in 8259, bit N is 1 means
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* @irq_mask: IRQ mask representing the 16 IRQs in 8259, bit N is 1 means
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* IRQ N is available to be routed
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* @lb_bdf: irq router's PCI bus/device/function number encoding
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* @ibase: IBASE register block base address
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