mirror of
https://github.com/AsahiLinux/u-boot
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omap5: Copy device tree from linux 5.7.y
Copy all the device tree files required for omap5 uevm support from mainline Linux. Signed-off-by: Tero Kristo <t-kristo@ti.com>
This commit is contained in:
Tero Kristo
Lokesh Vutla
parent
8812ed9725
commit
8f1ed2e4ed
8 changed files with 5771 additions and 0 deletions
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@ -856,6 +856,9 @@ dtb-$(CONFIG_TARGET_OMAP4_SDP4430) += \
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omap4-sdp.dtb \
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omap4-sdp-es23plus.dtb
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dtb-$(CONFIG_TARGET_OMAP5_UEVM) += \
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omap5-uevm.dtb
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dtb-$(CONFIG_TARGET_SAMA5D2_PTC_EK) += \
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at91-sama5d2_ptc_ek.dtb
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762
arch/arm/dts/omap5-board-common.dtsi
Normal file
762
arch/arm/dts/omap5-board-common.dtsi
Normal file
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@ -0,0 +1,762 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
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*/
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#include "omap5.dtsi"
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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aliases {
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display0 = &hdmi0;
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};
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chosen {
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stdout-path = &uart3;
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};
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vmain: fixedregulator-vmain {
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compatible = "regulator-fixed";
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regulator-name = "vmain";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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};
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vsys_cobra: fixedregulator-vsys_cobra {
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compatible = "regulator-fixed";
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regulator-name = "vsys_cobra";
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vin-supply = <&vmain>;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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};
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vdds_1v8_main: fixedregulator-vdds_1v8_main {
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compatible = "regulator-fixed";
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regulator-name = "vdds_1v8_main";
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vin-supply = <&smps7_reg>;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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vmmcsd_fixed: fixedregulator-mmcsd {
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compatible = "regulator-fixed";
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regulator-name = "vmmcsd_fixed";
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3000000>;
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};
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mmc3_pwrseq: sdhci0_pwrseq {
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compatible = "mmc-pwrseq-simple";
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clocks = <&clk32kgaudio>;
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clock-names = "ext_clock";
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};
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vmmcsdio_fixed: fixedregulator-mmcsdio {
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compatible = "regulator-fixed";
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regulator-name = "vmmcsdio_fixed";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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gpio = <&gpio5 12 GPIO_ACTIVE_HIGH>; /* gpio140 WLAN_EN */
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enable-active-high;
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startup-delay-us = <70000>;
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pinctrl-names = "default";
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pinctrl-0 = <&wlan_pins>;
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};
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/* HS USB Host PHY on PORT 2 */
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hsusb2_phy: hsusb2_phy {
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compatible = "usb-nop-xceiv";
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reset-gpios = <&gpio3 16 GPIO_ACTIVE_LOW>; /* gpio3_80 HUB_NRESET */
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clocks = <&auxclk1_ck>;
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clock-names = "main_clk";
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clock-frequency = <19200000>;
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#phy-cells = <0>;
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};
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/* HS USB Host PHY on PORT 3 */
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hsusb3_phy: hsusb3_phy {
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compatible = "usb-nop-xceiv";
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reset-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; /* gpio3_79 ETH_NRESET */
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#phy-cells = <0>;
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};
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tpd12s015: encoder {
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compatible = "ti,tpd12s015";
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pinctrl-names = "default";
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pinctrl-0 = <&tpd12s015_pins>;
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/* gpios defined in the board specific dts */
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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tpd12s015_in: endpoint {
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remote-endpoint = <&hdmi_out>;
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};
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};
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port@1 {
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reg = <1>;
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tpd12s015_out: endpoint {
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remote-endpoint = <&hdmi_connector_in>;
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};
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};
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};
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};
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hdmi0: connector {
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compatible = "hdmi-connector";
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label = "hdmi";
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type = "b";
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port {
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hdmi_connector_in: endpoint {
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remote-endpoint = <&tpd12s015_out>;
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};
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};
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};
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sound: sound {
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compatible = "ti,abe-twl6040";
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ti,model = "omap5-uevm";
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ti,jack-detection;
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ti,mclk-freq = <19200000>;
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ti,mcpdm = <&mcpdm>;
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ti,twl6040 = <&twl6040>;
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/* Audio routing */
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ti,audio-routing =
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"Headset Stereophone", "HSOL",
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"Headset Stereophone", "HSOR",
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"Line Out", "AUXL",
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"Line Out", "AUXR",
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"HSMIC", "Headset Mic",
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"Headset Mic", "Headset Mic Bias",
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"AFML", "Line In",
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"AFMR", "Line In";
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};
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};
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&gpio8 {
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/* TI trees use GPIO instead of msecure, see also muxing */
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p234 {
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gpio-hog;
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gpios = <10 GPIO_ACTIVE_HIGH>;
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output-high;
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line-name = "gpio8_234/msecure";
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};
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};
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&omap5_pmx_core {
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pinctrl-names = "default";
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pinctrl-0 = <
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&usbhost_pins
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&led_gpio_pins
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>;
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twl6040_pins: pinmux_twl6040_pins {
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pinctrl-single,pins = <
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OMAP5_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_141 */
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>;
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};
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mcpdm_pins: pinmux_mcpdm_pins {
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pinctrl-single,pins = <
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OMAP5_IOPAD(0x182, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_clks.abe_clks */
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OMAP5_IOPAD(0x19c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_ul_data.abemcpdm_ul_data */
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OMAP5_IOPAD(0x19e, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_dl_data.abemcpdm_dl_data */
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OMAP5_IOPAD(0x1a0, PIN_INPUT_PULLUP | MUX_MODE0) /* abemcpdm_frame.abemcpdm_frame */
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OMAP5_IOPAD(0x1a2, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_lb_clk.abemcpdm_lb_clk */
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>;
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};
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mcbsp1_pins: pinmux_mcbsp1_pins {
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pinctrl-single,pins = <
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OMAP5_IOPAD(0x18c, PIN_INPUT | MUX_MODE1) /* abedmic_clk2.abemcbsp1_fsx */
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OMAP5_IOPAD(0x18e, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* abedmic_clk3.abemcbsp1_dx */
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OMAP5_IOPAD(0x190, PIN_INPUT | MUX_MODE1) /* abeslimbus1_clock.abemcbsp1_clkx */
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OMAP5_IOPAD(0x192, PIN_INPUT_PULLDOWN | MUX_MODE1) /* abeslimbus1_data.abemcbsp1_dr */
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>;
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};
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mcbsp2_pins: pinmux_mcbsp2_pins {
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pinctrl-single,pins = <
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OMAP5_IOPAD(0x194, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcbsp2_dr.abemcbsp2_dr */
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OMAP5_IOPAD(0x196, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abemcbsp2_dx.abemcbsp2_dx */
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OMAP5_IOPAD(0x198, PIN_INPUT | MUX_MODE0) /* abemcbsp2_fsx.abemcbsp2_fsx */
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OMAP5_IOPAD(0x19a, PIN_INPUT | MUX_MODE0) /* abemcbsp2_clkx.abemcbsp2_clkx */
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>;
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};
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i2c1_pins: pinmux_i2c1_pins {
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pinctrl-single,pins = <
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OMAP5_IOPAD(0x1f2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */
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OMAP5_IOPAD(0x1f4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */
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>;
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};
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mcspi2_pins: pinmux_mcspi2_pins {
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pinctrl-single,pins = <
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OMAP5_IOPAD(0x0fc, PIN_INPUT | MUX_MODE0) /* mcspi2_clk */
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OMAP5_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0) /* mcspi2_simo */
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OMAP5_IOPAD(0x100, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi2_somi */
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OMAP5_IOPAD(0x102, PIN_OUTPUT | MUX_MODE0) /* mcspi2_cs0 */
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>;
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};
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mcspi3_pins: pinmux_mcspi3_pins {
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pinctrl-single,pins = <
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OMAP5_IOPAD(0x0b8, PIN_INPUT | MUX_MODE1) /* mcspi3_somi */
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OMAP5_IOPAD(0x0ba, PIN_INPUT | MUX_MODE1) /* mcspi3_cs0 */
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OMAP5_IOPAD(0x0bc, PIN_INPUT | MUX_MODE1) /* mcspi3_simo */
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OMAP5_IOPAD(0x0be, PIN_INPUT | MUX_MODE1) /* mcspi3_clk */
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>;
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};
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mmc3_pins: pinmux_mmc3_pins {
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pinctrl-single,pins = <
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OMAP5_IOPAD(0x01a4, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_clk */
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OMAP5_IOPAD(0x01a6, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_cmd */
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OMAP5_IOPAD(0x01a8, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data0 */
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OMAP5_IOPAD(0x01aa, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data1 */
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OMAP5_IOPAD(0x01ac, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data2 */
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OMAP5_IOPAD(0x01ae, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data3 */
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>;
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};
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wlan_pins: pinmux_wlan_pins {
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pinctrl-single,pins = <
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OMAP5_IOPAD(0x1bc, PIN_OUTPUT | MUX_MODE6) /* mcspi1_clk.gpio5_140 */
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>;
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};
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/* TI trees use GPIO mode; msecure mode does not work reliably? */
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palmas_msecure_pins: palmas_msecure_pins {
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pinctrl-single,pins = <
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OMAP5_IOPAD(0x180, PIN_OUTPUT | MUX_MODE6) /* gpio8_234 */
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>;
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};
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usbhost_pins: pinmux_usbhost_pins {
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pinctrl-single,pins = <
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OMAP5_IOPAD(0x0c4, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_strobe */
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OMAP5_IOPAD(0x0c6, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_data */
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OMAP5_IOPAD(0x1de, PIN_INPUT | MUX_MODE0) /* usbb3_hsic_strobe */
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OMAP5_IOPAD(0x1e0, PIN_INPUT | MUX_MODE0) /* usbb3_hsic_data */
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OMAP5_IOPAD(0x0b0, PIN_OUTPUT | MUX_MODE6) /* gpio3_80 HUB_NRESET */
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OMAP5_IOPAD(0x0ae, PIN_OUTPUT | MUX_MODE6) /* gpio3_79 ETH_NRESET */
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>;
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};
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led_gpio_pins: pinmux_led_gpio_pins {
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pinctrl-single,pins = <
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OMAP5_IOPAD(0x1d6, PIN_OUTPUT | MUX_MODE6) /* uart3_cts_rctx.gpio5_153 */
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>;
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};
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uart1_pins: pinmux_uart1_pins {
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pinctrl-single,pins = <
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OMAP5_IOPAD(0x0a0, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_cts */
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OMAP5_IOPAD(0x0a2, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_tx.uart1_cts */
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OMAP5_IOPAD(0x0a4, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rx.uart1_rts */
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OMAP5_IOPAD(0x0a6, PIN_OUTPUT | MUX_MODE0) /* uart1_rx.uart1_rts */
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>;
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};
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uart3_pins: pinmux_uart3_pins {
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pinctrl-single,pins = <
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OMAP5_IOPAD(0x1da, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_irsd.uart3_tx_irtx */
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OMAP5_IOPAD(0x1dc, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_rx_irrx.uart3_usbb3_hsic */
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>;
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};
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uart5_pins: pinmux_uart5_pins {
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pinctrl-single,pins = <
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OMAP5_IOPAD(0x1b0, PIN_INPUT_PULLUP | MUX_MODE0) /* uart5_rx.uart5_rx */
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OMAP5_IOPAD(0x1b2, PIN_OUTPUT | MUX_MODE0) /* uart5_tx.uart5_tx */
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OMAP5_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE0) /* uart5_cts.uart5_rts */
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OMAP5_IOPAD(0x1b6, PIN_OUTPUT | MUX_MODE0) /* uart5_cts.uart5_rts */
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>;
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};
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dss_hdmi_pins: pinmux_dss_hdmi_pins {
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pinctrl-single,pins = <
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OMAP5_IOPAD(0x13c, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */
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OMAP5_IOPAD(0x140, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_scl.hdmi_ddc_scl */
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OMAP5_IOPAD(0x142, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_sda.hdmi_ddc_sda */
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>;
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};
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tpd12s015_pins: pinmux_tpd12s015_pins {
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pinctrl-single,pins = <
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OMAP5_IOPAD(0x13e, PIN_INPUT_PULLDOWN | MUX_MODE6) /* hdmi_hpd.gpio7_193 */
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>;
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};
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};
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&omap5_pmx_wkup {
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pinctrl-names = "default";
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pinctrl-0 = <
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&usbhost_wkup_pins
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>;
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palmas_sys_nirq_pins: pinmux_palmas_sys_nirq_pins {
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pinctrl-single,pins = <
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/* sys_nirq1 is pulled down as the SoC is inverting it for GIC */
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OMAP5_IOPAD(0x068, PIN_INPUT_PULLUP | MUX_MODE0)
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>;
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};
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usbhost_wkup_pins: pinmux_usbhost_wkup_pins {
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pinctrl-single,pins = <
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OMAP5_IOPAD(0x05a, PIN_OUTPUT | MUX_MODE0) /* fref_clk1_out, USB hub clk */
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>;
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};
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wlcore_irq_pin: pinmux_wlcore_irq_pin {
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pinctrl-single,pins = <
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OMAP5_IOPAD(0x40, PIN_INPUT | MUX_MODE6) /* llia_wakereqin.gpio1_wk14 */
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>;
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};
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};
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&mmc1 {
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vmmc-supply = <&ldo9_reg>;
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bus-width = <4>;
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};
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&mmc2 {
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vmmc-supply = <&vmmcsd_fixed>;
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bus-width = <8>;
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ti,non-removable;
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};
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&mmc3 {
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vmmc-supply = <&vmmcsdio_fixed>;
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mmc-pwrseq = <&mmc3_pwrseq>;
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bus-width = <4>;
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non-removable;
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cap-power-off-card;
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pinctrl-names = "default";
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pinctrl-0 = <&mmc3_pins>;
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interrupts-extended = <&wakeupgen GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH
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&omap5_pmx_core 0x16a>;
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#address-cells = <1>;
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#size-cells = <0>;
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wlcore: wlcore@2 {
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compatible = "ti,wl1271";
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reg = <2>;
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pinctrl-names = "default";
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pinctrl-0 = <&wlcore_irq_pin>;
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interrupt-parent = <&gpio1>;
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interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; /* gpio 14 */
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ref-clock-frequency = <26000000>;
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};
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};
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&mmc4 {
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status = "disabled";
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};
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&mmc5 {
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status = "disabled";
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};
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&i2c1 {
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1_pins>;
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clock-frequency = <400000>;
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palmas: palmas@48 {
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compatible = "ti,palmas";
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/* sys_nirq/ext_sys_irq pins get inverted at mpuss wakeupgen */
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interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_LOW>;
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reg = <0x48>;
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interrupt-controller;
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#interrupt-cells = <2>;
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ti,system-power-controller;
|
||||
ti,mux-pad1 = <0xa1>;
|
||||
ti,mux-pad2 = <0x1b>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&palmas_sys_nirq_pins &palmas_msecure_pins>;
|
||||
|
||||
palmas_gpio: gpio {
|
||||
compatible = "ti,palmas-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
extcon_usb3: palmas_usb {
|
||||
compatible = "ti,palmas-usb-vid";
|
||||
ti,enable-vbus-detection;
|
||||
ti,enable-id-detection;
|
||||
ti,wakeup;
|
||||
id-gpios = <&palmas_gpio 0 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
clk32kgaudio: palmas_clk32k@1 {
|
||||
compatible = "ti,palmas-clk32kgaudio";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
rtc {
|
||||
compatible = "ti,palmas-rtc";
|
||||
interrupt-parent = <&palmas>;
|
||||
interrupts = <8 IRQ_TYPE_NONE>;
|
||||
ti,backup-battery-chargeable;
|
||||
ti,backup-battery-charge-high-current;
|
||||
};
|
||||
|
||||
gpadc: gpadc {
|
||||
compatible = "ti,palmas-gpadc";
|
||||
interrupts = <18 0
|
||||
16 0
|
||||
17 0>;
|
||||
#io-channel-cells = <1>;
|
||||
ti,channel0-current-microamp = <5>;
|
||||
ti,channel3-current-microamp = <10>;
|
||||
};
|
||||
|
||||
palmas_pmic {
|
||||
compatible = "ti,palmas-pmic";
|
||||
interrupt-parent = <&palmas>;
|
||||
interrupts = <14 IRQ_TYPE_NONE>;
|
||||
interrupt-names = "short-irq";
|
||||
|
||||
ti,ldo6-vibrator;
|
||||
|
||||
smps123-in-supply = <&vsys_cobra>;
|
||||
smps45-in-supply = <&vsys_cobra>;
|
||||
smps6-in-supply = <&vsys_cobra>;
|
||||
smps7-in-supply = <&vsys_cobra>;
|
||||
smps8-in-supply = <&vsys_cobra>;
|
||||
smps9-in-supply = <&vsys_cobra>;
|
||||
smps10_out2-in-supply = <&vsys_cobra>;
|
||||
smps10_out1-in-supply = <&vsys_cobra>;
|
||||
ldo1-in-supply = <&vsys_cobra>;
|
||||
ldo2-in-supply = <&vsys_cobra>;
|
||||
ldo3-in-supply = <&vdds_1v8_main>;
|
||||
ldo4-in-supply = <&vdds_1v8_main>;
|
||||
ldo5-in-supply = <&vsys_cobra>;
|
||||
ldo6-in-supply = <&vdds_1v8_main>;
|
||||
ldo7-in-supply = <&vsys_cobra>;
|
||||
ldo8-in-supply = <&vsys_cobra>;
|
||||
ldo9-in-supply = <&vmmcsd_fixed>;
|
||||
ldoln-in-supply = <&vsys_cobra>;
|
||||
ldousb-in-supply = <&vsys_cobra>;
|
||||
|
||||
regulators {
|
||||
smps123_reg: smps123 {
|
||||
/* VDD_OPP_MPU */
|
||||
regulator-name = "smps123";
|
||||
regulator-min-microvolt = < 600000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
smps45_reg: smps45 {
|
||||
/* VDD_OPP_MM */
|
||||
regulator-name = "smps45";
|
||||
regulator-min-microvolt = < 600000>;
|
||||
regulator-max-microvolt = <1310000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
smps6_reg: smps6 {
|
||||
/* VDD_DDR3 - over VDD_SMPS6 */
|
||||
regulator-name = "smps6";
|
||||
regulator-min-microvolt = <1350000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
smps7_reg: smps7 {
|
||||
/* VDDS_1v8_OMAP over VDDS_1v8_MAIN */
|
||||
regulator-name = "smps7";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
smps8_reg: smps8 {
|
||||
/* VDD_OPP_CORE */
|
||||
regulator-name = "smps8";
|
||||
regulator-min-microvolt = < 600000>;
|
||||
regulator-max-microvolt = <1310000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
smps9_reg: smps9 {
|
||||
/* VDDA_2v1_AUD over VDD_2v1 */
|
||||
regulator-name = "smps9";
|
||||
regulator-min-microvolt = <2100000>;
|
||||
regulator-max-microvolt = <2100000>;
|
||||
ti,smps-range = <0x80>;
|
||||
};
|
||||
|
||||
smps10_out2_reg: smps10_out2 {
|
||||
/* VBUS_5V_OTG */
|
||||
regulator-name = "smps10_out2";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
smps10_out1_reg: smps10_out1 {
|
||||
/* VBUS_5V_OTG */
|
||||
regulator-name = "smps10_out1";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
};
|
||||
|
||||
ldo1_reg: ldo1 {
|
||||
/* VDDAPHY_CAM: vdda_csiport */
|
||||
regulator-name = "ldo1";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
ldo2_reg: ldo2 {
|
||||
/* VCC_2V8_DISP: Does not go anywhere */
|
||||
regulator-name = "ldo2";
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
/* Unused */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ldo3_reg: ldo3 {
|
||||
/* VDDAPHY_MDM: vdda_lli */
|
||||
regulator-name = "ldo3";
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-boot-on;
|
||||
/* Only if Modem is used */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ldo4_reg: ldo4 {
|
||||
/* VDDAPHY_DISP: vdda_dsiport/hdmi */
|
||||
regulator-name = "ldo4";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
ldo5_reg: ldo5 {
|
||||
/* VDDA_1V8_PHY: usb/sata/hdmi.. */
|
||||
regulator-name = "ldo5";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
ldo6_reg: ldo6 {
|
||||
/* VDDS_1V2_WKUP: hsic/ldo_emu_wkup */
|
||||
regulator-name = "ldo6";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
ldo7_reg: ldo7 {
|
||||
/* VDD_VPP: vpp1 */
|
||||
regulator-name = "ldo7";
|
||||
regulator-min-microvolt = <2000000>;
|
||||
regulator-max-microvolt = <2000000>;
|
||||
/* Only for efuse reprograming! */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ldo8_reg: ldo8 {
|
||||
/* VDD_3v0: Does not go anywhere */
|
||||
regulator-name = "ldo8";
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-boot-on;
|
||||
/* Unused */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ldo9_reg: ldo9 {
|
||||
/* VCC_DV_SDIO: vdds_sdcard */
|
||||
regulator-name = "ldo9";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
ldoln_reg: ldoln {
|
||||
/* VDDA_1v8_REF: vdds_osc/mm_l4per.. */
|
||||
regulator-name = "ldoln";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
ldousb_reg: ldousb {
|
||||
/* VDDA_3V_USB: VDDA_USBHS33 */
|
||||
regulator-name = "ldousb";
|
||||
regulator-min-microvolt = <3250000>;
|
||||
regulator-max-microvolt = <3250000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
regen3_reg: regen3 {
|
||||
/* REGEN3 controls LDO9 supply to card */
|
||||
regulator-name = "regen3";
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
palmas_power_button: palmas_power_button {
|
||||
compatible = "ti,palmas-pwrbutton";
|
||||
interrupt-parent = <&palmas>;
|
||||
interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
twl6040: twl@4b {
|
||||
compatible = "ti,twl6040";
|
||||
#clock-cells = <0>;
|
||||
reg = <0x4b>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&twl6040_pins>;
|
||||
|
||||
/* sys_nirq/ext_sys_irq pins get inverted at mpuss wakeupgen */
|
||||
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
/* audpwron gpio defined in the board specific dts */
|
||||
|
||||
vio-supply = <&smps7_reg>;
|
||||
v2v1-supply = <&smps9_reg>;
|
||||
enable-active-high;
|
||||
|
||||
clocks = <&clk32kgaudio>, <&fref_xtal_ck>;
|
||||
clock-names = "clk32k", "mclk";
|
||||
};
|
||||
};
|
||||
|
||||
&mcpdm_module {
|
||||
/* Module on the SoC needs external clock from the PMIC */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcpdm_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mcpdm {
|
||||
clocks = <&twl6040>;
|
||||
clock-names = "pdmclk";
|
||||
};
|
||||
|
||||
&mcbsp1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcbsp1_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mcbsp2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcbsp2_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbhshost {
|
||||
port2-mode = "ehci-hsic";
|
||||
port3-mode = "ehci-hsic";
|
||||
};
|
||||
|
||||
&usbhsehci {
|
||||
phys = <0 &hsusb2_phy &hsusb3_phy>;
|
||||
};
|
||||
|
||||
&usb3 {
|
||||
extcon = <&extcon_usb3>;
|
||||
vbus-supply = <&smps10_out1_reg>;
|
||||
};
|
||||
|
||||
&dwc3 {
|
||||
extcon = <&extcon_usb3>;
|
||||
dr_mode = "otg";
|
||||
};
|
||||
|
||||
&mcspi1 {
|
||||
|
||||
};
|
||||
|
||||
&mcspi2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcspi2_pins>;
|
||||
};
|
||||
|
||||
&mcspi3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcspi3_pins>;
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1_pins>;
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart3_pins>;
|
||||
interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&omap5_pmx_core 0x19c>;
|
||||
};
|
||||
|
||||
&uart5 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart5_pins>;
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu0-supply = <&smps123_reg>;
|
||||
};
|
||||
|
||||
&dss {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
status = "ok";
|
||||
|
||||
/* vdda-supply populated in board specific dts file */
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&dss_hdmi_pins>;
|
||||
|
||||
port {
|
||||
hdmi_out: endpoint {
|
||||
remote-endpoint = <&tpd12s015_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
449
arch/arm/dts/omap5-l4-abe.dtsi
Normal file
449
arch/arm/dts/omap5-l4-abe.dtsi
Normal file
|
|
@ -0,0 +1,449 @@
|
|||
&l4_abe { /* 0x40100000 */
|
||||
compatible = "ti,omap5-l4-abe", "simple-bus";
|
||||
reg = <0x40100000 0x400>,
|
||||
<0x40100400 0x400>;
|
||||
reg-names = "la", "ap";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */
|
||||
<0x49000000 0x49000000 0x100000>;
|
||||
segment@0 { /* 0x40100000 */
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges =
|
||||
/* CPU to L4 ABE mapping */
|
||||
<0x00000000 0x00000000 0x000400>, /* ap 0 */
|
||||
<0x00000400 0x00000400 0x000400>, /* ap 1 */
|
||||
<0x00022000 0x00022000 0x001000>, /* ap 2 */
|
||||
<0x00023000 0x00023000 0x001000>, /* ap 3 */
|
||||
<0x00024000 0x00024000 0x001000>, /* ap 4 */
|
||||
<0x00025000 0x00025000 0x001000>, /* ap 5 */
|
||||
<0x00026000 0x00026000 0x001000>, /* ap 6 */
|
||||
<0x00027000 0x00027000 0x001000>, /* ap 7 */
|
||||
<0x00028000 0x00028000 0x001000>, /* ap 8 */
|
||||
<0x00029000 0x00029000 0x001000>, /* ap 9 */
|
||||
<0x0002a000 0x0002a000 0x001000>, /* ap 10 */
|
||||
<0x0002b000 0x0002b000 0x001000>, /* ap 11 */
|
||||
<0x0002e000 0x0002e000 0x001000>, /* ap 12 */
|
||||
<0x0002f000 0x0002f000 0x001000>, /* ap 13 */
|
||||
<0x00030000 0x00030000 0x001000>, /* ap 14 */
|
||||
<0x00031000 0x00031000 0x001000>, /* ap 15 */
|
||||
<0x00032000 0x00032000 0x001000>, /* ap 16 */
|
||||
<0x00033000 0x00033000 0x001000>, /* ap 17 */
|
||||
<0x00038000 0x00038000 0x001000>, /* ap 18 */
|
||||
<0x00039000 0x00039000 0x001000>, /* ap 19 */
|
||||
<0x0003a000 0x0003a000 0x001000>, /* ap 20 */
|
||||
<0x0003b000 0x0003b000 0x001000>, /* ap 21 */
|
||||
<0x0003c000 0x0003c000 0x001000>, /* ap 22 */
|
||||
<0x0003d000 0x0003d000 0x001000>, /* ap 23 */
|
||||
<0x0003e000 0x0003e000 0x001000>, /* ap 24 */
|
||||
<0x0003f000 0x0003f000 0x001000>, /* ap 25 */
|
||||
<0x00080000 0x00080000 0x010000>, /* ap 26 */
|
||||
<0x00080000 0x00080000 0x001000>, /* ap 27 */
|
||||
<0x000a0000 0x000a0000 0x010000>, /* ap 28 */
|
||||
<0x000a0000 0x000a0000 0x001000>, /* ap 29 */
|
||||
<0x000c0000 0x000c0000 0x010000>, /* ap 30 */
|
||||
<0x000c0000 0x000c0000 0x001000>, /* ap 31 */
|
||||
<0x000f1000 0x000f1000 0x001000>, /* ap 32 */
|
||||
<0x000f2000 0x000f2000 0x001000>, /* ap 33 */
|
||||
|
||||
/* L3 to L4 ABE mapping */
|
||||
<0x49000000 0x49000000 0x000400>, /* ap 0 */
|
||||
<0x49000400 0x49000400 0x000400>, /* ap 1 */
|
||||
<0x49022000 0x49022000 0x001000>, /* ap 2 */
|
||||
<0x49023000 0x49023000 0x001000>, /* ap 3 */
|
||||
<0x49024000 0x49024000 0x001000>, /* ap 4 */
|
||||
<0x49025000 0x49025000 0x001000>, /* ap 5 */
|
||||
<0x49026000 0x49026000 0x001000>, /* ap 6 */
|
||||
<0x49027000 0x49027000 0x001000>, /* ap 7 */
|
||||
<0x49028000 0x49028000 0x001000>, /* ap 8 */
|
||||
<0x49029000 0x49029000 0x001000>, /* ap 9 */
|
||||
<0x4902a000 0x4902a000 0x001000>, /* ap 10 */
|
||||
<0x4902b000 0x4902b000 0x001000>, /* ap 11 */
|
||||
<0x4902e000 0x4902e000 0x001000>, /* ap 12 */
|
||||
<0x4902f000 0x4902f000 0x001000>, /* ap 13 */
|
||||
<0x49030000 0x49030000 0x001000>, /* ap 14 */
|
||||
<0x49031000 0x49031000 0x001000>, /* ap 15 */
|
||||
<0x49032000 0x49032000 0x001000>, /* ap 16 */
|
||||
<0x49033000 0x49033000 0x001000>, /* ap 17 */
|
||||
<0x49038000 0x49038000 0x001000>, /* ap 18 */
|
||||
<0x49039000 0x49039000 0x001000>, /* ap 19 */
|
||||
<0x4903a000 0x4903a000 0x001000>, /* ap 20 */
|
||||
<0x4903b000 0x4903b000 0x001000>, /* ap 21 */
|
||||
<0x4903c000 0x4903c000 0x001000>, /* ap 22 */
|
||||
<0x4903d000 0x4903d000 0x001000>, /* ap 23 */
|
||||
<0x4903e000 0x4903e000 0x001000>, /* ap 24 */
|
||||
<0x4903f000 0x4903f000 0x001000>, /* ap 25 */
|
||||
<0x49080000 0x49080000 0x010000>, /* ap 26 */
|
||||
<0x49080000 0x49080000 0x001000>, /* ap 27 */
|
||||
<0x490a0000 0x490a0000 0x010000>, /* ap 28 */
|
||||
<0x490a0000 0x490a0000 0x001000>, /* ap 29 */
|
||||
<0x490c0000 0x490c0000 0x010000>, /* ap 30 */
|
||||
<0x490c0000 0x490c0000 0x001000>, /* ap 31 */
|
||||
<0x490f1000 0x490f1000 0x001000>, /* ap 32 */
|
||||
<0x490f2000 0x490f2000 0x001000>; /* ap 33 */
|
||||
|
||||
target-module@22000 { /* 0x40122000, ap 2 02.0 */
|
||||
compatible = "ti,sysc-omap2", "ti,sysc";
|
||||
reg = <0x2208c 0x4>;
|
||||
reg-names = "sysc";
|
||||
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
|
||||
SYSC_OMAP2_ENAWAKEUP |
|
||||
SYSC_OMAP2_SOFTRESET)>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
/* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
|
||||
clocks = <&abe_clkctrl OMAP5_MCBSP1_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x22000 0x1000>,
|
||||
<0x49022000 0x49022000 0x1000>;
|
||||
|
||||
mcbsp1: mcbsp@0 {
|
||||
compatible = "ti,omap4-mcbsp";
|
||||
reg = <0x0 0xff>, /* MPU private access */
|
||||
<0x49022000 0xff>; /* L3 Interconnect */
|
||||
reg-names = "mpu", "dma";
|
||||
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "common";
|
||||
ti,buffer-size = <128>;
|
||||
dmas = <&sdma 33>,
|
||||
<&sdma 34>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
target-module@24000 { /* 0x40124000, ap 4 04.0 */
|
||||
compatible = "ti,sysc-omap2", "ti,sysc";
|
||||
reg = <0x2408c 0x4>;
|
||||
reg-names = "sysc";
|
||||
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
|
||||
SYSC_OMAP2_ENAWAKEUP |
|
||||
SYSC_OMAP2_SOFTRESET)>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
/* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
|
||||
clocks = <&abe_clkctrl OMAP5_MCBSP2_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x24000 0x1000>,
|
||||
<0x49024000 0x49024000 0x1000>;
|
||||
|
||||
mcbsp2: mcbsp@0 {
|
||||
compatible = "ti,omap4-mcbsp";
|
||||
reg = <0x0 0xff>, /* MPU private access */
|
||||
<0x49024000 0xff>; /* L3 Interconnect */
|
||||
reg-names = "mpu", "dma";
|
||||
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "common";
|
||||
ti,buffer-size = <128>;
|
||||
dmas = <&sdma 17>,
|
||||
<&sdma 18>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
target-module@26000 { /* 0x40126000, ap 6 06.0 */
|
||||
compatible = "ti,sysc-omap2", "ti,sysc";
|
||||
reg = <0x2608c 0x4>;
|
||||
reg-names = "sysc";
|
||||
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
|
||||
SYSC_OMAP2_ENAWAKEUP |
|
||||
SYSC_OMAP2_SOFTRESET)>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
/* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
|
||||
clocks = <&abe_clkctrl OMAP5_MCBSP3_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x26000 0x1000>,
|
||||
<0x49026000 0x49026000 0x1000>;
|
||||
|
||||
mcbsp3: mcbsp@0 {
|
||||
compatible = "ti,omap4-mcbsp";
|
||||
reg = <0x0 0xff>, /* MPU private access */
|
||||
<0x49026000 0xff>; /* L3 Interconnect */
|
||||
reg-names = "mpu", "dma";
|
||||
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "common";
|
||||
ti,buffer-size = <128>;
|
||||
dmas = <&sdma 19>,
|
||||
<&sdma 20>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
target-module@28000 { /* 0x40128000, ap 8 08.0 */
|
||||
compatible = "ti,sysc";
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x28000 0x1000>,
|
||||
<0x49028000 0x49028000 0x1000>;
|
||||
};
|
||||
|
||||
target-module@2a000 { /* 0x4012a000, ap 10 0a.0 */
|
||||
compatible = "ti,sysc";
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x2a000 0x1000>,
|
||||
<0x4902a000 0x4902a000 0x1000>;
|
||||
};
|
||||
|
||||
target-module@2e000 { /* 0x4012e000, ap 12 0c.0 */
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x2e000 0x4>,
|
||||
<0x2e010 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
|
||||
SYSC_OMAP4_SOFTRESET)>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>,
|
||||
<SYSC_IDLE_SMART_WKUP>;
|
||||
/* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
|
||||
clocks = <&abe_clkctrl OMAP5_DMIC_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x2e000 0x1000>,
|
||||
<0x4902e000 0x4902e000 0x1000>;
|
||||
|
||||
dmic: dmic@0 {
|
||||
compatible = "ti,omap4-dmic";
|
||||
reg = <0x0 0x7f>, /* MPU private access */
|
||||
<0x4902e000 0x7f>; /* L3 Interconnect */
|
||||
reg-names = "mpu", "dma";
|
||||
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&sdma 67>;
|
||||
dma-names = "up_link";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
target-module@30000 { /* 0x40130000, ap 14 0e.0 */
|
||||
compatible = "ti,sysc";
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x30000 0x1000>,
|
||||
<0x49030000 0x49030000 0x1000>;
|
||||
};
|
||||
|
||||
mcpdm_module: target-module@32000 { /* 0x40132000, ap 16 10.0 */
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x32000 0x4>,
|
||||
<0x32010 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
|
||||
SYSC_OMAP4_SOFTRESET)>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>,
|
||||
<SYSC_IDLE_SMART_WKUP>;
|
||||
/* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
|
||||
clocks = <&abe_clkctrl OMAP5_MCPDM_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x32000 0x1000>,
|
||||
<0x49032000 0x49032000 0x1000>;
|
||||
|
||||
/* Must be only enabled for boards with pdmclk wired */
|
||||
status = "disabled";
|
||||
|
||||
mcpdm: mcpdm@0 {
|
||||
compatible = "ti,omap4-mcpdm";
|
||||
reg = <0x0 0x7f>, /* MPU private access */
|
||||
<0x49032000 0x7f>; /* L3 Interconnect */
|
||||
reg-names = "mpu", "dma";
|
||||
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&sdma 65>,
|
||||
<&sdma 66>;
|
||||
dma-names = "up_link", "dn_link";
|
||||
};
|
||||
};
|
||||
|
||||
target-module@38000 { /* 0x40138000, ap 18 12.0 */
|
||||
compatible = "ti,sysc-omap4-timer", "ti,sysc";
|
||||
reg = <0x38000 0x4>,
|
||||
<0x38010 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
|
||||
SYSC_OMAP4_SOFTRESET)>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>,
|
||||
<SYSC_IDLE_SMART_WKUP>;
|
||||
/* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
|
||||
clocks = <&abe_clkctrl OMAP5_TIMER5_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x38000 0x1000>,
|
||||
<0x49038000 0x49038000 0x1000>;
|
||||
|
||||
timer5: timer@0 {
|
||||
compatible = "ti,omap5430-timer";
|
||||
reg = <0x0 0x80>,
|
||||
<0x49038000 0x80>;
|
||||
clocks = <&abe_clkctrl OMAP5_TIMER5_CLKCTRL 24>;
|
||||
clock-names = "fck";
|
||||
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,timer-dsp;
|
||||
ti,timer-pwm;
|
||||
};
|
||||
};
|
||||
|
||||
target-module@3a000 { /* 0x4013a000, ap 20 14.0 */
|
||||
compatible = "ti,sysc-omap4-timer", "ti,sysc";
|
||||
reg = <0x3a000 0x4>,
|
||||
<0x3a010 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
|
||||
SYSC_OMAP4_SOFTRESET)>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>,
|
||||
<SYSC_IDLE_SMART_WKUP>;
|
||||
/* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
|
||||
clocks = <&abe_clkctrl OMAP5_TIMER6_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x3a000 0x1000>,
|
||||
<0x4903a000 0x4903a000 0x1000>;
|
||||
|
||||
timer6: timer@0 {
|
||||
compatible = "ti,omap5430-timer";
|
||||
reg = <0x0 0x80>,
|
||||
<0x4903a000 0x80>;
|
||||
clocks = <&abe_clkctrl OMAP5_TIMER6_CLKCTRL 24>;
|
||||
clock-names = "fck";
|
||||
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,timer-dsp;
|
||||
ti,timer-pwm;
|
||||
};
|
||||
};
|
||||
|
||||
target-module@3c000 { /* 0x4013c000, ap 22 16.0 */
|
||||
compatible = "ti,sysc-omap4-timer", "ti,sysc";
|
||||
reg = <0x3c000 0x4>,
|
||||
<0x3c010 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
|
||||
SYSC_OMAP4_SOFTRESET)>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>,
|
||||
<SYSC_IDLE_SMART_WKUP>;
|
||||
/* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
|
||||
clocks = <&abe_clkctrl OMAP5_TIMER7_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x3c000 0x1000>,
|
||||
<0x4903c000 0x4903c000 0x1000>;
|
||||
|
||||
timer7: timer@0 {
|
||||
compatible = "ti,omap5430-timer";
|
||||
reg = <0x0 0x80>,
|
||||
<0x4903c000 0x80>;
|
||||
clocks = <&abe_clkctrl OMAP5_TIMER7_CLKCTRL 24>;
|
||||
clock-names = "fck";
|
||||
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,timer-dsp;
|
||||
};
|
||||
};
|
||||
|
||||
target-module@3e000 { /* 0x4013e000, ap 24 18.0 */
|
||||
compatible = "ti,sysc-omap4-timer", "ti,sysc";
|
||||
reg = <0x3e000 0x4>,
|
||||
<0x3e010 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
|
||||
SYSC_OMAP4_SOFTRESET)>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>,
|
||||
<SYSC_IDLE_SMART_WKUP>;
|
||||
/* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
|
||||
clocks = <&abe_clkctrl OMAP5_TIMER8_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x3e000 0x1000>,
|
||||
<0x4903e000 0x4903e000 0x1000>;
|
||||
|
||||
timer8: timer@0 {
|
||||
compatible = "ti,omap5430-timer";
|
||||
reg = <0x0 0x80>,
|
||||
<0x4903e000 0x80>;
|
||||
clocks = <&abe_clkctrl OMAP5_TIMER8_CLKCTRL 24>;
|
||||
clock-names = "fck";
|
||||
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,timer-dsp;
|
||||
ti,timer-pwm;
|
||||
};
|
||||
};
|
||||
|
||||
target-module@80000 { /* 0x40180000, ap 26 1a.0 */
|
||||
compatible = "ti,sysc";
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x80000 0x10000>,
|
||||
<0x49080000 0x49080000 0x10000>;
|
||||
};
|
||||
|
||||
target-module@a0000 { /* 0x401a0000, ap 28 1c.0 */
|
||||
compatible = "ti,sysc";
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0xa0000 0x10000>,
|
||||
<0x490a0000 0x490a0000 0x10000>;
|
||||
};
|
||||
|
||||
target-module@c0000 { /* 0x401c0000, ap 30 1e.0 */
|
||||
compatible = "ti,sysc";
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0xc0000 0x10000>,
|
||||
<0x490c0000 0x490c0000 0x10000>;
|
||||
};
|
||||
|
||||
target-module@f1000 { /* 0x401f1000, ap 32 20.0 */
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0xf1000 0x4>,
|
||||
<0xf1010 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>,
|
||||
<SYSC_IDLE_SMART_WKUP>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
/* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
|
||||
clocks = <&abe_clkctrl OMAP5_AESS_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0xf1000 0x1000>,
|
||||
<0x490f1000 0x490f1000 0x1000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
2437
arch/arm/dts/omap5-l4.dtsi
Normal file
2437
arch/arm/dts/omap5-l4.dtsi
Normal file
File diff suppressed because it is too large
Load diff
200
arch/arm/dts/omap5-uevm.dts
Normal file
200
arch/arm/dts/omap5-uevm.dts
Normal file
|
|
@ -0,0 +1,200 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
#include "omap5-board-common.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TI OMAP5 uEVM board";
|
||||
compatible = "ti,omap5-uevm", "ti,omap5";
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0 0x80000000 0 0x7f000000>; /* 2032 MB */
|
||||
};
|
||||
|
||||
aliases {
|
||||
ethernet = ðernet;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
led1 {
|
||||
label = "omap5:blue:usr1";
|
||||
gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>; /* gpio5_153 D1 LED */
|
||||
linux,default-trigger = "heartbeat";
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
|
||||
evm_keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&evm_keys_pins>;
|
||||
|
||||
#address-cells = <7>;
|
||||
#size-cells = <0>;
|
||||
|
||||
btn1 {
|
||||
label = "BTN1";
|
||||
linux,code = <169>;
|
||||
gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; /* gpio3_83 */
|
||||
wakeup-source;
|
||||
autorepeat;
|
||||
debounce-interval = <50>;
|
||||
};
|
||||
};
|
||||
|
||||
evm_leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led1 {
|
||||
label = "omap5:red:led";
|
||||
gpios = <&gpio9 17 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "mmc0";
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led2 {
|
||||
label = "omap5:green:led";
|
||||
gpios = <&gpio9 18 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "mmc1";
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led3 {
|
||||
label = "omap5:blue:led";
|
||||
gpios = <&gpio9 19 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "mmc2";
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led4 {
|
||||
label = "omap5:green:led1";
|
||||
gpios = <&gpio9 2 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led5 {
|
||||
label = "omap5:green:led2";
|
||||
gpios = <&gpio9 3 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "default-on";
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led6 {
|
||||
label = "omap5:green:led3";
|
||||
gpios = <&gpio9 4 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led7 {
|
||||
label = "omap5:green:led4";
|
||||
gpios = <&gpio9 5 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "default-on";
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led8 {
|
||||
label = "omap5:green:led5";
|
||||
gpios = <&gpio9 6 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
vdda-supply = <&ldo4_reg>;
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
eeprom@50 {
|
||||
compatible = "atmel,24c02";
|
||||
reg = <0x50>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c5 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c5_pins>;
|
||||
|
||||
clock-frequency = <400000>;
|
||||
|
||||
gpio9: gpio@22 {
|
||||
compatible = "ti,tca6424";
|
||||
reg = <0x22>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc1_pins>;
|
||||
|
||||
cd-gpios = <&gpio5 24 GPIO_ACTIVE_LOW>; /* gpio5_152 */
|
||||
};
|
||||
|
||||
&omap5_pmx_core {
|
||||
evm_keys_pins: pinmux_evm_keys_gpio_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP5_IOPAD(0x0b6, PIN_INPUT | MUX_MODE6) /* gpio3_83 */
|
||||
>;
|
||||
};
|
||||
|
||||
i2c5_pins: pinmux_i2c5_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP5_IOPAD(0x1c6, PIN_INPUT | MUX_MODE0) /* i2c5_scl */
|
||||
OMAP5_IOPAD(0x1c8, PIN_INPUT | MUX_MODE0) /* i2c5_sda */
|
||||
>;
|
||||
};
|
||||
|
||||
mmc1_pins: pinmux_mmc1_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP5_IOPAD(0x1d4, PIN_INPUT_PULLUP | MUX_MODE6) /* gpio5_152 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&tpd12s015 {
|
||||
gpios = <&gpio9 0 GPIO_ACTIVE_HIGH>, /* TCA6424A P01, CT CP HPD */
|
||||
<&gpio9 1 GPIO_ACTIVE_HIGH>, /* TCA6424A P00, LS OE */
|
||||
<&gpio7 1 GPIO_ACTIVE_HIGH>; /* GPIO 193, HPD */
|
||||
};
|
||||
|
||||
&twl6040 {
|
||||
ti,audpwron-gpio = <&gpio5 13 GPIO_ACTIVE_HIGH>; /* gpio line 141 */
|
||||
};
|
||||
|
||||
&twl6040_pins {
|
||||
pinctrl-single,pins = <
|
||||
OMAP5_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_141 */
|
||||
>;
|
||||
};
|
||||
|
||||
&usbhsehci {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
hub@2 {
|
||||
compatible = "usb424,3503";
|
||||
reg = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
ethernet: usbether@3 {
|
||||
compatible = "usb424,9730";
|
||||
reg = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
&wlcore {
|
||||
compatible = "ti,wl1837";
|
||||
};
|
||||
583
arch/arm/dts/omap5.dtsi
Normal file
583
arch/arm/dts/omap5.dtsi
Normal file
|
|
@ -0,0 +1,583 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* Based on "omap4.dtsi"
|
||||
*/
|
||||
|
||||
#include <dt-bindings/bus/ti-sysc.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/pinctrl/omap.h>
|
||||
#include <dt-bindings/clock/omap5.h>
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
compatible = "ti,omap5";
|
||||
interrupt-parent = <&wakeupgen>;
|
||||
chosen { };
|
||||
|
||||
aliases {
|
||||
i2c0 = &i2c1;
|
||||
i2c1 = &i2c2;
|
||||
i2c2 = &i2c3;
|
||||
i2c3 = &i2c4;
|
||||
i2c4 = &i2c5;
|
||||
serial0 = &uart1;
|
||||
serial1 = &uart2;
|
||||
serial2 = &uart3;
|
||||
serial3 = &uart4;
|
||||
serial4 = &uart5;
|
||||
serial5 = &uart6;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x0>;
|
||||
|
||||
operating-points = <
|
||||
/* kHz uV */
|
||||
1000000 1060000
|
||||
1500000 1250000
|
||||
>;
|
||||
|
||||
clocks = <&dpll_mpu_ck>;
|
||||
clock-names = "cpu";
|
||||
|
||||
clock-latency = <300000>; /* From omap-cpufreq driver */
|
||||
|
||||
/* cooling options */
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
};
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x1>;
|
||||
|
||||
operating-points = <
|
||||
/* kHz uV */
|
||||
1000000 1060000
|
||||
1500000 1250000
|
||||
>;
|
||||
|
||||
clocks = <&dpll_mpu_ck>;
|
||||
clock-names = "cpu";
|
||||
|
||||
clock-latency = <300000>; /* From omap-cpufreq driver */
|
||||
|
||||
/* cooling options */
|
||||
#cooling-cells = <2>; /* min followed by max */
|
||||
};
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
#include "omap4-cpu-thermal.dtsi"
|
||||
#include "omap5-gpu-thermal.dtsi"
|
||||
#include "omap5-core-thermal.dtsi"
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
/* PPI secure/nonsecure IRQ */
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
interrupt-parent = <&gic>;
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a15-pmu";
|
||||
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@48211000 {
|
||||
compatible = "arm,cortex-a15-gic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
reg = <0 0x48211000 0 0x1000>,
|
||||
<0 0x48212000 0 0x2000>,
|
||||
<0 0x48214000 0 0x2000>,
|
||||
<0 0x48216000 0 0x2000>;
|
||||
interrupt-parent = <&gic>;
|
||||
};
|
||||
|
||||
wakeupgen: interrupt-controller@48281000 {
|
||||
compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
reg = <0 0x48281000 0 0x1000>;
|
||||
interrupt-parent = <&gic>;
|
||||
};
|
||||
|
||||
/*
|
||||
* The soc node represents the soc top level view. It is used for IPs
|
||||
* that are not memory mapped in the MPU view or for the MPU itself.
|
||||
*/
|
||||
soc {
|
||||
compatible = "ti,omap-infra";
|
||||
mpu {
|
||||
compatible = "ti,omap4-mpu";
|
||||
ti,hwmods = "mpu";
|
||||
sram = <&ocmcram>;
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
* XXX: Use a flat representation of the OMAP3 interconnect.
|
||||
* The real OMAP interconnect network is quite complex.
|
||||
* Since it will not bring real advantage to represent that in DT for
|
||||
* the moment, just use a fake OCP bus entry to represent the whole bus
|
||||
* hierarchy.
|
||||
*/
|
||||
ocp {
|
||||
compatible = "ti,omap5-l3-noc", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0 0xc0000000>;
|
||||
dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
|
||||
ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
|
||||
reg = <0 0x44000000 0 0x2000>,
|
||||
<0 0x44800000 0 0x3000>,
|
||||
<0 0x45000000 0 0x4000>;
|
||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
l4_wkup: interconnect@4ae00000 {
|
||||
};
|
||||
|
||||
l4_cfg: interconnect@4a000000 {
|
||||
};
|
||||
|
||||
l4_per: interconnect@48000000 {
|
||||
};
|
||||
|
||||
l4_abe: interconnect@40100000 {
|
||||
};
|
||||
|
||||
ocmcram: sram@40300000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x40300000 0x20000>; /* 128k */
|
||||
};
|
||||
|
||||
gpmc: gpmc@50000000 {
|
||||
compatible = "ti,omap4430-gpmc";
|
||||
reg = <0x50000000 0x1000>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&sdma 4>;
|
||||
dma-names = "rxtx";
|
||||
gpmc,num-cs = <8>;
|
||||
gpmc,num-waitpins = <4>;
|
||||
ti,hwmods = "gpmc";
|
||||
clocks = <&l3_iclk_div>;
|
||||
clock-names = "fck";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
|
||||
target-module@55082000 {
|
||||
compatible = "ti,sysc-omap2", "ti,sysc";
|
||||
reg = <0x55082000 0x4>,
|
||||
<0x55082010 0x4>,
|
||||
<0x55082014 0x4>;
|
||||
reg-names = "rev", "sysc", "syss";
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
|
||||
SYSC_OMAP2_SOFTRESET |
|
||||
SYSC_OMAP2_AUTOIDLE)>;
|
||||
clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
resets = <&prm_core 2>;
|
||||
reset-names = "rstctrl";
|
||||
ranges = <0x0 0x55082000 0x100>;
|
||||
#size-cells = <1>;
|
||||
#address-cells = <1>;
|
||||
|
||||
mmu_ipu: mmu@0 {
|
||||
compatible = "ti,omap4-iommu";
|
||||
reg = <0x0 0x100>;
|
||||
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#iommu-cells = <0>;
|
||||
ti,iommu-bus-err-back;
|
||||
};
|
||||
};
|
||||
|
||||
dmm@4e000000 {
|
||||
compatible = "ti,omap5-dmm";
|
||||
reg = <0x4e000000 0x800>;
|
||||
interrupts = <0 113 0x4>;
|
||||
ti,hwmods = "dmm";
|
||||
};
|
||||
|
||||
emif1: emif@4c000000 {
|
||||
compatible = "ti,emif-4d5";
|
||||
ti,hwmods = "emif1";
|
||||
ti,no-idle-on-init;
|
||||
phy-type = <2>; /* DDR PHY type: Intelli PHY */
|
||||
reg = <0x4c000000 0x400>;
|
||||
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
||||
hw-caps-read-idle-ctrl;
|
||||
hw-caps-ll-interface;
|
||||
hw-caps-temp-alert;
|
||||
};
|
||||
|
||||
emif2: emif@4d000000 {
|
||||
compatible = "ti,emif-4d5";
|
||||
ti,hwmods = "emif2";
|
||||
ti,no-idle-on-init;
|
||||
phy-type = <2>; /* DDR PHY type: Intelli PHY */
|
||||
reg = <0x4d000000 0x400>;
|
||||
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
|
||||
hw-caps-read-idle-ctrl;
|
||||
hw-caps-ll-interface;
|
||||
hw-caps-temp-alert;
|
||||
};
|
||||
|
||||
bandgap: bandgap@4a0021e0 {
|
||||
reg = <0x4a0021e0 0xc
|
||||
0x4a00232c 0xc
|
||||
0x4a002380 0x2c
|
||||
0x4a0023C0 0x3c>;
|
||||
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
|
||||
compatible = "ti,omap5430-bandgap";
|
||||
|
||||
#thermal-sensor-cells = <1>;
|
||||
};
|
||||
|
||||
/* OCP2SCP3 */
|
||||
sata: sata@4a141100 {
|
||||
compatible = "snps,dwc-ahci";
|
||||
reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
|
||||
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
|
||||
phys = <&sata_phy>;
|
||||
phy-names = "sata-phy";
|
||||
clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
|
||||
ti,hwmods = "sata";
|
||||
ports-implemented = <0x1>;
|
||||
};
|
||||
|
||||
target-module@56000000 {
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x5600fe00 0x4>,
|
||||
<0x5600fe10 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
clocks = <&gpu_clkctrl OMAP5_GPU_CLKCTRL 0>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x56000000 0x2000000>;
|
||||
|
||||
/*
|
||||
* Closed source PowerVR driver, no child device
|
||||
* binding or driver in mainline
|
||||
*/
|
||||
};
|
||||
|
||||
target-module@58000000 {
|
||||
compatible = "ti,sysc-omap2", "ti,sysc";
|
||||
reg = <0x58000000 4>,
|
||||
<0x58000014 4>;
|
||||
reg-names = "rev", "syss";
|
||||
ti,syss-mask = <1>;
|
||||
clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 0>,
|
||||
<&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
|
||||
<&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>,
|
||||
<&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 11>;
|
||||
clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x58000000 0x1000000>;
|
||||
|
||||
dss: dss@0 {
|
||||
compatible = "ti,omap5-dss";
|
||||
reg = <0 0x80>;
|
||||
status = "disabled";
|
||||
clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0x1000000>;
|
||||
|
||||
target-module@1000 {
|
||||
compatible = "ti,sysc-omap2", "ti,sysc";
|
||||
reg = <0x1000 0x4>,
|
||||
<0x1010 0x4>,
|
||||
<0x1014 0x4>;
|
||||
reg-names = "rev", "sysc", "syss";
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
|
||||
SYSC_OMAP2_ENAWAKEUP |
|
||||
SYSC_OMAP2_SOFTRESET |
|
||||
SYSC_OMAP2_AUTOIDLE)>;
|
||||
ti,syss-mask = <1>;
|
||||
clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x1000 0x1000>;
|
||||
|
||||
dispc@0 {
|
||||
compatible = "ti,omap5-dispc";
|
||||
reg = <0 0x1000>;
|
||||
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
|
||||
clock-names = "fck";
|
||||
};
|
||||
};
|
||||
|
||||
target-module@2000 {
|
||||
compatible = "ti,sysc-omap2", "ti,sysc";
|
||||
reg = <0x2000 0x4>,
|
||||
<0x2010 0x4>,
|
||||
<0x2014 0x4>;
|
||||
reg-names = "rev", "sysc", "syss";
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
|
||||
SYSC_OMAP2_AUTOIDLE)>;
|
||||
ti,syss-mask = <1>;
|
||||
clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x2000 0x1000>;
|
||||
|
||||
rfbi: encoder@0 {
|
||||
compatible = "ti,omap5-rfbi";
|
||||
reg = <0 0x100>;
|
||||
status = "disabled";
|
||||
clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>;
|
||||
clock-names = "fck", "ick";
|
||||
};
|
||||
};
|
||||
|
||||
target-module@5000 {
|
||||
compatible = "ti,sysc-omap2", "ti,sysc";
|
||||
reg = <0x5000 0x4>,
|
||||
<0x5010 0x4>,
|
||||
<0x5014 0x4>;
|
||||
reg-names = "rev", "sysc", "syss";
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
|
||||
SYSC_OMAP2_ENAWAKEUP |
|
||||
SYSC_OMAP2_SOFTRESET |
|
||||
SYSC_OMAP2_AUTOIDLE)>;
|
||||
ti,syss-mask = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x5000 0x1000>;
|
||||
|
||||
dsi1: encoder@0 {
|
||||
compatible = "ti,omap5-dsi";
|
||||
reg = <0 0x200>,
|
||||
<0x200 0x40>,
|
||||
<0x300 0x40>;
|
||||
reg-names = "proto", "phy", "pll";
|
||||
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
|
||||
clock-names = "fck";
|
||||
};
|
||||
};
|
||||
|
||||
target-module@9000 {
|
||||
compatible = "ti,sysc-omap2", "ti,sysc";
|
||||
reg = <0x9000 0x4>,
|
||||
<0x9010 0x4>,
|
||||
<0x9014 0x4>;
|
||||
reg-names = "rev", "sysc", "syss";
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>;
|
||||
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
|
||||
SYSC_OMAP2_ENAWAKEUP |
|
||||
SYSC_OMAP2_SOFTRESET |
|
||||
SYSC_OMAP2_AUTOIDLE)>;
|
||||
ti,syss-mask = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x9000 0x1000>;
|
||||
|
||||
dsi2: encoder@0 {
|
||||
compatible = "ti,omap5-dsi";
|
||||
reg = <0 0x200>,
|
||||
<0x200 0x40>,
|
||||
<0x300 0x40>;
|
||||
reg-names = "proto", "phy", "pll";
|
||||
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
|
||||
clock-names = "fck";
|
||||
};
|
||||
};
|
||||
|
||||
target-module@40000 {
|
||||
compatible = "ti,sysc-omap4", "ti,sysc";
|
||||
reg = <0x40000 0x4>,
|
||||
<0x40010 0x4>;
|
||||
reg-names = "rev", "sysc";
|
||||
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
||||
<SYSC_IDLE_NO>,
|
||||
<SYSC_IDLE_SMART>,
|
||||
<SYSC_IDLE_SMART_WKUP>;
|
||||
ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
|
||||
clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
|
||||
<&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
|
||||
clock-names = "fck", "dss_clk";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x40000 0x40000>;
|
||||
|
||||
hdmi: encoder@0 {
|
||||
compatible = "ti,omap5-hdmi";
|
||||
reg = <0 0x200>,
|
||||
<0x200 0x80>,
|
||||
<0x300 0x80>,
|
||||
<0x20000 0x19000>;
|
||||
reg-names = "wp", "pll", "phy", "core";
|
||||
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
|
||||
<&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
|
||||
clock-names = "fck", "sys_clk";
|
||||
dmas = <&sdma 76>;
|
||||
dma-names = "audio_tx";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
abb_mpu: regulator-abb-mpu {
|
||||
compatible = "ti,abb-v2";
|
||||
regulator-name = "abb_mpu";
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&sys_clkin>;
|
||||
ti,settling-time = <50>;
|
||||
ti,clock-cycles = <16>;
|
||||
|
||||
reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
|
||||
<0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
|
||||
reg-names = "base-address", "int-address",
|
||||
"efuse-address", "ldo-address";
|
||||
ti,tranxdone-status-mask = <0x80>;
|
||||
/* LDOVBBMPU_MUX_CTRL */
|
||||
ti,ldovbb-override-mask = <0x400>;
|
||||
/* LDOVBBMPU_VSET_OUT */
|
||||
ti,ldovbb-vset-mask = <0x1F>;
|
||||
|
||||
/*
|
||||
* NOTE: only FBB mode used but actual vset will
|
||||
* determine final biasing
|
||||
*/
|
||||
ti,abb_info = <
|
||||
/*uV ABB efuse rbb_m fbb_m vset_m*/
|
||||
1060000 0 0x0 0 0x02000000 0x01F00000
|
||||
1250000 0 0x4 0 0x02000000 0x01F00000
|
||||
>;
|
||||
};
|
||||
|
||||
abb_mm: regulator-abb-mm {
|
||||
compatible = "ti,abb-v2";
|
||||
regulator-name = "abb_mm";
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&sys_clkin>;
|
||||
ti,settling-time = <50>;
|
||||
ti,clock-cycles = <16>;
|
||||
|
||||
reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
|
||||
<0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
|
||||
reg-names = "base-address", "int-address",
|
||||
"efuse-address", "ldo-address";
|
||||
ti,tranxdone-status-mask = <0x80000000>;
|
||||
/* LDOVBBMM_MUX_CTRL */
|
||||
ti,ldovbb-override-mask = <0x400>;
|
||||
/* LDOVBBMM_VSET_OUT */
|
||||
ti,ldovbb-vset-mask = <0x1F>;
|
||||
|
||||
/*
|
||||
* NOTE: only FBB mode used but actual vset will
|
||||
* determine final biasing
|
||||
*/
|
||||
ti,abb_info = <
|
||||
/*uV ABB efuse rbb_m fbb_m vset_m*/
|
||||
1025000 0 0x0 0 0x02000000 0x01F00000
|
||||
1120000 0 0x4 0 0x02000000 0x01F00000
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cpu_thermal {
|
||||
polling-delay = <500>; /* milliseconds */
|
||||
coefficients = <65 (-1791)>;
|
||||
};
|
||||
|
||||
#include "omap5-l4.dtsi"
|
||||
#include "omap54xx-clocks.dtsi"
|
||||
|
||||
&gpu_thermal {
|
||||
coefficients = <117 (-2992)>;
|
||||
};
|
||||
|
||||
&core_thermal {
|
||||
coefficients = <0 2000>;
|
||||
};
|
||||
|
||||
#include "omap5-l4-abe.dtsi"
|
||||
#include "omap54xx-clocks.dtsi"
|
||||
|
||||
&prm {
|
||||
prm_dsp: prm@400 {
|
||||
compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
|
||||
reg = <0x400 0x100>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
prm_core: prm@700 {
|
||||
compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
|
||||
reg = <0x700 0x100>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
prm_iva: prm@1200 {
|
||||
compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
|
||||
reg = <0x1200 0x100>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
prm_device: prm@1c00 {
|
||||
compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
|
||||
reg = <0x1c00 0x100>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
1208
arch/arm/dts/omap54xx-clocks.dtsi
Normal file
1208
arch/arm/dts/omap54xx-clocks.dtsi
Normal file
File diff suppressed because it is too large
Load diff
129
include/dt-bindings/clock/omap5.h
Normal file
129
include/dt-bindings/clock/omap5.h
Normal file
|
|
@ -0,0 +1,129 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Copyright 2017 Texas Instruments, Inc.
|
||||
*/
|
||||
#ifndef __DT_BINDINGS_CLK_OMAP5_H
|
||||
#define __DT_BINDINGS_CLK_OMAP5_H
|
||||
|
||||
#define OMAP5_CLKCTRL_OFFSET 0x20
|
||||
#define OMAP5_CLKCTRL_INDEX(offset) ((offset) - OMAP5_CLKCTRL_OFFSET)
|
||||
|
||||
/* mpu clocks */
|
||||
#define OMAP5_MPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
|
||||
|
||||
/* dsp clocks */
|
||||
#define OMAP5_MMU_DSP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
|
||||
|
||||
/* abe clocks */
|
||||
#define OMAP5_L4_ABE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
|
||||
#define OMAP5_AESS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
|
||||
#define OMAP5_MCPDM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
|
||||
#define OMAP5_DMIC_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
|
||||
#define OMAP5_MCBSP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48)
|
||||
#define OMAP5_MCBSP2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50)
|
||||
#define OMAP5_MCBSP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58)
|
||||
#define OMAP5_TIMER5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68)
|
||||
#define OMAP5_TIMER6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x70)
|
||||
#define OMAP5_TIMER7_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78)
|
||||
#define OMAP5_TIMER8_CLKCTRL OMAP5_CLKCTRL_INDEX(0x80)
|
||||
|
||||
/* l3main1 clocks */
|
||||
#define OMAP5_L3_MAIN_1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
|
||||
|
||||
/* l3main2 clocks */
|
||||
#define OMAP5_L3_MAIN_2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
|
||||
|
||||
/* ipu clocks */
|
||||
#define OMAP5_MMU_IPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
|
||||
|
||||
/* dma clocks */
|
||||
#define OMAP5_DMA_SYSTEM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
|
||||
|
||||
/* emif clocks */
|
||||
#define OMAP5_DMM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
|
||||
#define OMAP5_EMIF1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
|
||||
#define OMAP5_EMIF2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
|
||||
|
||||
/* l4cfg clocks */
|
||||
#define OMAP5_L4_CFG_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
|
||||
#define OMAP5_SPINLOCK_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
|
||||
#define OMAP5_MAILBOX_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
|
||||
|
||||
/* l3instr clocks */
|
||||
#define OMAP5_L3_MAIN_3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
|
||||
#define OMAP5_L3_INSTR_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
|
||||
|
||||
/* l4per clocks */
|
||||
#define OMAP5_TIMER10_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
|
||||
#define OMAP5_TIMER11_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
|
||||
#define OMAP5_TIMER2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
|
||||
#define OMAP5_TIMER3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x40)
|
||||
#define OMAP5_TIMER4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48)
|
||||
#define OMAP5_TIMER9_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50)
|
||||
#define OMAP5_GPIO2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x60)
|
||||
#define OMAP5_GPIO3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68)
|
||||
#define OMAP5_GPIO4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x70)
|
||||
#define OMAP5_GPIO5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78)
|
||||
#define OMAP5_GPIO6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x80)
|
||||
#define OMAP5_I2C1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xa0)
|
||||
#define OMAP5_I2C2_CLKCTRL OMAP5_CLKCTRL_INDEX(0xa8)
|
||||
#define OMAP5_I2C3_CLKCTRL OMAP5_CLKCTRL_INDEX(0xb0)
|
||||
#define OMAP5_I2C4_CLKCTRL OMAP5_CLKCTRL_INDEX(0xb8)
|
||||
#define OMAP5_L4_PER_CLKCTRL OMAP5_CLKCTRL_INDEX(0xc0)
|
||||
#define OMAP5_MCSPI1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf0)
|
||||
#define OMAP5_MCSPI2_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf8)
|
||||
#define OMAP5_MCSPI3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x100)
|
||||
#define OMAP5_MCSPI4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x108)
|
||||
#define OMAP5_GPIO7_CLKCTRL OMAP5_CLKCTRL_INDEX(0x110)
|
||||
#define OMAP5_GPIO8_CLKCTRL OMAP5_CLKCTRL_INDEX(0x118)
|
||||
#define OMAP5_MMC3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x120)
|
||||
#define OMAP5_MMC4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x128)
|
||||
#define OMAP5_UART1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x140)
|
||||
#define OMAP5_UART2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x148)
|
||||
#define OMAP5_UART3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x150)
|
||||
#define OMAP5_UART4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x158)
|
||||
#define OMAP5_MMC5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x160)
|
||||
#define OMAP5_I2C5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x168)
|
||||
#define OMAP5_UART5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x170)
|
||||
#define OMAP5_UART6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x178)
|
||||
|
||||
/* l4_secure clocks */
|
||||
#define OMAP5_L4_SECURE_CLKCTRL_OFFSET 0x1a0
|
||||
#define OMAP5_L4_SECURE_CLKCTRL_INDEX(offset) ((offset) - OMAP5_L4_SECURE_CLKCTRL_OFFSET)
|
||||
#define OMAP5_AES1_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1a0)
|
||||
#define OMAP5_AES2_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1a8)
|
||||
#define OMAP5_DES3DES_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1b0)
|
||||
#define OMAP5_FPKA_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1b8)
|
||||
#define OMAP5_RNG_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1c0)
|
||||
#define OMAP5_SHA2MD5_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1c8)
|
||||
#define OMAP5_DMA_CRYPTO_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1d8)
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/* iva clocks */
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#define OMAP5_IVA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
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#define OMAP5_SL2IF_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
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/* dss clocks */
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#define OMAP5_DSS_CORE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
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/* gpu clocks */
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#define OMAP5_GPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
|
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|
||||
/* l3init clocks */
|
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#define OMAP5_MMC1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
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#define OMAP5_MMC2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
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#define OMAP5_USB_HOST_HS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58)
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#define OMAP5_USB_TLL_HS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68)
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#define OMAP5_SATA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x88)
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#define OMAP5_OCP2SCP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xe0)
|
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#define OMAP5_OCP2SCP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0xe8)
|
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#define OMAP5_USB_OTG_SS_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf0)
|
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|
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/* wkupaon clocks */
|
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#define OMAP5_L4_WKUP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
|
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#define OMAP5_WD_TIMER2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
|
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#define OMAP5_GPIO1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
|
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#define OMAP5_TIMER1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x40)
|
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#define OMAP5_COUNTER_32K_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50)
|
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#define OMAP5_KBD_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78)
|
||||
|
||||
#endif
|
||||
Loading…
Reference in a new issue