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https://github.com/AsahiLinux/u-boot
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- r2dplus updates
This commit is contained in:
commit
89150a9314
4 changed files with 41 additions and 4 deletions
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@ -10,6 +10,29 @@
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model = "R2D";
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compatible = "renesas,r2d", "renesas,sh7751";
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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serial0 = &scif1;
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};
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scif_clks: scif60 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <60000000>;
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u-boot,dm-pre-reloc;
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};
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scif1: serial@ffe80000 {
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compatible = "renesas,scif";
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reg = <0 0xffe80000 0 0x1000>;
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clocks = <&scif_clks>;
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clock-names = "fck";
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status = "okay";
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u-boot,dm-pre-reloc;
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};
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pci@fe200000 {
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compatible = "renesas,pci-sh7751";
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device_type = "pci";
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@ -53,7 +53,10 @@ _start:
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mov.l ._gd_init, r13 /* global data */
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mov.l ._stack_init, r15 /* stack */
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#if CONFIG_VAL(SYS_MALLOC_F_LEN)
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mov.l ._gd_malloc_base, r14
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mov.l r15, @r14
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#endif
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mov.l ._sh_generic_init, r0
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jsr @r0
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mov #0, r4
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@ -70,5 +73,8 @@ loop:
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._bss_start: .long bss_start
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._bss_end: .long bss_end
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._gd_init: .long (_start - GENERATED_GBL_DATA_SIZE)
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#if CONFIG_VAL(SYS_MALLOC_F_LEN)
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._gd_malloc_base: .long (_start - GENERATED_GBL_DATA_SIZE + GD_MALLOC_BASE)
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#endif
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._stack_init: .long (_start - GENERATED_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN - 16)
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._sh_generic_init: .long board_init_f
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@ -4,10 +4,11 @@ CONFIG_ENV_SIZE=0x40000
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CONFIG_ENV_SECT_SIZE=0x40000
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CONFIG_DEFAULT_DEVICE_TREE="sh7751-r2dplus"
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CONFIG_TARGET_R2DPLUS=y
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# CONFIG_SYS_MALLOC_F is not set
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CONFIG_BOOTDELAY=-1
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CONFIG_USE_BOOTARGS=y
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CONFIG_BOOTARGS="console=ttySC0,115200"
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CONFIG_USE_PREBOOT=y
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CONFIG_PREBOOT="pci enum"
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CONFIG_HUSH_PARSER=y
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CONFIG_CMD_IMLS=y
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CONFIG_CMD_DM=y
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@ -24,12 +25,20 @@ CONFIG_ENV_OVERWRITE=y
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CONFIG_ENV_IS_IN_FLASH=y
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CONFIG_ENV_ADDR=0xA0040000
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CONFIG_DM=y
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CONFIG_CLK=y
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CONFIG_MTD_NOR_FLASH=y
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CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_DM_ETH=y
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CONFIG_E1000=y
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CONFIG_EEPRO100=y
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CONFIG_PCNET=y
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CONFIG_RTL8139=y
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CONFIG_TULIP=y
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CONFIG_PCI=y
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CONFIG_DM_PCI=y
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CONFIG_DM_PCI_COMPAT=y
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CONFIG_SPECIFY_CONSOLE_INDEX=y
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CONFIG_DM_SERIAL=y
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CONFIG_SERIAL_RX_BUFFER=y
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CONFIG_SCIF_CONSOLE=y
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CONFIG_USE_PRIVATE_LIBGCC=y
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@ -35,7 +35,6 @@
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* SuperH Clock setting
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*/
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#define CONFIG_SYS_CLK_FREQ 60000000
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#define CONFIG_SYS_PLL_SETTLING_TIME 100/* in us */
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/*
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