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ddr: k3-am654: EMIF Tool update to 2.02 for IO optimizations and fixes

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EMIF tool for AM65x [1] is now updated from rev 1.98 to 2.02

This update includes
* Optimizations in IO configuration.
* Fix for byte enablement in GCR registers.
* Fixes for PG2.0 including ZQ control.

[1]: http://www.ti.com/lit/zip/sprcah7

Acked-by: James Doublesin <doublesin@ti.com>
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
This commit is contained in:
Praneeth Bajjuri 2020-05-07 22:35:56 -05:00 committed by Lokesh Vutla
parent ed9a3aa645
commit a665cb13dc
1 changed files with 14 additions and 14 deletions
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28
arch/arm/dts/k3-am654-base-board-ddr4-1600MTs.dtsi
View file

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
* This file was generated by AM65x_DRA80xM_EMIF_Tool_1.98.xlsm
* Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
* This file was generated by AM65x_DRA80xM_EMIF_Tool_2.02.xlsm
* http://www.ti.com/lit/pdf/spracj0
* Configuration Parameters
* Memory Type: DDR4
@ -24,7 +24,7 @@
#define DDRCTL_INIT4 0x00000020
#define DDRCTL_INIT5 0x00100000
#define DDRCTL_INIT6 0x00000480
#define DDRCTL_INIT7 0x000004E8
#define DDRCTL_INIT7 0x00000497
#define DDRCTL_DRAMTMG0 0x0C0A1B0D
#define DDRCTL_DRAMTMG1 0x00030313
#define DDRCTL_DRAMTMG2 0x0506050A
@ -33,10 +33,10 @@
#define DDRCTL_DRAMTMG5 0x04040302
#define DDRCTL_DRAMTMG6 0x00000004
#define DDRCTL_DRAMTMG7 0x00000404
#define DDRCTL_DRAMTMG8 0x03030A05
#define DDRCTL_DRAMTMG8 0x03030C05
#define DDRCTL_DRAMTMG9 0x00020208
#define DDRCTL_DRAMTMG10 0x001C180A
#define DDRCTL_DRAMTMG11 0x0E06010E
#define DDRCTL_DRAMTMG11 0x1106010E
#define DDRCTL_DRAMTMG12 0x00020008
#define DDRCTL_DRAMTMG13 0x0B100002
#define DDRCTL_DRAMTMG14 0x00000000
@ -84,33 +84,33 @@
#define DDRPHY_DCR 0x0000040C
#define DDRPHY_DTPR0 0x041A0B06
#define DDRPHY_DTPR1 0x28140000
#define DDRPHY_DTPR2 0x0034E255
#define DDRPHY_DTPR3 0x01D50800
#define DDRPHY_DTPR2 0x0034E300
#define DDRPHY_DTPR3 0x02800800
#define DDRPHY_DTPR4 0x31180805
#define DDRPHY_DTPR5 0x00250B06
#define DDRPHY_DTPR6 0x00000505
#define DDRPHY_ZQCR 0x008A2A58
#define DDRPHY_ZQ0PR0 0x000077DD
#define DDRPHY_ZQ1PR0 0x000077DD
#define DDRPHY_ZQ1PR0 0x00007799
#define DDRPHY_MR0 0x00000214
#define DDRPHY_MR1 0x00000501
#define DDRPHY_MR2 0x00000000
#define DDRPHY_MR3 0x00000020
#define DDRPHY_MR4 0x00000000
#define DDRPHY_MR5 0x00000480
#define DDRPHY_MR6 0x000004E8
#define DDRPHY_MR6 0x00000497
#define DDRPHY_MR11 0x00000000
#define DDRPHY_MR12 0x00000000
#define DDRPHY_MR13 0x00000000
#define DDRPHY_MR14 0x00000000
#define DDRPHY_MR22 0x00000000
#define DDRPHY_VTCR0 0xF3C32028
#define DDRPHY_VTCR0 0xF3C32017
#define DDRPHY_DX8SL0PLLCR0 0x021c4000
#define DDRPHY_DX8SL1PLLCR0 0x021c4000
#define DDRPHY_DX8SL2PLLCR0 0x021c4000
#define DDRPHY_DTCR0 0x8000B1C7
#define DDRPHY_DTCR1 0x00010236
#define DDRPHY_ACIOCR0 0x30070000
#define DDRPHY_ACIOCR0 0xF0070000
#define DDRPHY_ACIOCR3 0x00000001
#define DDRPHY_ACIOCR5 0x04800000
#define DDRPHY_IOVCR0 0x0F0C0C0C
@ -157,6 +157,6 @@
#define DDRPHY_DX8SL0DXCTL2 0x00141830
#define DDRPHY_DX8SL1DXCTL2 0x00141830
#define DDRPHY_DX8SL2DXCTL2 0x00141830
#define DDRPHY_DX8SL0DQSCTL 0x01264000
#define DDRPHY_DX8SL1DQSCTL 0x01264000
#define DDRPHY_DX8SL2DQSCTL 0x01264000
#define DDRPHY_DX8SL0DQSCTL 0x01264300
#define DDRPHY_DX8SL1DQSCTL 0x01264300
#define DDRPHY_DX8SL2DQSCTL 0x01264300