mirror of
https://github.com/AsahiLinux/u-boot
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Merge tag 'mmc-2020-6-15' of https://gitlab.denx.de/u-boot/custodians/u-boot-mmc
- fsl_esdhc sdr104 and hs200 fix and error path fix - fsl_esdhc workaround 3.3v io issue - ca_dw_mmc cleanup - presidio-asic emmc DT update.
This commit is contained in:
Tom Rini
commit
bb1ff1371e
6 changed files with 74 additions and 34 deletions
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@ -10,11 +10,9 @@
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#size-cells = <1>;
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mmc0: mmc@f4400000 {
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compatible = "snps,dw-cortina";
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compatible = "cortina,ca-mmc";
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reg = <0x0 0xf4400000 0x1000>;
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bus-width = <4>;
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io_ds = <0x77>;
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fifo-mode;
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sd_dll_ctrl = <0xf43200e8>;
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io_drv_ctrl = <0xf432004c>;
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};
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@ -727,6 +727,21 @@ config FSL_ESDHC
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This selects support for the eSDHC (Enhanced Secure Digital Host
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Controller) found on numerous Freescale/NXP SoCs.
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config FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND
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bool "enable eSDHC workaround for 3.3v IO reliability issue"
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depends on FSL_ESDHC && DM_MMC
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default n
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help
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When eSDHC operates at 3.3v, damage can accumulate in an internal
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level shifter at a higher than expected rate. The faster the interface
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runs, the more damage accumulates. This issue now is found on LX2160A
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eSDHC1 for only SD card. The hardware workaround is recommended to use
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an on-board level shifter that is 1.8v on SoC side and 3.3v on SD card
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side. For boards without hardware workaround, this option could be
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enabled, ensuring 1.8v IO voltage and disabling eSDHC if no card.
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This option assumes no hotplug, and u-boot has to make all the way to
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to linux to use 1.8v UHS-I speed mode if has card.
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config FSL_ESDHC_IMX
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bool "Freescale/NXP i.MX eSDHC controller support"
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help
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@ -19,6 +19,7 @@
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#define SD_CLK_SEL_200MHZ (0x2)
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#define SD_CLK_SEL_100MHZ (0x1)
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#define SD_CLK_SEL_50MHZ (0x0)
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#define IO_DRV_SD_DS_OFFSET (16)
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#define IO_DRV_SD_DS_MASK (0xff << IO_DRV_SD_DS_OFFSET)
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@ -44,15 +45,11 @@ static void ca_dwmci_clksel(struct dwmci_host *host)
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struct ca_dwmmc_priv_data *priv = host->priv;
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u32 val = readl(priv->sd_dll_reg);
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if (host->bus_hz >= 200000000) {
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val &= ~SD_CLK_SEL_MASK;
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val &= ~SD_CLK_SEL_MASK;
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if (host->bus_hz >= 200000000)
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val |= SD_CLK_SEL_200MHZ;
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} else if (host->bus_hz >= 100000000) {
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val &= ~SD_CLK_SEL_MASK;
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else if (host->bus_hz >= 100000000)
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val |= SD_CLK_SEL_100MHZ;
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} else {
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val &= ~SD_CLK_SEL_MASK;
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}
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writel(val, priv->sd_dll_reg);
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}
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@ -77,14 +74,14 @@ unsigned int ca_dwmci_get_mmc_clock(struct dwmci_host *host, uint freq)
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u8 clk_div;
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switch (sd_clk_sel) {
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case 2:
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clk_div = 1;
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case SD_CLK_SEL_50MHZ:
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clk_div = 4;
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break;
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case 1:
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case SD_CLK_SEL_100MHZ:
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clk_div = 2;
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break;
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default:
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clk_div = 4;
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clk_div = 1;
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}
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return SD_SCLK_MAX / clk_div / (host->div + 1);
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@ -100,9 +97,6 @@ static int ca_dwmmc_ofdata_to_platdata(struct udevice *dev)
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host->dev_index = 0;
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host->buswidth = dev_read_u32_default(dev, "bus-width", 1);
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if (host->buswidth != 1 && host->buswidth != 4)
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return -EINVAL;
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host->bus_hz = dev_read_u32_default(dev, "max-frequency", 50000000);
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priv->ds = dev_read_u32_default(dev, "io_ds", 0x33);
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host->fifo_mode = dev_read_bool(dev, "fifo-mode");
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@ -118,10 +112,8 @@ static int ca_dwmmc_ofdata_to_platdata(struct udevice *dev)
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return -EINVAL;
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host->ioaddr = dev_read_addr_ptr(dev);
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if (host->ioaddr == (void *)FDT_ADDR_T_NONE) {
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printf("DWMMC: base address is invalid\n");
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if (!host->ioaddr)
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return -EINVAL;
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}
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host->priv = priv;
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@ -140,10 +132,8 @@ static int ca_dwmmc_probe(struct udevice *dev)
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memcpy(&ca_dwmci_dm_ops, &dm_dwmci_ops, sizeof(struct dm_mmc_ops));
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dwmci_setup_cfg(&plat->cfg, host, host->bus_hz, MIN_FREQ);
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if (host->buswidth == 1) {
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(&plat->cfg)->host_caps &= ~MMC_MODE_8BIT;
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(&plat->cfg)->host_caps &= ~MMC_MODE_4BIT;
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}
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if (host->buswidth == 1)
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(&plat->cfg)->host_caps &= ~(MMC_MODE_8BIT | MMC_MODE_4BIT);
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host->mmc = &plat->mmc;
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host->mmc->priv = &priv->host;
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@ -164,7 +154,7 @@ static int ca_dwmmc_bind(struct udevice *dev)
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}
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static const struct udevice_id ca_dwmmc_ids[] = {
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{ .compatible = "snps,dw-cortina" },
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{ .compatible = "cortina,ca-mmc" },
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{ }
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};
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@ -1,7 +1,7 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
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* Copyright 2019 NXP Semiconductors
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* Copyright 2019-2020 NXP
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* Andy Fleming
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*
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* Based vaguely on the pxa mmc code:
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@ -630,16 +630,15 @@ static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
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static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
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{
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struct fsl_esdhc *regs = priv->esdhc_regs;
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int timeout = 1000;
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#ifdef CONFIG_ESDHC_DETECT_QUIRK
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if (CONFIG_ESDHC_DETECT_QUIRK)
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return 1;
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#endif
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while (!(esdhc_read32(®s->prsstat) & PRSSTAT_CINS) && --timeout)
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udelay(1000);
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if (esdhc_read32(®s->prsstat) & PRSSTAT_CINS)
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return 1;
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return timeout > 0;
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return 0;
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}
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static void fsl_esdhc_get_cfg_common(struct fsl_esdhc_priv *priv,
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@ -724,13 +723,38 @@ __weak int esdhc_status_fixup(void *blob, const char *compat)
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return 0;
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}
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#ifdef CONFIG_FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND
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static int fsl_esdhc_get_cd(struct udevice *dev);
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static void esdhc_disable_for_no_card(void *blob)
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{
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struct udevice *dev;
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for (uclass_first_device(UCLASS_MMC, &dev);
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dev;
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uclass_next_device(&dev)) {
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char esdhc_path[50];
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if (fsl_esdhc_get_cd(dev))
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continue;
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snprintf(esdhc_path, sizeof(esdhc_path), "/soc/esdhc@%lx",
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(unsigned long)dev_read_addr(dev));
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do_fixup_by_path(blob, esdhc_path, "status", "disabled",
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sizeof("disabled"), 1);
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}
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}
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#endif
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void fdt_fixup_esdhc(void *blob, bd_t *bd)
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{
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const char *compat = "fsl,esdhc";
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if (esdhc_status_fixup(blob, compat))
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return;
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#ifdef CONFIG_FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND
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esdhc_disable_for_no_card(blob);
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#endif
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do_fixup_by_compat_u32(blob, compat, "clock-frequency",
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gd->arch.sdhc_clk, 1);
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}
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@ -849,6 +873,7 @@ static int fsl_esdhc_probe(struct udevice *dev)
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struct fsl_esdhc_priv *priv = dev_get_priv(dev);
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fdt_addr_t addr;
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struct mmc *mmc;
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int ret;
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addr = dev_read_addr(dev);
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if (addr == FDT_ADDR_T_NONE)
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@ -882,7 +907,15 @@ static int fsl_esdhc_probe(struct udevice *dev)
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upriv->mmc = mmc;
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return esdhc_init_common(priv, mmc);
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ret = esdhc_init_common(priv, mmc);
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if (ret)
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return ret;
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#ifdef CONFIG_FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND
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if (!fsl_esdhc_get_cd(dev))
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esdhc_setbits32(&priv->esdhc_regs->proctl, PROCTL_VOLT_SEL);
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#endif
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return 0;
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}
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static int fsl_esdhc_get_cd(struct udevice *dev)
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@ -791,7 +791,7 @@ static int esdhc_set_voltage(struct mmc *mmc)
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switch (mmc->signal_voltage) {
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case MMC_SIGNAL_VOLTAGE_330:
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if (priv->vs18_enable)
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return -EIO;
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return -ENOTSUPP;
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#if CONFIG_IS_ENABLED(DM_REGULATOR)
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if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
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ret = regulator_set_value(priv->vqmmc_dev, 3300000);
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@ -972,7 +972,8 @@ static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
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if (priv->signal_voltage != mmc->signal_voltage) {
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ret = esdhc_set_voltage(mmc);
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if (ret) {
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printf("esdhc_set_voltage error %d\n", ret);
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if (ret != -ENOTSUPP)
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printf("esdhc_set_voltage error %d\n", ret);
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return ret;
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}
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}
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@ -1455,6 +1456,7 @@ static int fsl_esdhc_probe(struct udevice *dev)
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if (ret) {
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dev_dbg(dev, "no vqmmc-supply\n");
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} else {
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priv->vqmmc_dev = vqmmc_dev;
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ret = regulator_set_enable(vqmmc_dev, true);
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if (ret) {
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dev_err(dev, "fail to enable vqmmc-supply\n");
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@ -4,6 +4,7 @@
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*-------------------------------------------------------------------
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*
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* Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc
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* Copyright 2020 NXP
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*/
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#ifndef __FSL_ESDHC_H__
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@ -98,6 +99,7 @@
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#define PROCTL_DTW_4 0x00000002
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#define PROCTL_DTW_8 0x00000004
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#define PROCTL_D3CD 0x00000008
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#define PROCTL_VOLT_SEL 0x00000400
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#define CMDARG 0x0002e008
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