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arm: stm32mp: activate data cache on DDR in SPL

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Activate cache on DDR to improve the accesses to DDR used by SPL:
- CONFIG_SPL_BSS_START_ADDR
- CONFIG_SYS_SPL_MALLOC_START

Cache is configured only when DDR is fully initialized,
to avoid speculative access and issue in get_ram_size().
Data cache is deactivated at the end of SPL, to flush the data cache
and the TLB.

Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
This commit is contained in:
Patrick Delaunay 2020-04-30 16:30:21 +02:00
parent 7e8471cae5
commit dc7e5f190d
1 changed files with 19 additions and 0 deletions
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19
arch/arm/mach-stm32mp/spl.c
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@ -4,6 +4,7 @@
*/
#include <common.h>
#include <cpu_func.h>
#include <dm.h>
#include <hang.h>
#include <spl.h>
@ -128,4 +129,22 @@ void board_init_f(ulong dummy)
printf("DRAM init failed: %d\n", ret);
hang();
}
/*
* activate cache on DDR only when DDR is fully initialized
* to avoid speculative access and issue in get_ram_size()
*/
if (!CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
mmu_set_region_dcache_behaviour(STM32_DDR_BASE, STM32_DDR_SIZE,
DCACHE_DEFAULT_OPTION);
}
void spl_board_prepare_for_boot(void)
{
dcache_disable();
}
void spl_board_prepare_for_boot_linux(void)
{
dcache_disable();
}