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arm: asm/cache.c: Introduce arm_reserve_mmu

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As a preparation for turning reserve_mmu into an arch-specific variant,
introduce arm_reserve_mmu on ARM. It implements the default routine for
reserving memory for MMU TLB and needs to be weakly defined in order to allow
for machines to override it.

Without this decoupling, after introducing arch_reserve_mmu, there would be two
weak definitions for it, one in common/board_f.c and one in
arch/arm/lib/cache.c.

Signed-off-by: Ovidiu Panait <ovpanait@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Ovidiu Panait 2020-03-29 20:57:40 +03:00 committed by Tom Rini
parent 586b15bce8
commit 6184858b85
4 changed files with 20 additions and 2 deletions
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11
arch/arm/include/asm/cache.h
View file

@ -49,4 +49,15 @@ void dram_bank_mmu_setup(int bank);
*/
#define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
/*
* arm_reserve_mmu() - Reserve memory for MMU TLB table
*
* Default implementation for reserving memory for MMU TLB table. It is used
* during generic board init sequence in common/board_f.c. Weakly defined, so
* that machines can override it if needed.
*
* Return: 0 if OK
*/
int arm_reserve_mmu(void);
#endif /* _ASM_CACHE_H */

5
arch/arm/lib/cache.c
View file

@ -122,6 +122,11 @@ void invalidate_l2_cache(void)
#endif
__weak int reserve_mmu(void)
{
return arm_reserve_mmu();
}
__weak int arm_reserve_mmu(void)
{
#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
/* reserve TLB table */

3
arch/arm/mach-versal/cpu.c
View file

@ -9,6 +9,7 @@
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#include <asm/cache.h>
DECLARE_GLOBAL_DATA_PTR;
@ -107,7 +108,7 @@ u64 get_page_table_size(void)
}
#if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU)
int reserve_mmu(void)
int arm_reserve_mmu(void)
{
tcm_init(TCM_LOCK);
gd->arch.tlb_size = PGTABLE_SIZE;

3
arch/arm/mach-zynqmp/cpu.c
View file

@ -11,6 +11,7 @@
#include <asm/armv8/mmu.h>
#include <asm/io.h>
#include <zynqmp_firmware.h>
#include <asm/cache.h>
#define ZYNQ_SILICON_VER_MASK 0xF000
#define ZYNQ_SILICON_VER_SHIFT 12
@ -116,7 +117,7 @@ void tcm_init(u8 mode)
#endif
#ifdef CONFIG_SYS_MEM_RSVD_FOR_MMU
int reserve_mmu(void)
int arm_reserve_mmu(void)
{
tcm_init(TCM_LOCK);
gd->arch.tlb_size = PGTABLE_SIZE;