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https://github.com/AsahiLinux/u-boot
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powerpc: Remove configs/BSC9131RDB_NAND_SYSCLK100_defconfig board
DM_SPI and other driver model migration deadlines are expired for this board. Remove it. Patch-cc: Poonam Aggrwal <poonam.aggrwal@nxp.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
This commit is contained in:
Jagan Teki
parent
e3e6782d47
commit
f178468b5e
15 changed files with 0 additions and 1212 deletions
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@ -24,12 +24,6 @@ config TARGET_SOCRATES
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bool "Support socrates"
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select ARCH_MPC8544
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config TARGET_BSC9131RDB
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bool "Support BSC9131RDB"
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select ARCH_BSC9131
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select SUPPORT_SPL
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select BOARD_EARLY_INIT_F
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config TARGET_BSC9132QDS
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bool "Support BSC9132QDS"
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select ARCH_BSC9132
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@ -1579,7 +1573,6 @@ config SYS_FSL_LBC_CLK_DIV
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Defines divider of platform clock(clock input to
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eLBC controller).
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source "board/freescale/bsc9131rdb/Kconfig"
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source "board/freescale/bsc9132qds/Kconfig"
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source "board/freescale/c29xpcie/Kconfig"
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source "board/freescale/corenet_ds/Kconfig"
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@ -1,12 +0,0 @@
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if TARGET_BSC9131RDB
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config SYS_BOARD
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default "bsc9131rdb"
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config SYS_VENDOR
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default "freescale"
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config SYS_CONFIG_NAME
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default "BSC9131RDB"
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endif
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@ -1,9 +0,0 @@
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BSC9131RDB BOARD
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M: Poonam Aggrwal <poonam.aggrwal@nxp.com>
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S: Maintained
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F: board/freescale/bsc9131rdb/
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F: include/configs/BSC9131RDB.h
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F: configs/BSC9131RDB_NAND_defconfig
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F: configs/BSC9131RDB_NAND_SYSCLK100_defconfig
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F: configs/BSC9131RDB_SPIFLASH_defconfig
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F: configs/BSC9131RDB_SPIFLASH_SYSCLK100_defconfig
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@ -1,21 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright 2011-2012 Freescale Semiconductor, Inc.
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MINIMAL=
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ifdef CONFIG_SPL_BUILD
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ifdef CONFIG_SPL_INIT_MINIMAL
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MINIMAL=y
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endif
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endif
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ifdef MINIMAL
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obj-y += spl_minimal.o
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else
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obj-y += bsc9131rdb.o
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obj-y += ddr.o
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endif
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obj-y += law.o
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obj-y += tlb.o
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@ -1,151 +0,0 @@
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Overview
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--------
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- BSC9131 is integrated device that targets Femto base station market.
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It combines Power Architecture e500v2 and DSP StarCore SC3850 core
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technologies with MAPLE-B2F baseband acceleration processing elements.
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- It's MAPLE disabled personality is called 9231.
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The BSC9131 SoC includes the following function and features:
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. Power Architecture subsystem including a e500 processor with 256-Kbyte shared
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L2 cache
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. StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
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. The Multi Accelerator Platform Engine for Femto BaseStation Baseband
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Processing (MAPLE-B2F)
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. A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding,
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Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing,
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and CRC algorithms
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. Consists of accelerators for Convolution, Filtering, Turbo Encoding,
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Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion
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operations
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. DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with
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ECC, up to 400-MHz clock/800 MHz data rate
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. Dedicated security engine featuring trusted boot
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. DMA controller
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. OCNDMA with four bidirectional channels
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. Interfaces
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. Two triple-speed Gigabit Ethernet controllers featuring network acceleration
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including IEEE 1588. v2 hardware support and virtualization (eTSEC)
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. eTSEC 1 supports RGMII/RMII
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. eTSEC 2 supports RGMII
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. High-speed USB 2.0 host and device controller with ULPI interface
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. Enhanced secure digital (SD/MMC) host controller (eSDHC)
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. Antenna interface controller (AIC), supporting three industry standard
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JESD207/three custom ADI RF interfaces (two dual port and one single port)
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and three MAXIM's MaxPHY serial interfaces
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. ADI lanes support both full duplex FDD support and half duplex TDD support
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. Universal Subscriber Identity Module (USIM) interface that facilitates
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communication to SIM cards or Eurochip pre-paid phone cards
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. TDM with one TDM port
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. Two DUART, four eSPI, and two I2C controllers
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. Integrated Flash memory controller (IFC)
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. TDM with 256 channels
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. GPIO
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. Sixteen 32-bit timers
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The e500 core subsystem within the Power Architecture consists of the following:
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. 32-Kbyte L1 instruction cache
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. 32-Kbyte L1 data cache
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. 256-Kbyte L2 cache/L2 memory/L2 stash
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. programmable interrupt controller (PIC)
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. Debug support
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. Timers
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The SC3850 core subsystem consists of the following:
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. 32 Kbyte 8-way level 1 instruction cache (L1 ICache)
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. 32 Kbyte 8-way level 1 data cache (L1 DCache)
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. 512 Kbyte 8-way level 2 unified instruction/data cache (M2 memory)
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. Memory management unit (MMU)
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. Enhanced programmable interrupt controller (EPIC)
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. Debug and profiling unit (DPU)
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. Two 32-bit timers
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BSC9131RDB board Overview
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-------------------------
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1Gbyte DDR3 (on board DDR)
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128Mbyte 2K page size NAND Flash
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256 Kbit M24256 I2C EEPROM
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128 Mbit SPI Flash memory
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USB-ULPI
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eTSEC1: Connected to RGMII PHY
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eTSEC2: Connected to RGMII PHY
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DUART interface: supports one UARTs up to 115200 bps for console display
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USIM connector
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Frequency Combinations Supported
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--------------------------------
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Core MHz/CCB MHz/DDR(MT/s)
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1. 1000/500/800
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2. 800/400/667
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Boot Methods Supported
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-----------------------
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1. NAND Flash
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2. SPI Flash
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Default Boot Method
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--------------------
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NAND boot
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Building U-Boot
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--------------
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To build the U-Boot for BSC9131RDB:
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1. NAND Flash with sysclk 66MHz(J16 on RDB closed, default)
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make BSC9131RDB_NAND
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2. NAND Flash with sysclk 100MHz(J16 on RDB open)
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make BSC9131RDB_NAND_SYSCLK100
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3. SPI Flash with sysclk 66MHz(J16 on RDB closed, default)
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make BSC9131RDB_SPIFLASH
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4. SPI Flash with sysclk 100MHz(J16 on RDB open)
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make BSC9131RDB_SPIFLASH_SYSCLK100
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Memory map
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-----------
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0x0000_0000 0x7FFF_FFFF DDR 1G cacheable
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0xA0000000 0xBFFFFFFF Shared DSP core L2/M2 space 512M
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0xC100_0000 0xC13F_FFFF MAPLE-2F 4M
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0xC1F0_0000 0xC1F3_FFFF PA SRAM Region 0 256K
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0xC1F8_0000 0xC1F9_FFFF PA SRAM Region 1 128K
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0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K
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0xFEE0_0000 0xFEE0_0FFF DSP Boot ROM 4K
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0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M
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0xFF70_0000 0xFF7F_FFFF PA CCSR 1M
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0xFF80_0000 0xFFFF_FFFF Boot Page & NAND Buffer 8M
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DDR Memory map
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---------------
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0x0000_0000 0x36FF_FFFF Memory passed onto Linux
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0x3700_0000 0x37FF_FFFF PowerPC-DSP shared control area
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0x3800_0000 0x4FFF_FFFF DSP Private area
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Out of 880M, passed onto Linux, 1hugetlb page of 256M is reserved for
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data communcation between PowerPC and DSP core.
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Rest is PowerPC private area.
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Flashing Images
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---------------
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To place a new U-Boot image in the NAND flash and then boot
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with that new image temporarily, use this:
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tftp 1000000 u-boot-nand.bin
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nand erase 0 100000
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nand write 1000000 0 100000
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reset
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Using the Device Tree Source File
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---------------------------------
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To create the DTB (Device Tree Binary) image file,
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use a command similar to this:
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dtc -b 0 -f -I dts -O dtb bsc9131rdb.dts > bsc9131rdb.dtb
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Likely, that .dts file will come from here;
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linux-2.6/arch/powerpc/boot/dts/bsc9131rdb.dts
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Booting Linux
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-------------
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Place a linux uImage in the TFTP disk area.
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tftp 1000000 uImage
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tftp 2000000 rootfs.ext2.gz.uboot
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tftp c00000 bsc9131rdb.dtb
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bootm 1000000 2000000 c00000
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@ -1,82 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2011-2012 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <image.h>
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#include <init.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/cache.h>
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#include <asm/immap_85xx.h>
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#include <asm/io.h>
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#include <env.h>
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#include <miiphy.h>
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#include <linux/libfdt.h>
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#include <fdt_support.h>
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#include <fsl_mdio.h>
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#include <tsec.h>
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#include <jffs2/load_kernel.h>
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#include <mtd_node.h>
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#include <flash.h>
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#include <netdev.h>
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DECLARE_GLOBAL_DATA_PTR;
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int board_early_init_f(void)
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{
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42);
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setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS);
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clrbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43);
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setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK |
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MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD);
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setbits_be32(&gur->halt_req_mask, HALTED_TO_HALT_REQ_MASK_0);
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clrsetbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_IFC_AD_GPIO_MASK |
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MPC85xx_PMUXCR_IFC_AD17_GPO_MASK,
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MPC85xx_PMUXCR_IFC_AD_GPIO |
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MPC85xx_PMUXCR_IFC_AD17_GPO | MPC85xx_PMUXCR_SDHC_USIM);
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return 0;
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}
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int checkboard(void)
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{
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struct cpu_type *cpu;
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cpu = gd->arch.cpu;
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printf("Board: %sRDB\n", cpu->name);
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return 0;
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
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#ifdef CONFIG_FDT_FIXUP_PARTITIONS
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static const struct node_info nodes[] = {
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{ "fsl,ifc-nand", MTD_DEV_TYPE_NAND, },
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};
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#endif
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int ft_board_setup(void *blob, bd_t *bd)
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{
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phys_addr_t base;
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phys_size_t size;
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ft_cpu_setup(blob, bd);
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base = env_get_bootm_low();
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size = env_get_bootm_size();
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fdt_fixup_memory(blob, (u64)base, (u64)size);
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#ifdef CONFIG_FDT_FIXUP_PARTITIONS
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fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
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#endif
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fsl_fdt_fixup_dr_usb(blob, bd);
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return 0;
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}
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#endif
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@ -1,170 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2011-2012 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <init.h>
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#include <vsprintf.h>
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#include <asm/mmu.h>
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#include <asm/immap_85xx.h>
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#include <asm/processor.h>
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#include <fsl_ddr_sdram.h>
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#include <fsl_ddr_dimm_params.h>
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#include <asm/io.h>
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#include <asm/fsl_law.h>
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#ifndef CONFIG_SYS_DDR_RAW_TIMING
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#define CONFIG_SYS_DRAM_SIZE 1024
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fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
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.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
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.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
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.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
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.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
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.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
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.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
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.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
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.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
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.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
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.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
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.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
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.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
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.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
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.ddr_data_init = CONFIG_MEM_INIT_VALUE,
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.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
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.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
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.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
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.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
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.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
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.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
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.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL_800,
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.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
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.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
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.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
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};
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fixed_ddr_parm_t fixed_ddr_parm_0[] = {
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{750, 850, &ddr_cfg_regs_800},
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{0, 0, NULL}
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};
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unsigned long get_sdram_size(void)
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{
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return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DRAM_SIZE);
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}
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/*
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* Fixed sdram init -- doesn't use serial presence detect.
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*/
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phys_size_t fixed_sdram(void)
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{
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int i;
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char buf[32];
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fsl_ddr_cfg_regs_t ddr_cfg_regs;
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phys_size_t ddr_size;
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ulong ddr_freq, ddr_freq_mhz;
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ddr_freq = get_ddr_freq(0);
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ddr_freq_mhz = ddr_freq / 1000000;
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printf("Configuring DDR for %s MT/s data rate\n",
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strmhz(buf, ddr_freq));
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for (i = 0; fixed_ddr_parm_0[i].max_freq > 0; i++) {
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if ((ddr_freq_mhz > fixed_ddr_parm_0[i].min_freq) &&
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(ddr_freq_mhz <= fixed_ddr_parm_0[i].max_freq)) {
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memcpy(&ddr_cfg_regs, fixed_ddr_parm_0[i].ddr_settings,
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sizeof(ddr_cfg_regs));
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break;
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}
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}
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if (fixed_ddr_parm_0[i].max_freq == 0) {
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panic("Unsupported DDR data rate %s MT/s data rate\n",
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strmhz(buf, ddr_freq));
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}
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ddr_size = (phys_size_t) CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
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fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
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if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, ddr_size,
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LAW_TRGT_IF_DDR_1) < 0) {
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printf("ERROR setting Local Access Windows for DDR\n");
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return 0;
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}
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return ddr_size;
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}
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#else /* CONFIG_SYS_DDR_RAW_TIMING */
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/* Micron MT41J256M8HX-15E */
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dimm_params_t ddr_raw_timing = {
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.n_ranks = 1,
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.rank_density = 1073741824u,
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.capacity = 1073741824u,
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.primary_sdram_width = 32,
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.ec_sdram_width = 0,
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.registered_dimm = 0,
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.mirrored_dimm = 0,
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.n_row_addr = 15,
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.n_col_addr = 10,
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.n_banks_per_sdram_device = 8,
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.edc_config = 0,
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.burst_lengths_bitmask = 0x0c,
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.tckmin_x_ps = 1870,
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.caslat_x = 0x1e << 4, /* 5,6,7,8 */
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.taa_ps = 13125,
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.twr_ps = 15000,
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||||
.trcd_ps = 13125,
|
||||
.trrd_ps = 7500,
|
||||
.trp_ps = 13125,
|
||||
.tras_ps = 37500,
|
||||
.trc_ps = 50625,
|
||||
.trfc_ps = 160000,
|
||||
.twtr_ps = 7500,
|
||||
.trtp_ps = 7500,
|
||||
.refresh_rate_ps = 7800000,
|
||||
.tfaw_ps = 37500,
|
||||
};
|
||||
|
||||
int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
|
||||
unsigned int controller_number,
|
||||
unsigned int dimm_number)
|
||||
{
|
||||
const char dimm_model[] = "Fixed DDR on board";
|
||||
|
||||
if ((controller_number == 0) && (dimm_number == 0)) {
|
||||
memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
|
||||
memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
|
||||
memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void fsl_ddr_board_options(memctl_options_t *popts,
|
||||
dimm_params_t *pdimm,
|
||||
unsigned int ctrl_num)
|
||||
{
|
||||
int i;
|
||||
popts->clk_adjust = 6;
|
||||
popts->cpo_override = 0x1f;
|
||||
popts->write_data_delay = 2;
|
||||
popts->half_strength_driver_enable = 1;
|
||||
/* Write leveling override */
|
||||
popts->wrlvl_en = 1;
|
||||
popts->wrlvl_override = 1;
|
||||
popts->wrlvl_sample = 0xf;
|
||||
popts->wrlvl_start = 0x8;
|
||||
popts->trwt_override = 1;
|
||||
popts->trwt = 0;
|
||||
|
||||
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
|
||||
popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
|
||||
popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* CONFIG_SYS_DDR_RAW_TIMING */
|
||||
|
|
@ -1,18 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2011-2012 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/fsl_law.h>
|
||||
#include <asm/mmu.h>
|
||||
|
||||
struct law_entry law_table[] = {
|
||||
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
|
||||
SET_LAW(CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS, LAW_SIZE_1M,
|
||||
LAW_TRGT_IF_DSP_CCSR),
|
||||
SET_LAW(CONFIG_SYS_FSL_DSP_M2_RAM_ADDR, LAW_SIZE_16M,
|
||||
LAW_TRGT_IF_OCN_DSP),
|
||||
};
|
||||
|
||||
int num_law_entries = ARRAY_SIZE(law_table);
|
||||
|
|
@ -1,105 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <init.h>
|
||||
#include <ns16550.h>
|
||||
#include <asm/io.h>
|
||||
#include <nand.h>
|
||||
#include <linux/compiler.h>
|
||||
#include <asm/fsl_law.h>
|
||||
#include <fsl_ddr_sdram.h>
|
||||
#include <asm/global_data.h>
|
||||
#include <linux/delay.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
/*
|
||||
* Fixed sdram init -- doesn't use serial presence detect.
|
||||
*/
|
||||
static void sdram_init(void)
|
||||
{
|
||||
struct ccsr_ddr __iomem *ddr =
|
||||
(struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
|
||||
|
||||
__raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
|
||||
__raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
|
||||
#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
|
||||
__raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
|
||||
__raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
|
||||
#endif
|
||||
__raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3);
|
||||
__raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0);
|
||||
__raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1);
|
||||
__raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2);
|
||||
|
||||
__raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2);
|
||||
__raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode);
|
||||
__raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2);
|
||||
|
||||
__raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval);
|
||||
__raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
|
||||
__raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl);
|
||||
|
||||
__raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl);
|
||||
__raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
|
||||
__raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
|
||||
__raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl);
|
||||
|
||||
/* Set, but do not enable the memory */
|
||||
__raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg);
|
||||
|
||||
asm volatile("sync;isync");
|
||||
udelay(500);
|
||||
|
||||
/* Let the controller go */
|
||||
out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
|
||||
|
||||
set_next_law(CONFIG_SYS_NAND_DDR_LAW, LAW_SIZE_1G, LAW_TRGT_IF_DDR_1);
|
||||
}
|
||||
|
||||
void board_init_f(ulong bootflag)
|
||||
{
|
||||
u32 plat_ratio;
|
||||
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
|
||||
|
||||
/* initialize selected port with appropriate baud rate */
|
||||
plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
|
||||
plat_ratio >>= 1;
|
||||
gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
|
||||
|
||||
NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
|
||||
gd->bus_clk / 16 / CONFIG_BAUDRATE);
|
||||
|
||||
puts("\nNAND boot... ");
|
||||
|
||||
/* Initialize the DDR3 */
|
||||
sdram_init();
|
||||
|
||||
/* copy code to RAM and jump to it - this should not return */
|
||||
/* NOTE - code has to be copied out of NAND buffer before
|
||||
* other blocks can be read.
|
||||
*/
|
||||
relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
|
||||
}
|
||||
|
||||
void board_init_r(gd_t *gd, ulong dest_addr)
|
||||
{
|
||||
nand_boot();
|
||||
}
|
||||
|
||||
void putc(char c)
|
||||
{
|
||||
if (c == '\n')
|
||||
NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
|
||||
|
||||
NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
|
||||
}
|
||||
|
||||
void puts(const char *str)
|
||||
{
|
||||
while (*str)
|
||||
putc(*str++);
|
||||
}
|
||||
|
|
@ -1,61 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2011-2012 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/mmu.h>
|
||||
|
||||
struct fsl_e_tlb_entry tlb_table[] = {
|
||||
/* TLB 0 - for temp stack in cache */
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
|
||||
CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
|
||||
CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
|
||||
CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
|
||||
/* TLB 1 */
|
||||
/* *I*** - Covers boot page */
|
||||
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 0, BOOKE_PAGESZ_4K, 1),
|
||||
#ifdef CONFIG_SPL_NAND_BOOT
|
||||
SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 10, BOOKE_PAGESZ_4K, 1),
|
||||
#endif
|
||||
|
||||
/* *I*G* - CCSRBAR (PA) */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 1, BOOKE_PAGESZ_1M, 1),
|
||||
|
||||
/* CCSRBAR (DSP) */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_FSL_DSP_CCSRBAR,
|
||||
CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS,
|
||||
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 2, BOOKE_PAGESZ_1M, 1),
|
||||
|
||||
#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
|
||||
0, 8, BOOKE_PAGESZ_1G, 1),
|
||||
#endif
|
||||
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 3, BOOKE_PAGESZ_1M, 1)
|
||||
|
||||
};
|
||||
|
||||
int num_tlb_entries = ARRAY_SIZE(tlb_table);
|
||||
|
|
@ -1,64 +0,0 @@
|
|||
CONFIG_PPC=y
|
||||
CONFIG_SYS_TEXT_BASE=0x00201000
|
||||
CONFIG_ENV_SIZE=0x20000
|
||||
CONFIG_ENV_OFFSET=0xE0000
|
||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_SPL=y
|
||||
CONFIG_SPL_TEXT_BASE=0xFFFFE000
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_BSC9131RDB=y
|
||||
CONFIG_SYS_CUSTOM_LDSCRIPT=y
|
||||
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SYS_CLK_100"
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
# CONFIG_MISC_INIT_R is not set
|
||||
# CONFIG_SPL_FRAMEWORK is not set
|
||||
CONFIG_SPL_NAND_BOOT=y
|
||||
CONFIG_SPL_NAND_SUPPORT=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_MTDPARTS=y
|
||||
CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash,"
|
||||
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
|
||||
CONFIG_ENV_IS_IN_NAND=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_FSL_CAAM=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_PHY_ATHEROS=y
|
||||
CONFIG_PHY_BROADCOM=y
|
||||
CONFIG_PHY_DAVICOM=y
|
||||
CONFIG_PHY_LXT=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_NATSEMI=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_PHY_SMSC=y
|
||||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_TSEC_ENET=y
|
||||
# CONFIG_PCI is not set
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_FSL_ESPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
CONFIG_FDT_FIXUP_PARTITIONS=y
|
||||
|
|
@ -1,63 +0,0 @@
|
|||
CONFIG_PPC=y
|
||||
CONFIG_SYS_TEXT_BASE=0x00201000
|
||||
CONFIG_ENV_SIZE=0x20000
|
||||
CONFIG_ENV_OFFSET=0xE0000
|
||||
CONFIG_SPL_SERIAL_SUPPORT=y
|
||||
CONFIG_SPL=y
|
||||
CONFIG_SPL_TEXT_BASE=0xFFFFE000
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_BSC9131RDB=y
|
||||
CONFIG_SYS_CUSTOM_LDSCRIPT=y
|
||||
CONFIG_SYS_LDSCRIPT="arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
# CONFIG_MISC_INIT_R is not set
|
||||
# CONFIG_SPL_FRAMEWORK is not set
|
||||
CONFIG_SPL_NAND_BOOT=y
|
||||
CONFIG_SPL_NAND_SUPPORT=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_MTDPARTS=y
|
||||
CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash,"
|
||||
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
|
||||
CONFIG_ENV_IS_IN_NAND=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_FSL_CAAM=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_PHY_ATHEROS=y
|
||||
CONFIG_PHY_BROADCOM=y
|
||||
CONFIG_PHY_DAVICOM=y
|
||||
CONFIG_PHY_LXT=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_NATSEMI=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_PHY_SMSC=y
|
||||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_TSEC_ENET=y
|
||||
# CONFIG_PCI is not set
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_FSL_ESPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
CONFIG_FDT_FIXUP_PARTITIONS=y
|
||||
|
|
@ -1,56 +0,0 @@
|
|||
CONFIG_PPC=y
|
||||
CONFIG_SYS_TEXT_BASE=0x11000000
|
||||
CONFIG_ENV_SIZE=0x2000
|
||||
CONFIG_ENV_OFFSET=0x100000
|
||||
CONFIG_ENV_SECT_SIZE=0x10000
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_BSC9131RDB=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH,SYS_CLK_100"
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
# CONFIG_MISC_INIT_R is not set
|
||||
CONFIG_HUSH_PARSER=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_MTDPARTS=y
|
||||
CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash,"
|
||||
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_FSL_CAAM=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_PHY_ATHEROS=y
|
||||
CONFIG_PHY_BROADCOM=y
|
||||
CONFIG_PHY_DAVICOM=y
|
||||
CONFIG_PHY_LXT=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_NATSEMI=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_PHY_SMSC=y
|
||||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_TSEC_ENET=y
|
||||
# CONFIG_PCI is not set
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_FSL_ESPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
CONFIG_FDT_FIXUP_PARTITIONS=y
|
||||
|
|
@ -1,56 +0,0 @@
|
|||
CONFIG_PPC=y
|
||||
CONFIG_SYS_TEXT_BASE=0x11000000
|
||||
CONFIG_ENV_SIZE=0x2000
|
||||
CONFIG_ENV_OFFSET=0x100000
|
||||
CONFIG_ENV_SECT_SIZE=0x10000
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_BSC9131RDB=y
|
||||
CONFIG_FIT=y
|
||||
CONFIG_FIT_VERBOSE=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
|
||||
CONFIG_BOOTDELAY=10
|
||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
||||
# CONFIG_MISC_INIT_R is not set
|
||||
CONFIG_HUSH_PARSER=y
|
||||
# CONFIG_CMD_FLASH is not set
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_CMD_MTDPARTS=y
|
||||
CONFIG_MTDIDS_DEFAULT="nand0=ff800000.flash,"
|
||||
CONFIG_MTDPARTS_DEFAULT="mtdparts=ff800000.flash:1m(uboot),8m(kernel),512k(dtb),-(fs)"
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_FSL_CAAM=y
|
||||
# CONFIG_MMC is not set
|
||||
CONFIG_MTD=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_PHY_ATHEROS=y
|
||||
CONFIG_PHY_BROADCOM=y
|
||||
CONFIG_PHY_DAVICOM=y
|
||||
CONFIG_PHY_LXT=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_NATSEMI=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_PHY_SMSC=y
|
||||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_TSEC_ENET=y
|
||||
# CONFIG_PCI is not set
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_FSL_ESPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
CONFIG_FDT_FIXUP_PARTITIONS=y
|
||||
|
|
@ -1,337 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2011-2012 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
/*
|
||||
* BSC9131 RDB board configuration file
|
||||
*/
|
||||
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#define CONFIG_NAND_FSL_IFC
|
||||
|
||||
#ifdef CONFIG_SPIFLASH
|
||||
#define CONFIG_RAMBOOT_SPIFLASH
|
||||
#define CONFIG_SYS_RAMBOOT
|
||||
#define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_MTD_RAW_NAND
|
||||
#define CONFIG_SPL_INIT_MINIMAL
|
||||
#define CONFIG_SPL_FLUSH_IMAGE
|
||||
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
|
||||
|
||||
#define CONFIG_SPL_MAX_SIZE 8192
|
||||
#define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000
|
||||
#define CONFIG_SPL_RELOC_STACK 0x00100000
|
||||
#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
|
||||
#define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
|
||||
#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
|
||||
#else
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
|
||||
#endif
|
||||
|
||||
/* High Level Configuration Options */
|
||||
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
#define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on 9131 RDB */
|
||||
#if defined(CONFIG_SYS_CLK_100)
|
||||
#define CONFIG_SYS_CLK_FREQ 100000000 /* SYSCLK for 9131 RDB */
|
||||
#else
|
||||
#define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for 9131 RDB */
|
||||
#endif
|
||||
|
||||
#define CONFIG_HWCONFIG
|
||||
/*
|
||||
* These can be toggled for performance analysis, otherwise use default.
|
||||
*/
|
||||
#define CONFIG_L2_CACHE /* toggle L2 cache */
|
||||
#define CONFIG_BTB /* enable branch predition */
|
||||
|
||||
/* DDR Setup */
|
||||
#undef CONFIG_SYS_DDR_RAW_TIMING
|
||||
#undef CONFIG_DDR_SPD
|
||||
#define CONFIG_SYS_SPD_BUS_NUM 0
|
||||
#define SPD_EEPROM_ADDRESS 0x52 /* I2C access */
|
||||
|
||||
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
extern unsigned long get_sdram_size(void);
|
||||
#endif
|
||||
#define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
|
||||
|
||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
|
||||
#define CONFIG_CHIP_SELECTS_PER_CTRL 1
|
||||
|
||||
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
|
||||
#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
|
||||
#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
|
||||
|
||||
#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
|
||||
#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
|
||||
#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
|
||||
#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
|
||||
|
||||
#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
|
||||
#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
|
||||
#define CONFIG_SYS_DDR_RCW_1 0x00000000
|
||||
#define CONFIG_SYS_DDR_RCW_2 0x00000000
|
||||
#define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
|
||||
#define CONFIG_SYS_DDR_CONTROL_2 0x24401000
|
||||
#define CONFIG_SYS_DDR_TIMING_4 0x00000001
|
||||
#define CONFIG_SYS_DDR_TIMING_5 0x02401400
|
||||
|
||||
#define CONFIG_SYS_DDR_TIMING_3_800 0x00030000
|
||||
#define CONFIG_SYS_DDR_TIMING_0_800 0x00110104
|
||||
#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644
|
||||
#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa888cf
|
||||
#define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000
|
||||
#define CONFIG_SYS_DDR_MODE_1_800 0x00441420
|
||||
#define CONFIG_SYS_DDR_MODE_2_800 0x8000c000
|
||||
#define CONFIG_SYS_DDR_INTERVAL_800 0x0c300100
|
||||
#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608
|
||||
|
||||
/*
|
||||
* Base addresses -- Note these are effective addresses where the
|
||||
* actual resources get mapped (not physical addresses)
|
||||
*/
|
||||
/* relocated CCSRBAR */
|
||||
#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
|
||||
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR_DEFAULT
|
||||
|
||||
#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses */
|
||||
/* CONFIG_SYS_IMMR */
|
||||
/* DSP CCSRBAR */
|
||||
#define CONFIG_SYS_FSL_DSP_CCSRBAR CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
|
||||
#define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
|
||||
|
||||
/*
|
||||
* Memory map
|
||||
*
|
||||
* 0x0000_0000 0x3FFF_FFFF DDR 1G cacheable
|
||||
* 0x8800_0000 0x8810_0000 IFC internal SRAM 1M
|
||||
* 0xB000_0000 0xB0FF_FFFF DSP core M2 memory 16M
|
||||
* 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M
|
||||
* 0xC1F0_0000 0xC1F3_FFFF PA L2 SRAM Region 0 256K
|
||||
* 0xC1F8_0000 0xC1F9_FFFF PA L2 SRAM Region 1 128K
|
||||
* 0xFED0_0000 0xFED0_3FFF SEC Secured RAM 16K
|
||||
* 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M
|
||||
* 0xFF70_0000 0xFF7F_FFFF PA CCSR 1M
|
||||
* 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND flash buffer 8M
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
* IFC Definitions
|
||||
*/
|
||||
|
||||
/* NAND Flash on IFC */
|
||||
#define CONFIG_SYS_NAND_BASE 0xff800000
|
||||
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
|
||||
|
||||
#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
|
||||
| CSPR_PORT_SIZE_8 /* Port Size = 8 bit*/ \
|
||||
| CSPR_MSEL_NAND /* MSEL = NAND */ \
|
||||
| CSPR_V)
|
||||
#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
|
||||
|
||||
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
|
||||
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
|
||||
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
|
||||
| CSOR_NAND_RAL_2 /* RAL = 2Byes */ \
|
||||
| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
|
||||
| CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
|
||||
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
|
||||
|
||||
/* NAND Flash Timing Params */
|
||||
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x03) \
|
||||
| FTIM0_NAND_TWP(0x05) \
|
||||
| FTIM0_NAND_TWCHT(0x02) \
|
||||
| FTIM0_NAND_TWH(0x04))
|
||||
#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x1C) \
|
||||
| FTIM1_NAND_TWBE(0x1E) \
|
||||
| FTIM1_NAND_TRR(0x07) \
|
||||
| FTIM1_NAND_TRP(0x05))
|
||||
#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x08) \
|
||||
| FTIM2_NAND_TREH(0x04) \
|
||||
| FTIM2_NAND_TWHRE(0x11))
|
||||
#define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04)
|
||||
|
||||
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 1
|
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
|
||||
|
||||
#define CONFIG_SYS_NAND_DDR_LAW 11
|
||||
|
||||
/* Set up IFC registers for boot location NAND */
|
||||
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
|
||||
#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
|
||||
#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
|
||||
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
|
||||
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
|
||||
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
|
||||
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_LOCK
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000/* End of used area in RAM */
|
||||
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
|
||||
- GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
|
||||
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/
|
||||
|
||||
/* Serial Port */
|
||||
#undef CONFIG_SERIAL_SOFTWARE_FIFO
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
#define CONFIG_NS16550_MIN_FUNCTIONS
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
|
||||
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
|
||||
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
|
||||
/* I2C EEPROM */
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
|
||||
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
|
||||
|
||||
/* eSPI - Enhanced SPI */
|
||||
|
||||
#if defined(CONFIG_TSEC_ENET)
|
||||
|
||||
#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
|
||||
#define CONFIG_TSEC1 1
|
||||
#define CONFIG_TSEC1_NAME "eTSEC1"
|
||||
#define CONFIG_TSEC2 1
|
||||
#define CONFIG_TSEC2_NAME "eTSEC2"
|
||||
|
||||
#define TSEC1_PHY_ADDR 0
|
||||
#define TSEC2_PHY_ADDR 3
|
||||
|
||||
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
||||
#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
||||
|
||||
#define TSEC1_PHYIDX 0
|
||||
|
||||
#define TSEC2_PHYIDX 0
|
||||
|
||||
#define CONFIG_ETHPRIME "eTSEC1"
|
||||
|
||||
#endif /* CONFIG_TSEC_ENET */
|
||||
|
||||
/*
|
||||
* Environment
|
||||
*/
|
||||
#if defined(CONFIG_RAMBOOT_SPIFLASH)
|
||||
#elif defined(CONFIG_MTD_RAW_NAND)
|
||||
#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
|
||||
#endif
|
||||
|
||||
#define CONFIG_LOADS_ECHO /* echo on for serial download */
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#else
|
||||
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
|
||||
#endif
|
||||
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 64 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
|
||||
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USB_EHCI_HCD
|
||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
|
||||
#define CONFIG_USB_EHCI_FSL
|
||||
#define CONFIG_HAS_FSL_DR_USB
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Dynamic MTD Partition support with mtdparts
|
||||
*/
|
||||
|
||||
/*
|
||||
* Environment Configuration
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_TSEC_ENET)
|
||||
#define CONFIG_HAS_ETH0
|
||||
#endif
|
||||
|
||||
#define CONFIG_HOSTNAME "BSC9131rdb"
|
||||
#define CONFIG_ROOTPATH "/opt/nfsroot"
|
||||
#define CONFIG_BOOTFILE "uImage"
|
||||
#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"uboot=" CONFIG_UBOOTPATH "\0" \
|
||||
"loadaddr=1000000\0" \
|
||||
"bootfile=uImage\0" \
|
||||
"consoledev=ttyS0\0" \
|
||||
"ramdiskaddr=2000000\0" \
|
||||
"ramdiskfile=rootfs.ext2.gz.uboot\0" \
|
||||
"fdtaddr=1e00000\0" \
|
||||
"fdtfile=bsc9131rdb.dtb\0" \
|
||||
"bdev=sda1\0" \
|
||||
"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
|
||||
"bootm_size=0x37000000\0" \
|
||||
"othbootargs=ramdisk_size=600000 " \
|
||||
"default_hugepagesz=256m hugepagesz=256m hugepages=1\0" \
|
||||
"usbext2boot=setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs; " \
|
||||
"usb start;" \
|
||||
"ext2load usb 0:4 $loadaddr $bootfile;" \
|
||||
"ext2load usb 0:4 $fdtaddr $fdtfile;" \
|
||||
"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
|
||||
|
||||
#define CONFIG_RAMBOOTCOMMAND \
|
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs; " \
|
||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
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Reference in a new issue