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For 2020.10

Browse source 
-----------
 
 - fixes for Toradex board
 - fix warnings from previous PR
 - HAB: reset instead of panic after failure
 - new board:  MYiR Tech MYS-6ULX
 - mx6cuboxi: use OF_PLATDATA
 - further changes for DM
 
 Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/714513163
 -----BEGIN PGP SIGNATURE-----
 
 iG0EABECAC0WIQS2TmnA27QKhpKSZe309WXkmmjvpgUCXykjtQ8cc2JhYmljQGRl
 bnguZGUACgkQ9PVl5Jpo76a1WQCcD+objdS+90mDdT0yTpW3jHS4YiwAn2V2rTTo
 4hKj5yxRg3cvb/pBAmbQ
 =TyRs
 -----END PGP SIGNATURE-----

Merge tag 'u-boot-imx-20200804' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

For 2020.10
-----------

- fixes for Toradex board
- fix warnings from previous PR
- HAB: reset instead of panic after failure
- new board:  MYiR Tech MYS-6ULX
- mx6cuboxi: use OF_PLATDATA
- further changes for DM

Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/714513163
This commit is contained in:
Tom Rini 2020-08-04 11:11:02 -04:00
commit f1c0b7cd4b
52 changed files with 1718 additions and 249 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
arch/arm/Kconfig
View file

@ -1940,6 +1940,7 @@ source "board/hisilicon/hikey/Kconfig"
source "board/hisilicon/hikey960/Kconfig"
source "board/hisilicon/poplar/Kconfig"
source "board/isee/igep003x/Kconfig"
source "board/myir/mys_6ulx/Kconfig"
source "board/spear/spear300/Kconfig"
source "board/spear/spear310/Kconfig"
source "board/spear/spear320/Kconfig"

1
arch/arm/dts/Makefile
View file

@ -721,6 +721,7 @@ dtb-$(CONFIG_MX6UL) += \
dtb-$(CONFIG_MX6ULL) += \
imx6ull-14x14-evk.dtb \
imx6ull-colibri.dtb \
imx6ull-myir-mys-6ulx-eval.dtb \
imx6ull-phytec-segin-ff-rdk-emmc.dtb \
imx6ull-dart-6ul.dtb \
imx6ull-somlabs-visionsom.dtb \

45
arch/arm/dts/imx6ull-colibri-u-boot.dtsi
View file

@ -3,6 +3,15 @@
* Copyright 2019 Toradex AG
*/
/ {
aliases {
u-boot,dm-pre-reloc;
mmc0 = &usdhc1;
usb0 = &usbotg1; /* required for ums */
display0 = &lcdif;
};
};
&pinctrl_uart1 {
u-boot,dm-pre-reloc;
};
@ -10,3 +19,39 @@
&pinctrl_uart1_ctrl1 {
u-boot,dm-pre-reloc;
};
&lcdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif_dat
&pinctrl_lcdif_ctrl>;
status = "okay";
display = <&display0>;
u-boot,dm-pre-reloc;
display0: display0 {
bits-per-pixel = <18>;
bus-width = <24>;
status = "okay";
display-timings {
native-mode = <&timing_vga>;
timing_vga: 640x480 {
u-boot,dm-pre-reloc;
clock-frequency = <25175000>;
hactive = <640>;
vactive = <480>;
hback-porch = <40>;
hfront-porch = <24>;
vback-porch = <32>;
vfront-porch = <11>;
hsync-len = <96>;
vsync-len = <2>;
de-active = <1>;
hsync-active = <0>;
vsync-active = <0>;
pixelclk-active = <0>;
};
};
};
};

43
arch/arm/dts/imx6ull-colibri.dtsi
View file

@ -8,13 +8,6 @@
#include "imx6ull.dtsi"
/ {
aliases {
u-boot,dm-pre-reloc;
mmc0 = &usdhc1;
usb0 = &usbotg1; /* required for ums */
display0 = &lcdif;
};
chosen {
stdout-path = &uart1;
};
@ -151,42 +144,6 @@
};
};
&lcdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif_dat
&pinctrl_lcdif_ctrl>;
status = "okay";
display = <&display0>;
u-boot,dm-pre-reloc;
display0: display0 {
bits-per-pixel = <18>;
bus-width = <24>;
status = "okay";
display-timings {
native-mode = <&timing_vga>;
timing_vga: 640x480 {
u-boot,dm-pre-reloc;
clock-frequency = <25175000>;
hactive = <640>;
vactive = <480>;
hback-porch = <48>;
hfront-porch = <16>;
vback-porch = <33>;
vfront-porch = <10>;
hsync-len = <96>;
vsync-len = <2>;
de-active = <1>;
hsync-active = <0>;
vsync-active = <0>;
pixelclk-active = <0>;
};
};
};
};
/* PWM <A> */
&pwm4 {
pinctrl-names = "default";

19
arch/arm/dts/imx6ull-myir-mys-6ulx-eval.dts Normal file
View file

@ -0,0 +1,19 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2020 Linumiz
* Author: Parthiban Nallathambi <parthiban@linumiz.com>
*/
/dts-v1/;
#include "imx6ull.dtsi"
#include "imx6ull-myir-mys-6ulx.dtsi"
#include "imx6ull-mys-6ulx-u-boot.dtsi"
/ {
model = "MYiR i.MX6ULL MYS-6ULX Single Board Computer with NAND";
compatible = "myir,imx6ull-mys-6ulx-eval", "fsl,imx6ull";
};
&gpmi {
status = "okay";
};

238
arch/arm/dts/imx6ull-myir-mys-6ulx.dtsi Normal file
View file

@ -0,0 +1,238 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2020 Linumiz
* Author: Parthiban Nallathambi <parthiban@linumiz.com>
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pwm/pwm.h>
/ {
model = "MYiR MYS-6ULX Single Board Computer";
compatible = "fsl,imx6ull";
chosen {
stdout-path = &uart1;
};
reg_vdd_5v: regulator-vdd-5v {
compatible = "regulator-fixed";
regulator-name = "VDD_5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
};
reg_vdd_3v3: regulator-vdd-3v3 {
compatible = "regulator-fixed";
regulator-name = "VDD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
vin-supply = <&reg_vdd_5v>;
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
phy-mode = "rmii";
phy-handle = <&ethphy0>;
phy-supply = <&reg_vdd_3v3>;
status = "okay";
mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
reg = <0>;
interrupt-parent = <&gpio5>;
interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
clocks = <&clks IMX6UL_CLK_ENET_REF>;
clock-names = "rmii-ref";
};
};
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "disabled";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&usbotg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_otg1_id>;
dr_mode = "otg";
status = "okay";
};
&usbotg2 {
dr_mode = "host";
disable-over-current;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
no-1-8-v;
keep-power-in-suspend;
wakeup-source;
vmmc-supply = <&reg_vdd_3v3>;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
bus-width = <8>;
non-removable;
keep-power-in-suspend;
vmmc-supply = <&reg_vdd_3v3>;
};
&iomuxc {
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0
>;
};
pinctrl_gpmi_nand: gpminandgrp {
fsl,pins = <
MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1
MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1
MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1
MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000
MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1
MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1
MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1
MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1
MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1
MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1
MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1
MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1
MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1
MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1
MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
>;
};
pinctrl_usb_otg1_id: usbotg1idgrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
>;
};
};

24
arch/arm/dts/imx6ull-mys-6ulx-u-boot.dtsi Normal file
View file

@ -0,0 +1,24 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2020 Linumiz
* Author: Parthiban Nallathambi <parthiban@linumiz.com>
*/
&pinctrl_uart1 {
u-boot,dm-pre-reloc;
};
&gpmi {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
&usdhc1 {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};
&usdhc2 {
u-boot,dm-spl;
u-boot,dm-pre-reloc;
};

2
arch/arm/dts/imx7-colibri-emmc.dts
View file

@ -5,13 +5,13 @@
/dts-v1/;
#include "imx7-colibri.dtsi"
#include "imx7-colibri-u-boot.dtsi"
/ {
model = "Toradex Colibri iMX7D 1GB (eMMC)";
compatible = "toradex,imx7d-colibri-emmc", "fsl,imx7d";
aliases {
u-boot,dm-pre-reloc;
mmc0 = &usdhc3;
mmc1 = &usdhc1;
display1 = &lcdif;

10
arch/arm/dts/imx7-colibri-rawnand.dts
View file

@ -5,17 +5,19 @@
/dts-v1/;
#include "imx7-colibri.dtsi"
#include "imx7-colibri-u-boot.dtsi"
/ {
model = "Toradex Colibri iMX7S/D";
compatible = "toradex,imx7-colibri", "fsl,imx7";
chosen {
stdout-path = &uart1;
aliases {
display1 = &lcdif;
usb0 = &usbotg1; /* required for ums */
};
aliases {
usb0 = &usbotg1; /* required for ums */
chosen {
stdout-path = &uart1;
};
reg_5v0: regulator-5v0 {

39
arch/arm/dts/imx7-colibri-u-boot.dtsi Normal file
View file

@ -0,0 +1,39 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright 2020 Toradex
*/
&lcdif {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif_dat
&pinctrl_lcdif_ctrl>;
display = <&display0>;
u-boot,dm-pre-reloc;
display0: display0 {
bits-per-pixel = <18>;
bus-width = <18>;
status = "okay";
display-timings {
native-mode = <&timing_vga>;
timing_vga: 640x480 {
clock-frequency = <25175000>;
hactive = <640>;
vactive = <480>;
hback-porch = <40>;
hfront-porch = <24>;
vback-porch = <32>;
vfront-porch = <11>;
hsync-len = <96>;
vsync-len = <2>;
de-active = <1>;
hsync-active = <0>;
vsync-active = <0>;
pixelclk-active = <0>;
};
};
};
};

65
arch/arm/dts/imx7-colibri.dtsi
View file

@ -172,6 +172,38 @@
>;
};
pinctrl_lcdif_dat: lcdif-dat-grp {
fsl,pins = <
MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79
MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79
MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79
MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79
MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79
MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79
MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79
MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79
MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79
MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79
MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79
MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79
MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79
MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79
MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79
MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79
MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79
MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79
>;
};
pinctrl_lcdif_ctrl: lcdif-ctrl-grp {
fsl,pins = <
MX7D_PAD_LCD_CLK__LCD_CLK 0x79
MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79
MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79
MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79
>;
};
pinctrl_enet1: enet1grp {
fsl,pins = <
MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x14
@ -227,36 +259,3 @@
>;
};
};
&lcdif {
status = "okay";
display = <&display0>;
u-boot,dm-pre-reloc;
display0: display0 {
bits-per-pixel = <18>;
bus-width = <24>;
status = "okay";
display-timings {
native-mode = <&timing_vga>;
timing_vga: 640x480 {
u-boot,dm-pre-reloc;
clock-frequency = <25175000>;
hactive = <640>;
vactive = <480>;
hback-porch = <48>;
hfront-porch = <16>;
vback-porch = <33>;
vfront-porch = <10>;
hsync-len = <96>;
vsync-len = <2>;
de-active = <1>;
hsync-active = <0>;
vsync-active = <0>;
pixelclk-active = <0>;
};
};
};
};

22
arch/arm/dts/imx8mm-verdin.dts
View file

@ -16,6 +16,12 @@
stdout-path = &uart1;
};
aliases {
eeprom0 = &eeprom_module;
eeprom1 = &eeprom_carrier_board;
eeprom2 = &eeprom_display_adapter;
};
/* fixed clock dedicated to SPI CAN controller */
clk20m: oscillator {
compatible = "fixed-clock";
@ -321,8 +327,8 @@
vcc-supply = <&ldo5_reg>;
};
eeprom@50 {
compatible = "st,24c02";
eeprom_module: eeprom@50 {
compatible = "st,24c02", "atmel,24c02", "i2c-eeprom";
pagesize = <16>;
reg = <0x50>;
};
@ -377,16 +383,16 @@
status = "okay";
};
/* EEPROM on MIPI-DSI to HDMI adapter */
eeprom_50: eeprom@50 {
compatible = "st,24c02";
/* EEPROM on display adapter (MIPI DSI Display Adapter) */
eeprom_display_adapter: eeprom@50 {
compatible = "st,24c02", "atmel,24c02", "i2c-eeprom";
pagesize = <16>;
reg = <0x50>;
};
/* EEPROM on Verdin Development board */
eeprom_57: eeprom@57 {
compatible = "st,24c02";
/* EEPROM on carrier board */
eeprom_carrier_board: eeprom@57 {
compatible = "st,24c02", "atmel,24c02", "i2c-eeprom";
pagesize = <16>;
reg = <0x57>;
};

2
arch/arm/mach-imx/imx8m/soc.c
View file

@ -933,7 +933,7 @@ static void acquire_buildinfo(void)
/* Get ARM Trusted Firmware commit id */
arm_smccc_smc(IMX_SIP_BUILDINFO, IMX_SIP_BUILDINFO_GET_COMMITHASH,
0, 0 , 0, 0, 0, 0, &res);
0, 0, 0, 0, 0, 0, &res);
atf_commit = res.a0;
if (atf_commit == 0xffffffff) {
debug("ATF does not support build info\n");

12
arch/arm/mach-imx/mx6/Kconfig
View file

@ -460,6 +460,18 @@ config TARGET_MX6ULL_14X14_EVK
select MX6ULL
imply CMD_DM
config TARGET_MYS_6ULX
bool "MYiR MYS-6ULX"
select MX6ULL
select DM
select DM_ETH
select DM_GPIO
select DM_I2C
select DM_MMC
select DM_SERIAL
select DM_THERMAL
select SUPPORT_SPL
config TARGET_NITROGEN6X
bool "nitrogen6x"
imply USB_ETHER_ASIX

2
arch/arm/mach-imx/mx7/soc.c
View file

@ -218,7 +218,7 @@ const struct rproc_att hostmap[] = {
{ 0x00940000, 0x00940000, 0x20000 }, /* OCRAM_PXP */
{ 0x20240000, 0x00940000, 0x20000 }, /* OCRAM_PXP */
{ 0x10000000, 0x80000000, 0x0fff0000 }, /* DDR Code alias */
{ 0x80000000, 0x80000000, 0xe0000000 }, /* DDRC */
{ 0x80000000, 0x80000000, 0x60000000 }, /* DDRC */
{ /* sentinel */ }
};
#endif

6
arch/arm/mach-imx/spl.c
View file

@ -293,8 +293,7 @@ __weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
CSF_PAD_SIZE, offset)) {
image_entry();
} else {
puts("spl: ERROR: image authentication fail\n");
hang();
panic("spl: ERROR: image authentication fail\n");
}
}
}
@ -320,8 +319,7 @@ void board_spl_fit_post_load(ulong load_addr, size_t length)
if (imx_hab_authenticate_image(load_addr,
offset + IVT_SIZE + CSF_PAD_SIZE,
offset)) {
puts("spl: ERROR: image authentication unsuccessful\n");
hang();
panic("spl: ERROR: image authentication unsuccessful\n");
}
}
#endif

12
board/myir/mys_6ulx/Kconfig Normal file
View file

@ -0,0 +1,12 @@
if TARGET_MYS_6ULX
config SYS_BOARD
default "mys_6ulx"
config SYS_VENDOR
default "myir"
config SYS_CONFIG_NAME
default "mys_6ulx"
endif

9
board/myir/mys_6ulx/MAINTAINERS Normal file
View file

@ -0,0 +1,9 @@
MYS_6ULX BOARD
M: Parthiban Nallathambi <parthiban@linumiz.com>
S: Maintained
F: arch/arm/dts/imx6ull-myir-mys-6ulx-nand.dts
F: arch/arm/dts/imx6ull-myir-mys-6ulx.dtsi
F: arch/arm/dts/imx6ull-mys-6ulx-u-boot.dtsi
F: board/myir/mys_6ulx/
F: configs/myir_mys_6ulx_defconfig
F: include/configs/mys_6ulx.h

4
board/myir/mys_6ulx/Makefile Normal file
View file

@ -0,0 +1,4 @@
# SPDX-License-Identifier: GPL-2.0+
obj-y := mys_6ulx.o
obj-$(CONFIG_SPL_BUILD) += spl.o

52
board/myir/mys_6ulx/README Normal file
View file

@ -0,0 +1,52 @@
How to use U-Boot on MYiR MYS-6ULX Single Board Computer
--------------------------------------------------------
- Configure and build U-Boot for MYS-6ULX iMX6ULL:
$ make mrproper
$ make myir_mys_6ulx_defconfig
$ make
This will generate SPL and u-boot-dtb.img images.
Boot from MMC/SD:
- The SPL and u-boot-dtb.img images need to be flashed into the micro SD card:
$ sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1; sync
$ sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=69; sync
- Boot mode settings:
Boot switch position: SW1 -> 0
SW2 -> 1
SW3 -> 0
SW4 -> 1
Boot from NAND:
- Boot the board using SD/MMC or Serial download and load the SPL into memory
either from SD/MMC or TFTP.
Default MTD layout is 512k(spl),1m(uboot),1m(uboot-dup),-(ubi)
Flash SPL to NAND from SD/MMC,
$ ext4load mmc 0:2 $loadaddr SPL
$ nand erase.part spl
$ nandbcb init $loadaddr 0x0 $filesize
Flash u-boot proper to NAND from SD/MMC,
$ ext4load mmc 0:2 $loadaddr u-boot-dtb.img
$ nand erase.part uboot
$ nand write $loadaddr uboot $filesize
- Boot mode settings:
Boot switch position: SW1 -> 1
SW2 -> 0
SW3 -> 0
SW4 -> 1
- Connect the Serial cable to UART0 and the PC for the console.
- Reset the board using and U-Boot should boot from NAND.

117
board/myir/mys_6ulx/mys_6ulx.c Normal file
View file

@ -0,0 +1,117 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2020 Linumiz
* Author: Parthiban Nallathambi <parthiban@linumiz.com>
*/
#include <init.h>
#include <asm/arch/clock.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <fsl_esdhc_imx.h>
#include <linux/bitops.h>
#include <miiphy.h>
#include <netdev.h>
#include <usb.h>
#include <usb/ehci-ci.h>
DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
return 0;
}
#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | \
PAD_CTL_HYS)
static iomux_v3_cfg_t const uart1_pads[] = {
MX6_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static iomux_v3_cfg_t const uart5_pads[] = {
MX6_PAD_UART5_TX_DATA__UART5_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_UART5_RX_DATA__UART5_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_GPIO1_IO09__UART5_DCE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_GPIO1_IO08__UART5_DCE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
}
#ifdef CONFIG_FEC_MXC
static int setup_fec(void)
{
struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
int ret;
/*
* Use 50M anatop loopback REF_CLK1 for ENET1,
* clear gpr1[13], set gpr1[17].
*/
clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK);
ret = enable_fec_anatop_clock(0, ENET_50MHZ);
if (ret)
return ret;
enable_enet_clk(1);
return 0;
}
int board_phy_config(struct phy_device *phydev)
{
/*
* Defaults + Enable status LEDs (LED1: Activity, LED0: Link) & select
* 50 MHz RMII clock mode.
*/
phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
#endif /* CONFIG_FEC_MXC */
int board_early_init_f(void)
{
setup_iomux_uart();
return 0;
}
int board_init(void)
{
/* Address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
#ifdef CONFIG_FEC_MXC
setup_fec();
#endif
return 0;
}
int checkboard(void)
{
u32 cpurev = get_cpu_rev();
printf("Board: MYiR MYS-6ULX %s Single Board Computer\n",
get_imx_type((cpurev & 0xFF000) >> 12));
return 0;
}

206
board/myir/mys_6ulx/spl.c Normal file
View file

@ -0,0 +1,206 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2020 Linumiz
* Author: Parthiban Nallathambi <parthiban@linumiz.com>
*/
#include <common.h>
#include <init.h>
#include <spl.h>
#include <asm/arch/clock.h>
#include <asm/io.h>
#include <asm/arch/mx6-ddr.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/sys_proto.h>
#include <fsl_esdhc_imx.h>
/* Configuration for Micron MT41K128M16JT-125, 32M x 16 x 8 -> 256MiB */
static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
.grp_addds = 0x00000030,
.grp_ddrmode_ctl = 0x00020000,
.grp_b0ds = 0x00000030,
.grp_ctlds = 0x00000030,
.grp_b1ds = 0x00000030,
.grp_ddrpke = 0x00000000,
.grp_ddrmode = 0x00020000,
.grp_ddr_type = 0x000c0000,
};
static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
.dram_dqm0 = 0x00000030,
.dram_dqm1 = 0x00000030,
.dram_ras = 0x00000030,
.dram_cas = 0x00000030,
.dram_odt0 = 0x00000030,
.dram_odt1 = 0x00000030,
.dram_sdba2 = 0x00000000,
.dram_sdclk_0 = 0x00000030,
.dram_sdqs0 = 0x00000030,
.dram_sdqs1 = 0x00000030,
.dram_reset = 0x00000030,
};
static struct mx6_mmdc_calibration mx6_mmcd_calib = {
.p0_mpwldectrl0 = 0x00000000,
.p0_mpdgctrl0 = 0x41480148,
.p0_mprddlctl = 0x40403E42,
.p0_mpwrdlctl = 0x40405852,
};
struct mx6_ddr_sysinfo ddr_sysinfo = {
.dsize = 0, /* Bus size = 16bit */
.cs_density = 32,
.ncs = 1,
.cs1_mirror = 0,
.rtt_wr = 1,
.rtt_nom = 1,
.walat = 1, /* Write additional latency */
.ralat = 5, /* Read additional latency */
.mif3_mode = 3, /* Command prediction working mode */
.bi_on = 1, /* Bank interleaving enabled */
.pd_fast_exit = 1,
.sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
.ddr_type = DDR_TYPE_DDR3,
.refsel = 1, /* Refresh cycles at 32KHz */
.refr = 7, /* 8 refresh commands per refresh cycle */
};
/* MT41K128M16JT-125 (2Gb density) */
static struct mx6_ddr3_cfg mem_ddr = {
.mem_speed = 1600,
.density = 2,
.width = 16,
.banks = 8,
.rowaddr = 14,
.coladdr = 10,
.pagesz = 2,
.trcd = 1375,
.trcmin = 4875,
.trasmin = 3500,
};
static void ccgr_init(void)
{
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
writel(0xFFFFFFFF, &ccm->CCGR0);
writel(0xFFFFFFFF, &ccm->CCGR1);
writel(0xFFFFFFFF, &ccm->CCGR2);
writel(0xFFFFFFFF, &ccm->CCGR3);
writel(0xFFFFFFFF, &ccm->CCGR4);
writel(0xFFFFFFFF, &ccm->CCGR5);
writel(0xFFFFFFFF, &ccm->CCGR6);
}
static void spl_dram_init(void)
{
mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
}
#ifdef CONFIG_FSL_ESDHC_IMX
#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \
PAD_CTL_HYS)
static iomux_v3_cfg_t const usdhc1_pads[] = {
MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_UART1_RTS_B__USDHC1_CD_B | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
#ifndef CONFIG_NAND_MXS
static iomux_v3_cfg_t const usdhc2_pads[] = {
MX6_PAD_NAND_RE_B__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_WE_B__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_DATA00__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_DATA01__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_DATA02__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_DATA03__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_DATA04__USDHC2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_DATA05__USDHC2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_DATA06__USDHC2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_NAND_DATA07__USDHC2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
#endif
static struct fsl_esdhc_cfg usdhc_cfg[] = {
{
.esdhc_base = USDHC1_BASE_ADDR,
.max_bus_width = 4,
},
#ifndef CONFIG_NAND_MXS
{
.esdhc_base = USDHC2_BASE_ADDR,
.max_bus_width = 8,
},
#endif
};
int board_mmc_getcd(struct mmc *mmc)
{
return 1;
}
int board_mmc_init(struct bd_info *bis)
{
int i, ret;
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
SETUP_IOMUX_PADS(usdhc1_pads);
usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
break;
#ifndef CONFIG_NAND_MXS
case 1:
SETUP_IOMUX_PADS(usdhc2_pads);
usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
break;
#endif
default:
printf("Warning - USDHC%d controller not supporting\n",
i + 1);
return 0;
}
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
if (ret) {
printf("Warning: failed to initialize mmc dev %d\n", i);
return ret;
}
}
return 0;
}
#endif /* CONFIG_FSL_ESDHC_IMX */
void board_init_f(ulong dummy)
{
ccgr_init();
/* Setup AIPS and disable watchdog */
arch_cpu_init();
/* Setup iomux and fec */
board_early_init_f();
/* Setup GP timer */
timer_init();
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
/* DDR initialization */
spl_dram_init();
}

20
board/phytec/pcm058/README
View file

@ -61,17 +61,21 @@ Then, clear the SPI flash:
=> sf probe
=> sf erase 0x0 0x1000000
Load the SPL from raw MMC into memory and copy to the SPI. The SPL is maximum
392*512-byte blocks in size therefore 0x188 blocks, totaling 0x31000 bytes:
Load the equivalent of u-boot-with-spl.imx from the raw MMC into memory and
copy to the SPI. The SPL is expected at an offset of 0x400, and its size is
maximum 392*512-byte blocks in size, therefore 0x188 blocks, totaling 0x31000
bytes. Assume U-boot should fit into 640KiB, therefore 0x500 512-byte blocks,
totalling 0xA0000 bytes. Adding these together:
=> mmc read ${loadaddr} 0x2 0x188
=> sf write ${loadaddr} 0x400 0x31000
=> mmc read ${loadaddr} 0x2 0x688
=> sf write ${loadaddr} 0x400 0xD1000
Load the U-boot binary into memory and copy to the SPI. U-boot should fit into
640KiB, so 0x500 512-byte blocks, totalling 0xA0000 bytes:
The SPL is located at offset 0x400, and U-boot at 0x31400 in SPI flash, as to
match the SD Card layout. This would allow, instead of reading from the SD Card
above, with networking and TFTP correctly configured, the equivalent of:
=> mmc read ${loadaddr} 0x18a 0x500
=> sf write ${loadaddr} 0x40000 0xA0000
=> tftp u-boot-with-spl.imx
=> sf write ${fileaddr} 0x400 ${filesize}
The default NAND bootscripts expect a single MTD partition named "rootfs",
which in turn contains the UBI volumes "fit" (which contains the kernel fit-

40
board/toradex/colibri-imx6ull/colibri-imx6ull.c
View file

@ -57,32 +57,7 @@ static void setup_gpmi_nand(void)
}
#endif /* CONFIG_NAND_MXS */
#ifdef CONFIG_VIDEO_MXS
static iomux_v3_cfg_t const lcd_pads[] = {
MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
};
#ifdef CONFIG_DM_VIDEO
static iomux_v3_cfg_t const backlight_pads[] = {
/* Backlight On */
MX6_PAD_JTAG_TMS__GPIO1_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
@ -95,8 +70,6 @@ static iomux_v3_cfg_t const backlight_pads[] = {
static int setup_lcd(void)
{
imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads));
/* Set BL_ON */
@ -153,11 +126,6 @@ int board_init(void)
#ifdef CONFIG_NAND_MXS
setup_gpmi_nand();
#endif
#ifdef CONFIG_VIDEO_MXS
setup_lcd();
#endif
return 0;
}
@ -203,6 +171,12 @@ int board_late_init(void)
}
#endif /* CONFIG_CMD_USB_SDP */
#if defined(CONFIG_DM_VIDEO)
setup_lcd();
show_boot_logo();
#endif
return 0;
}

1
board/toradex/colibri_imx7/MAINTAINERS
View file

@ -9,5 +9,6 @@ F: include/configs/colibri_imx7.h
F: configs/colibri_imx7_defconfig
F: configs/colibri_imx7_emmc_defconfig
F: arch/arm/dts/imx7-colibri.dtsi
F: arch/arm/dts/imx7-colibri-u-boot.dtsi
F: arch/arm/dts/imx7-colibri-emmc.dts
F: arch/arm/dts/imx7-colibri-rawnand.dts

44
board/toradex/colibri_imx7/colibri_imx7.c
View file

@ -100,32 +100,7 @@ static void setup_gpmi_nand(void)
}
#endif
#ifdef CONFIG_VIDEO_MXS
static iomux_v3_cfg_t const lcd_pads[] = {
MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
};
#ifdef CONFIG_DM_VIDEO
static iomux_v3_cfg_t const backlight_pads[] = {
/* Backlight On */
MX7D_PAD_SD1_WP__GPIO5_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL),
@ -139,8 +114,6 @@ static iomux_v3_cfg_t const backlight_pads[] = {
static int setup_lcd(void)
{
imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads));
/* Set BL_ON */
@ -215,10 +188,6 @@ int board_init(void)
setup_gpmi_nand();
#endif
#ifdef CONFIG_VIDEO_MXS
setup_lcd();
#endif
#ifdef CONFIG_USB_EHCI_MX7
imx_iomux_v3_setup_multiple_pads(usb_cdet_pads, ARRAY_SIZE(usb_cdet_pads));
gpio_request(USB_CDET_GPIO, "usb-cdet-gpio");
@ -382,4 +351,15 @@ int board_usb_phy_mode(int port)
return USB_INIT_HOST;
}
}
int board_late_init(void)
{
#if defined(CONFIG_DM_VIDEO)
setup_lcd();
show_boot_logo();
#endif
return 0;
}
#endif

18
board/toradex/common/Kconfig
View file

@ -20,6 +20,12 @@ config TDX_HAVE_NAND
config TDX_HAVE_NOR
bool
config TDX_HAVE_EEPROM
bool
config TDX_HAVE_EEPROM_EXTRA
bool
if TDX_CFG_BLOCK
config TDX_CFG_BLOCK_IS_IN_MMC
@ -37,6 +43,11 @@ config TDX_CFG_BLOCK_IS_IN_NOR
depends on TDX_HAVE_NOR
default y
config TDX_CFG_BLOCK_IS_IN_EEPROM
bool
depends on TDX_HAVE_EEPROM
default y
config TDX_CFG_BLOCK_DEV
int "Toradex config block eMMC device ID"
depends on TDX_CFG_BLOCK_IS_IN_MMC
@ -66,4 +77,11 @@ config TDX_CFG_BLOCK_2ND_ETHADDR
Ethernet carrier boards. This options enables the code to set the
second Ethernet address as environment variable (eth1addr).
config TDX_CFG_BLOCK_EXTRA
bool "Support for additional EEPROMs (carrier board, display adapter)"
depends on TDX_HAVE_EEPROM_EXTRA
help
Enables fetching auxilary config blocks from carrier board/display
adapter EEPROMs.
endif

1
board/toradex/common/Makefile
View file

@ -8,4 +8,5 @@ obj- := __dummy__.o
else
obj-$(CONFIG_TDX_CFG_BLOCK) += tdx-cfg-block.o
obj-y += tdx-common.o
obj-y += tdx-eeprom.o
endif

406
board/toradex/common/tdx-cfg-block.c
View file

@ -5,6 +5,8 @@
#include <common.h>
#include "tdx-cfg-block.h"
#include "tdx-eeprom.h"
#include <command.h>
#include <asm/cache.h>
@ -37,21 +39,31 @@ DECLARE_GLOBAL_DATA_PTR;
#define TAG_VALID 0xcf01
#define TAG_MAC 0x0000
#define TAG_CAR_SERIAL 0x0021
#define TAG_HW 0x0008
#define TAG_INVALID 0xffff
#define TAG_FLAG_VALID 0x1
#define TDX_EEPROM_ID_MODULE 0
#define TDX_EEPROM_ID_CARRIER 1
#if defined(CONFIG_TDX_CFG_BLOCK_IS_IN_MMC)
#define TDX_CFG_BLOCK_MAX_SIZE 512
#elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NAND)
#define TDX_CFG_BLOCK_MAX_SIZE 64
#elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NOR)
#define TDX_CFG_BLOCK_MAX_SIZE 64
#elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_EEPROM)
#define TDX_CFG_BLOCK_MAX_SIZE 64
#else
#error Toradex config block location not set
#endif
#ifdef CONFIG_TDX_CFG_BLOCK_EXTRA
#define TDX_CFG_BLOCK_EXTRA_MAX_SIZE 64
#endif
struct toradex_tag {
u32 len:14;
u32 flags:2;
@ -62,6 +74,11 @@ bool valid_cfgblock;
struct toradex_hw tdx_hw_tag;
struct toradex_eth_addr tdx_eth_addr;
u32 tdx_serial;
#ifdef CONFIG_TDX_CFG_BLOCK_EXTRA
u32 tdx_car_serial;
bool valid_cfgblock_carrier;
struct toradex_hw tdx_car_hw_tag;
#endif
const char * const toradex_modules[] = {
[0] = "UNKNOWN MODULE",
@ -124,6 +141,18 @@ const char * const toradex_modules[] = {
[57] = "Verdin iMX8M Mini DualLite 1GB",
};
const char * const toradex_carrier_boards[] = {
[0] = "UNKNOWN CARRIER BOARD",
[155] = "Dahlia",
[156] = "Verdin Development Board",
};
const char * const toradex_display_adapters[] = {
[0] = "UNKNOWN DISPLAY ADAPTER",
[157] = "Verdin DSI to HDMI Adapter",
[159] = "Verdin DSI to LVDS Adapter",
};
#ifdef CONFIG_TDX_CFG_BLOCK_IS_IN_MMC
static int tdx_cfg_block_mmc_storage(u8 *config_block, int write)
{
@ -224,6 +253,20 @@ static int write_tdx_cfg_block_to_nor(unsigned char *config_block)
}
#endif
#ifdef CONFIG_TDX_CFG_BLOCK_IS_IN_EEPROM
static int read_tdx_cfg_block_from_eeprom(unsigned char *config_block)
{
return read_tdx_eeprom_data(TDX_EEPROM_ID_MODULE, 0x0, config_block,
TDX_CFG_BLOCK_MAX_SIZE);
}
static int write_tdx_cfg_block_to_eeprom(unsigned char *config_block)
{
return write_tdx_eeprom_data(TDX_EEPROM_ID_MODULE, 0x0, config_block,
TDX_CFG_BLOCK_MAX_SIZE);
}
#endif
int read_tdx_cfg_block(void)
{
int ret = 0;
@ -247,6 +290,8 @@ int read_tdx_cfg_block(void)
ret = read_tdx_cfg_block_from_nand(config_block);
#elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NOR)
ret = read_tdx_cfg_block_from_nor(config_block);
#elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_EEPROM)
ret = read_tdx_cfg_block_from_eeprom(config_block);
#else
ret = -EINVAL;
#endif
@ -263,7 +308,12 @@ int read_tdx_cfg_block(void)
valid_cfgblock = true;
offset = 4;
while (offset < TDX_CFG_BLOCK_MAX_SIZE) {
/*
* check if there is enough space for storing tag and value of the
* biggest element
*/
while (offset + sizeof(struct toradex_tag) +
sizeof(struct toradex_hw) < TDX_CFG_BLOCK_MAX_SIZE) {
tag = (struct toradex_tag *)(config_block + offset);
offset += 4;
if (tag->id == TAG_INVALID)
@ -322,7 +372,6 @@ static int get_cfgblock_interactive(void)
it = 'y';
#endif
#if defined(CONFIG_TARGET_APALIS_IMX8) || \
defined(CONFIG_TARGET_APALIS_IMX8X) || \
defined(CONFIG_TARGET_COLIBRI_IMX6ULL) || \
@ -493,7 +542,8 @@ static int get_cfgblock_interactive(void)
return 0;
}
static int get_cfgblock_barcode(char *barcode)
static int get_cfgblock_barcode(char *barcode, struct toradex_hw *tag,
u32 *serial)
{
if (strlen(barcode) < 16) {
printf("Argument too short, barcode is 16 chars long\n");
@ -501,30 +551,137 @@ static int get_cfgblock_barcode(char *barcode)
}
/* Get hardware information from the first 8 digits */
tdx_hw_tag.ver_major = barcode[4] - '0';
tdx_hw_tag.ver_minor = barcode[5] - '0';
tdx_hw_tag.ver_assembly = barcode[7] - '0';
tag->ver_major = barcode[4] - '0';
tag->ver_minor = barcode[5] - '0';
tag->ver_assembly = barcode[7] - '0';
barcode[4] = '\0';
tdx_hw_tag.prodid = simple_strtoul(barcode, NULL, 10);
tag->prodid = simple_strtoul(barcode, NULL, 10);
/* Parse second part of the barcode (serial number */
barcode += 8;
tdx_serial = simple_strtoul(barcode, NULL, 10);
*serial = simple_strtoul(barcode, NULL, 10);
return 0;
}
static int do_cfgblock_create(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
static int write_tag(u8 *config_block, int *offset, int tag_id,
u8 *tag_data, size_t tag_data_size)
{
u8 *config_block;
struct toradex_tag *tag;
size_t size = TDX_CFG_BLOCK_MAX_SIZE;
if (!offset || !config_block)
return -EINVAL;
tag = (struct toradex_tag *)(config_block + *offset);
tag->id = tag_id;
tag->flags = TAG_FLAG_VALID;
/* len is provided as number of 32bit values after the tag */
tag->len = (tag_data_size + sizeof(u32) - 1) / sizeof(u32);
*offset += sizeof(struct toradex_tag);
if (tag_data && tag_data_size) {
memcpy(config_block + *offset, tag_data,
tag_data_size);
*offset += tag_data_size;
}
return 0;
}
#ifdef CONFIG_TDX_CFG_BLOCK_EXTRA
int read_tdx_cfg_block_carrier(void)
{
int ret = 0;
u8 *config_block = NULL;
struct toradex_tag *tag;
size_t size = TDX_CFG_BLOCK_EXTRA_MAX_SIZE;
int offset;
/* Allocate RAM area for carrier config block */
config_block = memalign(ARCH_DMA_MINALIGN, size);
if (!config_block) {
printf("Not enough malloc space available!\n");
return -ENOMEM;
}
memset(config_block, 0, size);
ret = read_tdx_eeprom_data(TDX_EEPROM_ID_CARRIER, 0x0, config_block,
size);
if (ret)
return ret;
/* Expect a valid tag first */
tag = (struct toradex_tag *)config_block;
if (tag->flags != TAG_FLAG_VALID || tag->id != TAG_VALID) {
valid_cfgblock_carrier = false;
ret = -EINVAL;
goto out;
}
valid_cfgblock_carrier = true;
offset = 4;
while (offset + sizeof(struct toradex_tag) +
sizeof(struct toradex_hw) < TDX_CFG_BLOCK_MAX_SIZE) {
tag = (struct toradex_tag *)(config_block + offset);
offset += 4;
if (tag->id == TAG_INVALID)
break;
if (tag->flags == TAG_FLAG_VALID) {
switch (tag->id) {
case TAG_CAR_SERIAL:
memcpy(&tdx_car_serial, config_block + offset,
sizeof(tdx_car_serial));
break;
case TAG_HW:
memcpy(&tdx_car_hw_tag, config_block +
offset, 8);
break;
}
}
/* Get to next tag according to current tags length */
offset += tag->len * 4;
}
out:
free(config_block);
return ret;
}
int check_pid8_sanity(char *pid8)
{
char s_carrierid_verdin_dev[5];
char s_carrierid_dahlia[5];
sprintf(s_carrierid_verdin_dev, "0%d", VERDIN_DEVELOPMENT_BOARD);
sprintf(s_carrierid_dahlia, "0%d", DAHLIA);
/* sane value check, first 4 chars which represent carrier id */
if (!strncmp(pid8, s_carrierid_verdin_dev, 4))
return 0;
if (!strncmp(pid8, s_carrierid_dahlia, 4))
return 0;
return -EINVAL;
}
int try_migrate_tdx_cfg_block_carrier(void)
{
char pid8[8];
int offset = 0;
int ret = CMD_RET_SUCCESS;
int err;
int force_overwrite = 0;
size_t size = TDX_CFG_BLOCK_EXTRA_MAX_SIZE;
u8 *config_block;
memset(pid8, 0x0, 8);
ret = read_tdx_eeprom_data(TDX_EEPROM_ID_CARRIER, 0x0, (u8 *)pid8, 8);
if (ret)
return ret;
if (check_pid8_sanity(pid8))
return -EINVAL;
/* Allocate RAM area for config block */
config_block = memalign(ARCH_DMA_MINALIGN, size);
@ -534,12 +691,189 @@ static int do_cfgblock_create(struct cmd_tbl *cmdtp, int flag, int argc,
}
memset(config_block, 0xff, size);
/* we try parse PID8 concatenating zeroed serial number */
tdx_car_hw_tag.ver_major = pid8[4] - '0';
tdx_car_hw_tag.ver_minor = pid8[5] - '0';
tdx_car_hw_tag.ver_assembly = pid8[7] - '0';
pid8[4] = '\0';
tdx_car_hw_tag.prodid = simple_strtoul(pid8, NULL, 10);
/* Valid Tag */
write_tag(config_block, &offset, TAG_VALID, NULL, 0);
/* Product Tag */
write_tag(config_block, &offset, TAG_HW, (u8 *)&tdx_car_hw_tag,
sizeof(tdx_car_hw_tag));
/* Serial Tag */
write_tag(config_block, &offset, TAG_CAR_SERIAL, (u8 *)&tdx_car_serial,
sizeof(tdx_car_serial));
memset(config_block + offset, 0, 32 - offset);
ret = write_tdx_eeprom_data(TDX_EEPROM_ID_CARRIER, 0x0, config_block,
size);
if (ret) {
printf("Failed to write Toradex Extra config block: %d\n",
ret);
ret = CMD_RET_FAILURE;
goto out;
}
printf("Successfully migrated to Toradex Config Block from PID8\n");
out:
free(config_block);
return ret;
}
static int get_cfgblock_carrier_interactive(void)
{
char message[CONFIG_SYS_CBSIZE];
int len;
printf("Supported carrier boards:\n");
printf("CARRIER BOARD NAME\t\t [ID]\n");
for (int i = 0; i < sizeof(toradex_carrier_boards) /
sizeof(toradex_carrier_boards[0]); i++)
if (toradex_carrier_boards[i])
printf("%s \t\t [%d]\n", toradex_carrier_boards[i], i);
sprintf(message, "Choose your carrier board (provide ID): ");
len = cli_readline(message);
tdx_car_hw_tag.prodid = simple_strtoul(console_buffer, NULL, 10);
do {
sprintf(message, "Enter carrier board version (e.g. V1.1B): V");
len = cli_readline(message);
} while (len < 4);
tdx_car_hw_tag.ver_major = console_buffer[0] - '0';
tdx_car_hw_tag.ver_minor = console_buffer[2] - '0';
tdx_car_hw_tag.ver_assembly = console_buffer[3] - 'A';
while (len < 8) {
sprintf(message, "Enter carrier board serial number: ");
len = cli_readline(message);
}
tdx_car_serial = simple_strtoul(console_buffer, NULL, 10);
return 0;
}
static int do_cfgblock_carrier_create(struct cmd_tbl *cmdtp, int flag, int argc,
char * const argv[])
{
u8 *config_block;
size_t size = TDX_CFG_BLOCK_EXTRA_MAX_SIZE;
int offset = 0;
int ret = CMD_RET_SUCCESS;
int err;
int force_overwrite = 0;
if (argc >= 3) {
if (argv[2][0] == '-' && argv[2][1] == 'y')
force_overwrite = 1;
}
/* Allocate RAM area for config block */
config_block = memalign(ARCH_DMA_MINALIGN, size);
if (!config_block) {
printf("Not enough malloc space available!\n");
return CMD_RET_FAILURE;
}
memset(config_block, 0xff, size);
read_tdx_cfg_block_carrier();
if (valid_cfgblock_carrier && !force_overwrite) {
char message[CONFIG_SYS_CBSIZE];
sprintf(message, "A valid Toradex Carrier config block is present, still recreate? [y/N] ");
if (!cli_readline(message))
goto out;
if (console_buffer[0] != 'y' &&
console_buffer[0] != 'Y')
goto out;
}
if (argc < 3 || (force_overwrite && argc < 4)) {
err = get_cfgblock_carrier_interactive();
} else {
if (force_overwrite)
err = get_cfgblock_barcode(argv[3], &tdx_car_hw_tag,
&tdx_car_serial);
else
err = get_cfgblock_barcode(argv[2], &tdx_car_hw_tag,
&tdx_car_serial);
}
if (err) {
ret = CMD_RET_FAILURE;
goto out;
}
/* Valid Tag */
write_tag(config_block, &offset, TAG_VALID, NULL, 0);
/* Product Tag */
write_tag(config_block, &offset, TAG_HW, (u8 *)&tdx_car_hw_tag,
sizeof(tdx_car_hw_tag));
/* Serial Tag */
write_tag(config_block, &offset, TAG_CAR_SERIAL, (u8 *)&tdx_car_serial,
sizeof(tdx_car_serial));
memset(config_block + offset, 0, 32 - offset);
err = write_tdx_eeprom_data(TDX_EEPROM_ID_CARRIER, 0x0, config_block,
size);
if (err) {
printf("Failed to write Toradex Extra config block: %d\n",
ret);
ret = CMD_RET_FAILURE;
goto out;
}
printf("Toradex Extra config block successfully written\n");
out:
free(config_block);
return ret;
}
#endif /* CONFIG_TDX_CFG_BLOCK_EXTRA */
static int do_cfgblock_create(struct cmd_tbl *cmdtp, int flag, int argc,
char * const argv[])
{
u8 *config_block;
size_t size = TDX_CFG_BLOCK_MAX_SIZE;
int offset = 0;
int ret = CMD_RET_SUCCESS;
int err;
int force_overwrite = 0;
if (argc >= 3) {
#ifdef CONFIG_TDX_CFG_BLOCK_EXTRA
if (!strcmp(argv[2], "carrier"))
return do_cfgblock_carrier_create(cmdtp, flag,
--argc, ++argv);
#endif /* CONFIG_TDX_CFG_BLOCK_EXTRA */
if (argv[2][0] == '-' && argv[2][1] == 'y')
force_overwrite = 1;
}
/* Allocate RAM area for config block */
config_block = memalign(ARCH_DMA_MINALIGN, size);
if (!config_block) {
printf("Not enough malloc space available!\n");
return CMD_RET_FAILURE;
}
memset(config_block, 0xff, size);
read_tdx_cfg_block();
if (valid_cfgblock) {
#if defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NAND)
@ -581,9 +915,11 @@ static int do_cfgblock_create(struct cmd_tbl *cmdtp, int flag, int argc,
err = get_cfgblock_interactive();
} else {
if (force_overwrite)
err = get_cfgblock_barcode(argv[3]);
err = get_cfgblock_barcode(argv[3], &tdx_hw_tag,
&tdx_serial);
else
err = get_cfgblock_barcode(argv[2]);
err = get_cfgblock_barcode(argv[2], &tdx_hw_tag,
&tdx_serial);
}
if (err) {
ret = CMD_RET_FAILURE;
@ -595,39 +931,25 @@ static int do_cfgblock_create(struct cmd_tbl *cmdtp, int flag, int argc,
tdx_eth_addr.nic = htonl(tdx_serial << 8);
/* Valid Tag */
tag = (struct toradex_tag *)config_block;
tag->id = TAG_VALID;
tag->flags = TAG_FLAG_VALID;
tag->len = 0;
offset += 4;
write_tag(config_block, &offset, TAG_VALID, NULL, 0);
/* Product Tag */
tag = (struct toradex_tag *)(config_block + offset);
tag->id = TAG_HW;
tag->flags = TAG_FLAG_VALID;
tag->len = 2;
offset += 4;
memcpy(config_block + offset, &tdx_hw_tag, 8);
offset += 8;
write_tag(config_block, &offset, TAG_HW, (u8 *)&tdx_hw_tag,
sizeof(tdx_hw_tag));
/* MAC Tag */
tag = (struct toradex_tag *)(config_block + offset);
tag->id = TAG_MAC;
tag->flags = TAG_FLAG_VALID;
tag->len = 2;
offset += 4;
write_tag(config_block, &offset, TAG_MAC, (u8 *)&tdx_eth_addr,
sizeof(tdx_eth_addr));
memcpy(config_block + offset, &tdx_eth_addr, 6);
offset += 6;
memset(config_block + offset, 0, 32 - offset);
#if defined(CONFIG_TDX_CFG_BLOCK_IS_IN_MMC)
err = tdx_cfg_block_mmc_storage(config_block, 1);
#elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NAND)
err = write_tdx_cfg_block_to_nand(config_block);
#elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_NOR)
err = write_tdx_cfg_block_to_nor(config_block);
#elif defined(CONFIG_TDX_CFG_BLOCK_IS_IN_EEPROM)
err = write_tdx_cfg_block_to_eeprom(config_block);
#else
err = -EINVAL;
#endif
@ -667,8 +989,10 @@ static int do_cfgblock(struct cmd_tbl *cmdtp, int flag, int argc,
return CMD_RET_USAGE;
}
U_BOOT_CMD(cfgblock, 4, 0, do_cfgblock,
"Toradex config block handling commands",
"create [-y] [barcode] - (Re-)create Toradex config block\n"
"cfgblock reload - Reload Toradex config block from flash"
U_BOOT_CMD(
cfgblock, 5, 0, do_cfgblock,
"Toradex config block handling commands",
"create [-y] [barcode] - (Re-)create Toradex config block\n"
"create carrier [-y] [barcode] - (Re-)create Toradex Carrier config block\n"
"cfgblock reload - Reload Toradex config block from flash"
);

16
board/toradex/common/tdx-cfg-block.h
View file

@ -80,12 +80,28 @@ enum {
VERDIN_IMX8MMDL,
};
enum {
DAHLIA = 155,
VERDIN_DEVELOPMENT_BOARD = 156,
};
enum {
VERDIN_DSI_TO_HDMI_ADAPTER = 157,
VERDIN_DSI_TO_LVDS_ADAPTER = 159,
};
extern const char * const toradex_modules[];
extern const char * const toradex_carrier_boards[];
extern bool valid_cfgblock;
extern struct toradex_hw tdx_hw_tag;
extern struct toradex_hw tdx_car_hw_tag;
extern struct toradex_eth_addr tdx_eth_addr;
extern u32 tdx_serial;
extern u32 tdx_car_serial;
int read_tdx_cfg_block(void);
int read_tdx_cfg_block_carrier(void);
int try_migrate_tdx_cfg_block_carrier(void);
#endif /* _TDX_CFG_BLOCK_H */

54
board/toradex/common/tdx-common.c
View file

@ -9,6 +9,13 @@
#include <init.h>
#include <linux/libfdt.h>
#ifdef CONFIG_DM_VIDEO
#include <bmp_logo.h>
#include <dm.h>
#include <splash.h>
#include <video.h>
#endif
#include "tdx-cfg-block.h"
#include <asm/setup.h>
#include "tdx-common.h"
@ -19,6 +26,12 @@
static char tdx_serial_str[9];
static char tdx_board_rev_str[6];
#ifdef CONFIG_TDX_CFG_BLOCK_EXTRA
static char tdx_car_serial_str[9];
static char tdx_car_rev_str[6];
static char *tdx_carrier_board_name;
#endif
#ifdef CONFIG_REVISION_TAG
u32 get_board_rev(void)
{
@ -88,6 +101,28 @@ int show_board_info(void)
toradex_modules[tdx_hw_tag.prodid],
tdx_board_rev_str,
tdx_serial_str);
#ifdef CONFIG_TDX_CFG_BLOCK_EXTRA
if (read_tdx_cfg_block_carrier()) {
printf("MISSING TORADEX CARRIER CONFIG BLOCKS\n");
try_migrate_tdx_cfg_block_carrier();
} else {
tdx_carrier_board_name = (char *)
toradex_carrier_boards[tdx_car_hw_tag.prodid];
sprintf(tdx_car_serial_str, "%08u", tdx_car_serial);
sprintf(tdx_car_rev_str, "V%1d.%1d%c",
tdx_car_hw_tag.ver_major,
tdx_car_hw_tag.ver_minor,
(char)tdx_car_hw_tag.ver_assembly +
'A');
env_set("carrier_serial#", tdx_car_serial_str);
printf("Carrier: Toradex %s %s, Serial# %s\n",
tdx_carrier_board_name,
tdx_car_rev_str,
tdx_car_serial_str);
}
#endif
}
/*
@ -168,3 +203,22 @@ int ft_common_board_setup(void *blob, struct bd_info *bd)
}
#endif /* CONFIG_TDX_CFG_BLOCK */
#if defined(CONFIG_DM_VIDEO)
int show_boot_logo(void)
{
struct udevice *dev;
int ret;
int xpos, ypos;
splash_get_pos(&xpos, &ypos);
ret = uclass_get_device(UCLASS_VIDEO, 0, &dev);
if (ret)
return ret;
ret = video_bmp_display(dev, (ulong)bmp_logo_bitmap, xpos, ypos, true);
return ret;
}
#endif /* CONFIG_DM_VIDEO */

4
board/toradex/common/tdx-common.h
View file

@ -11,4 +11,8 @@
int ft_common_board_setup(void *blob, struct bd_info *bd);
#if defined(CONFIG_DM_VIDEO)
int show_boot_logo(void);
#endif
#endif /* _TDX_COMMON_H */

90
board/toradex/common/tdx-eeprom.c Normal file
View file

@ -0,0 +1,90 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (c) 2020 Toradex
*/
#include <dm.h>
#include <i2c_eeprom.h>
#include <linux/errno.h>
DECLARE_GLOBAL_DATA_PTR;
static int get_tdx_eeprom(u32 eeprom_id, struct udevice **devp)
{
int ret = 0;
int node;
ofnode eeprom;
char eeprom_str[16];
const char *path;
if (!gd->fdt_blob) {
printf("%s: don't have a valid gd->fdt_blob!\n", __func__);
return -EFAULT;
}
node = fdt_path_offset(gd->fdt_blob, "/aliases");
if (node < 0)
return -ENODEV;
sprintf(eeprom_str, "eeprom%d", eeprom_id);
path = fdt_getprop(gd->fdt_blob, node, eeprom_str, NULL);
if (!path) {
printf("%s: no alias for %s\n", __func__, eeprom_str);
return -ENODEV;
}
eeprom = ofnode_path(path);
if (!ofnode_valid(eeprom)) {
printf("%s: invalid hardware path to EEPROM\n", __func__);
return -ENODEV;
}
ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, eeprom, devp);
if (ret) {
printf("%s: cannot find EEPROM by node\n", __func__);
return ret;
}
return ret;
}
int read_tdx_eeprom_data(u32 eeprom_id, int offset, u8 *buf,
int size)
{
struct udevice *dev;
int ret;
ret = get_tdx_eeprom(eeprom_id, &dev);
if (ret)
return ret;
ret = i2c_eeprom_read(dev, 0x0, buf, size);
if (ret) {
printf("%s: error reading data from EEPROM id: %d!, ret = %d\n",
__func__, eeprom_id, ret);
return ret;
}
return ret;
}
int write_tdx_eeprom_data(u32 eeprom_id, int offset, u8 *buf,
int size)
{
struct udevice *dev;
int ret;
ret = get_tdx_eeprom(eeprom_id, &dev);
if (ret)
return ret;
ret = i2c_eeprom_write(dev, 0x0, buf, size);
if (ret) {
printf("%s: error writing data to EEPROM id: %d, ret = %d\n",
__func__, eeprom_id, ret);
return ret;
}
return ret;
}

14
board/toradex/common/tdx-eeprom.h Normal file
View file

@ -0,0 +1,14 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (c) 2020 Toradex
*/
#ifndef _TDX_EEPROM_H
#define _TDX_EEPROM_H
#include <i2c_eeprom.h>
int read_tdx_eeprom_data(u32 eeprom_id, int offset, uint8_t *buf, int size);
int write_tdx_eeprom_data(u32 eeprom_id, int offset, uint8_t *buf, int size);
#endif /* _TDX_EEPROM_H */

6
board/toradex/verdin-imx8mm/Kconfig
View file

@ -12,9 +12,15 @@ config SYS_CONFIG_NAME
config TDX_CFG_BLOCK
default y
config TDX_CFG_BLOCK_EXTRA
default y
config TDX_HAVE_MMC
default y
config TDX_HAVE_EEPROM_EXTRA
default y
config TDX_CFG_BLOCK_DEV
default "0"

1
configs/colibri-imx6ull_defconfig
View file

@ -92,3 +92,4 @@ CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_DM_VIDEO=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_FDT_FIXUP_PARTITIONS=y
CONFIG_SYS_WHITE_ON_BLACK=y

2
configs/colibri_imx7_defconfig
View file

@ -91,3 +91,5 @@ CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_DM_VIDEO=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_FDT_FIXUP_PARTITIONS=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SYS_WHITE_ON_BLACK=y

2
configs/colibri_imx7_emmc_defconfig
View file

@ -85,3 +85,5 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0x4000
CONFIG_CI_UDC=y
CONFIG_DM_VIDEO=y
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SYS_WHITE_ON_BLACK=y

1
configs/mx6cuboxi_defconfig
View file

@ -43,6 +43,7 @@ CONFIG_SPL_OF_CONTROL=y
CONFIG_OF_LIST="imx6dl-hummingboard2-emmc-som-v15 imx6q-hummingboard2-emmc-som-v15"
CONFIG_MULTI_DTB_FIT=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SPL_OF_PLATDATA=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y

69
configs/myir_mys_6ulx_defconfig Normal file
View file

@ -0,0 +1,69 @@
CONFIG_ARM=y
CONFIG_ARCH_MX6=y
CONFIG_SYS_TEXT_BASE=0x87800000
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x4000
CONFIG_TARGET_MYS_6ULX=y
CONFIG_SPL_TEXT_BASE=0x908000
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_NR_DRAM_BANKS=8
CONFIG_SPL=y
CONFIG_DEFAULT_DEVICE_TREE="imx6ull-myir-mys-6ulx-eval"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
CONFIG_BOOTDELAY=3
# CONFIG_USE_BOOTCOMMAND is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_SPL_DMA=y
CONFIG_SPL_NAND_SUPPORT=y
CONFIG_SPL_USB_HOST_SUPPORT=y
CONFIG_SPL_USB_GADGET=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_MEMTEST_START=0x80000000
CONFIG_SYS_MEMTEST_END=0x90000000
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
# CONFIG_RANDOM_UUID is not set
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
CONFIG_CMD_USB=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
CONFIG_MTDPARTS_DEFAULT="gpmi-nand:512k(spl),1m(uboot),1m(uboot-dup),-(ubi)"
CONFIG_CMD_UBI=y
# CONFIG_ISO_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM_I2C_GPIO=y
CONFIG_SYS_I2C_MXC=y
CONFIG_FSL_USDHC=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_MXS=y
CONFIG_NAND_MXS_DT=y
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
CONFIG_SYS_NAND_U_BOOT_OFFS=0x80000
CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND=0x180000
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_DM_PMIC=y
# CONFIG_SPL_PMIC_CHILDREN is not set
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_MXC_UART=y
CONFIG_USB=y
CONFIG_DM_USB=y
CONFIG_USB_GADGET=y
CONFIG_SMBIOS_MANUFACTURER="MYiR"

3
configs/pcm058_defconfig
View file

@ -7,7 +7,7 @@ CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_ENV_SIZE=0x4000
CONFIG_ENV_OFFSET=0x100000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
CONFIG_SYS_SPI_U_BOOT_OFFS=0x31400
CONFIG_MX6_OCRAM_256KB=y
CONFIG_TARGET_PCM058=y
CONFIG_DM_GPIO=y
@ -35,6 +35,7 @@ CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x18a
CONFIG_SPL_DMA=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y

3
configs/pico-imx6_defconfig
View file

@ -66,6 +66,9 @@ CONFIG_DM_MMC=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_ATHEROS=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_RGMII=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX6=y
CONFIG_MXC_UART=y

1
configs/verdin-imx8mm_defconfig
View file

@ -75,6 +75,7 @@ CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_MXC=y
CONFIG_MISC=y
CONFIG_I2C_EEPROM=y
CONFIG_DM_MMC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_FSL_ESDHC_IMX=y

29
drivers/ddr/imx/imx8m/ddrphy_utils.c
View file

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2018 NXP
*/
* Copyright 2018 NXP
*/
#include <common.h>
#include <errno.h>
@ -201,7 +201,7 @@ unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr)
}
unsigned int look_for_max(unsigned int data[],
unsigned int addr_start, unsigned int addr_end)
unsigned int addr_start, unsigned int addr_end)
{
unsigned int i, imax = 0;
@ -233,9 +233,9 @@ void get_trained_CDD(u32 fsp)
if (i == 0) {
cdd_cha[0] = (tmp >> 8) & 0xff;
} else if (i == 6) {
cdd_cha[11]=tmp & 0xff;
cdd_cha[11] = tmp & 0xff;
} else {
cdd_chb[ i * 2 - 1] = tmp & 0xff;
cdd_chb[i * 2 - 1] = tmp & 0xff;
cdd_chb[i * 2] = (tmp >> 8) & 0xff;
}
}
@ -254,7 +254,8 @@ void get_trained_CDD(u32 fsp)
g_cdd_ww_max[fsp] = cdd_cha_ww_max > cdd_chb_ww_max ? cdd_cha_ww_max : cdd_chb_ww_max;
} else {
unsigned int ddr4_cdd[64];
for( i = 0; i < 29; i++) {
for (i = 0; i < 29; i++) {
tmp = reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + (0x54012 + i) * 4);
ddr4_cdd[i * 2] = tmp & 0xff;
ddr4_cdd[i * 2 + 1] = (tmp >> 8) & 0xff;
@ -269,18 +270,18 @@ void get_trained_CDD(u32 fsp)
void update_umctl2_rank_space_setting(unsigned int pstat_num)
{
unsigned int i,ddr_type;
unsigned int i, ddr_type;
unsigned int addr_slot, rdata, tmp, tmp_t;
unsigned int ddrc_w2r,ddrc_r2w,ddrc_wr_gap,ddrc_rd_gap;
unsigned int ddrc_w2r, ddrc_r2w, ddrc_wr_gap, ddrc_rd_gap;
ddr_type = reg32_read(DDRC_MSTR(0)) & 0x3f;
for (i = 0; i < pstat_num; i++) {
addr_slot = i ? (i + 1) * 0x1000 : 0;
if (ddr_type == 0x20) {
/* update r2w:[13:8], w2r:[5:0] */
rdata=reg32_read(DDRC_DRAMTMG2(0) + addr_slot);
rdata = reg32_read(DDRC_DRAMTMG2(0) + addr_slot);
ddrc_w2r = rdata & 0x3f;
if(is_imx8mp())
if (is_imx8mp())
tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1);
else
tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1) + 1;
@ -297,7 +298,7 @@ void update_umctl2_rank_space_setting(unsigned int pstat_num)
reg32_write((DDRC_DRAMTMG2(0) + addr_slot), tmp_t);
} else {
/* update w2r:[5:0] */
rdata=reg32_read(DDRC_DRAMTMG9(0) + addr_slot);
rdata = reg32_read(DDRC_DRAMTMG9(0) + addr_slot);
ddrc_w2r = rdata & 0x3f;
if (is_imx8mp())
tmp = ddrc_w2r + (g_cdd_wr_max[i] >> 1);
@ -310,7 +311,7 @@ void update_umctl2_rank_space_setting(unsigned int pstat_num)
/* update r2w:[13:8] */
rdata = reg32_read(DDRC_DRAMTMG2(0) + addr_slot);
ddrc_r2w = (rdata >> 8) & 0x3f;
if(is_imx8mp())
if (is_imx8mp())
tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1);
else
tmp = ddrc_r2w + (g_cdd_rw_max[i] >> 1) + 1;
@ -324,7 +325,7 @@ void update_umctl2_rank_space_setting(unsigned int pstat_num)
/* update rankctl: wr_gap:11:8; rd:gap:7:4; quasi-dymic, doc wrong(static) */
rdata = reg32_read(DDRC_RANKCTL(0) + addr_slot);
ddrc_wr_gap = (rdata >> 8) & 0xf;
if(is_imx8mp())
if (is_imx8mp())
tmp = ddrc_wr_gap + (g_cdd_ww_max[i] >> 1);
else
tmp = ddrc_wr_gap + (g_cdd_ww_max[i] >> 1) + 1;
@ -342,7 +343,7 @@ void update_umctl2_rank_space_setting(unsigned int pstat_num)
}
}
if(is_imx8mq()) {
if (is_imx8mq()) {
/* update rankctl: wr_gap:11:8; rd:gap:7:4; quasi-dymic, doc wrong(static) */
rdata = reg32_read(DDRC_RANKCTL(0));
ddrc_wr_gap = (rdata >> 8) & 0xf;

27
drivers/gpio/mxc_gpio.c
View file

@ -13,6 +13,8 @@
#include <asm/arch/imx-regs.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <dt-structs.h>
#include <mapmem.h>
enum mxc_gpio_direction {
MXC_GPIO_DIRECTION_IN,
@ -22,6 +24,10 @@ enum mxc_gpio_direction {
#define GPIO_PER_BANK 32
struct mxc_gpio_plat {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
/* Put this first since driver model will copy the data here */
struct dtd_gpio_mxc dtplat;
#endif
int bank_index;
struct gpio_regs *regs;
};
@ -280,6 +286,12 @@ static int mxc_gpio_probe(struct udevice *dev)
int banknum;
char name[18], *str;
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct dtd_gpio_mxc *dtplat = &plat->dtplat;
plat->regs = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
#endif
banknum = plat->bank_index;
if (IS_ENABLED(CONFIG_ARCH_IMX8))
sprintf(name, "GPIO%d_", banknum);
@ -297,14 +309,15 @@ static int mxc_gpio_probe(struct udevice *dev)
static int mxc_gpio_ofdata_to_platdata(struct udevice *dev)
{
fdt_addr_t addr;
struct mxc_gpio_plat *plat = dev_get_platdata(dev);
if (!CONFIG_IS_ENABLED(OF_PLATDATA)) {
fdt_addr_t addr;
addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
return -EINVAL;
plat->regs = (struct gpio_regs *)addr;
plat->regs = (struct gpio_regs *)addr;
}
plat->bank_index = dev->req_seq;
return 0;
@ -332,6 +345,8 @@ U_BOOT_DRIVER(gpio_mxc) = {
.bind = mxc_gpio_bind,
};
U_BOOT_DRIVER_ALIAS(gpio_mxc, fsl_imx6q_gpio)
#if !CONFIG_IS_ENABLED(OF_CONTROL)
static const struct mxc_gpio_plat mxc_plat[] = {
{ 0, (struct gpio_regs *)GPIO1_BASE_ADDR },

92
drivers/mmc/fsl_esdhc_imx.c
View file

@ -33,6 +33,9 @@
#include <dm.h>
#include <asm-generic/gpio.h>
#include <dm/pinctrl.h>
#include <dt-structs.h>
#include <mapmem.h>
#include <dm/ofnode.h>
#if !CONFIG_IS_ENABLED(BLK)
#include "mmc_private.h"
@ -102,6 +105,11 @@ struct fsl_esdhc {
};
struct fsl_esdhc_plat {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
/* Put this first since driver model will copy the data here */
struct dtd_fsl_esdhc dtplat;
#endif
struct mmc_config cfg;
struct mmc mmc;
};
@ -1378,25 +1386,19 @@ __weak void init_clk_usdhc(u32 index)
{
}
static int fsl_esdhc_probe(struct udevice *dev)
static int fsl_esdhc_ofdata_to_platdata(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
const void *fdt = gd->fdt_blob;
int node = dev_of_offset(dev);
struct esdhc_soc_data *data =
(struct esdhc_soc_data *)dev_get_driver_data(dev);
#if CONFIG_IS_ENABLED(DM_REGULATOR)
struct udevice *vqmmc_dev;
int ret;
#endif
const void *fdt = gd->fdt_blob;
int node = dev_of_offset(dev);
fdt_addr_t addr;
unsigned int val;
struct mmc *mmc;
#if !CONFIG_IS_ENABLED(BLK)
struct blk_desc *bdesc;
#endif
int ret;
addr = dev_read_addr(dev);
if (addr == FDT_ADDR_T_NONE)
@ -1404,8 +1406,6 @@ static int fsl_esdhc_probe(struct udevice *dev)
priv->esdhc_regs = (struct fsl_esdhc *)addr;
priv->dev = dev;
priv->mode = -1;
if (data)
priv->flags = data->flags;
val = dev_read_u32_default(dev, "bus-width", -1);
if (val == 8)
@ -1469,6 +1469,63 @@ static int fsl_esdhc_probe(struct udevice *dev)
priv->vs18_enable = 1;
}
#endif
#endif
return 0;
}
static int fsl_esdhc_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
struct fsl_esdhc_priv *priv = dev_get_priv(dev);
struct esdhc_soc_data *data =
(struct esdhc_soc_data *)dev_get_driver_data(dev);
struct mmc *mmc;
#if !CONFIG_IS_ENABLED(BLK)
struct blk_desc *bdesc;
#endif
int ret;
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct dtd_fsl_esdhc *dtplat = &plat->dtplat;
unsigned int val;
priv->esdhc_regs = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
val = plat->dtplat.bus_width;
if (val == 8)
priv->bus_width = 8;
else if (val == 4)
priv->bus_width = 4;
else
priv->bus_width = 1;
if (dtplat->non_removable)
priv->non_removable = 1;
else
priv->non_removable = 0;
if (CONFIG_IS_ENABLED(DM_GPIO) && !priv->non_removable) {
struct udevice *gpiodev;
struct driver_info *info;
info = (struct driver_info *)dtplat->cd_gpios->node;
ret = device_get_by_driver_info(info, &gpiodev);
if (ret)
return ret;
ret = gpio_dev_request_index(gpiodev, gpiodev->name, "cd-gpios",
dtplat->cd_gpios->arg[0], GPIOD_IS_IN,
dtplat->cd_gpios->arg[1], &priv->cd_gpio);
if (ret)
return ret;
}
#endif
if (data)
priv->flags = data->flags;
/*
* TODO:
@ -1520,9 +1577,11 @@ static int fsl_esdhc_probe(struct udevice *dev)
return ret;
}
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
ret = mmc_of_parse(dev, &plat->cfg);
if (ret)
return ret;
#endif
mmc = &plat->mmc;
mmc->cfg = &plat->cfg;
@ -1644,9 +1703,10 @@ static int fsl_esdhc_bind(struct udevice *dev)
#endif
U_BOOT_DRIVER(fsl_esdhc) = {
.name = "fsl-esdhc-mmc",
.name = "fsl_esdhc",
.id = UCLASS_MMC,
.of_match = fsl_esdhc_ids,
.ofdata_to_platdata = fsl_esdhc_ofdata_to_platdata,
.ops = &fsl_esdhc_ops,
#if CONFIG_IS_ENABLED(BLK)
.bind = fsl_esdhc_bind,
@ -1655,4 +1715,6 @@ U_BOOT_DRIVER(fsl_esdhc) = {
.platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
.priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),
};
U_BOOT_DRIVER_ALIAS(fsl_esdhc, fsl_imx6q_usdhc)
#endif

6
drivers/pinctrl/nxp/pinctrl-imx6.c
View file

@ -41,8 +41,8 @@ static const struct udevice_id imx6_pinctrl_match[] = {
{ /* sentinel */ }
};
U_BOOT_DRIVER(imx6_pinctrl) = {
.name = "imx6-pinctrl",
U_BOOT_DRIVER(fsl_imx6q_iomuxc) = {
.name = "fsl_imx6q_iomuxc",
.id = UCLASS_PINCTRL,
.of_match = of_match_ptr(imx6_pinctrl_match),
.probe = imx6_pinctrl_probe,
@ -51,3 +51,5 @@ U_BOOT_DRIVER(imx6_pinctrl) = {
.ops = &imx_pinctrl_ops,
.flags = DM_FLAG_PRE_RELOC,
};
U_BOOT_DRIVER_ALIAS(fsl_imx6q_iomuxc, fsl_imx6dl_iomuxc)

4
drivers/video/imx/mxc_ipuv3_fb.c
View file

@ -665,8 +665,8 @@ static const struct udevice_id ipuv3_video_ids[] = {
{ }
};
U_BOOT_DRIVER(ipuv3_video) = {
.name = "ipuv3_video",
U_BOOT_DRIVER(fsl_imx6q_ipu) = {
.name = "fsl_imx6q_ipu",
.id = UCLASS_VIDEO,
.of_match = ipuv3_video_ids,
.bind = ipuv3_video_bind,

2
include/configs/imx8mn_evk.h
View file

@ -10,6 +10,8 @@
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M)
#define CONFIG_SPL_MAX_SIZE (148 * 1024)
#define CONFIG_SYS_MONITOR_LEN SZ_512K
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR

2
include/configs/imx8mp_evk.h
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@ -10,6 +10,8 @@
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M)
#define CONFIG_SPL_MAX_SIZE (152 * 1024)
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR

2
include/configs/imx8mq_evk.h
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@ -10,6 +10,8 @@
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M)
#define CONFIG_SPL_MAX_SIZE (124 * 1024)
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR

76
include/configs/mys_6ulx.h Normal file
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@ -0,0 +1,76 @@
/* SPDX-License-Identifier: GPL-2.0+
*
* Copyright (C) 2020 Linumiz
* Author: Parthiban Nallathambi <parthiban@linumiz.com>
*/
#ifndef __MYS_6ULX_H
#define __MYS_6ULX_H
#include <linux/sizes.h>
#include "mx6_common.h"
/* SPL options */
#include "imx6_spl.h"
#define CONFIG_SYS_FSL_USDHC_NUM 1
/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
/* Console configs */
#define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configs */
#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_HZ 1000
/* Physical Memory Map */
#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
#define PHYS_SDRAM_SIZE SZ_256M
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
/* NAND */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
/* USB Configs */
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
#define CONFIG_MXC_USB_FLAGS 0
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_IMX_THERMAL
#define CONFIG_EXTRA_ENV_SETTINGS \
"console=ttymxc0,115200n8\0" \
"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
"fdt_addr_r=0x82000000\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"kernel_addr_r=0x81000000\0" \
"pxefile_addr_r=0x87100000\0" \
"ramdisk_addr_r=0x82100000\0" \
"scriptaddr=0x87000000\0" \
BOOTENV
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
func(UBIFS, ubifs, 0) \
func(PXE, pxe, na) \
func(DHCP, dhcp, na)
#include <config_distro_bootcmd.h>
#endif /* __MYS_6ULX_H */