There are a few options which use lower case. We should use upper case for
all CONFIG options.
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Add usbtty/nand hunk to include/configs/spear3xx_evb.h]
Signed-off-by: Tom Rini <trini@konsulko.com>
This is a workaround to fix SATA CRC error. Once the root cause
is found the ECC disabling will be removed.
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
As per the top level U-Boot README "Board Initialisation Flow"
section, board_init_f() should return without calling board_init_r()
directly. Clearing BSS and calling board_init_r() will be done in
crt0_64.S.
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
According to design specification, the L2 cache operates at the same
frequency as the A72 CPUs in the cluster with a 3-cycle latency, so
increase the L2 Data RAM and Tag RAM latency to 3 cycles, or else,
will run into different call trace issues.
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The deep sleep function of LS1 platform, is mapped into PSCI system
suspend function, this patch adds implementation of it.
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The EPU Finite State Machie (FSM) is used in both the last stage of
system suspend and the earliest stage of system resume.
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The v7_flush_dcache_all function will be called by ls102xa platform system
suspend, it is necessary to make it a public call instead of a local one, but
changing the LENTRY to ENTRY isn't enough, because there is another one using
the same name, so this one gets a psci_ prefix.
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <york.sun@nxp.com>
As the access to serders protocol unselected PCIe controller will
hang. So disable the R/W permission to unselected PCIe controller
including its CCSR, IO space and memory space according to the
serders protocol field of RCW.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Move forward the basic non-secure access enable operation, so the
subsequent individual device access permission can override it.
And collect the dispersed callers in board level, and then move
them to SoC level.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Up to now, the function is_serdes_configed() doesn't check if the map
of serdes protocol is initialized before accessing it. The function
is_serdes_configed() will get wrong result when it was called before
the serdes protocol maps initialized. As the first element of the map
isn't used for any device, so use it as the flag to indicate if the
map has been initialized.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
As part of Secure Boot Chain of trust, PPA image must be validated
before the image is started.
The code for the same has been added.
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
DDR erratum A008336 only applies to DDR controller v5.2.0.
DDR controller v5.2.1 already has default 0x43b30002 in
EDDRTQCR1 register for optimal performance.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Move this option to Kconfig and set its default value to 4; this
increases the number of supported CPUs for some boards.
It consumes 1KB memory per CPU for PSCI stack, but it should not
be a big deal, given the amount of memory used for the modern OSes.
Reviewed-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Add ARCH_SUPPORT_PSCI as a non-configurable option that platforms
can select. Then, move CONFIG_ARMV7_PSCI, which is automatically
enabled if both ARMV7_NONSEC and ARCH_SUPPORT_PSCI are enabled.
Reviewed-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
If CONFIG_ARMV7_NONSEC is enabled, the linker script requires
CONFIG_ARMV7_PSCI_NR_CPUS regardless of CONFIG_ARMV7_PSCI.
Reviewed-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Currently MX6 SPL DDR initialization hardcodes the REF_SEL and
REFR fields of the MDREF register as 1 and 7, respectively for
DDR3 and 0 and 3 for LPDDR2.
Looking at the MDREF initialization done via DCD we see that
boards do need to initialize these fields differently:
$ git grep 0x021b0020 board/
board/bachmann/ot1200/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800
board/ccv/xpress/imximage.cfg:DATA 4 0x021b0020 0x00000800 /* MMDC0_MDREF */
board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x7800
board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/mx6qp.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6sabresd/mx6dlsabresd.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6slevk/imximage.cfg:DATA 4 0x021b0020 0x00001800
board/freescale/mx6sxsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00000800
board/freescale/mx6sxsabresd/imximage.cfg:DATA 4 0x021b0020 0x00000800
board/warp/imximage.cfg:DATA 4 0x021b0020 0x00001800
So introduce a mechanism for users to be able to configure
REFSEL and REFR fields as needed.
Keep all the mx6 SPL users in their current REF_SEL and REFR values,
so no functional changes for the existing users.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Eric Nelson <eric@nelint.com>
Add support for Advantech DMS-BA16 board. The board is based on Advantech
BA16 module which has a i.MX6D processor. The board supports:
- FEC Ethernet
- USB Ports
- SDHC and MMC boot
- SPI NOR
- LVDS and HDMI display
Basic information about the module:
- Module manufacturer: Advantech
- CPU: Freescale ARM Cortex-A9 i.MX6D
- SPECS:
Up to 2GB Onboard DDR3 Memory;
Up to 16GB Onboard eMMC NAND Flash
Supports OpenGL ES 2.0 and OpenVG 1.1
HDMI, 24-bit LVDS
1x UART, 2x I2C, 8x GPIO,
4x Host USB 2.0 port, 1x USB OTG port,
1x micro SD (SDHC),1x SDIO, 1x SATA II,
1x 10/100/1000 Mbps Ethernet, 1x PCIe X1 Gen2
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Cc: u-boot@lists.denx.de
Cc: sbabic@denx.de
This series moves the CONFIG_SYS_CACHELINE_SIZE. First, in nearly all
cases we are mirroring the values used by the Linux Kernel here. Also,
so long as (and in this case, it is true) we implement flushes in hunks
that are no larger than the smallest implementation (and given that we
mirror the Linux Kernel, again we are fine) it is OK to align higher.
The biggest changes here are that we always use 64 bytes for CPU_V7 even
if for example the underlying core is only 32 bytes (this mirrors
Linux). Second, we say ARM64 uses 64 bytes not 128 (as found in the
Linux Kernel) as we do not need multi-platform support (to this degree)
and only the Cavium ThunderX 88xx series has a use for such large
alignment.
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Stefan Roese <sr@denx.de>
Cc: Nagendra T S <nagendra@mistralsolutions.com>
Cc: Vaibhav Hiremath <hvaibhav@ti.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Steve Rae <steve.rae@raedomain.com>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Stefan Agner <stefan.agner@toradex.com>
Acked-by: Heiko Schocher <hs@denx.de>
Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Cc: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Paul Kocialkowski <contact@paulk.fr>
Cc: Anatolij Gustschin <agust@denx.de>
Acked-by: "Pali Rohár" <pali.rohar@gmail.com>
Cc: Adam Ford <aford173@gmail.com>
Cc: Steve Sakoman <sakoman@gmail.com>
Cc: Grazvydas Ignotas <notasas@gmail.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Robert Baldyga <r.baldyga@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Thomas Weber <weber@corscience.de>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: David Feng <fenghua@phytium.com.cn>
Cc: Alison Wang <b18965@freescale.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: York Sun <york.sun@nxp.com>
Cc: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Cc: Mingkai Hu <mingkai.hu@nxp.com>
Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Cc: Aneesh Bansal <aneesh.bansal@freescale.com>
Cc: Saksham Jain <saksham.jain@nxp.com>
Cc: Qianyu Gong <qianyu.gong@nxp.com>
Cc: Wang Dongsheng <dongsheng.wang@nxp.com>
Cc: Alex Porosanu <alexandru.porosanu@freescale.com>
Cc: Hongbo Zhang <hongbo.zhang@nxp.com>
Cc: tang yuantian <Yuantian.Tang@freescale.com>
Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Cc: Josh Wu <josh.wu@atmel.com>
Cc: Bo Shen <voice.shen@atmel.com>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Hannes Schmelzer <oe5hpm@oevsv.at>
Cc: Thomas Chou <thomas@wytron.com.tw>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Sam Protsenko <semen.protsenko@linaro.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Christophe Ricard <christophe-h.ricard@st.com>
Cc: Anand Moon <linux.amoon@gmail.com>
Cc: Beniamino Galvani <b.galvani@gmail.com>
Cc: Carlo Caione <carlo@endlessm.com>
Cc: huang lin <hl@rock-chips.com>
Cc: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Cc: Xu Ziyuan <xzy.xu@rock-chips.com>
Cc: "jk.kernel@gmail.com" <jk.kernel@gmail.com>
Cc: "Ariel D'Alessandro" <ariel@vanguardiasur.com.ar>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Samuel Egli <samuel.egli@siemens.com>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Ian Campbell <ijc@hellion.org.uk>
Cc: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Cc: Boris Brezillon <boris.brezillon@free-electrons.com>
Cc: Andre Przywara <andre.przywara@arm.com>
Cc: Bernhard Nortmann <bernhard.nortmann@web.de>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Ben Whitten <ben.whitten@gmail.com>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Alexander Graf <agraf@suse.de>
Cc: Sekhar Nori <nsekhar@ti.com>
Cc: Vitaly Andrianov <vitalya@ti.com>
Cc: "Andrew F. Davis" <afd@ti.com>
Cc: Murali Karicheri <m-karicheri2@ti.com>
Cc: Carlos Hernandez <ceh@ti.com>
Cc: Ladislav Michl <ladis@linux-mips.org>
Cc: Ash Charles <ashcharles@gmail.com>
Cc: Mugunthan V N <mugunthanvnm@ti.com>
Cc: Daniel Allred <d-allred@ti.com>
Cc: Gong Qianyu <Qianyu.Gong@freescale.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Chin Liang See <clsee@altera.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Paul Kocialkowski <contact@paulk.fr>
There is no reason to duplicate code for DRA7xx platforms as there
can be Rail grouping. The maximum voltage detection algorithm can still
be run on other platforms with no Rail grouping and does not harm as
it gives the same result.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
gpio_en field is introduced to detect if pmic is controlled by GPIO.
Make this field 0 on all TPS659* pmics available on DRA7/OMAP5 based platforms
and remove the #ifndefs.
Reviewed-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Linux stopped the use of keyword 'boolean' in Kconfig.
Refer to commit 6341e62b212a2541efb0160c470e90bd226d5496 ("kconfig:
use bool instead of boolean for type definition attributes")
in Linux Kernel.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Flush operations need to be cacheline aligned to take effect, make
sure to flush always complete cachelines. This avoids messages such
as:
CACHE: Misaligned operation at range [00900000, 009004d9]
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
We create 2 sets of page tables: One for normal operation, one for
emergency (used while modifying the former).
Because the page tables grow dynamically, we have code that checks
for overflow. Unfortunately we didn't adjust the available space
variable while creating the emergency tables, so potentially someone
might run into an overflow there (not seen in real world yet though!).
Fix it by properly adjusting the size as well as the base offset in
emergency page table creation.
Reported-by: York Sun <york.sun@nxp.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: York Sun <york.sun@nxp.com>
These config targets were added well before the Kconfig migration began
as a way to demonstrate how to make these platforms work with cut down
features. At this point in time they no longer serve a good purpose so
remove them.
Signed-off-by: Tom Rini <trini@konsulko.com>
We need to ensure that CONFIG_PHYS_64BIT is configured via Kconfig so
that it is always available to the build system. Otherwise we can run
into cases where we have inconsistent sizes of certain attributes.
Ravi Babu reported offset mismatch of struct dwc3 across files since
commit 95ebc253e6 ("types.h: move and redefine resource_size_t").
Since the commit, resource_addr_t points to phys_addr_t, whose size
is dependent on CONFIG_PHYS_64BIT for ARM architecture.
I tried my best to use "select" where possible (for example, ARMv8
architecture) because I think this kind of option is generally user-
unconfigurable. However, I see some of PowerPC boards have 36BIT
defconfigs as well as 32BIT ones. I moved CONFIG_PHYS_64BIT to the
defconfigs for such boards.
CONFIG_36BIT is no longer referenced, so all of the defines were
removed from CONFIG_SYS_EXTRA_OPTIONS.
Fixes: 95ebc253e6 ("types.h: move and redefine resource_size_t")
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reported-by: Ravi Babu <ravibabu@ti.com>
Acked-by: Stefan Roese <sr@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <york.sun@nxp.com>
As part of testing booting Linux kernels on Rockchip devices, it was
discovered by Ziyuan Xu and Sandy Patterson that we had multiple and for
some cases incomplete isb definitions. This was causing a failure to
boot of the Linux kernel.
In order to solve this problem as well as cover any corner cases that we
may also have had a number of changes are made in order to consolidate
things. First, <asm/barriers.h> now becomes the source of isb/dsb/dmb
definitions. This however introduces another complexity. Due to
needing to build SPL for 32bit tegra with -march=armv4 we need to borrow
the __LINUX_ARM_ARCH__ logic from the Linux Kernel in a more complete
form. Move this from arch/arm/lib/Makefile to arch/arm/Makefile and add
a comment about it. Now that we can always know what the target CPU is
capable off we can get always do the correct thing for the barrier. The
final part of this is that need to be consistent everywhere and call
isb()/dsb()/dmb() and NOT call ISB/DSB/DMB in some cases and the
function names in others.
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Acked-by: Sandy Patterson <apatterson@sightlogix.com>
Reported-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Reported-by: Sandy Patterson <apatterson@sightlogix.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
The PPA binary may be stored on QSPI flash instead of NOR.
So, deprecated CONFIG_SYS_LS_PPA_FW_IN_NOR in favour of
CONFIG_SYS_LS_PPA_FW_IN_XIP to prevent fragmentation of code
by addition of a new QSPI specific flag.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
According to AM572x DM SPRS953A, QSPI bus speed can be 76.8MHz, hence
update QSPI input clock divider value (DPLL_PER_HS13) to provide 76.8MHz
clock, so that driver can use the same.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
This commit adds support for the Toradex Computer on Modules
Colibri iMX7S/iMX7D. The two modules/SoC's are very similar hence
can be easily supported by one board. The board code detects RAM
size at runtime which is one of the differences between the two
boards. The board also uses the UART's in DTE mode, hence making
use of the new DTE support via serial DM.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
MMU bit in SCTLR needs to be set explicitly after tables are
created. It isn't an issue for EL3 becuase this bit is already
set by early MMU setup. But for other exception levels this
bit was not set.
Signed-off-by: York Sun <york.sun@nxp.com>
This patch implements PSCI functions for ls102xa SoC following PSCI v1.0,
they are as the list:
psci_version,
psci_features,
psci_cpu_suspend,
psci_affinity_info,
psci_system_reset,
psci_system_off.
Tested on LS1021aQDS, LS1021aTWR.
Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com>
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The input parameter CPU ID needs to be validated before furher oprations such
as CPU_ON, this patch introduces the function to do this.
Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com>
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This patch adds all the PSCI v1.0 functions in to the common framework, with
all the functions returning "not implemented" by default, as a common framework
all the dummy functions are added here, it is up to every platform developer to
decide which version of PSCI and which functions to implement.
Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com>
Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The LS1046A processor is built on the QorIQ LS series architecture
combining four ARM A72 processor cores with DPAA 1.0 support.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Mihai Bantea <mihai.bantea@freescale.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
New SoC LS1046A belongs to Freescale Chassis Generation 2 and
has two SerDes so we need to add this support in fsl_lsch2.
The SoC related SerDes 2 support will be added in SoC patch.
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Add support to detect Cortex-A72 core for printing it out.
The Initiator Version of A72 core should be 0x4.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
A couple of commits have modified the am33xx/am437x ddr2/ddr3
initialization path to fix certain issues, but have had the side effect
of causing L3 noc errors during initialization. The two commits are:
69b918 "am33xx,ddr3: fix ddr3 sdram configuration"
fc46ba "arm: am437x: Enable hardware leveling for EMIF"
The EMIF_REG_INITREF_DIS_MASK bit still needs to be set for all
platforms. This delays initialization and refresh until a later stage.
The 500us timer can be programmed for platforms that require it
and for platforms that don't require it. It is currently hardcoded
for 400MHz systems. For systems with a higher memory frequency
this needs to be a larger value, and for systems with a lower
memory frequency this can be a lower value. This can be
considered a separate issue and corrected in a later commit.
Signed-off-by: Russ Dill <Russ.Dill@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The delay needs to be before the write to ref_ctrl register
which initiates refreshes. An improper initialization sequence
generates an L3 noc error.
Signed-off-by: Russ Dill <Russ.Dill@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Commit 17c2987 introduces an undesired dependency on CONFIG_SPL_LOAD_FIT
when building U-Boot for AM57xx and DRA7xx high-security (HS) devices that
causes the build to break when that option is not active. Fix this issue
by only building the u-boot_HS.img target when building U-Boot into an
actual FIT image.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Commit e29878f introduces an undesired dependency on CONFIG_SPL_LOAD_FIT
when building U-Boot for AM43xx high-security (HS) devices that causes the
build to break when that option is not active. Fix this issue by only
building the u-boot_HS.img target when building U-Boot into an actual
FIT image.
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
identify_nand_chip hangs forever in loop when NAND is not present.
As IGEPv2 comes either with NAND or OneNAND flash, add reset timeout
to let function fail gracefully allowing caller to know NAND is
not present. On NAND equipped board, reset succeeds on first read,
so 1000 loops seems to be safe timeout.
Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
Implement a hook to allow boards to save boot-time CPU state for later
use. When U-Boot is chain-loaded by another bootloader, CPU registers may
contain useful information such as system configuration information. This
feature mirrors the equivalent ARMv7 feature.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
According to the IMX6DQRM Reference Manual, the description
of bit 7 (axi_alt_sel) of the CCM_CBCDR register is:
"AXI alternative clock select
0 pll2 396MHz PFD will be selected as alternative clock for AXI root clock
1 pll3 540MHz PFD will be selected as alternative clock for AXI root clock "
The current logic is inverted, so fix it to match the reference manual.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Set the enable-method in the cpu node to PSCI, and create device
node for PSCI, when PSCI was enabled.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
If the PSCI and PPA is ready, skip the fixup for spin-table and
waking secondary cores. Otherwise, change SMP method to spin-table,
and the device node of PSCI will be removed.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The FSL Primary Protected Application (PPA) is a software component
loaded during boot which runs in TrustZone and remains resident
after boot.
Use the secure firmware framework to integrate FSL PPA into U-Boot.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This framework is introduced for ARMv8 secure monitor mode firmware.
The main functions of the framework are, on EL3, verify the firmware,
load it to the secure memory and jump into it, and while it returned
to U-Boot, do some necessary setups at the 'target exception level'
that is determined by the respective secure firmware.
So far, the framework support only FIT format image, and need to define
the name of which config node should be used in 'configurations' and
the name of property for the raw secure firmware image in that config.
The FIT image should be stored in Byte accessing memory, such as NOR
Flash, or else it should be copied to main memory to use this framework.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This function assume that the d-cache and MMU has been enabled earlier,
so it just created MMU table in main memory. But the assumption is not
always correct, for example, the early setup is done in EL3, while
enable_caches() is called when the PE has turned into another EL.
Define the function mmu_setup() for fsl-layerscape to cover the weak
one.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Drop platform code to create static MMU tables. Use common framework
to create MMU tables on the run. Tested on LS2080ARDB with secure and
non-secure ram scenarios.
Signed-off-by: York Sun <york.sun@nxp.com>
Use existing Kconfig symbols to let the user configure whether to
build a U-Boot with non-secure mode support or not. This also allows
to enable virtualization extension easily.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
This can be useful if the same U-Boot binary is used for boards
available with a i.MX 7Solo and i.MX 7Dual.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Introduce virtual and physical addresses in the mapping table. This change
have no impact on existing boards because they all use idential mapping.
Signed-off-by: York Sun <york.sun@nxp.com>
When page tables are created, allow later table to be created on
previous block entry. Splitting block feature is already working
with current code. This patch only rearranges the code order and
adds one condition to call split_block().
Signed-off-by: York Sun <york.sun@nxp.com>
Make setup_pgtages() and get_tcr() available for platform code to
customize MMU tables.
Remove unintentional call of create_table().
Signed-off-by: York Sun <york.sun@nxp.com>
Secure_ram variable was put in generic global data. But only ARMv8
uses this variable. Move it to ARM specific data structure.
Signed-off-by: York Sun <york.sun@nxp.com>
Now that we have a secure data section for storing variables, there
should be no need for platform code to get the stack address.
Make psci_get_cpu_stack_top a local function, as it should only be
used in armv7/psci.S and only by psci_stack_setup.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Now that we have a secure data section and space to store per-CPU target
PC address, switch to it instead of storing the target PC on the stack.
Also save clobbered r4-r7 registers on the stack and restore them on
return in psci_cpu_on for Tegra, i.MX7, and LS102xA platforms.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Now that we have a data section, add helper functions to save and fetch
per-CPU target PC.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The secure monitor may need to store global or static values within the
secure section of memory, such as target PC or CPU power status.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
sunxi and i.mx7 both define the __secure modifier to put functions in
the secure section. Move this to a common place.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
As the PSCI implementation grows, we might exceed the size of the secure
memory that holds the firmware.
Add a configurable CONFIG_ARMV7_SECURE_MAX_SIZE so platforms can define
how much secure memory is available. The linker then checks the size of
the whole secure section against this.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
psci_text_end was used to calculate the PSCI stack address following the
secure monitor text. Now that we have an explicit secure stack section,
this is no longer used.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Now that we have a secure stack section that guarantees usable memory,
allocate the PSCI stacks in that section.
Also add a diagram detailing how the stacks are placed in memory.
Reserved space for the target PC remains unchanged. This should be
moved to global variables within a secure data section in the future.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Until now we've been using memory beyond psci_text_end as stack space
for the secure monitor or PSCI implementation, even if space was not
allocated for it.
This was partially fixed in ("ARM: allocate extra space for PSCI stack
in secure section during link phase"). However, calculating stack space
from psci_text_end in one place, while allocating the space in another
is error prone.
This patch adds a separate empty secure stack section, with space for
CONFIG_ARMV7_PSCI_NR_CPUS stacks, each 1 KB. There's also
__secure_stack_start and __secure_stack_end symbols. The linker script
handles calculating the correct VMAs for the stack section. For
platforms that relocate/copy the secure monitor before using it, the
space is not allocated in the executable, saving space.
For platforms that do not define CONFIG_ARMV7_PSCI_NR_CPUS, a whole page
of stack space for 4 CPUs is allocated, matching the previous behavior.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Targets that define CONFIG_ARMV7_SECURE_BASE will copy the secure section
to another address before execution.
Since the secure section in the u-boot image is only storage, there's
no reason to page align it and increase the binary image size.
Page align the secure section only when CONFIG_ARMV7_SECURE_BASE is not
defined. And instead of just aligning the __secure_start symbol, align
the whole .__secure_start section. This also makes the section empty,
so we need to add KEEP() to the input entry to prevent the section from
being garbage collected.
Also use ld constant "COMMONPAGESIZE" instead of hardcoded page size.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This patch finishes the rewrite of sunxi specific PSCI parts into C
code.
The assembly-only stack setup code has been factored out into a common
function for ARMv7. The GIC setup code can be renamed as psci_arch_init.
And we can use an empty stub function for psci_text_end.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Every platform has the same stack setup code in assembly as part of
psci_arch_init.
Move this out into a common separate function, psci_stack_setup, for
all platforms. This will allow us to move the remaining parts of
psci_arch_init into C code, or drop it entirely.
Also provide a stub no-op psci_arch_init for platforms that don't need
their own specific setup code.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
At present armv7 will unhappily invalidate a cache region and print an
error message. Make it skip the operation instead, as it does with other
cache operations.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Marek Vasut <marex@denx.de>
Errata i727 is applicable on all OMAP5 and DRA7 variants but enabled only
on OMAP5 ES1.0. So, enable it on all platforms.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This patch adds SDRAM support for stm32f746 discovery board.
This patch depends on previous patch.
This patch is based on STM32F4 and emcraft's[1].
[1]: https://github.com/EmcraftSystems/u-boot
Signed-off-by: Toshifumi NISHINAGA <tnishinaga.dev@gmail.com>
Modify the SPL build procedure for AM437x high-security (HS) device
variants to create a secure u-boot_HS.img FIT blob that contains U-Boot
and DTB artifacts signed (and optionally encrypted) with a TI-specific
process based on the CONFIG_TI_SECURE_DEVICE config option and the
externally-provided image signing tool.
Also populate the corresponding FIT image post processing call to be
performed during SPL runtime.
Signed-off-by: Madan Srinivas <madans@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Modify the SPL build procedure for AM57xx and DRA7xx high-security (HS)
device variants to create a secure u-boot_HS.img FIT blob that contains
U-Boot and DTB artifacts signed with a TI-specific process based on the
CONFIG_TI_SECURE_DEVICE config option and the externally-provided image
signing tool.
Also populate the corresponding FIT image post processing call to be
performed during SPL runtime.
Signed-off-by: Daniel Allred <d-allred@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Adds commands so that when a secure device is in use and the SPL is
built to load a FIT image (with combined U-Boot binary and various
DTBs), these components that get fed into the FIT are all processed to
be signed/encrypted/etc. as per the operations performed by the
secure-binary-image.sh script of the TI SECDEV package. Furthermore,
perform minor comments cleanup to make better use of the available
space.
Signed-off-by: Daniel Allred <d-allred@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Adds an API that verifies a signature attached to an image (binary
blob). This API is basically a entry to a secure ROM service provided by
the device and accessed via an SMC call, using a particular calling
convention.
Signed-off-by: Daniel Allred <d-allred@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Adds a generic C-callable API for making secure ROM calls on OMAP and
OMAP-compatible devices. This API provides the important function of
flushing the ROM call arguments to memory from the cache, so that the
secure world will have a coherent view of those arguments. Then is
simply calls the omap_smc_sec routine.
Signed-off-by: Daniel Allred <d-allred@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Add an interface for calling secure ROM APIs across a range of OMAP and
OMAP compatible high-security (HS) device variants. While at it, also
perform minor cleanup/alignment without any change in functionality.
Signed-off-by: Daniel Allred <d-allred@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Adds missing flush_dcache_range and invalidate_dcache_range dummy
(empty) placeholder functions to the #else portion of the #ifndef
CONFIG_SYS_DCACHE_OFF, where full implementations of these functions
are defined.
Signed-off-by: Daniel Allred <d-allred@ti.com>
Signed-off-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
There are two enable methods supported by ARM64 Linux; psci and
spin-table. The latter is simpler and helpful for quick SoC bring
up. My main motivation for this patch is to improve the spin-table
support, which allows us to boot an ARMv8 system without the ARM
Trusted Firmware.
Currently, we have multi-entry code in arch/arm/cpu/armv8/start.S
and the spin-table is supported in a really ad-hoc way, and I see
some problems:
- We must hard-code CPU_RELEASE_ADDR so that it matches the
"cpu-release-addr" property in the DT that comes from the
kernel tree.
- The Documentation/arm64/booting.txt in Linux requires that
the release address must be zero-initialized, but it is not
cared by the common code in U-Boot. We must do it in a board
function.
- There is no systematic way to protect the spin-table code from
the kernel. We are supposed to do it in a board specific manner,
but it is difficult to predict where the spin-table code will be
located after the relocation. So, it also makes difficult to
hard-code /memreserve/ in the DT of the kernel.
So, here is a patch to solve those problems; the DT is run-time
modified to reserve the spin-table code (+ cpu-release-addr).
Also, the "cpu-release-addr" property is set to an appropriate
address after the relocation, which means we no longer need the
hard-coded CPU_RELEASE_ADDR.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Upon further review this breaks most other platforms as we need to check
what core we're running on before touching it at all.
This reverts commit d73718f323.
Signed-off-by: Tom Rini <trini@konsulko.com>
Custom Board based on MX6 Dual, 1GB RAM and eMMC.
There are two variants of the board with and without
PCIe (ZC5202 and ZC5601).
Signed-off-by: Stefano Babic <sbabic@denx.de>
For A53, data coherency is enabled only when the CPUECTLR.SMPEN bit is
set. The SMPEN bit should be set before enabling the data cache.
If not enabled, the cache is not coherent with other cores and
data corruption could occur.
For A57/A72, SMPEN bit enables the processor to receive instruction
cache and TLB maintenance operations broadcast from other processors
in the cluster. This bit should be set before enabling the caches and
MMU, or performing any cache and TLB maintenance operations.
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Freescale ARMv8 SoC name ends with "A" to represent ARM SoCs.
like LS2080A, LS1043A, LS1012A.
So append "A" to SoC names.
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The SPL code already knows which boot device it calls the spl_boot_mode()
on, so pass that information into the function. This allows the code of
spl_boot_mode() avoid invoking spl_boot_device() again, but it also lets
board_boot_order() correctly alter the behavior of the boot process.
The later one is important, since in certain cases, it is desired that
spl_boot_device() return value be overriden using board_boot_order().
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@konsulko.com>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
[add newly introduced zynq variant]
Signed-aff-by: Andreas Bießmann <andreas@biessmann.org>
The handling of the "usage counter" is incorrect, and the clock should
only be disabled when transitioning from 1 to 0.
Reported-by: Chris Brand <chris.brand@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>
The Kona Peripheral Slave CCU has 4 policy mask registers, not 8.
Signed-off-by: Chris Brand <chris.brand@broadcom.com>
Signed-off-by: Steve Rae <srae@broadcom.com>
gic_kick_secondary_cpus can directly return to the caller of
smp_kick_all_cpus. We do not have to use x29 register here.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The register CLKCNCSR controls the frequency of all cores in the same
cluster.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
To make the PSCI backend more maintainable and easier to port to newer
SoCs, rewrite the current PSCI implementation in C.
Some inline assembly bits are required to access coprocessor registers.
PSCI stack setup is the only part left completely in assembly. In theory
this part could be split out of psci_arch_init into a separate common
function, and psci_arch_init could be completely in C.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Instead of hardcoding the GIC addresses in the PSCI implementation,
provide a base address in the cpu header.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Use SUNXI_CPUCFG_BASE across all families. This makes writing common
PSCI code easier.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The PSCI implementation expects at most 2 pages worth of space reserved
at the end of the secure section for its stacks. If PSCI is relocated to
secure SRAM, then everything is fine. If no secure SRAM is available,
and PSCI remains in main memory, the reserved memory space doesn't cover
the space used by the stack.
If one accesses PSCI after Linux has fully booted, the memory that should
have been reserved for the PSCI stacks may have been used by the kernel
or userspace, and would be corrupted. Observed after effects include the
system hanging or telinit core dumping when trying to reboot. It seems
the init process gets hit the most on my test bed.
This fix allocates the space used by the PSCI stacks in the secure
section by skipping pages in the linker script, but only when there is
no secure SRAM, to avoid bloating the binary.
This fix is only a stop gap. It would be better to rework the stack
allocation mechanism, maybe with proper usage of CONFIG_ macros and an
explicit symbol.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
For psci_get_cpu_stack_top() to be usable in C code, it must adhere to
the ARM calling conventions. Since it could be called when the stack
is still unavailable, and the entry code to linux also expects r1 and
r2 to remain unchanged, stick to r0 and r3.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This errata a008751 is applied on Soc specific file currently.This will be
moved to a file where all the errata implementation will take place for usb
for fsl. This patch removes the errata workaround from soc specific file
for LS2080.
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms,
similar to PPC and ARMv7.
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
board/am57xx supports all boards based on am57xx. Rename the taget
as TARGET_AM57XX_EVM.
Fixes: 74cc8b097d ("board: ti: beagle_x15: Rename to indicate support for TI am57xx evms")
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Add initial support for NXP's S32V234 SoC and S32V234EVB board.
The S32V230 family is designed to support computation-intensive applications
for image processing. The S32V234, as part of the S32V230 family, is a
high-performance automotive processor designed to support safe
computation-intensive applications in the area of vision and sensor fusion.
Code originally writen by:
Original-signed-off-by: Stoica Cosmin-Stefan <cosminstefan.stoica@freescale.com>
Original-signed-off-by: Mihaela Martinas <Mihaela.Martinas@freescale.com>
Original-signed-off-by: Eddy Petrișor <eddy.petrisor@gmail.com>
Signed-off-by: Eddy Petrișor <eddy.petrisor@nxp.com>
At present CONFIG_SKIP_LOWLEVEL_INIT prevents U-Boot from calling
lowlevel_init(). This means that the instruction cache is not enabled and
the board runs very slowly.
What is really needed in many cases is to skip the call to lowlevel_init()
but still perform CP15 init. Add an option to handle this.
Reviewed-by: Heiko Schocher <hs@denx.de>
Tested-on: smartweb, corvus, taurus, axm
Tested-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
Currently omap_vcores which holds pmic data is being assigned based
on the SoC type. PMIC is not a part of SoC. It is logical to
to assign omap_vcores based on board type. Hence over ride the
vcores_init function and assign omap_vcores based on the board type.
Reported-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Environment variable mcinitcmd is defined to initiate MC and DPL
deployment from the location where it is stored (NOR, NAND, SD, SATA,
USB) during booting. If this variable is not defined then macro
MC_BOOT_ENV_VAR will be null and MC will not be booted and DPL will
not be applied during U-boot booting.
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The SP805-WDT module on LS2080A requires configuration of PMU's
PCTBENR register to enable watchdog counter decrement and reset
signal generation. The watchdog clock needs to be enabled first.
Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Enable Spread Spectrum for the MPU by calculating the required
values and setting the registers accordingly.
Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Both comments look like being copy & paste errors.
Signed-off-by: Michael Heimpold <michael.heimpold@i2se.com>
Cc: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Some SPL loaders (like Allwinner's boot0, and Broadcom's boot0)
require a header before the actual U-Boot binary to both check its
validity and to find other data to load. Sometimes this header may
only be a few bytes of information, and sometimes this might simply
be space that needs to be reserved for a post-processing tool.
Introduce a config option to allow assembler preprocessor commands
to be inserted into the code at the appropriate location; typical
assembler preprocessor commands might be:
.space 1000
.word 0x12345678
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Steve Rae <srae@broadcom.com>
Commit Notes:
Please note that the current code:
start.S (arm64) and
vectors.S (arm)
already jumps over some portion of data already, so this option basically
just increases the size of this region (and the resulting binary).
For use with Allwinner's boot0 blob there is a tool called boot0img[1],
which fills the header to allow booting A64 based boards.
For the Pine64 we need a 1536 byte header (including the branch
instruction) at the moment, so we add this to the defconfig.
[1] https://github.com/apritzel/pine64/tree/master/tools
END
Reviewed-by: Tom Rini <trini@konsulko.com>
The QorIQ LS1012A processor, optimized for battery-backed or
USB-powered, integrates a single ARM Cortex-A53 core with a hardware
packet forwarding engine and high-speed interfaces to deliver
line-rate networking performance.
This patch add support of LS1012A SoC along with
- Update platform & DDR clock read logic as per SVR
- Define MMDC controller register set.
- Update LUT base address for PCIe
- Avoid L3 platform cache compilation
- Update USB address, errata
- SerDes table
- Added CSU IDs for SDHC2, SAI-1 to SAI-4
Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
Signed-off-by: Makarand Pawagi <makarand.pawagi@mindspeed.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
SoC overviews are getting repeated across board folders.
So, Organize SoC overview at common location i.e. fsl-layerscape/doc
Also move README.lsch2 and README.lsch3 in same folder.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c: In function
‘get_sys_info’:
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c:29:6: warning:
unused variable ‘rcw_tmp’ [-Wunused-variable]
u32 rcw_tmp;
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Other than LS1043A, LS1012A also Chassis Gen2 Architecture compliant.
So Avoid LS1043A specific defines in arch/arm
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
It is not mandatory for Layerscape SoCs to have SMMU. SoCs like
LS1012A are layerscape SoC without SMMU IP.
So put SMMU configuration code under SMMU_BASE.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The pmic registers for variants of am57xx boards are different
hence we need to assign them carefully based on the board type.
Add a function to assign omap_vcores after the board detection.
Signed-off-by: Keerthy <j-keerthy@ti.com>
The voltage values for each voltage domain at an OPP is identical
across all the SoCs in the DRA7 family. The current code defines
one set of macros for DRA75x/DRA74x SoCs and another set for DRA72x
macros. Consolidate both these sets into a single set.
This is done so as to minimize the number of macros used when voltage
values will be added for other OPPs as well.
Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Define a set of common macros for the efuse register offsets
(different for each OPP) that are used to get the AVS Class 0
voltage values and ABB configuration values. Assign these
common macros to the register offsets for OPP_NOM by default
for all voltage domains. These common macros can then be
redefined properly to point to the OPP specific efuse register
offset based on the desired OPP to program a specific voltage
domain.
Signed-off-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
CONFIG_USB_XHCI_OMAP is enabled for host mode independent of CONFIG_USB_DWC3
which is meant for gadget mode only. We need enable/disbale_usb_clocks() for
host mode as well so provide for it.
Fixes: 09cc14f4bc ("ARM: AM43xx: Add functions to enable and disable USB clocks"
Signed-off-by: Roger Quadros <rogerq@ti.com>
All the output clock parameters of a DPLL needs to be programmed before
locking the DPLL. But it is being configured after locking the DPLL which
could potentially bypass DPLL. So fixing this sequence.
Reported-by: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Since 1e6ad55c05 ("armv8/cache: Change cache invalidate and flush
function"), this routine can be used for both cache flushing and
cache invalidation. So, it is better to not include "flush" in
this routine name.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
__asm_dcache_all can directly return to the caller of
__asm_{flush,invalidate}_dcache_all.
We do not have to waste x16 register here.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The CDCE913 and CDCEL913 devices are modular PLL-based, low cost,
high performance , programmable clock synthesizers. They generate
upto 3 output clocks from a single input frequency. Each output can
be programmed for any clock-frequency.
Adding support for the same.
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Adds an fdt.c file in that defines the ft_cpu_setup() function,
which should be called from a board-specific ft_board_setup()).
This ft_cpu_setup() will currently do nothing for non-secure (GP)
devices but contains pertinent updates for booting on secure (HS)
devices.
Update the omap5 Makefile to include the fdt.c in the build.
Signed-off-by: Daniel Allred <d-allred@ti.com>
Signed-off-by: Madan Srinivas <madans@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Update the CPU string output so that the device
type is now included as part of the CPU string that
is printed as the SPL or u-boot comes up. This update
adds a suffix of the form "-GP" or "-HS" for production
devices, so that general purpose (GP) and high security
(HS) can be distiguished. Applies to all OMAP5 variants.
Signed-off-by: Daniel Allred <d-allred@ti.com>
Signed-off-by: Madan Srinivas <madans@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Updates the SPL build so that when CONFIG_TI_SECURE_DEVICE
is in use (which it should be when building for secure parts),
the TI secure development package is used to create a valid
secure boot image. The u-boot SPL build processes is NOT aware
of the details of creating the boot image - all of that information
is encapsulated in the TI secure development package, which is
available from TI. More info can be found in README.ti-secure
Right now, two image types are generated, MLO and X-LOADER. The types
are important, as certain boot modes implemented by the device's ROM
boot loader require one or the other (they are not equivalent). The
output filenames are u-boot-spl_HS_MLO and u-boot-spl_HS_X-LOADER. The
u-boot-spl_HS_MLO image is also copied to a file named MLO, which is
the name that the device ROM bootloader requires for loading from the
FAT partition of an SD card (same as on non-secure devices).
Signed-off-by: Daniel Allred <d-allred@ti.com>
Signed-off-by: Madan Srinivas <madans@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Tested-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Modifies the config.mk to build secure images when building
the SPL for secure devices.
Depending on the boot media, different images are needed
for secure devices. The build generates u-boot*_HS_* files
as appropriate for the different boot modes. The same u-boot
binary file is processed slightly differently to produce a
different boot image, depending on whether the user wants to
boot off SPI, QSPI or other boot media.
Refer to README.ti-secure for more information.
Signed-off-by: Madan Srinivas <madans@ti.com>
Signed-off-by: Daniel Allred <d-allred@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Tested-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Adds a centralized config_secure.mk in omap-common for
OMAP-style TI secure devices to use for boot image generation
Depending on the boot media, different images are needed for
secure devices. These commands generates u-boot*_HS_* files that
need to be used to boot secure devices.
Please refer to README.ti-secure for more information.
Signed-off-by: Daniel Allred <d-allred@ti.com>
Signed-off-by: Madan Srinivas <madans@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Tested-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Defines CONFIG_TI_SECURE_DEVICE which needs to be turned on
when building images for secure devices. This flag is used
to invoke the secure image creation tools for creating a
boot image that can be used on secure devices. This flag
may also be used to conditionally compile code specific
to secure devices.
This terminology will be used by all OMAP architecture devices,
hence introducing to a common location.
With the creation of Kconfig for omap-common, moved the
sourcing of the Kconfig files for the omap3/4/5 and am33xx
devices from arch/arm/KConfig to the omap-common one.
Signed-off-by: Madan Srinivas <madans@ti.com>
Signed-off-by: Daniel Allred <d-allred@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Tested-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Adding support for AM43xx secure devices require the addition
of some SOC specific config options like the amount of memory
used by public ROM and the address of the entry point of u-boot
or SPL, as seen by the ROM code, for the image to be built
correctly.
This mandates the addition of am AM43xx CONFIG option and the
ARM Kconfig file has been modified to source this SOC Kconfig
file. Moving the TARGET_AM43XX_EVM config option to the SOC
KConfig and out of the arch/arm/Kconfig.
Updating defconfigs to add the CONFIG_AM43XX=y statement and
removing the #define CONFIG_AM43XX from the header file.
Signed-off-by: Madan Srinivas <madans@ti.com>
Signed-off-by: Daniel Allred <d-allred@ti.com>
Tested-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Adds a new Kconfig file for AM33xx class devices. We
need a common place to define CONFIG parameters
for these SOCs, especially for adding support
for secure devices.
a) Adds a definition for ISW_ENTRY_ADDR. This is the
address to which the ROM branches when the SOC
ROM hands off execution to the boot loader.
CONFIG_SYS_TEXT_BASE and CONFIG_SPL_TEXT_BASE are set
to this value for AM43xx devices.
b) Adds CONFIG_PUB_ROM_DATA_SIZE which is used to
calculate CONFIG_SPL_MAX_SIZE. This value indicates the
amount of memory needed by the ROM to store data during
the boot process.
Currently, these CONFIG options are used only by AM43xx,
but in future other AM33xx class SOCs will also use them.
Signed-off-by: Madan Srinivas <madans@ti.com>
Signed-off-by: Daniel Allred <d-allred@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Tested-by: Andreas Dannenberg <dannenberg@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Add a psci_system_reset() which calls the SYSTEM_RESET function of
PSCI 0.2 and can be used by boards that support it to implement
reset_cpu().
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This driver supports the standard PWM API. There are 5 PWMs. Four are used
normally and the last is normally used as a timer.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Correct get_cpu_speed_grade_hz for i.MX6DQP, otherwise we
will get wrong speed grade info i.MX6DQP.
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Use simpler runtime cpu dection macros.
i.MX6DL and i.MX6SOLO work the same, so use is_mx6sdl.
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
i.MX6DL and i.MX6SOLO work the same, add i.MX6SOLO support
when enable/disable_ldb_di_clock_sources.
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Support RAM and MMC boot mode in SPL also with SPL_FIT images.
In MMC boot mode two boot options are available:
1) Boot flow with ATF(EL3) and full U-Boot(EL2):
aarch64-linux-gnu-objcopy -O binary bl31.elf bl31.bin
mkimage -A arm64 -O linux -T kernel -C none -a 0xfffe5000 -e 0xfffe5000
-d bl31.bin atf.ub
cp spl/boot.bin <sdcard fat partition>
cp atf.ub <sdcard fat partition>
cp u-boot.bin <sdcard fat partition>
2) Boot flow with full U-Boot(EL3):
cp spl/boot.bin <sdcard>
cp u-boot*.img <sdcard>
3) emmc boot mode
dd if=/dev/zero of=sd.img bs=1024 count=1024
parted sd.img mktable msdos
parted sd.img mkpart p fat32 0% 100%
kpartx -a sd.img
mkfs.vfat /dev/mapper/loop0p1
mount /dev/mapper/loop0p1 /mnt/
cp spl/boot.bin /mnt
cp u-boot.img /mnt
cp u-boot.bin /mnt
cp atf.ub /mnt
umount /dev/mapper/loop0p1
kpartx -d sd.img
cp sd.img /tftpboot/
and program it via u-boot
tftpb 10000 sd.img
mmcinfo
mmc write 10000 0 $filesize
mmc rescan
mmc part
ls mmc 0
psu_init() function contains low level SoC setup generated for every HW
design by Xilinx design tools. xil_io.h is only supporting file to fix
all dependencies from tools. The same solution was used on Xilinx Zynq.
The patch also change CONFIG_SYS_INIT_SP_ADDR to the end of OCM which
stays at the same location all the time.
Bootrom expects starting address to be at 0xfffc0000 that's why this
address is SPL_TEXT_BASE.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
MMCSD_MODE_FAT has been renamed to MMCSD_MODE_FS by commit 205b4f33.
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
MMCSD_MODE_FAT has be renmaed to MMCSD_MODE_FS by commit 205b4f33.
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
init_early_memctl_regs() is also be called in board_early_init_f().
So remove the duplicated call in spl code.
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
As the issue about the stack will get corrupted when switching between
the early and final mmu tables is fixed by commit 70e21b064, the
workaround to flush dcache is unnecessary and should be removed.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
For Qoriq PPC&ARM v7 platforms, the crypto node is being fixup'ed in
order to update the SEC internal version (aka SEC ERA). This patch
adds the same functionality to the ARMv8 SoCs.
Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Barrier transactions from CCI400 need to be disabled till
the DDR is configured, otherwise it may lead to system hang.
The patch adds workaround to fix the erratum.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The clock parent of the AHB root clock when using mux option 1
is the SYS PLL 270MHz clock. This is specified in Table 5-11
Clock Root Table of the i.MX 7Dual Applications Processor
Reference Manual.
While it could be a documentation error, the 270MHz parent is
also mentioned in the boot ROM configuration in Table 6-28: The
clock is by default at 135MHz due to a POST_PODF value of 1
(=> divider of 2).
Signed-off-by: Stefan Agner <stefan@agner.ch>
The current delays in the DDR initialization routines for am33xx
architectures are sometimes not running long enough leading to DDR
init errors. On am437x, this shows up as an L3 NOC error after the
kernel boots. This is due to the timer not being initialized
properly, but instead still containing the timer init values from
the boot ROM which cause timers to expire in 1/4th the time
required.
timer_init is typically not called until board_init_r, however on
am33xx/am43xx udelay is required in sdram_init which is called
from board_init_f, so a call to timer_init is required earlier.
Note that this issue introduced in v2015.01 by:
b352dde "am33xx: Drop timer_init call from s_init".
Although this could instead fixed by reverting said commit, it
would cause timer_init to be called twice in both SPL and non-SPL
cases. This gives a little more fine grained control and also
matches what is being done on omap-command and fsl-layerscape.
Signed-off-by: Russ Dill <russ.dill@ti.com>
Commit 724219a65f "ARM: always perform per-CPU GIC init" removed some
ifdefs to unify the MULTIENTRY-vs-non-MULTIENTRY paths. However, the
wrong endif was removed. This patch adds back that missing endif, and
adds a new ifdef to match the endif the now-correctly-terminated block
used to match against. Use "git show -U25 724219a65f55" to see enough
context to make the original issue clear.
In practical terms, this makes no difference to runtime behaviour. The
code that was incorrectly compiled into the binary when ifndef MULTIENTRY
is a no-op for other cases, since branch_if_master evaluates to a hard-
coded jump. The only issues were:
- A few extra instructions were added to the binary.
- The comment on the endif at the very end of the function, indicating
which ifdef it matched, were wrong.
An alternative might be to simply fix the comment on that trailing ifdef,
but that only addresses the second point above, not the first.
Fixes: 724219a65f ("ARM: always perform per-CPU GIC init")
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Unfortunately with this change we now are unable to do FS mode boots
from MMC1 as with the way the code works today we will always load and
assume that the hard-coded raw location contains U-Boot. Further, we
cannot fix this by just changing other logic to try FS-then-RAW as it
would also make us have to ignore what order the ROM is telling us to
try.
This reverts commit 22d90d560a.
Signed-off-by: Tom Rini <trini@konsulko.com>
ABB should be initialized for all required domains voltage domain
for DRA7: IVA, GPU, EVE in addition to the existing MPU domain. If
we do not do this, kernel configuring just the frequency using the
default boot loader configured voltage can fail on many corner lot
units and has been hard to debug. This specifically is a concern with
DRA7 generation of SoCs since other than VDD_MPU, all other domains
are only permitted to setup the voltages to required OPP only at boot.
Reported-by: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Since we setup the voltage and frequency for the MM domain, we *must*
setup the ABB configuration needed for the domain as well. If we do not
do this, kernel configuring just the frequency using the default boot
loader configured voltage can fail on many corner lot units.
Reported-by: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
ABB TX_DONE mask will vary depending on ABB module. For example,
3630 never had ABB on IVA domain, while OMAP5 does use ABB on MM domain,
DRA7 has it on all domains with the exception of CORE, RTC.
Hence, move the txdone mask definition over to structure describing
voltage domain.
Signed-off-by: Nishanth Menon <nm@ti.com>
This information is already available under vcores->volts.efuse.reg.
There is no reason for duplicating the information since AVS Class 0
definitions are common for OMAP5 and DRA7 and defined with
STD_FUSE_OPP_* macros. This allows a central location of defining
the ABB and voltage definitions especially since they are reused.
This also makes it simpler to prevent mistakes involved when changing
the boot OPP for the device.
Signed-off-by: Nishanth Menon <nm@ti.com>
Add support for Technexion's PICO-IMX6UL-EMMC board.
For information about this board, please visit:
http://www.technexion.com/products/pico/pico-som/pico-imx6-emmc
Signed-off-by: Richard Hu <richard.hu@technexion.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Due to incorrect placement of the clock gate cell in the ldb_di[x]_clk tree,
the glitchy parent mux of ldb_di[x]_clk can cause a glitch to enter the
ldb_di_ipu_div divider. If the divider gets locked up, no ldb_di[x]_clk is
generated, and the LVDS display will hang when the ipu_di_clk is sourced from
ldb_di_clk.
To fix the problem, both the new and current parent of the ldb_di_clk should
be disabled before the switch. This patch ensures that correct steps are
followed when ldb_di_clk parent is switched in the beginning of boot.
This patch was ported from the 3.10.17 NXP kernel
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/?h=imx_3.10.17_1.0.1_ga&id=eecbe9a52587cf9eec30132fb9b8a6761f3a1e6d
NXP errata number: ERR009219, EB821
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
The current code in ARMv8's lowlevel_init() skips the per-CPU GIC
initialization ifndef CONFIG_ARMV8_MULTIENTRY. However, the per-CPU init
should always occur; it's just the one-time init that should only happen
on the master.
Once this consideration is taken into account, the only difference between
the paths when CONFIG_ARMV8_MULTIENTRY is undefined/defined is the use of
branch_if_slave. Naively, any unified code would need to invoke this
conditionally upon ifdef CONFIG_ARMV8_MULTIENTRY. However, branch_if_slave
already checks CONFIG_ARMV8_MULTIENTRY and does nothing if it isn't
defined, so we don't even need that ifdef at the call site.
Reported-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
v7_maint_dcache_all() does not work reliable when build with gcc6,
see: https://bugzilla.redhat.com/show_bug.cgi?id=1318788
While debugging this I learned that v7_maint_dcache_all() is unreliable
when build with gcc5 too when it is marked as noinline.
This commit fixes the reliability issues by replacing the C-code with
the ready to use asm implementation from the kernel.
Given that this code when written as C-code clearly is quite fragile
(also see the existing comments about the C-code being the way it is
to get optimal assembly) and that we have a proven asm alternative,
I believe that this is the best solution.
Note that we actually already had a copy of the kernel's
v7_flush_dcache_all() before this commit in
arch/arm/mach-uniphier/arm32/lowlevel_init.S.
This commit moves that code arch/arm/cpu/armv7/cache_v7_asm.S, renames
it to __v7_flush_dcache_all(), and adds a v7_flush_dcache_all() wrapper
which saves / restores the clobbered registers for use from C-code.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
There are ARM SoCs (such as the BCM2837) do not contain an ARM GIC. Fix
the ARMv8 CPU startup code to compile in this case.
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
LS2080A is the primary SoC, and LS2085A is a personality with AIOP
and DPAA DDR. The RDB and QDS boards support both personality. By
detecting the SVR at runtime, a single image per board can support
both SoCs. It gives users flexibility to swtich SoC without the need
to reprogram the board.
Signed-off-by: York Sun <york.sun@nxp.com>
CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
This option enable adding new platform suport just by adding defconfig
and DTS file which will target generic configuration for SoC.
Make no sense to extend Kconfig just create a pointer between DTS and
configuration file.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This moves the sniper board from the lge to lg, in order to match the devicetree
vendor prefix already defined in the kernel.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Some of the code in arch/arm/cpu/armv7/sunxi is actually armv7 specific, while
most of it is just generic code that could as well be used on an AArch64 SoC.
Move all files that are not really tied to armv7 into a new mach-sunxi
directory.
Signed-off-by: Alexander Graf <agraf@suse.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The A83T has 3 USB PHYs: 1 for USB OTG, 1 for standard USB 1.1/2.0 host,
1 for USB HSIC.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
As the need for various magic sram pokes has shown this maybe useful
info to have. e.g. this shows one of my a23 tablets having an id of
1661 rather then the usual 1650 for the a23.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
I noticed that for certain SoC versions boot0 does a magic poke when
build for A33. I'm not aware of this actually being necessary anywhere,
but better safe then sorry.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
During secure boot, SMMU is enabled on POR by SP bootrom. SMMU needs
to be put in bypass mode in uboot to enable CAAM transcations to pass
through.
For non-secure boot, SP BootROM doesn't enable SMMU, which is in
bypass mode out of reset.
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Saksham Jain <saksham.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The qspi_cfg register is set by PBI when booting from QSPI. No need
to changing it again.
Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
SRAM is used for early stack, but kernel disables its clock on suspend.
Re-enable SRAM clock on startup, otherwise u-boot crashes on resume from suspend.
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
We currently always modify the SVC versions of registers and only support
the short descriptor PTE format.
Some boards however (like the RPi2) run in HYP mode. There, we need to modify
the HYP version of system registers and HYP mode only supports the long
descriptor PTE format.
So this patch introduces support for both long descriptor PTEs and HYP mode
registers.
Signed-off-by: Alexander Graf <agraf@suse.de>
do_set_iodelay can now be used from board files based on needs of the
platforms variation they have.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Since many platforms may need different pad configuration required
depending on variation of the platform with minor deltas, it is
easier to maintain a sub step based approach to allow for pin mux
and iodelay configuration which may depend on the platform variations
and need to be done in IO isolation.
While we retain the older __recalibrate_iodelay function which provides
a ready sequencing, __recalibrate_iodelay_start and
__recalibrate_iodelay_end may be alternatively used now and the callers
will be responsible for the correct sequencing of operations.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Based on data from EMIF configuration tool 1.1.1. Expected update for
CTRL_WKUP_EMIF1_SDRAM_CONFIG_EXT in the next revision of the tool has
been incorporated as well.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Add support for detection of SR2.0 version of DRA72x family of
processors.
Signed-off-by: Ravi Babu <ravibabu@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
If including MX7D in CONFIG_SYS_EXTRA_OPTIONS, CONFIG_ROM_UNIFIED_SECTIONS
will not effect.So move MX7D to Kconfig entry from CONFIG_SYS_EXTRA_OPTIONS to
"select MX7D" to boards using i.MX7 Dual.
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
If including MX6SX in CONFIG_SYS_EXTRA_OPTIONS, CONFIG_ROM_UNIFIED_SECTIONS
will not effect.So move MX6SX to Kconfig entry from CONFIG_SYS_EXTRA_OPTIONS to
"select MX6SX" to boards using i.MX6 SoloX.
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
This patch add support for the CCV xPress board which is equipped
with the i.MX6UL. And provides the following interfaces:
- 128MiB DDR
- UART
- I2C
- eMMC (with booting)
- Ethernet
- USB
This patch adds two build targets. One with and one without SPL. The
non-SPL version is used for loading U-Boot via USB (imx_usb_loader).
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Make the watchdog registers 16-bit wide, as they are according to TRM.
Signed-off-by: Leonid Iziumtsev <leonid.iziumtsev@se.atlascopco.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
Switch the DDR3 calibration from ad-hoc implementation of wait_for_bit()
to generic implementation of wait_for_bit().
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Configure the PMIC_STBY_REQ pin as open drain 100K according
to the design team's requirement for the PMIC_STBY_REQ pin
for i.MX 6UltraLite TO1.0.
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
To i.MX6UL, default ARM rate and AHB rate is 396M and 198M,
no need to set them.
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Since the MX6UL/SL/SX only has one DDR channel, in CCM_CCDR register
the bit[17] for mmdc_ch0 is reserved and its proper state should be 1.
When clear this bit, the periph_clk_sel cannot be set and that
CDHIPR[periph_clk_sel_busy] handshake never clears.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Acked-by: Stefano Babic <sbabic@denx.de>
In mctl_channel_init, (0x50<<26) which overflows 32bit.
It was supposed to be 0x50<<16,corrected now.
Reported-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
cpu_eth_init is no longer called for dm enabled eth drivers, this
was causing the sunxi gmac eth controller to no longer work in u-boot.
This commit fixes this by calling the clock, reset and pinmux setup
function from s_init() and enabling the phy power pin (if any) from
board_init().
The enabling of phy power cannot be done from s_init because it uses dm
and dm is not ready yet at this point.
Note that the mdelay is dropped as the phy gets enabled much earlier
now, so it is no longer needed.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Tested-by: Karsten Merker <merker@debian.org>
Tested-by: Michael Haas <haas@computerlinguist.org>
The H3 has USB0 - USB3, add support for having a USB vbus pin for USB3.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Fix a copy and paste error which caused us to use the uart rather then
the twi reset bits in clock_twi_onoff for sun9i.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
clock_sun8i_a83.c did not contain a clock_twi_onoff implementation
at all, this is fixed by moving the clock_sun6i.c implementation,
which is correct for the a83 too, to a shared location.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The clock_sun6i.c implementation was not deasserting the reset for
the regular i2c controllers, this commit fixes this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
I've had this one a23 tablet which would not boot and I've finally
figured out what the problem is by looking at the released boot0 code,
it seems the magic sram controller poke which we need to do in s_init()
depends on the revision of the a23.
Specifically this change is needed to get the A23 SoC I have with the
following serial to boot: "E6071AB 26Y7".
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Update the link script to drop this code when not needed. This is only done
for two architectures at present.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
The eSDHC could select to use platform clock or peripheral clock to
generate SD clock. The default selection is platform clock. So, fix
the clock frequency value that's calculated for eSDHC.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The serdes protocol entries in Serdes table 1 for protocol
0x03, 0x33, 0x35 and in Serdes table 2 for protocols 0x45
and 0x47 are updated to reflect the entries in
current Reference Manual.
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@nxp.com>
Reported-by: Jose Rivera <german.rivera@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Remove stream ID partitioning support that has been made
obsolete by upstream device tree bindings that specify how
representing how PCI requester IDs are mapped to MSI specifiers
and SMMU stream IDs.
Signed-off-by: Stuart Yoder <stuart.yoder@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Enable wuo config to accelerate coherent ordered writes for LS2080A
and LS2085A.
WRIOP IP is connected to RNI-20 Node.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
With commit 7985cdf we converted all systems except for the Layerscape
SoCs to the generic descriptor table based page table setup.
On the Layerscape SoCs however, we just provide an empty table stub
and do the setup ourselves. To reserve enough memory for the tables,
we need to override the default counting mechanism which would end up
with an empty table because we have no maps.
Fixes: 7985cdf
Reported-by: York Sun <york.sun@nxp.com>
CC: Alison Wang <alison.wang@nxp.com>
CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Tested-by: York Sun <york.sun@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Starting with 96e5b03 we use a linker list for partition table
information. However since we use this in SPL we need to make sure that
the SPL linker scripts include these as well. While doing this, it's
best to simply include all linker lists to future proof ourselves.
Cc: Andreas Bießmann <andreas.devel@googlemail.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reported-by: Nishanth Menon <nm@ti.com>
Tested-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
On OMAP4 platforms that also need to calculate their DDR settings we are
now getting very close to the linker limit size. Since OMAP44XX is only
seen with LPDDR2, remove some run time tests for LPDDR2 or DDR3 as we
will know that we don't have it for OMAP44XX.
Cc: Nishanth Menon <nm@ti.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Our current arm64 exception handlers all panic and never return to the
exception triggering code.
But if any handler wanted to continue execution after fixups, it would
need help from the exception handling code to restore all registers.
This patch implements that help. With this code, exception handlers on
aarch64 can successfully return to the place the exception happened (or
somewhere else if they modify elr).
Signed-off-by: Alexander Graf <agraf@suse.de>
After booting has finished, EFI allows firmware to still interact with the OS
using the "runtime services". These callbacks live in a separate address space,
since they are available long after U-Boot has been overwritten by the OS.
This patch adds enough framework for arbitrary code inside of U-Boot to become
a runtime service with the right section attributes set. For now, we don't make
use of it yet though.
We could maybe in the future map U-boot environment variables to EFI variables
here.
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Now that we have an easy way to describe memory regions and enable the MMU,
there really shouldn't be anything holding people back from running with
caches enabled on AArch64. To make sure people catch early if they're missing
on the caching fun, give them a compile error.
Signed-off-by: Alexander Graf <agraf@suse.de>
By now the code to only have a single page table level with 64k page
size and 42 bit address space is no longer used by any board in tree,
so we can safely remove it.
To clean up code, move the layerscape mmu code to the new defines,
removing redundant field definitions.
Signed-off-by: Alexander Graf <agraf@suse.de>
Now that we have nice table driven page table creating code that gives
us everything we need, move to that.
Signed-off-by: Alexander Graf <agraf@suse.de>
The MMU range table can vary depending on things we may only find
out at runtime. While the very simple ThunderX variant does not
change, other boards will, so move the definition from a static
entry in a header file to the board file.
Signed-off-by: Alexander Graf <agraf@suse.de>
The idea to generate our pages tables from an array of memory ranges
is very sound. However, instead of hard coding the code to create up
to 2 levels of 64k granule page tables, we really should just create
normal 4k page tables that allow us to set caching attributes on 2M
or 4k level later on.
So this patch moves the full_va mapping code to 4k page size and
makes it fully flexible to dynamically create as many levels as
necessary for a map (including dynamic 1G/2M pages). It also adds
support to dynamically split a large map into smaller ones when
some code wants to set dcache attributes.
With all this in place, there is very little reason to create your
own page tables in board specific files.
Signed-off-by: Alexander Graf <agraf@suse.de>
When running in EL1, AArch64 knows two page table maps. One with addresses
that start with all zeros (TTBR0) and one with addresses that start with all
ones (TTBR1).
In U-Boot we don't care about the high up maps, so just disable them to ensure
we don't walk an invalid page table by accident.
Reported-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
Based on the memory map we can determine a lot of hard coded fields of
TCR, like the maximum VA and max PA we want to support. Calculate those
dynamically to reduce the chance for pit falls.
Signed-off-by: Alexander Graf <agraf@suse.de>
Since the SAR registers are filled with garbage on cold reset, this checks for a
warm reset to assert the validity of reboot mode.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reboot mode is written to SAR memory before reboot in the form of a string.
This mechanism is supported on OMAP4 by various TI kernels.
It is up to each board to make use of this mechanism or not.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
This correctly enables the USB PHY clocks, by enabling CM_ALWON_USBPHY_CLKCTRL
and correctly setting CM_L3INIT_USBPHY_CLKCTRL's value.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
On (at least) OMAP4, the USB DPLL is required to be setup for the internal PHY
to work properly. The internal PHY is used by default with the MUSB USB OTG
controller.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
The Amazon Kindle Fire (first generation) codename kc1 is a tablet that was
released by Amazon back in 2011.
It is using an OMAP4430 SoC GP version, which allows running U-Boot and the
U-Boot SPL from the ground up.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
I2C is often enabled withing the U-Boot SPL, thus those clocks are required to
be enabled early (especially when the bootrom doesn't enable them for us).
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
This removes a duplicate reference to CM_L3INIT_USBPHY_CLKCTRLin
enable_basic_uboot_clocks. Also, a doubled whitespace is removed.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
save_omap_boot_params is called from spl_board_init in the SPL context. Thus,
there is no reason to duplicate that call on arch_cpu_init.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
There is no distinction between essential and non-essential mux configuration,
so it doesn't make sense to have an "essential" prefix.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Individual boards might provide their own emif_get_device_timings function and
use the jedec timings in their own way, hence those have to be exported.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Individual boards might provide their own emif_get_device_timings function and
use the elpidia timings in their own way, hence those have to be exported.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Individual boards might provide their own emif_get_device_details function and
use elpidia device details in their own way, hence those have to be exported.
This also wraps existing definitions with the proper ifdef logic.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
This introduces a define for the offset to the reboot reason, rather than
hardcoding it.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
This switches reboot mode handling to a string-based interface, that allows more
flexibility to set a common interface with the next generations of OMAP devices.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
To make SPL_OF_CONTROL work on ARM64 SoCs, _image_binary_end must be
defined in the linker script.
LD spl/u-boot-spl
lib/built-in.o: In function `fdtdec_setup':
lib/fdtdec.c:1186: undefined reference to `_image_binary_end'
lib/fdtdec.c:1186: undefined reference to `_image_binary_end'
make[1]: *** [spl/u-boot-spl] Error 1
make: *** [spl/u-boot-spl] Error 2
Note:
CONFIG_SPL_SEPARATE_BSS must be defined as well on ARM64 SoCs.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The newer versions of DRA7 boards has EEPROM populated with DDR
size specified in it. Moving DRA7 specific emif related settings
to board files so that emif settings can be identified based on EEPROM.
Acked-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
A few boards still use ns16550_platdata structures, but assume the structure
is going to be in a specific order. By explicitly naming each entry,
this should also help 'future-proof' in the event the structure changes.
Tested on the Logic PD Torpedo + Wireless.
I only changed a handful of devices that used the same syntax as the Logic
board. Appologies if I missed one or stepped on toes. Thanks to Derald Woods
and Alexander Graf.
Signed-off-by: Adam Ford <aford173@gmail.com>
V6: Add fix to arch/arm/cpu/armv7/am33xx/board.c
V5: Add fix to arch/arm/cpu/arm926ejs/lpc32xx/devices.c
V4: Fix subject heading
V3: Remove reg_offset out in all the structs. It was reverted out, and and if
it did exist, it would get initialized to 0 by default.
V2: I hastily copy-pasted the boards without looking at the UART number.
This addresses 3 boards that use UART3 and not UART1.
Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Early system initialization is being done before initf_dm is being called
in U-Boot. Then system will fail to boot if any of the DM enabled driver
is being called in this system initialization code. So, rearrange the
code a bit so that DM enabled drivers can be called during early system
initialization.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Given that DRA7/OMAP5 SoCs can support more than 2GB of memory,
enable interleaving for this higher memory to increase performance.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Read and write leveling can be enabled independently. Check for these
enable bits before updating the read and write leveling output values.
This will allow to use the combination of software and hardware leveling.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Commit (20fae0a - ARM: DRA7: DDR: Enable SR in Power Management Control)
enables Self refresh mode by default and during warm reset the EMIF
contents are preserved. After warm reset EMIF sees that it is idle and
puts DDR in self-refresh. When in SR, leveling operations cannot be done
as DDR can only accept SR exit command, so its hanging during warm reset.
In order to fix this reset the power management control register before
EMIF initialization if it is a warm reset.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
On DRA7, refresh ctrl shadow should be updated with
the final value.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Current AM57xx evm supports both BeagleBoard-X15
(http://beagleboard.org/x15) and AM57xx EVM
(http://www.ti.com/tool/tmdxevm5728).
The AM572x EValuation Module(EVM) provides an affordable platform to
quickly start evaluation of Sitara. ARM Cortex-A15 AM57x Processors
(AM5728, AM5726, AM5718, AM5716) and accelerate development for HMI,
machine vision, networking, medical imaging and many other industrial
applications. This EVM is based on the same BeagleBoard-X15 Chassis
and adds mPCIe, mSATA, LCD, touchscreen, Camera, push button and TI's
wlink8 offering.
Since the EEPROM contents are compatible between the BeagleBoard-X15 and
the AM57xx-evm, we add support for the detection logic to enable
support for various user programmable scripting capability.
NOTE: U-boot configuration is currently a superset of AM57xx evm and
BeagleBoard-X15 and no additional configuration tweaking is needed.
This change also sets up the stage for future support of TI AM57xx EVMs
to the same base bootloader build.
Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Many TI EVMs have capability to store relevant board information
such as DDR description in EEPROM. Further many pad configuration
variations can occur as part of revision changes in the platform.
In-order to support these at runtime, we for a board detection hook
which is available for override from board files that may desire to do
so.
NOTE: All TI EVMs are capable of detecting board information based on
early clocks that are configured. However, in case of additional needs
this can be achieved within the override logic from within the board
file.
Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Early clock initialization is currently done in two stages for OMAP4/5
SoCs. The first stage is the initialization of console clocks and
then we initialize basic clocks for functionality necessary for SoC
initialization and basic board functionality.
By splitting up prcm_init and centralizing this clock initialization,
we setup the code for follow on patches that can do board specific
initialization such as board detection which will depend on these
basic clocks.
As part of this change, since the early clock initialization
is centralized, we no longer need to expose the console clock
initialization.
NOTE: we change the sequence slightly by initializing console clocks
timer after the io settings are complete, but this is not expected
to have any functioanlity impact since we setup the basic IO drive
strength initialization as part of do_io_settings.
Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
If HDMI_IH_FC_STAT2_OVERFLOW_MASK is set, we need to
do TMDS software reset and write to clear fc_invidconf register.
We need minimum 3 times to write to clear the fc_invidconf
register, so choose 5 loops here.
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Signed-off-by: Sandor Yu <sandor.yu@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Read the number of cores in the fuses to distinguish between
the dual and solo versions.
Tested on a mx7d sabresd and on a mx7solo warp7.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Add support for GE B450v3, B650v3 and B850v3 boards. The boards
are based on Advantech BA16 module which has a i.MX6D processor.
The boards support:
- FEC Ethernet
- USB Ports
- SDHC and MMC boot
- SPI NOR
- LVDS and HDMI display
Basic information about the module:
- Module manufacturer: Advantech
- CPU: Freescale ARM Cortex-A9 i.MX6D
- SPECS:
Up to 2GB Onboard DDR3 Memory;
Up to 16GB Onboard eMMC NAND Flash
Supports OpenGL ES 2.0 and OpenVG 1.1
HDMI, 24-bit LVDS
1x UART, 2x I2C, 8x GPIO,
4x Host USB 2.0 port, 1x USB OTG port,
1x micro SD (SDHC),1x SDIO, 1x SATA II,
1x 10/100/1000 Mbps Ethernet, 1x PCIe X1 Gen2
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Now that we fall back to the FS code path when we don't find u-boot
at the raw sector offset, there is no good reason to not default to
raw boot.
With this patch, I can successfully boot u-boot from a raw sector
offset on beagle-xm.
Signed-off-by: Alexander Graf <agraf@suse.de>
This introduces some minor cleanups, regarding aspects such as board name, code
and headers organization as well as deprecated and missing config options.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
The initialization for smmu and stream id is moved into the common soc
code.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Memory controller performance is not optimal with default internal
target queue register value, write required value for optimal DDR
performance.
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Add support for phy 1-3.
Signed-off-by: Jelle van der Waa <jelle@vdwaa.nl>
[hdegoede@redhat.com: use setclrbits_le32 instead of read-modify-write]
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
In current design, if any peripheral was assigned to both A7 and M4,
it will receive ipg_stop or ipg_wait when any of the 2 platforms
enter low power mode. We will have a risk that, if A7 enter wait,
M4 enter stop, peripheral will have chance to get ipg_stop and ipg_wait
asserted same time. Also if M4 enters stop mode, A7 will have no
chance to access the peripheral.
There are 26 peripherals affected by this IC issue:
SIM2(sim2/emvsim2)
SIM1(sim1/emvsim1)
UART1/UART2/UART3/UART4/UART5/UART6/UART7
SAI1/SAI2/SAI3
WDOG1/WDOG2/WDOG3/WDOG4
GPT1/GPT2/GPT3/GPT4
PWM1/PWM2/PWM3/PWM4
ENET1/ENET2
Software Workaround:
The solution is to set the peripherals to Domain0 by A core, since A core
in Domain0. The peripherals which will be used by M4, will be set to Domain1
by M4.
For example, A core set WDOG4 to domain0, but when M4 boots up, M4 will
set WDOG4 to domain1, because M4 will use WDOG4.
So the peripherals are not shared by them. This way requires
the uboot implemented the RDC driver and set the 26 IPs above
to domain 0 only. M4 image will set the M4 to domain 1 and
set peripheral which it will use to domain 1.
This patch enables the CONFIG_IMX_RDC and CONFIG_IMX_BOOTAUX for
i.MX7D SABRESD board, and setup the 26 IP resources to domain 0.
Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Implement arch_auxiliary_core_up and arch_auxiliary_core_check_up.
arch_auxiliary_core_check_up is used to check whether M4 is running
or not. arch_auxiliary_core_up is to boot M4 core, the m4 core will
use the pc and stack which is set in arch_auxiliary_core_up to set R15
and R13 register and boot.
Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Implement arch_auxiliary_core_up and arch_auxiliary_core_check_up.
arch_auxiliary_core_check_up is used to check whether M4 is running
or not. arch_auxiliary_core_up is to boot M4 core, the m4 core will
use the pc and stack which is set in arch_auxiliary_core_up to set R15
and R13 register and boot.
Signed-off-by: Ye.Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
commit 216d286c7e [imx: mx6: implement
mmc_get_env_dev] introduced selection of the environment device according
to the boot device when booting from SD/MMC.
Extend this functionality for also selecting the device partition.
Signed-off-by: Soeren Moch <smoch@web.de>
The defconfig patch will enable the the SPL and NAND settings.
The update to Kconfig will allow the SPL to configured in and
built.
Signed-off-by: Derald D. Woods <woods.technical@gmail.com>
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Correct spelling of "U-Boot" shall be used in all written text
(documentation, comments in source files etc.).
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
Implement mmc_get_env_dev, devno can be got from smbr1 of SRC.
Introduce a weak function board_mmc_get_env_dev, different
boards can implement it according to different sdhc controllers
that used by the board.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Move mmc_get_env_devno to soc.c and rename to mmc_get_env_dev to
match the one in common/env_mmc.c.
Introduce a weak function board_mmc_get_env_dev. Different
boards can implement this according to sdhc controller which
is used by the board.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
The checking with max frequency supported is not correct, because the temp
is calculated by max pre and post dividers. We can decrease any divider to
meet the max frequency limitation. Actually, the calculation below the codes
is doing this way to find best pre and post dividers.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Wrong checking for the base_addr paramter with LCDIF1 and LCDIF2. Always
enter the -EINVAL return.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Initial version for mx6sx SABREAUTO board support with features:
PMIC, QSPI, NAND flash, SD/MMC, USB, Ethernet, I2C, IO Expander.
Signed-off-by: Ye Li <ye.li@nxp.com>
Add DDR3 calibration code for i.MX6Q, i.MX6D and i.MX6DL. This code
fine-tunes the behavior of the MMDC controller in order to improve
the signal integrity and memory stability.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
829520: Code bounded by indirect conditional branch might corrupt
instruction stream.
Workaround: Set CPUACTLR_EL1[4] = 1'b1 to disable the Indirect
Predictor.
833471: VMSR FPSCR functional failure or deadlock.
Workaround: Set CPUACTLR[38] to 1, which forces FPSCR write flush.
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
"DISCARD" will remove ._secure.text relocate, but PSCI framework
has already used some absolute address those need to relocate.
Use readelf -t -r u-boot show us:
.__secure_start addr: 601408e4
.__secure_end addr: 60141460
60141140 00000017 R_ARM_RELATIVE
46 _secure_monitor:
47 #ifdef CONFIG_ARMV7_PSCI
48 ldr r5, =_psci_vectors
60141194 00000017 R_ARM_RELATIVE
6014119c 00000017 R_ARM_RELATIVE
601411a4 00000017 R_ARM_RELATIVE
601411ac 00000017 R_ARM_RELATIVE
64 _psci_table:
66 .word psci_cpu_suspend
...
72 .word psci_migrate
60141344 00000017 R_ARM_RELATIVE
6014145c 00000017 R_ARM_RELATIVE
202 ldr r5, =psci_text_end
Solutions:
1. Change absolute address to RelAdr.
Based on LDR (immediate, ARM), we only have 4K offset to jump.
Now PSCI code size is close to 4K size that is LDR limit jump size,
so even if the LDR is based on the current instruction address,
there is also have a risk for RelAdr. If we use two jump steps I
think we can fix this issue, but looks too hack, so give up this way.
2. Enable "DISCARD" only for CONFIG_ARMV7_SECURE_BASE has defined.
If CONFIG_ARMV7_SECURE_BASE is defined in platform, all of secure
will in the BASE address that is absolute.
Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Add code to aid tracking down cache alignment issues.
In case DEBUG is defined in the cache.c, this code will
check alignment of each attempt to flush/invalidate data
cache and print a warning if the alignment is incorrect.
If DEBUG is not defined, this code is optimized out.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@konsulko.com>
eth_get_dev_by_index() is an API which is not available in driver
model. Use eth_get_dev_by_name() instead, which can also simplifly
the code logic a little bit.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
QSPI and IFC are pin-multiplexed on LS1043A. So we use
ls1043aqds_sdcard_ifc_defconfig to support IFC in SD boot and
ls1043aqds_sdcard_qspi_defconfig to support QSPI in SD boot.
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Chain of Trust is enabled for ARM platforms (LS1021 and LS1043).
In board_late_init(), fsl_setenv_chain_of_trust() is called which
will perform the following:
- If boot mode is non-secure, return (No Change)
- If boot mode is secure, set the following environmet variables:
bootdelay = 0 (To disable Boot Prompt)
bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script)
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Remove SECURE_IOU option which is not needed. U-Boot itself can detect
which EL level it is on and based on that use do platform setup.
It also simplify usage because one Kconfig entry is gone.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Banana-pi M3 has LPDDR3 DRAM. this adds support for LPDDR3 for A83T.
Mostly the timing parameters are different from DDR3.
Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Different A83T boards have different DRAM types. Banapi M3 has LPDDR3,
Allwinner Homlet v1.2 has DDR3.
This adds groundwork to support for new DRAM type for A83T.
Introduce CONFIG_DRAM_TYPE, It'll be 3 for DDR3 and 7 for LPDDR3, must
be set in respective board defconfig.
Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This removes the redundant lines of code from mctl_sys_init.
Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
H3 has the same power sequencing procedure as the A31/A31s, which
includes the power clamps.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
H3's CCU includes some switches which disable non-secure access to some
of the more critical clock controls, such as MBUS, PLLs, and main
platform busses.
Configure them to enable non-secure access.
For now the only SoC that has this feature is the H3. For other
platforms just use a default (weak) empty function so things do
not break.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Secure Memory Touch Arbiter is the same thing as the TrustZone
Protection Controller found on A31/A31s.
Access to many peripherals on the H3 can be controlled by the SMTA,
and the settings default to secure access only.
This patch supports the new settings, and sets them to allow non-secure
access.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
LS2080A has support for 8 DPMAC ports out of which
only 5 ports can be used at a time.
Enabling all 8 DPMAC ports of LS2080A personality.
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Acked-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Updated the default sata register values to enhance the
performance and stability.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
SYSCLK frequency is dependent on on-board switch settings. It may
vary as per requirement. boot-loader is aware of board switch
configurations.
So Fixup Linux device tree from boot-loader.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
CC: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: York Sun <york.sun@nxp.com>
The management data input/output (MDIO) requires open-drain,
i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports
this feature. So to TO1.1, need to enable open drain by setting
bits GPR0[8:7] for TO1.1.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Check "Figure 19-5. BUS clock generation" of i.MX 6SoloX Applications
Processor Reference Manual and "Figure 18-5. BUS clock generation" of
i.MX 6UltraLite Applications Processor Reference Manual. If mmdc clk
sources from pll4_main_clk(pll_audio), the calculation is wrong.
Fix mmdc_ch0 clk calculation. Also add PLL_AUDIO/VIDEO support
for decode_pll.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jelle van der Waa <jelle@vdwaa.nl>
[hdegoede@redhat.com: Minor cleanups]
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
applied with fixing 2 checkpatch warnings:
WARNING: please, no space before tabs
Signed-off-by: Heiko Schocher <hs@denx.de>
To prepare timer driver to DM/DT conversion do not build the
exiting timer driver when CONFIG_TIMER is defined. But since
omap's SPL doesn't support DM yet so built timer driver only for
SPL build when CONFIG_TIMER is defined.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
This commit adds functions issuing calls to secure monitor or
hypervisore. This allows using services such as Power State
Coordination Interface (PSCI) provided by firmware, e.g. ARM
Trusted Firmware (ATF)
The SMC call can destroy all registers declared temporary by the
calling conventions. The clobber list is "x0..x17" because of
this
Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com>
Signed-off-by: Corey Minyard <cminyard@mvista.com>
Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
This patch adds code which sets up 2-level page tables on ARM64 thus
extending available VA space. CPUs implementing 64k translation
granule are able to use direct PA-VA mapping of the whole 48 bit
address space.
It also adds the ability to reset the SCTRL register at the very beginning
of execution to avoid interference from stale mappings set up by early
firmware/loaders/etc.
Signed-off-by: Sergey Temerkhanov <s.temerkhanov@gmail.com>
Signed-off-by: Radha Mohan Chintakuntla <rchintakuntla@cavium.com>
For NXP LPC32xx boards the change enables SPL_DM option, this allows
to use any driver model UART driver in SPL images, hence a restriction
on HSUART in SPL image is removed and well as definitions for non-DM
NS16550 driver, its DM version is used instead.
Because SPL_DM requires malloc(), enable CONFIG_SPL_SYS_MALLOC_SIMPLE
for LPC32xx boards.
The change adds about 5KB to the resulting SPL image (for devkit3250
board SPL image is increased from 10672 to 15608 bytes).
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
On NXP LPC32xx platform for non-SPL builds the change adds
standard (NS16550) and high-speed UARTs to driver model.
Due to specific of DM NS16550 device description UART clock can not be
got in runtime and by default it is set to 13MHz, if board PERIPH_CLK
is different, this should be specified in board configuration file.
For SPL builds HSUARTs are disabled and non-DM NS16550 driver is
compiled, if needed.
The change also updates default configs of devkit3250 and work_92105
boards to reflect updates in platform files.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
On these platforms we have many cases of boards that enable device model
and GPIO support but do not enable OF_CONTROL and pass in a device tree
with the binary. We need to bring in the platform data here as well.
Tested on Beaglebone Black.
Reported-by: Robert Nelson <robertcnelson@gmail.com>
Reported-by: Francisco Aguerre <franciscoaguerre@gmail.com>
Reported-by: Jason Kridner <jkridner@beagleboard.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
For some board designs, it might be useful to switch the DC-DC
clock source to something else rather the default 24 MHz, e.g.
for EMI reasons.
For this, override the mxs_power_setup_dcdc_clocksource function
in your board support files.
Example:
void mxs_power_setup_dcdc_clocksource(void)
{
mxs_power_switch_dcdc_clocksource(POWER_MISC_FREQSEL_20MHZ);
}
Signed-off-by: Michael Heimpold <mhei@heimpold.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
Consecutive write transactions from core to PCI express outbound
path hangs after 25 to 30 transactions depending on core freq.
This erratum enable the mbist clock through COP register setting.
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Freescale ARM-based Layerscape contains a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds SATA feature on ls2080aqds, ls2080ardb and
ls1043aqds boards.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
For LS1043, SEC read/writes are made snoopable by setting
the corresponding bits in SCFG to avoid coherency issues.
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
usec2ticks() function has been defined for ARMv8 which will
be used by SEC Driver.
Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
MC and debug server are not board-specific. Move reserving memory to SoC
file, using the new board_reserve_ram_top function. Reduce debug server
memory by 2MB to make room for secure memory.
In the system with MC and debug server, the top of u-boot memory
is not the end of memory. PRAM is not used for this reservation.
Signed-off-by: York Sun <yorksun@freescale.com>
DDR has been set as secure in MMU tables. Non-secure master such
as SDHC DMA cannot access data correctly. Mixing secure and non-
secure MMU entries requirs the MMU tables themselves in secure
memory. This patch moves MMU tables into a secure DDR area.
Early MMU tables are changed to set DDR as non-secure. A new
table is added into final MMU tables so secure memory can have
2MB granuality.
gd->secure_ram tracks the location of this secure memory. For
ARMv8 SoCs, the RAM base is not zero and RAM is divided into several
banks. gd->secure_ram needs to be maintained before using. This
maintenance is board-specific, depending on the SoC and memory
bank of the secure memory falls into.
Signed-off-by: York Sun <yorksun@freescale.com>
As the errata A008336 and A008514 do not apply to all LS series SoCs
(such as LS1021A, LS1043A) we move them to an soc specific file
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This is a workaround for hardware erratum.
Write the value of 63b2_0042h to EDDRTQCFG will optimal the
memory controller performance.
The value: 63b2_0042h comes from the hardware team.
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Enable snoop and DVM message on all CCI-400 slave ports. Setting
on disabled feature (snoop or DVM) is ignored by CCI-400.
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
[York Sun: Add commit message]
Reviewed-by: York Sun <yorksun@freescale.com>
Since the changes in a1e56cf the way that we had board_mmc_init()
structured for OMAP parts (so that we always report device 0) are no
longer functional. For now, make the case of booting from the second
device initialize both devices (we have no devices that only have the
second device as MMC). A further rework and consolidation of the
functions should be done at a later date.
Tested on Beaglebone Black (SD and eMMC boot).
Reported-by: Vagrant Cascadian <vagrant@debian.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Enable the IP feature's snoop signal to support
hardware snoop for cache coherence.
SNPCNFGCR contains the bits to drive snoop signal
for various masters.
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Create a soc.c file to put the code for soc special settings.
Signed-off-by: Yuan Yao <yao.yuan@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
GCC 5.x does not like sizeof(array_variable) and errors out. Change these
calls to be instead sizeof(u8) (as that's what serdes_prtcl_map is) *
SERDES_PRCTL_COUNT (the number of array elements).
Cc: York Sun <yorksun@freescale.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch fixes the DDR3 initialization procedure in
order to comply with DDR3 standard. A 500 us delay is specified
between the DDR3 reset and clock enable signal. Until now,
this delay was not respected. Some DDR3 chips don't bother
but the bigger the RAM becomes the more likely it seems that
this delay is needed. We observed that DRAM > 256 MB from
the manufacturer Samsung have an issue when the specification
is not respected.
Changes:
1) Add a 1 ms wait for L3 timeout error trigger
2) Don't delay DDR3 initialization
Bit 31 of emif_sdram_ref_ctrl shouldn't be set because his
suppresses the initialization of DDR3
Signed-off-by: Samuel Egli <samuel.egli@siemens.com>
Reviewed-by: James Doublesin <doublesin@ti.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Felipe Balbi <balbi@ti.com>
Cc: Roger Meier <r.meier@siemens.com>
Cc: Heiko Schocher <hs@denx.de>
The read delays were set incorrectly, leading to reliability
issues at higher DRAM clock speeds. This commit adjusts this
to match the vendor boot0 behaviour.
Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Tested-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Add some spaces around operators.
Signed-off-by: Olliver Schinagl <o.schinagl@ultimaker.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Commit 6c739c5d added code to enable i2c bus 4 and 5 on the sun7i SoC
but forgot to extend the range check in clock_twi_onoff, resulting in
the clock not getting enabled.
The range-check is not needed at all, since clock_twi_onoff only gets
called with such high indexes when CONFIG_I2C3_ENABLE / CONFIG_I2C4_ENABLE
is set and Kconfig already only allows these on sun6i / sun7i.
This commit removes the range-check all together fixing i2c bus 4 and 5
not working on sun7i.
Signed-off-by: Olliver Schinagl <o.schinagl@ultimaker.com>
[hdegoede@redhat.com] Remove range check instead of extending it
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Add support for A83T dram. Register are different from sun8i A33.
init code is similar to A33 dram init.
hope we'll shift duplicate code in dram_sun8i_*
to dram helper in future.
Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Add basic clocks pll1, pll5, and some default values from allwinner u-boot.
Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
[hdegoede@redhat.com] Fix PLL6 init to run at 600 MHz instead of 288 MHz,
fixing the mmc support not working
[hdegoede@redhat.com] Fix PLL init code to properly wait for the PLL-s to
stabilize, fixing cold-booting directly from sdcard not working
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Enabled support for AXP818 in SPL and u-boot.
DCDC1, DCDC2, DCDC3 and DCSC5 are enabled.
Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
On A83T, PB9,PB10 are UART0 pins.
On allwinner A83T Dev board(h8homlet), this uart0 serial connector
is exposed.
Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Allwinner A83T is octa-core cortex-a7 SOC.
This enables support for A83T.
SMP is not yet supported.
Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
We now want to make sure that we have the platform data for NS16550 when
we do not have OF_CONTROL set.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
With gcc-5.x we get warning about inline non-static functions referring to
static elements.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
At the moment, the desired brownout is at 1.0V. However,
this setting cannot be realized by hardware since we have
only 3 bits to represent the voltage difference from the
target value.
Target value is 1500 mV, brownout target is 1000 mV,
voltage steps are 25 mV.
Register content calculation:
(1500 [mV] - 1000 [mV]) / 25 [mV] = 20 (decimal) = 0x14
Register takes only 3 bits, that is 0x4.
But 0x4 * 25 [mV] = 100 [mV], that means that actual
brownout level is 1500 [mV] - 100 [mV] = 1.4 V.
Minimum possible BO level is
1500 [mV] - 0x7 * 25 [mV] = 1315 [mV].
So lets use this value as desired BO value (which is
also the same as FSL bootlets use).
Signed-off-by: Michael Heimpold <mhei@heimpold.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
If the core runs at higher than x3 speed of the platform, there is
possiblity about sev instruction to getting missed by other cores.
This is because of SoC Run Control block may not able to sample
the EVENTI(Sev) signals.
Configure Run Control and EPU to periodically send out EVENTI signals to
wake up A57 cores.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
When one core is released, other cores may not have valid entry
address. Those cores are trapped by "wfe" and wait for further
instruction. When their address is set, they need to be kicked
off by "sev".
Signed-off-by: York Sun <yorksun@freescale.com>
For most device addresses excution shouldn't be allowed. Revise
the MMU table to enforce execute-never bits. OCRAM, DDR and IFC
are allowed for excution.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reported-by: Zhichun Hua <zhichun.hua@freescale.com>
The global_data pointer (gd) has been set earlier in crt0_64.S.
So there's no need to assign it again. Remove gdata since it is going
away in U-Boot.
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Freescale's LS2085A is a another personality of LS2080A SoC with
support of AIOP and DP-DDR.
This Patch adds support of LS2085A Personality.
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: Updated MAINTAINERS files
Dropped #ifdef in cpu.h
Add CONFIG_SYS_NS16550=y in defconfig]
Reviewed-by: York Sun <yorksun@freescale.com>
LS2080A is a prime personality of Freescale’s LS2085A. It is a non-AIOP
personality without support of DP-DDR, L2 switch, 1588, PCIe endpoint etc.
So renaming existing LS2085A code base to reflect LS2080A (Prime personality)
Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
[York Sun: Dropped #ifdef in cpu.c for cpu_type_list]
Reviewed-by: York Sun <yorksun@freescale.com>
Management complex Firmware, DPL and DPC are depolyed during u-boot boot
sequence.
Add new DPAA2 commands to manage Management Complex (MC) i.e. start mc, aiop
and apply DPL from u-boot command prompt.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Current implementation only consider SGMIIs for dpmac initialization.
XFI serdes protocols also uses dpmac.
Also, fix lane protocol parsing logic to consider both XFIs and SGMIIs.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch addresses a problem mentioned recently on this mailing list:
[1].
In that posting a LS1021 based system was locking up at about 5 minutes
after boot,but the problem was mysteriously related to the toolchain
used for building u-boot.Debugging the problem reveals a stuck
interrupt 29 on the GIC.
It appears Freescale's LS1021 support in u-boot erroneously sets the
64-bit ARM generic PL1 physical time CompareValue register to all-ones
with a 32-bit value.This causes the timer compare to fire 344 seconds
after u-boot configures it.Depending on how fast u-boot gets the
kernel booted,this amounts to about 5-minutes of Linux uptime before
locking up.
Apparently the bug is masked by some toolchains. Perhaps this is
explained by default compiler options, word sizes, or binutils versions.
To fix the above issue, the generic physical timer is disabled
before jumping to the OS.
[1]
https://lists.yoctoproject.org/pipermail/meta-freescale/2015-June/014400.html
Signed-off-by: Chris Kilgour <techie@whiterocker.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch addresses a problem mentioned recently on this mailing list:
[1].
In that posting a LS1021 based system was locking up at about 5 minutes
after boot, but the problem was mysteriously related to the toolchain
used for building u-boot. Debugging the problem reveals a stuck
interrupt 29 on the GIC.
It appears Freescale's LS1021 support in u-boot erroneously sets the
64-bit ARM generic PL1 physical time CompareValue register to all-ones
with a 32-bit value. This causes the timer compare to fire 344 seconds
after u-boot configures it. Depending on how fast u-boot gets the
kernel booted, this amounts to about 5-minutes of Linux uptime before
locking up.
Apparently the bug is masked by some toolchains. Perhaps this is
explained by default compiler options, word sizes, or binutils versions.
At any rate this patch makes the manipulation explicitly 64-bit which
alleviates the issue.
[1]
https://lists.yoctoproject.org/pipermail/meta-freescale/2015-June/014400.html
Signed-off-by: Chris Kilgour <techie@whiterocker.com>
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
On mx6sx, the CCM register bits for GPMI are different as other
mx6 platforms. Modify the GPMI clock function to support mx6sx.
Signed-off-by: Ye.Li <B37916@freescale.com>
Congatec has several MX6 boards based on quad, dual, dual-lite and solo.
Add SPL support so that all the variants can be supported
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
serial_init() reads global_data, since global_data is not yet
initialized, this can cause unwanted behaviour leading to QSPI XIP boot
hang. Also, since serial_init() is anyways called later from
boar_init_f(), it does not make sense to do the same in s_init().
Tested on AM437x IDK EVM with QSPI XIP boot.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
The 3.4 kernel from the Allwinner SDK is clocking AHB1 at 200MHz
on Allwinner H3 and using PLL6 as the clock source (PLL6/3).
This can be verified by reading the value of the AHB1_APB1_CFG_REG
register via /dev/mem. It always reads as 0x3180 regardless of
the current cpufreq operating point. So this configuration should
be safe for use in U-Boot too.
PLL6 also needs to be configured before it is used as the clock
source, according to the "CCU / Programming Guidelines" section
of the Allwinner manual.
The current low AHB1 clock speed is limiting the USB transfer
speed when booting via FEL. This patch can increase the FEL USB
transfer speed from ~510 KB/s to ~950 KB/s.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Based on existing A23/A33 code and the original H3 boot0.
Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Add initial sun8i H3 support, only uart + mmc are supported for now.
Signed-off-by: Jens Kuske <jenskuske@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Put jump trampoline to TCM at 0 and setup R5 reset address to 0.
Jump trampoline ensures that jump to the right location.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Currently the mmc device that SPL looks at is always mmc0, regardless
of the BOOT_DEVICE_MMCx value. This forces some boards to
implement hacks in order to boot from other mmc devices.
Make SPL take into account the correct mmc device.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Reviewed-by: Tom Rini <trini@konsulko.com>
Make spl_*_load_image() functions return a value instead of
hanging if a problem is encountered. This enables main spl code
to make the decision whether to hang or not, thus preparing
it to support alternative boot devices.
Some boot devices (namely nand and spi) do not hang on error.
Instead, they return normally and SPL proceeds to boot the
contents of the load address. This is considered a bug and
is rectified by hanging on error for these devices as well.
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Tom Rini <trini@konsulko.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Ian Campbell <ijc@hellion.org.uk>
Cc: Hans De Goede <hdegoede@redhat.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Jagan Teki <jteki@openedev.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
BeagleBoard X15 (http://beagleboard.org/x15) support in u-boot does
actually support two different platform configuration offered by
TI. In addition to BeagleBoard X15, it also supports the TMDXEVM5728
(or more commonly known as AM5728-evm).
Information about the TI AM57xx EVM can be found here
http://www.ti.com/tool/tmdxevm5728
The EVM configuration is 1-1 compatible with BeagleBoard X15 with the
additional support for mPCIe, mSATA, LCD, touchscreen, Camera, push
button and TI's wlink8 offering.
Hence, we rename the beagle_x15 directory to am57xx to support TI
EVMs that use the AM57xx processor. By doing this we have common code
reuse. This sets the stage to have a common u-boot image solution for
multiple TI EVMs such as that already done for am335x and am437x. This
sets the stage for upcoming multiple TI EVMs that share the same code
base.
NOTE: Commit eae7ae1853 ("am437x: Add am57xx_evm_defconfig using
CONFIG_DM") introduced DT support for beagle_x15 under am57xx_evm
platform name. However, this ignored the potential confusion arising for
users as a result. To prevent this, existing beagle_x15_defconfig is
renamed as am57xx_evm_nodt_defconfig to denote that this is the "non
device tree" configuration for the same platform. We still retain
am57xx-beagle-x15.dts at this point, since we just require the common
minimum dts.
As a result of this change, users should expect changes in build
procedures('make am57xx_evm_nodt_defconfig' instead of 'make
beagle_x15_defconfig'). Hopefully, this would be a one-time change.
Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
Signed-off-by: Schuyler Patton <spatton@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
We need to power down lcdif before uboot reset to make reset can pass
stress test.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Implement mxs_set_lcdclk, enable_lcdif_clock and enable_pll_video.
The three API can be used to configure lcdif related clock when
CONFIG_VIDEO_MXS enabled.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Change mxs_set_lcdclk prototype to add a new parameter
base_addr. There are two LCD interfaces for i.MX6SX,
we may support LCDIF1 or LCDIF2.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Anatolij Gustschin <agust@denx.de>
Acked-by: Anatolij Gustschin <agust@denx.de>
1. add basic psci support for imx7 chip.
2. support cpu_on and cpu_off.
3. switch to non-secure mode when boot linux kernel.
4. set csu allow accessing all peripherial register in non-secure mode.
Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
The code such as PSCI in section named secure is bundled with
u-boot image, and when bootm, the code will be copied to their
runtime address same to compliation/linking address -
CONFIG_ARMV7_SECURE_BASE.
When compile the PSCI code and link it into the u-boot image,
there will be relocation entries in .rel.dyn section for PSCI.
Actually, we do not needs these relocation entries.
If still keep the relocation entries in .rel.dyn section,
r0 at line 103 and 106 in arch/arm/lib/relocate.S may be an invalid
address which may not support read/write for one SoC.
102 /* relative fix: increase location by offset */
103 add r0, r0, r4
104 ldr r1, [r0]
105 add r1, r1, r4
106 str r1, [r0]
So discard them to avoid touching the relocation entry in
arch/arm/lib/relocate.S.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Tom Warren <twarren@nvidia.com>
Cc: York Sun <yorksun@freescale.com>
Cc: Hans De Goede <hdegoede@redhat.com>
Cc: Ian Campbell <ijc@hellion.org.uk>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@konsulko.com>
Cc: Jan Kiszka <jan.kiszka@siemens.com>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
In order for noncached_init() to operate correctly, SoCs must set up a
custom page table with fine-grained (2MiB) sections, which can be
configured from noncached_init().
This is currently performed by arch/arm/cpu/armv8/{fsl-lsch3,zynqmp}/cpu.c
by cut/pasting and re-implementing mmu_setup, enable_caches(), etc. There
are some other reasons for the duplication there though, such as enabling
icache early, and enabling dcaching earlier with a different configuration.
This change makes mmu_setup() a weak implementation, so that the MMU setup
code can be replaced without having to duplicate other code that calls it.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Old sector number is not being cleared from FLASH_CR register. For example
when first erased sector was 001 and then you want to erase sector 010,
sector 011 gets erased instead.
This patch clears old sector number from FLASH_CR register before a new
one is written.
Signed-off-by: Vadzim Dambrouski <pftbest@gmail.com>
flash_lock call is inside a for loop, so after the first iteration flash
is locked and no more sectors can be erased.
Move flash_lock out of the loop.
Signed-off-by: Vadzim Dambrouski <pftbest@gmail.com>
After consulting with some of the SPDX team, the conclusion is that
Makefiles are worth adding SPDX-License-Identifier tags too, and most of
ours have one. This adds tags to ones that lack them and converts a few
that had full (or in one case, very partial) license blobs into the
equivalent tag.
Cc: Kate Stewart <kstewart@linuxfoundation.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
When building a Thumb-1-only target with CONFIG_SYS_THUMB_BUILD,
some files fail to build, most of the time because they include
mcr instructions, which only exist for Thumb-2.
This patch introduces a Kconfig option CONFIG_THUMB2 and uses
it to select between Thumb-2 and ARM mode for the aforementioned
files.
Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net>
The CPU name for Exynos was concatenated with cpu id,
but for new Exynos platforms, like Chromebook Peach Pi
based on Exynos5800, the name of SoC variant does not
include the real SoC cpu id (0x5422).
For such case, the CPU name should be defined in device tree.
This commit introduces new device-tree property for Exynos:
- "cpu-model" - with cpu name string
If defined, then the cpu id is not printed.
Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Rework unified section macro select via Kconfig option
instead of macro definition in mx7_common header file.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Add CONFIG_ROM_UNIFIED_SECTIONS for mx6sx and mx6ul target
platforms to resolve corresponding HAB_RVT_BASE base address,
the RVT table contains pointers to the HAB API functions in
ROM code.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Rework secure boot support for imx6, move existing hab support
for imx6 into imx-common for SoC reuse.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Move common chip revision id's to main cpu header file
mx25 generic include cpu header for chip revision
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Freescale ARM-based Layerscape LS102xA contain a SATA controller
which comply with the serial ATA 3.0 specification and the
AHCI 1.3 specification.
This patch adds SATA feature on ls1021aqds and ls1021atwr boards.
Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
After the secondary cores enter U-Boot, use CONFIG_ARMV8_MULTIENTRY to
make secondary cores excute in spin loop.
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch adds esdhc support for ls1043ardb.
Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
LS1043ARDB Specification:
-------------------------
Memory subsystem:
* 2GByte DDR4 SDRAM (32bit bus)
* 128 Mbyte NOR flash single-chip memory
* 512 Mbyte NAND flash
* 16 Mbyte high-speed SPI flash
* SD connector to interface with the SD memory card
Ethernet:
* XFI 10G port
* QSGMII with 4x 1G ports
* Two RGMII ports
PCIe:
* PCIe2 (Lanes C) to mini-PCIe slot
* PCIe3 (Lanes D) to PCIe slot
USB 3.0: two super speed USB 3.0 type A ports
UART: supports two UARTs up to 115200 bps for console
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Freescale LayerScape with Chassis Generation 2 is a set of SoCs with
ARMv8 cores and 2rd generation of Chassis.
Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
There are two LS series processors are built on ARMv8 Layersacpe
architecture currently, LS2085A and LS1043A. They are based on
ARMv8 core although use different chassis, so create fsl-layerscape
to refactor the common code for the LS series processors which also
paves the way for adding LS1043A platform.
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Hou Zhiqiang <B48286@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Enable snooping for CAAM read & write transactions by
programming the SCFG snoop configuration register:
SCFG_SNPCNFGCR[SECRDSNP]
SCFG_SNPCNFGCR[SECWRSNP]
Signed-off-by: Horia Geantă <horia.geanta@freescale.com>
Reviewed-by: Zhengxiong Jin <Jason.Jin@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
As QSPI/DSPI and IFC are pin multiplexed, IFC is disabled
in SD boot for QSPI. This patch will add fdt support for
this rule.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Pointer 'reg' returned from call to function 'fdt_getprop' may be
NULL, will be passed to function and may be dereferenced there by
passing argument 1 to function 'of_read_number'. So check pointer
'reg' first.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Since there is a common function to grab the serial number from the die id bits,
it makes sense have one to parse that serial number and feed it to the serial
ATAG.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
This introduces omap_die_id_display to display the full die id.
There is no need to store it in an environment variable, that no boot script
is using anyway.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
Now that we have a common prototype to grab the omap die id, functions to figure
out a serial number and usb ethernet address can use it directly.
Those also get an omap_die_id prefix for better consistency.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
This introduces omap5 support for omap_die_id, which matches the common
omap_die_id definition. It replaces board-specific code to grab the die id bits.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
This introduces omap4 support for omap_die_id, which matches the common
omap_die_id definition. It replaces board-specific code to grab the die id bits.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
This replaces the previous get_dieid definition with omap_die_id, that matches
the common omap_die_id definition.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
This introduces a common definition for omap_die_id, that aims at providing a
common interface for accessing omap platform's die id bits.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
So far, even if CONFIG_MMC was not enabled the board code was trying to use
the MMC-related functions, resulting in linker errors.
Protect those calls by an ifdef.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Stop prefixing the axp functions for setting voltages, etc. with the
model number, there ever is only one pmic driver built into u-boot,
this allows simplifying the callers.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
common/dlmalloc.c is quite big, both in .text and .data usage. E.g. for a
Mele_M9 sun6i board build this reduces .text from 0x4214 to 0x3b94 bytes,
and .data from 0x54c to 0x144 bytes.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Reviewed-by: Tom Rini <trini@konsulko.com>
For EL3 and EL2, the documentation says that bits 31 and 23 are reserved
but should be written as 1.
For EL1, only bit 23 is not reserved, so only write bit 31 as 1.
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Since commit 623d96e89aca6("imx: wdog: correct wcr register settings")
issuing a 'reset' command causes the system to hang.
Unlike i.MX and Vybrid, the watchdog controller on LS102x is big-endian.
This means that the watchdog on LS1021 has been working by accident as
it does not use the big-endian accessors in drivers/watchdog/imx_watchdog.c.
Commit 623d96e89aca6("imx: wdog: correct wcr register settings") only
revelead the endianness problem on LS102x.
In order to fix the reset hang, introduce a reset_cpu() implementation that
is specific for ls102x, which accesses the watchdog WCR register in big-endian
format. All that is required to reset LS102x is to clear the SRS bit.
This approach is a temporary workaround to avoid a regression for LS102x
in the 2015.10 release. The proper fix is to make the watchdog driver
endian-aware, so that it can work for i.MX, Vybrid and LS102x.
Reported-by: Sinan Akman <sinan@writeme.com>
Tested-by: Sinan Akman <sinan@writeme.com>
Reviewed-by: Wolfgang Denk <wd@denx.de>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Execution branches on feedback mode are swapped, this has no effect
if default direct mode is on (then p_div is equal to 1 and Fout equals
to Fcco), that's why the problem remained unnoticed for a long time.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
We run 4 Arndale boards in our automated test framework, they have
been running quite happily for quite some time using a Debian Wheezy
userspace.
However when upgrading to a Debian Jessie we started seeing frequent
segmentation faults from gcc when building the kernel, to the extent
that it is unable to successfully build the kernel twice in a row, and
often fails on the first attempt.
Searching around I found https://bugs.launchpad.net/arndale/+bug/1081417
which pointed towards http://www.spinics.net/lists/kvm-arm/msg03723.html
and CPU Errata 773022 and 774769.
This errata needs to be applied to all processors in an SMP system,
meaning that the usual strategy of applying them in
arch/arm/cpu/armv7/start.S is not appropriate (since that applies to
the boot processor only). Instead we apply these errata in the secure
monitor which is code that is traversed by all processors as they are
brought up.
The net affect on Arndale is that ACTLR changes from 0x40 to
0x2000042. I ran 17 kernel compile iterations overnight with no
segfaults.
Runtime testing was done on our v2014.10 based branch and forward
ported (with only minimal and trivial contextual conflicts) to current
master, where it has been build tested only.
I suppose in theory these errata apply to any Exynos5250 based boards,
but Arndale is the only one I have access to and I have therefore
chosen to be conservative and only apply it there.
Also, reorder CONFIG_ARM_ERRATA_794072 in README to make the list
numerically sorted.
Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
We should follow 'read->set/clr bit->write' flow for enable_fec_anatop_clock,
otherwise we may overridden configuration before enable_fec_anatop_clock.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Cc: Fabio Estevam <fabio.estevam@freescale.com>
This patch extends the misc_init_r() function on sunxi boards
to test for the presence of a suitable "sunxi" SPL header. If
found, and the loader ("fel" utility) provided a non-zero value
for the boot.scr address, then the corresponding environment
variable fel_scriptaddr gets set.
misc_init_r() also sets (or clears) the "fel_booted" variable depending
on the active boot device, using the same logic as spl_boot_device().
The goal is to provide sufficient information (within the U-Boot
environment) to make intelligent decisions on how to continue the boot
process, allowing specific customizations for the "FEL boot" case.
Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
crt0.S will both memset the bss sectioan and call board_init_r for us,
so there is no need to do either ourselves.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
drop select CPU_V7 for board target, since ARCH_MX7 selects CPU_V7.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Some platforms have the means to determine the counter frequency at
runtime, so give them an opportunity to do so.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This arch does not seem to be supported / used at all in the current
U-Boot mainline source tree any more. So lets remove the core u8500 code
and code that was only referenced by this platform.
Please note that this patch also removes these config options:
- CONFIG_PL011_SERIAL_RLCR
- CONFIG_PL011_SERIAL_FLUSH_ON_INIT
As they only seem to be referenced by u8500 based boards. Without any
such board in the current code, these config option don't make sense
any more. Lets remove them as well.
If someone still wants to use this platform, then please send patches
to re-enable support by adding at least one board that references this
code.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: John Rigby <john.rigby@linaro.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Discard the 'select CPU_V7' from Kconfig in arch/arm/cpu/armv7/mx6
for different targets, because ARCH_MX6 selects CPU_V7.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
This patch is to support mx6ul_9x9_evk board based on mx6ul_14x14_evk,
the difference between mx6ul 9x9 evk and mx6ul 14x14 evk are:
1. mx6ul 9x9 evk use pfuze3000, while mx6ul 14x14 evk use DCDC.
2. mx6ul 9x9 evk supports 256MB LPDDR2, while mx6ul 14x14 evk
supports 512MB DDR3
3. mx6ul_9x9_evk use 9x9 package, while mx6ul_14x14_evk use 14x14 package.
This patch add the following:
1. Discard PHYS_SDRAM_SIZE from header file, use imx_ddr_size()
2. Introduce a macro is_mx6ul_9x9_evk using
CONFIG_IS_ENABLED(TARGET_MX6UL_9X9_EVK) to avoid "#ifdef xxx" in non-SPL
part. To SPL part, CONFIG_IS_ENABLED(TARGET_MX6UL_9X9_EVK) can not work,
so still use "#ifdef CONFIG_TARGET_MX6UL_9X9_EVK" to differentiate with
mx6ul_14x14_evk. And we have no way to dymaically checking this chip
is 9x9 or 14x14.
3. mx6ul_9x9_evk use pfuze3000, so enabled POWER related configurations.
POWER related configurations also effect for mx6ul_14x14_evk. But
power_init_board implementation using 'if (is_mx6ul_9x9_evk())' to
do initialization for mx6ul_9x9_evk, and do nothing for mx6ul_14x14_evk.
4. mx6ul_9x9_evk use lpddr2 with size 256MB, so add related SPL DRAM
configurations.
5. Enable CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG and setting dtb file
according to board_rev and board_name.
6. Add TARGET_MX6UL_9X9_EVK Kconfig entry
Boot Log:
U-Boot SPL 2015.10-rc2-00356-g536ce34 (Sep 06 2015 - 12:22:53)
reading u-boot.img
reading u-boot.img
U-Boot 2015.10-rc2-00356-g536ce34 (Sep 06 2015 - 12:22:53 +0800)
CPU: Freescale i.MX6UL rev1.0 792 MHz (running at 396 MHz)
CPU: Commercial temperature grade (0C to 95C) at 41C
Reset cause: POR
Board: MX6UL 9x9 EVK
I2C: ready
DRAM: 256 MiB
PMIC: PFUZE3000 DEV_ID=0x30 REV_ID=0x11
MMC: FSL_SDHC: 0, FSL_SDHC: 1
In: serial
Out: serial
Err: serial
Net: FEC1
Hit any key to stop autoboot: 0
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
This reverts commit 059323fb6a8f21637bb617919715c2427f24777c.
This commit 059323fb6a8f21637bb617919715c2427f24777c use JESD79-3E which
is not the newest spec. Should use JESD79-3F in which tRFC is 260ns for
4Gb chip.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Add imx-common cpu support for imx7d SoC
- Update reset_cause for imx7d
- Enable watchdog driver built for imx7d
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Add imx7d basic SoC system support
Misc arch dependent functions for system bring up
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
* Add Clock control module (CCM) support
* iMX7D SoC introduces 3 main clock sysmtem abstraction for clock
root frequency generation denominated clock slices.
Core clock slice: hihg speed clock for ARM core
Bus clock slice: for bus clocks
IP clock slice: Peripheral clocks
* At system boot ROM enables PLL_ARM, PLL_DDR, PLL_SYS, PLL_ENET
In u-boot, we have to:
- Configure PFD3- PFD7 for freq we needed in u-boot
- Set clock root for peripherals (ip channel)
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Move common imx6 arch init setup, init.c can be extended
and reused to support imx7 SoC keeping init arch common
code.
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Rework cache settings for imx6, move cache configuration
to imx-common/cache.c so it can be reused for newer SoC
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Rework imx_thermal driver to be used across i.MX
processor that support thermal sensor
Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
>From source code comments:
"x0: 0 flush & invalidate, 1 invalidate only"
Current value 0xffff can make invalidate work, since we only judge whether
input value is 0 or not, see following code:
"
tbz w1, #0, 1f
dc isw, x9
b 2f
1: dc cisw, x9 /* clean & invalidate by set/way */
2: subs x6, x6, #1 /* decrement the way */
"
Later we may add "2 clean only" support. So following the comments,
correct value from 0xffff to 1.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
This patch adds the "nandecc" command to switch between the SPEAr600 internal
1-bit HW ECC and the 4-bit SW BCH4 ECC. This can be needed to support NAND
chips with a stronger ECC than 1-bit, as on the x600. And to dynamically
switch between both ECC schemes for backwards compatibility.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
clrsetbits_le32/clrbits_le32 takes mask of the bits as input that
are needed to be set/clear. But emif driver passes the shift of the bits.
Fixing it here.
Reported-by: Mark Mckeown <m-mckeown@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Because there is an originally defined CLK_DMA_ENABLE macro in clk.h,
no reason to add another DMA_CLK_ENABLE macro with the same value.
Remove DMA_CLK_ENABLE, since it does not follow naming convention from
the code, this implies renaming of DMA_CLK_ENABLE to CLK_DMA_ENABLE in
lpc32xx/devices.c file.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
Booting the kernel fails on RK3288 (and probably other rockchip SoCs)
when the i-cache is disabled/flushed before d-cache.
I have not investigated whether this is due to U-Boot hanging or whether
it's very early in the linux boot, but following the approach of the
various rockchip U-Boot forks (first disable d-cache then i-cache) makes
things work.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
Since we need to support runtime check for different drivers, we need
to add get_cpu_rev for vf610, otherwise there will be build errors.
This patch introduces a dummy CPU id which is not read from chip
silicon. Later when we can get the real id from chip, can fix the
value of MXC_CPU_VF610 then.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Suggested-by: Stefano Babic <sbabic@denx.de>
Cc: Stefano Babic <sbabic@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
there is a 2b board version of the aristainetos2
board. Differences to the v2:
- spi cs for the nor flash and display controller
changed
- some pinmux changes
- LED gpio settings changed
Signed-off-by: Heiko Schocher <hs@denx.de>
There is no need to expose SoC choice to user, we already got
the SoC according to the build target. So default "select MX6UL"
for MX6UL_14x14_EVK target.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Add SPL boot support for mx6slevk board.
1. Introduce a configuration file mx6slevk_spl_defconfig.
2. i.MX6SL has same DRAM space with i.MX6SX, need to change SPL DRAM SPACE.
3. Include imx6_spl.h and related SPL macro in mx6slevk.h.
4. select SUPPORT_SPL for TARGET_MX6SLEVK.
5. Add SPL board code to do related initialization.
Boot Log:
U-Boot SPL 2015.07-00544-g1594a76 (Aug 17 2015 - 01:56:59)
reading u-boot.img
reading u-boot.img
U-Boot 2015.07-00544-g1594a76 (Aug 17 2015 - 01:56:59 +0000)
CPU: Freescale i.MX6SL rev1.2 996 MHz (running at 396 MHz)
CPU: Commercial temperature grade (0C to 95C) at 50C
Reset cause: POR
Board: MX6SLEVK
I2C: ready
DRAM: 1 GiB
PMIC: PFUZE100 ID=0x10
MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2
*** Warning - bad CRC, using default environment
In: serial
Out: serial
Err: serial
Net: FEC [PRIME]
Hit any key to stop autoboot: 0
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Add LPDDR2 support:
1. Implement a function mx6_lpddr2_cfg to initialize MMDC for LPDDR2.
2. Introduce a structure mx6_lpddr2_cfg, most entrys are same to
mx6_ddr3_cfg, but still keep it a single one for easy to choose
parameters for LPDDR2.
3. If ddr_type is LPDDR2, use mx6_lpddr2_cfg to init MMDC.
4. Update comments.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
To i.MX6, DDR3 and LPDDR2 is supported, so rename function mx6_dram_cfg
to mx6_ddr3_cfg and the original mx6_dram_cfg function only is a wrapper.
The new reimplemented function mx6_dram_cfg only invokes mx6_ddr3_cfg
when ddr_type is for DDR3. Later we can use ddr_type to initialize
MMDC for LPDDR2.
Initialize ddr_type for different boards which enable SPL.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Define two structure mx6sl_iomux_ddr_regs and mx6sl_iomux_grp_regs.
Add a new function mx6sl_dram_iocfg to configure dram io.
Add header file to define macros for register address.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
To Chip density 4Gb, tRFC should be 300ns, see
"Table 61 — Refresh parameters by device density" of JESD79-3E.
tXS(min) is max(5nCK, tRFC(min) + 10ns).
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
i.MX 6SoloLite only supports MMDC0, so do not access MMDC1 for i.MX 6SL.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
To i.MX6SX/UL, two ethernet interfaces are supported.
Add ENET2 clock support:
1. Introduce a new input parameter "fec_id", only 0 and 1 are allowed.
To value 1, only i.MX6SX/UL can pass the check.
2. Modify board code who use this api to follow new api prototype.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Nikolaos Pasaloukos <Nikolaos.Pasaloukos@imgtec.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Stefan Roese <sr@denx.de>
Rewrite get_cpu_rev, from "static const char *get_cpu_rev(void)" to
"u32 get_cpu_rev(void)". To align with get_cpu_rev of other i.MXes.
Also write get_imx_type to replace get_cpu_type, since we have
macro named get_cpu_type.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Use new formula for get_cpu_rev, since we need to use this formula
to do runtime check for all i.MXes.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Implement get_cpu_rev to support runtime check using is_cpu_type.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Move TARGET_xx Kconfig option based on mx6 to arch/arm/cpu/armv7/mx6/Kconfig.
Add enable "CONFIG_ARCH_MX6" for boards based on mx6.
Then we can choose target boards using "make ARCH=arm menuconfig"
with ARCH_MX6 defined.
If using original way, we have no chance to enable ARCH_MX6 when
"make menuconfig". Even define CONFIG_ARCH_MX6=y in xx_defconfig,
kconfig will complains "arch/../configs/platinum_titanium_defconfig:3:
warning: override: TARGET_PLATINUM_TITANIUM changes choice state"
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Eric Bénard <eric@eukrea.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Christian Gmeiner <christian.gmeiner@gmail.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Soeren Moch <smoch@web.de>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Soeren Moch <smoch@web.de>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Remove this ad-hoc mkimage invocation in MXS Makefile and replace
it with the standard mkimage rule instead.
This patch fixes recent build issues introduced by the patch
92a655c mkimage: Set up a file size parameter and keep it updated
These build issues could be triggered by building for example the
MX28EVK and the u-boot.sb image:
$ make mx28evk_defconfig
$ make V=1 u-boot.sb
[...]
make -f ./scripts/Makefile.build obj=arch/arm/cpu/arm926ejs/mxs u-boot.sb
./tools/mkimage -n arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg -T mxsimage u-boot.sb
./tools/mkimage: Can't open (null): Bad address
arch/arm/cpu/arm926ejs/mxs/Makefile:82: recipe for target 'u-boot.sb' failed
make[1]: *** [u-boot.sb] Error 1
Makefile:989: recipe for target 'u-boot.sb' failed
make: *** [u-boot.sb] Error 2
With this patch:
./tools/mkimage -n arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg -T mxsimage -d arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg u-boot.sb
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Juha Lumme <juha.lumme@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This patch rewrites MMU translation table entries. To start, all table
entries are written as "invalid", then "device-ngnrnr" and "normal" are
written to the entries to enable access to specific addresses.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Every QSGMII SerDes Protocol usage 4 MACs.
So add/repeat QSGMII information for 4 MACs in dpmac_info strucuture.
Signed-off-by: King Chung Lo@freescale.com <KingChungLo@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Update 0x33 and 0x35 serdes protocol as per updated SoC document
in array serdes1_cfg_tbl.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch adds a minimal framework for Dickens CCN-504
interconnect configuration - mainly related to adding Clusters/cores
to snoop/DVM domain and setting QoS of the RN-I ports.
LS2085A platform makes use of these configurations to support
better network data performance and to boot a SMP Linux.
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Stout is an entry level development board based on R-Car H2 SoC (R8A7790)
This commit supports the following peripherals:
- SCIFA, I2C, Ethernet, QSPI, SDHI0/2, CPLD
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
On the A31s the RTC is by default secured. Thus when u-boot
loads the kernel in non-secure world, the RTC is unavailable. The
SoC has a TrustZone Protection Controller, which can be used to
enable non-secure access to the RTC.
On the A31 the TZPC doesn't seem to do anything, i.e. changes to
its register contents do not affect access to the RTC.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Now that we have separate function to enable USB clocks, remove
enabling USB clocks from enable_basic_clocks(). Now board_usb_init()
should take care to invoke enable_usb_clocks() for enabling
USB clocks.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Added functions to enable and disable USB clocks which can be invoked
during USB init and USB exit respectively.
Cc: Roger Quadros <rogerq@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Added functions to enable and disable USB clocks which can be invoked
during USB init and USB exit respectively.
Cc: Roger Quadros <rogerq@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Enabled clocks for the second dwc3 controller and second USB PHY present in
DRA7.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
The SYS_BOOT-based fallback shouldn't only check for one of the conditions of
use and then let the switch/case handle each boot device without enforcing the
conditions for each type of boot device again.
For instance, this behaviour would trigger the fallback for UART when
BOOT_DEVICE_UART is defined, CONFIG_SPL_YMODEM_SUPPORT is enabled (which should
be a show-stopper) and e.g. BOOT_DEVICE_USB is enabled and not
CONFIG_SPL_USB_SUPPORT.
Separating the logic for USB and UART solves this.
In addition, this adds support for more peripheral devices (USBETH and CPGMAC)
to the fallback mechanism. Note that the USBETH boot device should always be
different from the USB boot device (each should match a different bootrom
handoff case).
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Acked-by: Hannes Schmelzer <oe5hpm@oevsv.at>
Tested-by: Hannes Schmelzer <oe5hpm@oevsv.at>
The designware ethernet driver supports d-cache now. So there is nothing
stopping us now to enable the caches completely on SPEAr.
Tested on SPEAr600 x600 board.
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Vipin Kumar <vk.vipin@gmail.com>
The SPL implementation for SPEAr600 is older than the common SPL
infrastructure. This patch now moves the SPEAr600 SPL over to the
common SPL code.
Tested on the only SPEAr board that currently uses SPL in mainline
U-Boot, the x600.
Signed-off-by: Stefan Roese <sr@denx.de>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Vipin Kumar <vk.vipin@gmail.com>
DP83865 ethernet phy used on DRA74x-evm is quirky and the datasheet
provided IODELAY values for standard RGMII phys do not work.
Silicon Revision(SR) 2.0 provides an alternative bit configuration
that allows us to do a "gross adjustment" to launch the data off a
different internal clock edge. Manual IO Delay overrides are still
necessary to fine tune the clock-to-data delays. This is a necessary
workaround for the quirky ethernet Phy we have on the platform.
NOTE: SMA registers are spare "kitchen sink" registers that does
contain bits for other workaround as necessary as well. Hence the
control for the same is introduced in a generic SoC specific, board
generic location.
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Add support for detection of ES2.0 version of DRA7 family of
processors. ES2.0 is an incremental revision with various fixes
including the following:
- reset logic fixes
- few assymetric aging logic fixes
- MMC clock rate fixes
- Ethernet speed fixes
- edma fixes for mcasp
[ravibabu@ti.com: posted internal for an older bootloader]
Signed-off-by: Ravi Babu <ravibabu@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Cleaning up order of include files by sorting them alphabetically
keeping in mind to leave common.h on top.
Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
This patch moves pxa to the common timer functions added in commit
8dfafdd - Introduce common timer functions <Rob Herring>
The (removed) pxa timer code (specifically __udelay()) could deadlock at
the 32-bit boundary of get_ticks(). get_ticks() returned a 32-bit value
cast up to a 64-bit value. If get_ticks() + tmo in __udelay() crossed
the 32-bit boundary, the while condition became unconditionally true and
locked the processor. Rather than patch the specific pxa issues, simply
move everything over to the common code.
Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@konsuiko.com>
Since commit 3ff46cc42b ("arm: relocate the exception vectors")
pxa does not boot anymore.
Add a specific relocate_vectors macro that skips the vector relocation,
as the pxa SoC does not provide RAM at the high vectors address
(0xFFFF0000), and (0x00000000) maps to ROM.
This allows pxa to boot again.
Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com>
USB EHCI on SPEAr600 has not been tested for a while. The base controller
addresses are missing. This patch adds the defines to the header. And adds
the missing code.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Vipin Kumar <vk.vipin@gmail.com>
Cc: Marek Vasut <marex@denx.de>
Added usb dwc3 driver support for zynqmp
this also supports the DFU and LTHOR to download
the linux images on to RAM and cen be booted from
those linux images.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Based on the patch:
"armv8: caches: Added routine to set non cacheable region"
(sha1: dad17fd510)
it is necessary to add platform specific hook.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
As we discussed a couple of times, negative CONFIG options make our
life difficult; CONFIG_SYS_NO_FLASH, CONFIG_SYS_DCACHE_OFF, ...
and here is another one.
Now, there are three boards enabling OF_CONTROL on SPL:
- socfpga_arria5_defconfig
- socfpga_cyclone5_defconfig
- socfpga_socrates_defconfig
This commit adds CONFIG_SPL_OF_CONTROL for them and deletes
CONFIG_SPL_DISABLE_OF_CONTROL from the other boards to invert
the logic.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Incorporate USB driver from legacy LPCLinux NXP BSP.
The files taken from the legacy patch are:
- lpc32xx USB driver
- lpc3250 header file USB registers definition.
The legacy driver was updated and clean-up as part of the integration with the latest u-boot.
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Acked-by: Marek Vasut <marex@denx.de>
Tested-by: Vladimir Zapolskiy <vz@mleia.com>
Incorporate DMA driver from legacy LPCLinux NXP BSP.
The files taken from the legacy patch are:
- lpc32xx DMA driver
- lpc3250 header file DMA registers definition.
The legacy driver was updated and clean-up as part of the integration with the latest u-boot.
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Acked-by: Marek Vasut <marex@denx.de>
Tested-by: Vladimir Zapolskiy <vz@mleia.com>
Adds functions to enable and disable edma3 clocks which can be invoked
by drivers using edma3 to control the clocks.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Adds functions to enable and disable edma3 clocks which can be invoked
by drivers using edma3 to control the clocks.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Add do_disable_clocks() to disable clock domains and module clocks.
These clocks are enabled using do_enable_clocks().
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
Add do_disable_clocks() to disable clock domains and module clocks.
These clocks are enabled using do_enable_clocks().
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Vignesh R <vigneshr@ti.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
CONFIG_SYS_BOARD_DRAM_INIT is not defined anywhere. So lets get rid
of all references here.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Add support for optional soft reset (i.e. "RESOUT_N" not asserted during reset).
To be compatible with the original U-Boot code, when the "addr" parameter is 0, a hard is performed; for any other values, a soft reset is done.
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Move arch/arm/cpu/armv7/exynos/* to arch/arm/mach-exynos/* to allow
reuse of existing code for ARMv8 based Exynos platforms.
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Masahiro Yamada <yamada.m@jp.panasonic.com>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Tested-by: Przemyslaw Marczak <p.marczak@samsung.com>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Add support for the mipi pll, this is necessary for getting higher dotclocks
with lcd panels.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
We now have the CONFIG_SPL_DM for code within SPL to toggle caring about
DM or not. Without this change platforms that do enable CONFIG_DM but
not CONFIG_SPL_DM may be broken (such as OMAP5).
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: Tom Rini <trini@konsulko.com>
The "method" parameter was part of the original port of the driver from
the kernel. At some point this may have been added to allow for future
differentiation (as omap1 and omap2 have different GPIO IP blocks, so
this wasn't an unreasonable thing to do). At this point however it's
just extra overhead, so drop.
Signed-off-by: Tom Rini <trini@konsulko.com>
- Re-sync DT files for am33xx with Linux Kernel v4.1
- Include DT file now for the "AM335x GP EVM" and build target for it,
via device tree and DM.
- We only need to provide platform data for UART when OF_CONTROL isn't
also enabled really. We can just push GPIO to coming from DT
Signed-off-by: Tom Rini <trini@konsulko.com>
Add spi clock to the list of am43xx basic clocks to make the SPI
subsystem available on am43xx systems.
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Reviewed-by: Jagan Teki <jteki@openedev.com>
The semantics for non-static functions declared inline have changed in
gcc5, causing the empty functions not to be emitted as an external
symbol.
Since lowlevel_init() is only referenced from start.S, it should not be
declared inline at all.
Reported-by: Otavio Salvador <otavio@ossystems.com.br>
Tested-by: Otavio Salvador <otavio@ossystems.com.br>
[trini: Reword commit message]
Signed-off-by: Tom Rini <trini@konsulko.com>
DRA72x processor variants are single core and it does not export ACP[1].
Hence, we have no source for generating an external snoop requests which
appear to be key to the deadlock in DRA72x design.
Since we build the same image for DRA74x and DRA72x platforms, lets
runtime detect and disable the workaround (in favor of performance) on
DRA72x platforms.
[1] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0438i/BABIAJAG.html
Suggested-by: Richard Woodruff <r-woodruff2@ti.com>
Suggested-by: Brad Griffis <bgriffis@ti.com>
Reviewed-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Add workaround for Cortex-A15 ARM erratum 801819 which says in summary
that "A livelock can occur in the L2 cache arbitration that might
prevent a snoop from completing. Under certain conditions this can
cause the system to deadlock. "
Recommended workaround is as follows:
Do both of the following:
1) Do not use the write-back no-allocate memory type.
2) Do not issue write-back cacheable stores at any time when the cache
is disabled (SCTLR.C=0) and the MMU is enabled (SCTLR.M=1). Because it
is implementation defined whether cacheable stores update the cache when
the cache is disabled it is not expected that any portable code will
execute cacheable stores when the cache is disabled.
For implementations of Cortex-A15 configured without the “L2 arbitration
register slice” option (typically one or two core systems), you must
also do the following:
3) Disable write-streaming in each CPU by setting ACTLR[28:25] = 0b1111
So, we provide an option to disable write streaming on OMAP5 and DRA7.
It is a rare condition to occur and may be enabled selectively based
on platform acceptance of risk.
Applies to: A15 revisions r2p0, r2p1, r2p2, r2p3 or r2p4 and REVIDR[3]
is set to 0.
Note: certain unicore SoCs *might* not have REVIDR[3] not set, but
might not meet the condition for the erratum to occur when they donot
have ACP (Accelerator Coherency Port) hooked to ACE (AXI Coherency
Extensions). Such SoCs will need the work around handled in the SoC
specific manner, since there is no ARM generic manner to detect such
configurations.
Based on ARM errata Document revision 18.0 (22 Nov 2013)
Suggested-by: Richard Woodruff <r-woodruff2@ti.com>
Suggested-by: Brad Griffis <bgriffis@ti.com>
Reviewed-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Current many cpu use the same flush_cache() function, which just call
the flush_dcache_range().
So implement a weak flush_cache() for all the cpus to use.
In original weak flush_cache() in arch/arm/lib/cache.c, there has some
code for ARM1136 & ARM926ejs. But in the arch/arm/cpu/arm1136/cpu.c and
arch/arm/cpu/arm926ejs/cache.c, there implements a real flush_cache()
function as well. That means the original code for ARM1136 & ARM926ejs
in weak flush_cache() of arch/arm/lib/cache.c is totally useless.
So in this patch remove such code in flush_cache() and only call
flush_dcache_range().
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Since some driver like ohci, lcd used dcache functions. But some ARM
cpu don't implement the invalidate_dcache_range()/flush_dcache_range()
functions.
To avoid compiling errors this patch adds an weak empty stub function
for all ARM cpu in arch/arm/lib/cache.c.
And ARM cpu still can implemnt its own cache functions on the cpu folder.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Reviewed-by: York Sun <yorksun@freescale.com>
As both cores are similar merge the cache handling code for both CPUs
to arm11 directory.
Signed-off-by: Alexander Stein <alexanders83@web.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
[trini: Add hunk to arch/arm/cpu/arm1136/Makefile]
Signed-off-by: Tom Rini <trini@konsulko.com>
Apparently lcd_panel_disable is not defined anywhere, so no config for
an arm1136 board would have set CONFIG_LCD. Remove the unused code.
Signed-off-by: Alexander Stein <alexanders83@web.de>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Tested-by: Stephen Warren <swarren@wwwdotorg.org>
The LG Optimus Black (P970) codename sniper is a smartphone that was designed
and manufactured by LG Electronics (LGE) and released back in 2011.
It is using an OMAP3630 SoC GP version, which allows running U-Boot and the
U-Boot SPL from the ground up. This port is aimed at running an Android version
such as Replicant, the fully free Android distribution. However, support for
upstream Linux with device-tree and common GNU/Linux distros boot commands
could be added in the future.
For more information about the journey to freeing this device, please read the
series of blog posts at:
http://code.paulk.fr/article20/a-hacker-s-journey-freeing-a-phone-from-the-ground-up-first-part
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Add CONFIG_OF_SUPPORT]
Signed-off-by: Tom Rini <trini@konsulko.com>
Reboot mode is written in scratchpad memory before reboot in the form of a
single char, that is the first letter of the reboot mode string as passed to the
reboot function.
This mechanism is supported on OMAP3 both my the upstream kernel and by various
TI kernels.
It is up to each board to make use of this mechanism or not.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
The change adds support of LPC32xx SLC NAND controller.
LPC32xx SoC has two different mutually exclusive NAND controllers to
communicate with single and multiple layer chips.
This simple driver allows to specify NAND chip timings and defines
custom read_buf()/write_buf() operations, because access to 8-bit data
register must be 32-bit aligned.
Support of hardware ECC calculation is not implemented (data
correction is always done by software), since it requires a working
DMA engine.
The driver can be included to an SPL image.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
LPC32xx MAC and clock control configuration requires some minor quirks
to deal with a phy connected by RMII.
It's worth to mention that the kernel and legacy BSP from NXP sets
SUPP_RESET_RMII == (1 << 11) bit, however the description of this bit is
missing in shared LPC32x0 User Manual UM10326 Rev. 3, July 22, 2011
and in LPC32x0 Draft User Mannual Rev. 00.27, November 20, 2008, also
in my tests an SMSC LAN8700 phy device connected over RMII seems to
work correctly without touching this bit.
Add support of RMII, if CONFIG_RMII is defined, this option is aligned
with a number of boards, which already define the same config value.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
USB devices are not really designed to get the power bounced off and on
at them. Esp. USB powered harddisks do not like this.
Currently we power off the USB ports both on a "usb reset" and when
booting the kernel, causing the usb-power to bounce off and then back
on again.
This patch removes the powering off calls, fixing the undesirable power
bouncing.
Note this requires some special handling for the OTG port:
1) We must skip the external vbus check if we've already enabled our own
vbus to avoid false positives
2) If on an usb reset we no longer detect that the id-pin is grounded, turn
off vbus as that means an external vbus may be present now
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Spring is the first ARM-based HP Chromebook 11. It is similar to snow
and it uses the same Samsung Exynos5250 chip. But has some unusual
features. Mainline support for it has lagged snow (both in kernel and
U-Boot). Now that the exynos5 code is common we can support spring just
by adding a device tree and a few lines of configuration.
Signed-off-by: Simon Glass <sjg@chromium.org>
Line up the display with the line below, e.g.:
CPU: Exynos5250 @ 1.7 GHz
Model: Google Spring
DRAM: 2 GiB
MMC: EXYNOS DWMMC: 0
Also show the speed as GHz where appropriate.
Signed-off-by: Simon Glass <sjg@chromium.org>
As a debugging aid, allow UART3 to be used as a debug UART in SPL. This
is a precursor to proper UART support, which requires a substantial
refactor.
Signed-off-by: Simon Glass <sjg@chromium.org>
USB-related options are usually prefixed with CONFIG_USB and platform-specific
adaptation for the MUSB controller already have a CONFIG_USB_MUSB prefix, so
this switches all MUSB-related options to a CONFIG_USB_MUSB prefix, for
consistency.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Bootrom will put cpus into WFE state when boot cpu release cpus, so
target cpu cannot correctly go to spin state.
Add 'sev' to wakeup non-boot cpu that hold on bootrom space, let target
cpu can fall into u-boot spin table.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
1. Define two structures mx6ul_iomux_ddr_regs and mx6ul_iomux_grp_regs.
2. Add a new function mx6ul_dram_iocfg to configure dram io.
3. Refactor MMDC1 macro, discard "#ifdef CONFIG_MX6SX". Since
only mmdc0 channel exists on i.MX6SX/UL, redefine MMDC1 macro support
runtime check, but not hardcoding #ifdef macros.
4. Introduce mx6ul-ddr.h, which includes the register address for DRAM
IO configuration.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
1.Update WDOG settings.
2.No need to gate/ungate all PFDs for i.MX6UL.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
i.MX6UL features an Cortex-A7 core, it does not have PL310 as other i.MX6
chips. To Cortex-A7 core, If D-Cache is enabled, L2 Cache is enabled.
There is on specific switch for on/off L2 Cache, so default select
SYS_L2CACHE_OFF.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
1. Add enet, uart, i2c, ipg clock support for i.MX6UL.
2. Correct get_periph_clk, it should account for
MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK.
3. Refactor get_mmdc_ch0_clk to make all i.MX6 share one function,
but not use 'ifdef'.
4. Use CONFIG_FSL_QSPI for enable_qspi_clk, but not #ifdef CONFIG_MX6SX.
5. Use CONFIG_PCIE_IMX for pcie clock settings, use CONFIG_CMD_SATA for
sata clock settings. In this way, we not need "#if defined(CONFIG_MX6Q)
|| defined....", only need one CONFIG_PCIE_IMX in header file.
Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
CPU_V7 is already selected by ARCH_MX6, so no point in selecting it again
by boards that depend on ARCH_MX6.
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
cm-fx6 is an MX6 based board, and the menuconfig hierarchy should
reflect that. Make TARGET_CM_FX6 dependant on ARCH_MX6.
Cc: Stefano Babic <sbabic@denx.de>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
The i.MX6DQP has a PRG module, need to enable its clock for using IPU.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Brown Oliver <B37094@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Since the i.MX6QP has fixed the issue in boot ROM, so remove the workaround
for i.MX6QP.
Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Since i.MX6QP changes some CCM registers, so modify the clocks settings to
follow the hardware changes.
In c files, use runtime check and discard #ifdef.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Add cpu type for i.MX6QP/DP.
This patch also fix is_mx6dqp(), since get_cpu_rev can return MXC_CPU_MX6QP
and MXC_CPU_MX6DP, we should use:
(is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)).
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Added routine mmu_set_region_dcache_behaviour() to set a
particular region as non cacheable.
Define dummy routine for mmu_set_region_dcache_behaviour()
to handle incase of dcache off.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
While generating the page tables, a running integer index is shifted by
SECTION_SHIFT (29) and causes overflow for any integer bigger than 7.
The page tables therefore alias to the same 8 sections and cause U-Boot
to hang once the MMU is enabled.
Fix this by making the index a 64-bit unsigned integer and so avoid the
overflow.
swarren notes: currently "i" ranges from 0..8191 on all ARM64 boards, and
"j" varies depending on RAM size; from 4 to 11 for a board with 4GB at
physical address 2GB, as some Tegra boards have.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Pass directly boot_addr which is LOVEC (0) or HIVEC (0xffff0000).
No reason to use magic values 0 and 1.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Define a new config "zynqmp_ep" for ZynqMP instead
of xilinx_zynqmp. This defconfig supports all emulation
platforms of ZynqMP. Also renamed TARGET_XILINX_ZYNQMP
to ARCH_ZYNQMP.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Move the zynqmp Kconfig from board to arch
as there may be different boards under same
architecture.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
While most stm32f4 run at 168 MHz, stm32f429 can work till 180 MHz.
Add option to select 180 MHz through macro CONFIG_SYS_CLK_FREQ.
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
To: Albert Aribaud <albert.u.boot@aribaud.net>
To: Tom Rini <trini@konsulko.com>
To: Kamil Lulko <rev13@wp.pl>
Cc: u-boot@lists.denx.de
Because the top-level Makefile forces all the source files
to include include/linux/kconfig.h (see the UBOOTINCLUDE define),
these includes are redundant.
By the way, there are exceptions for the statement above; host
programs. In fact, host tools in U-Boot depend on a particular
board configuration, although I think they should not. So, some
files still include <linux/config.h> to work around build errors
on host tools.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Simon Glass <sjg@chromium.org>
All am33xx device tree are using device-tree, so get_board_rev is never actually
called. Thus, we can get rid of it to make the code easier to maintain.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
Despite being defined with __weak, this declaration of get_board_rev will
conflict with the fallback one when ONFIG_REVISION_TAG is not defined.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Tom Rini <trini@konsulko.com>
This introduces code to read the value of the SYS_BOOT pins on the OMAP5, as
well as the memory-preferred scheme for the interpretation of each value.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
This introduces code to read the value of the SYS_BOOT pins on the OMAP4, as
well as the memory-preferred scheme for the interpretation of each value.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
This introduces code to read the value of the SYS_BOOT pins on the OMAP3, as
well as the memory-preferred scheme for the interpretation of each value.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
OMAP devices might boot from peripheral devices, such as UART or USB.
When that happens, the U-Boot SPL tries to boot the next stage (complete U-Boot)
from that peripheral device, but in most cases, this is not a valid boot device.
This introduces a fallback option that reads the SYS_BOOT pins, that are used by
the bootrom to determine which device to boot from. It is intended for the
SYS_BOOT value to be interpreted in the memory-preferred scheme, so that the
U-Boot SPL can load the next stage from a valid location.
Practically, this options allows loading the U-Boot SPL through USB and have it
load the next stage according to the memory device selected by SYS_BOOT instead
of stalling.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Now that SPL boot devices are clearly defined, we can use BOOT_DEVICE_QSPI_4
instead of a hardcoded value.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
This introduces OMAP3 support for the common omap boot code, as well as a
major cleanup of the common omap boot code.
First, the omap_boot_parameters structure becomes platform-specific, since its
definition differs a bit across omap platforms. The offsets are removed as well
since it is U-Boot's coding style to use structures for mapping such kind of
data (in the sense that it is similar to registers). It is correct to assume
that romcode structure encoding is the same as U-Boot, given the description
of these structures in the TRMs.
The original address provided by the bootrom is passed to the U-Boot binary
instead of a duplicate of the structure stored in global data. This allows to
have only the relevant (boot device and mode) information stored in global data.
It is also expected that the address where the bootrom stores that information
is not overridden by the U-Boot SPL or U-Boot.
The save_omap_boot_params is expected to handle all special cases where the data
provided by the bootrom cannot be used as-is, so that spl_boot_device and
spl_boot_mode only return the data from global data.
All of this is only relevant when the U-Boot SPL is used. In cases it is not,
save_boot_params should fallback to its weak (or board-specific) definition.
save_omap_boot_params should not be called in that context either.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
On some boards the otg is wired up in host-only mode in this case we
have no vbus-det gpio.
Stop logging an error from sunxi_usb_phy_vbus_detect() in this case, and
stop treating sunxi_usb_phy_vbus_detect() returning a negative errno, as
if a charger is plugged into the otg port.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Add support for reading the id pin value of the otg connector to the usb
phy code.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Make possible using a single `u-boot-sunxi-with-spl.bin` binary for both NAND
memory and SD card. Detection where SPL was read from is implemented in
`spl_boot_device`.
Signed-off-by: Daniel Kochmański <dkochmanski@turtle-solutions.eu>
CC: Roy Spliet <r.spliet@ultimaker.com>
Cc: Ian Campbell <ijc@hellion.org.uk>
[hdegoede@redhat.com: Some small coding style fixes]
Acked-by: Hans De Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
USB download gadget functions such as thor and dfu have a separate config option
for the USB gadget part of the code, independent from the command part.
This switches the fastboot USB gadget to the same scheme, for better
consistency.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Tested-by: Lukasz Majewski <l.majewski@samsung.com>
Test HW: Odroid_XU3 (Exynos5422), trats (Exynos4210)
Driver-model I2C drivers can be picked up by the linker script rule for
legacy drivers. Change the order to avoid this.
We could make the legacy code depend on !CONFIG_DM_I2C but that is not
necessary and it is good to keep conditions to a minimum.
Signed-off-by: Simon Glass <sjg@chromium.org>
The SPL device tree size must be minimised to save memory. Only include
properties that are needed by SPL - this is determined by the presence
of the "u-boot,dm-pre-reloc" property. Also remove a predefined list of
unused properties from the nodes that remain.
Signed-off-by: Simon Glass <sjg@chromium.org>
When final MMU table is setup in DDR, TCR attributes must match
those of the memroy for cacheability and shareability.
Signed-off-by: Zhichun Hua <zhichun.hua@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
Base on PSCI services, implement CPU_ON/CPU_OFF for ls102xa platform.
Tested on LS1021AQDS, LS1021ATWR.
Test CPU hotplug times: 60K
Test kernel boot times: 1.2K
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Acked-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
timer_wait is moved from sunxi/psci_sun7i.S, and it can be converted
completely into a reusable armv7 generic timer. LS1021A will use it
as well.
Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: York Sun <yorksun@freescale.com>
As the function 'sprintf' does not check buffer boundaries but outputs
to the buffer 'enet' of fixed size (16), this patch removes the function
'sprintf', and uses 'strcpy' instead. It will assign the character
arrays 'enet' and 'phy' the corresponding character strings.
Signed-off-by: Alison Wang <alison.wang@freescale.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch adds the infrastructure to update device
tree nodes to convey SMMU stream IDs in the device
tree. Fixups are implemented for PCI controllers
initially.
Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch updates the setting of required bits for A57 cores erratas
- 828024 and 826974
Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com>
Signed-off-by: Dai Haruki <dai.haruki at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
Update SoC README to provide details of
- Memory regions
- Memory used by MC and Debug server
Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
This patch adds support to print out the SoC personality.
Freescale LS20xx SoCs (compliant to Chassis-3 specifications) can
have 6 personalities: LS2045AE, LS2045A, LS2080AE, LS2080A,
LS2085AE and LS2085A
Signed-off-by: Bhupesh Sharma <bhupesh.sharma at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
DDR speed should be in MT/s, not MHz.
Signed-off-by: York Sun <yorksun at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
call ft_pci_setup() to disable PCIe dts node if corresponding
PCIe controller is disabled according to RCW
Signed-off-by: Minghuan Lian <Minghuan.Lian at freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
hab_status command returns a memory dump of the hab event log. But the
raw data is not human-readable. Parsing such data into readable event
will help to minimize debbuging time.
Signed-off-by: Ulises Cardenas <Ulises.Cardenas@freescale.com>
Add I2C4 clock support for i.MX6SX. Since we use runtime check,
but not macro, we need to remove `#ifdef ..` in crm_regs.h, or
gcc will fail to compile the code succesfully.
Making the macros only for i.MX6SX open to other i.MX6x maybe not
a good choice, but we have runtime check.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
enable_spi_clock does the same thing with enable_cspi_clock, so
remove enable_cspi_clock.
Remove enable_cspi_clock prototype in header file
convert cm_fx6/spl.c to use enable_spi_clk
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
The A33 adds a pinmux function for UART0 in the PB pin group.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The original code was configuring the external pins after enabling
the R_PIO clock, which meant the configuration never made it to
the pin controller the first time in SPL.
Why this was working before is uncertain. Maybe the state was left
from a previous boot sequence, or RSB just happened to be the default
configuration. However with some A33 chips, SPL failed to configure
the PMIC. This was seen by me and Maxime on the Sinlinx SinA33 dev
board.
Reordering the calls fixed this.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Commit 487b327 ("sunxi: GPIO pin mux hardware-feature-specific function
index defines") renamed all GPIO index defines, but missed the PORT F
UART0 setup functions.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
stv0991 has cadence qspi controller for flash interfacing, this
patch configures the device pads & clock for the controller.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Reviewed-by: Jagannadh Teki <jteki@openedev.com>
This reverts commit f76eba38b3.
This patch did not have a full and proper copyright/S-o-b chain.
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Conflicts:
include/configs/sun6i.h
include/configs/sun8i.h
The DIGPROG register map:
23 ------- 16 | 15 ------ 8 | 7 --- 0 |
Major upper | Major Lower | Minor |
We also need to account for Major Lower.
Signed-off-by: Ye.Li <B37916@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
This is the first patch to remove the
CONFIG_SYS_EXTRA_OPTIONS.
This patch implements CPU type selection from Kconfig.
Further Kconfig stuff is added later.
Signed-off-by: Markus Niebel <Markus.Niebel@tq-group.com>
Some archs/boards specify their own default by pre-defining the config
which causes the Kconfig system to mix up the order of the configs in
the defconfigs... This will cause merge pain if allowed to proliferate.
Remove the configs that behave this way from the archs.
A few configs still remain, but that is because they only exist as
defaults and do not have a proper Kconfig entry. Those appear to be:
SPIFLASH
DISPLAY_BOARDINFO
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
[trini: rastaban, am43xx_evm_usbhost_boot, am43xx_evm_ethboot updates,
drop DM_USB from MSI_Primo81 as USB_MUSB_SUNXI isn't converted yet to DM]
Signed-off-by: Tom Rini <trini@konsulko.com>
DRA7/AM57xx devices can be operated in many different configurations.
When the SoC is supposed to support a configuration where low power mode
state may involve the SoC completely powered off and DDR is in self
refresh, SoC EMIF controller should not be the master of the reset
signal and an external entity might be in control of things.
The default configuration of Linux on TI evms involve not powering off
the voltage rails (due to various reasons including reliability concerns)
and must not allow DDR reset to be controlled by EMIF. On platforms
where external entity might control the reset signal, this configuration
will be a "dont care".
Fixes: 536d874708 ("ARM: DRA7: Update DDR IO registers")
Tested-by: Keerthy <j-keerthy@ti.com>
Acked-by: Brad Griffis <bgriffis@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Currently on sun6i after a "reset" the prompt returns and the user can
even type stuff until the watchdog triggers and does the actual reset.
This is somewhat unexpected behavior for the "reset" command, this
commit adds an endless loop to wait for the watchdog to trigger so that
we do not return to the prompt.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Unlike OMAP5, EMIF PHY used in DRA7 will be left in unknown state after
warm reset, emif needs to be configured to bring it back to a known
state. So configure EMIF during warm reset.
Reported-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
The recent changes for hw leveling on am33xx were not intended for
DDR2 boards, only DDR3. Update emif_sdram_type to take a sdram_config
value to check against. This lets us pass in the value we would use to
configure, when we have not yet configured the board yet. In other cases
update the call to be as functional as before and check an already
programmed value in.
Tested-by: Yan Liu <yan-liu@ti.com>
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
On AM57xx evm I2C5 is used to detect the LCD board by reading the
EEPROM present on the bus.
Enable i2c5 clocks to help that.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
In addition to the regular mux configuration, certain pins of DRA7
require to have "manual mode" also programmed, when predefined
delay characteristics cannot be used for the interface.
struct iodelay_cfg_entry is introduced for populating
manual mode IO timings.
For configuring manual mode, along with the normal pad
configuration do the following steps:
- Select MODESELECT field of each assocaited PAD.
CTRL_CORE_PAD_XXX[8]:MODESELECT = 1(Enable MANUAL_MODE macro along with mux)
- Populate A_DELAY, G_DELAY values that are specified in DATA MANUAL.
And pass the offset of the CFG_XXX register in iodelay_cfg_entry.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
On DRA7, in addition to the regular muxing of pins, an additional
hardware module called IODelay which is also expected to be
configured. This "IODelay" module has it's own register space that is
independent of the control module.
It is advocated strongly in TI's official documentation considering
the existing design of the DRA7 family of processors during mux or
IODelay recalibration, there is a potential for a significant glitch
which may cause functional impairment to certain hardware. It is
hence recommended to do muxing as part of IOdelay recalibration.
IODELAY recalibration sequence:
- Complete AVS voltage change on VDD_CORE_L
- Unlock IODLAY config registers.
- Perform IO delay calibration with predefined values.
- Isolate all the IOs
- Update the delay mechanism for each IO with new calibrated values.
- Configure PAD configuration registers
- De-isolate all the IOs.
- Relock IODELAY config registers.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
do_set_mux32() is redefined in dra7xx and beagle_x15 boards.
IO delay recalibration sequence also needs this.
Making it generic to avoid duplication.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
When DLL_CALIB_INTERVAL is set, an extra delay is added
which is not required and it consumes EMIF bandwidth.
So making the DLL_CALIB_CTRL[8:0]DLL_CALIB_INTERVAL bits to 0.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
DDRIO_2 and LPDDR2CH1_1 registers are not present
for DRA7. So not configuring these registers for DRA7xx
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Updating EMIF registers to enable HW leveling
on DRA72-evm.
Also updating the timing registers.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
DRA7 EMIF supports Full leveling for DDR3.
Adding support for the Full leveling sequence.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
We plan to enable device tree in SPL by default. Before doing this,
explicitly disable it for all boards.
Signed-off-by: Simon Glass <sjg@chromium.org>
This function is used before jumping to U-Boot, but in that case we don't
always want to disable caches.
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
This fixes ethernet no longer working on boards which use a gpio to enable
the phy.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Before this commit the code for determining the disconnect threshold was
checking for sun4i or sun6i assuming that those where the exception and
that newer SoCs use a disconnect threshold of 2 like sun7i does.
But it turns out that newer SoCs actually use a disconnect threshold of 3
and sun5i and sun7i are the exceptions, so check for those instead.
Here are the settings from the various Allwinner SDK sources:
sun4i-a10: USBC_Phy_Write(usbc_no, 0x2a, 3, 2);
sun5i-a13: USBC_Phy_Write(usbc_no, 0x2a, 2, 2);
sun6i-a31: USBC_Phy_Write(usbc_no, 0x2a, 3, 2);
sun7i-a20: USBC_Phy_Write(usbc_no, 0x2a, 2, 2);
sun8i-a23: USBC_Phy_Write(usbc_no, 0x2a, 3, 2);
sun8i-h3: USBC_Phy_Write(usbc_no, 0x2a, 3, 2);
sun9i-a80: USBC_Phy_Write(usbc_no, 0x2a, 3, 2);
Note this commit makes no functional changes for sun4i - sun7i, and
changes the disconnect threshold for sun8i to match what Allwinner uses.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
In case the DC-DC is already enabled mxs_enable_4p2_dcdc_input() returns
without reenabling brown out detection. So fix this issue by
moving the return before brown out deactivation.
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: Marek Vasut <marex@denx.de>
This updates r8a7790 QoS to revision 0.973.
This commit can changed from KConfig to fit contents of the QoS.
Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
sun8i can share the PSCI backend with sun6i. Only difference
is sun8i does not have CPU power clamp controls.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This adds PSCI support for sun6i. So far it only supports
the PWR_ON method.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The PSCI code only works for sun7i. Rename it with _sun7i suffix,
and build only if building for sun7i.
This paves the way for adding PSCI support for other platforms.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The PSCI CPU_ON code accesses quite a few registers. Document
their names to make it easier to cross reference.
Also explain "lock cpu" and "unlock cpu" as enabling/disabling
debug access.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
This commit adds support to the sunxi SPL to load u-boot from the internal
NAND. Note this only adds support to access the boot partitions to load
u-boot, full NAND support to load the kernel, etc. from the nand data
partition will come later.
Signed-off-by: Roy Spliet <r.spliet@ultimaker.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Add initial sun9i (A80) support, only uart + mmc are supported for now.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The latest versions of the fel tool support loading normal u-boot builds
directly, and this is now the preferred way to use the fel boot method.
This commit removes support for the old deprecated standalone fel builds.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Unlike the A31 and the A23 the A33 actually has a SID inside the SoC again,
but sid[3] is 0 (at least on some SoCs), so it is better to use the axp221
sid.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Make DRAM_ODT_EN Kconfig setting a bool, add a separate DRAM_ODT_CORRECTION
setting for A23 SoCs and use DRAM_ODT_EN Kconfig everywhere instead of
only in dram_sun4i.c and hardcoding odt_en elsewhere.
Note this commit makes no functional changes for existing boards,
its purpose is to allow changing the odt_en value on future A33 boards.
For sun4i/sun5i/sun7i boards which set DRAM_ODT_EN=y (which no defconfigs
currently do) this patch turns on odt for both the DQ and the DQS lines,
whereas previously it was possibly (but not desirable) to turn odt on only
for one of them by setting the in DRAM_ODT_EN option to 1 or 2 instead of 3.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
When porting the allwinner dram init code to u-boot we missed some code
setting an extra bit when doing auto dram config.
This commits add this bit, fixing dram init not working on the ga10h
10" a33 tablet which I'm bringing up atm.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Add support for UART2 (2-pin version but note that RTS/CTS pins are available
pn that port for possible future use), can be selected in config
by using CONFIG_CONS_INDEX=3
Signed-off-by: Laurent Itti <laurentitti@gmail.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
The MX6 has a temperature grade defined by OCOTP_MEM0[7:6] which is at 0x480
in the Fusemap Description Table in the reference manual. Return this value
as well as min/max temperature based on the value.
Note that the IMX6SDLRM and the IMX6SXRM do not indicate this in the
their Fusemap Description Table however Freescale has confirmed that these
eFUSE bits match the description within the IMX6DQRM and that they will
be added to the next revision of the respective reference manuals.
This has been tested with IMX6 Automative and Industrial parts.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
The IMX6 has four different speed grades determined by eFUSE SPEED_GRADING
indicated by OCOTP_CFG3[17:16] which is at 0x440 in the Fusemap Description
Table. Return this frequency so that it can be used elsewhere.
Note that the IMX6SDLRM and the IMX6SXRM do not indicate this in the
their Fusemap Description Table however Freescale has confirmed that these
eFUSE bits match the description within the IMX6DQRM and that they will
be added to the next revision of the respective reference manuals.
These have been tested with IMX6 Quad/Solo/Dual-light 800Mhz and 1GHz grades.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Commit fa8b7d66f49f0c7bd41467fe78f6488d8af6976a introduced fast-exit support
to the MMDC however enabling it on the DDR3 got missed. Make sure we enable
it on the DDR3 as well.
Gateworks uses Micron memory as well as Winbond in MX6. We have found in
testing that we need to enable fast-exit for Winbond stability. Gateworks
boards are currently the only boards using the MX6 SPL and enabling
fast-exit mode.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Having bit 22 cleared in the PL310 Auxiliary Control register (shared
attribute override enable) has the side effect of transforming Normal
Shared Non-cacheable reads into Cacheable no-allocate reads.
Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.
This was inspired by a patch from Catalin Marinas [1] and also from recent
discussions in the linux-arm-kernel list [2] where Russell King and Rob Herring
suggested that bootloaders should initialize the cache.
[1] http://lists.infradead.org/pipermail/linux-arm-kernel/2010-November/031810.html
[2] https://lkml.org/lkml/2015/2/20/199
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
This is proposal for clamping the MMDC/DDR3 clocks to the maximum supported
frequencies as per imx6 SOC models, and for dynamically calculating valid
clock value based on mem_speed.
Currently the code uses impossible values for mem_speed (1333, 1600 MT/s) for
calculating the DDR timings, and uses fixed clock (528 or 400 MHz) which
doesn't take into account DDR3 memory limitations.
Signed-off-by: Nikolay Dimitrov <picmaster@mail.bg>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Upstream Linux is broken with default configs when PSCI, thus non-secure
mode is enabled. So the user should explicitly enable this mode, e.g.
when she disabled CONFIG_CPU_IDLE in Linux (in which case it's safe to
use). We can revert this workaround once Linux got fixed.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
These registers can be used to prevent non-secure world from accessing a
megabyte aligned region of RAM, use them to protect the u-boot secure monitor
code.
At first I tried to do this from s_init(), however this inexplicably causes
u-boot's networking (e.g. DHCP) to fail, while networking under Linux was fine.
So instead I have added a new weak arch function protect_secure_section()
called from relocate_secure_section() and reserved the region there. This is
better overall since it defers the reservation until after the sec vs. non-sec
decision (which can be influenced by an envvar) has been made when booting the
os.
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
[Jan: tiny style adjustment]
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Tested-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Tegra boards will have to initialize power management for the PSCI
support this way.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
In this case the secure code lives in RAM, and hence the memory node in
the device tree needs to be adjusted. This avoids that the OS will map
and possibly access the reservation.
Add support for setting CONFIG_ARMV7_SECURE_RESERVE_SIZE to carve out
such a region. We only support cutting off memory from the beginning or
the end of a RAM bank as we do not want to increase their number (which
would happen if punching a hole) for simplicity reasons
This will be used in a subsequent patch for Jetson-TK1.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Use a per-CPU variable for saving the target PC during CPU_ON
operations. This allows us to run this service independently on targets
that have more than 2 cores and also core-local power control.
CC: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Tested-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This algorithm will be useful on Tegra as well, plus we will need it for
making _psci_target_pc per-CPU.
CC: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Tested-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Tom Warren <twarren@nvidia.com>
_sunxi_cpu_entry can be converted completely into a reusable
psci_cpu_entry. Tegra124 will use it as well.
As with psci_disable_smp, also the enabling is designed to be overloaded
in cased SMP is not controlled via ACTLR.
CC: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Tested-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Move parts of sunxi's psci_cpu_off into psci_cpu_off_common, namely
cache disabling and flushing, clrex and the disabling of SMP for the
dying CPU. These steps are apparently generic for ARMv7 and will be
reused for Tegra124 support.
As the way of disabled SMP is not architectural, though commonly done
via ACLTR, the related function can be overloaded.
CC: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Tested-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Will be required for obtaining the ID of the current CPU in shared PSCI
functions. The default implementation requires a dense ID space and only
supports a single cluster. Therefore, the functions can be overloaded in
cases where these assumptions do not hold.
CC: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Tested-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Tom Warren <twarren@nvidia.com>
CONFIG_ARMV7_VIRT depends on CONFIG_ARMV7_NONSEC, thus doesn't need to
be taken into account additionally. CONFIG_ARMV7_PSCI is only set on
boards that support CONFIG_ARMV7_NONSEC, and it only works on those.
CC: Tang Yuantian <Yuantian.Tang@freescale.com>
CC: York Sun <yorksun@freescale.com>
CC: Steve Rae <srae@broadcom.com>
CC: Andre Przywara <andre.przywara@linaro.org>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Tested-by: Alison Wang <alison.wang@freescale.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>
By making the board selections optional, every defconfig will include
the board selection when running savedefconfig so if a new board is
added to the top of the list of choices the former top's defconfig will
still be correct.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Cc: Tom Rini <trini@konsulko.com>
Because all the SOCFPGA boards define CONFIG_SPL_FRAMEWORK
(see include/configs/socfpga_common.h), u-boot.img is automatically
added to the target image list by the top Makefile.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
The compiler option "-Iboard/$(VENDOR)/$(BOARD)" just exists here
for iocsr_config.c to be able to include iocsr_config.h.
Use "..." instead of <...> to include a header in the same directory.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Move arch/arm/cpu/armv7armada-xp/* -> arch/arm/mach-mvebu/*
Since this platform will be extended to support other Marvell SoC's as
well, lets rename it directly to mvebu.
This will be used by the upcoming Armada 38x suport (A38x).
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Tested-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Tested-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Once we add support for the ohci controller the phy-init and phy-power-on
functions may be called twice (once by the ehci code and once by the ohci
code) protect them against this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The 2/3 usb-phys on the sunxi SoCs are really a single separate functional
block, and are modelled as such in devicetree. So once we've moved all the
sunxi usb code to the driver-model then phy_probe will be called once
for the entire block from the driver-model enumeration code.
Move to this now as this also avoids problems with phy_probe being called
multiple times once we introduce ohci support. This also allows us to get rid
of the sunxi_usb_phy_enabled_count variable as phy_probe now is guaranteed
to be called only once.
Since we're effectively rewriting the probe / remove functions, move them
to the end of the file while we are at it, as that is the most logical place
for them.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The usbc.? files now only contain usb-phy related code, rename them to make
this clear.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Rename the sunxi_usbc_foo functions to sunxi_usb_phy_bar to make it clear
that these are usb-phy functions. Also change the verbs & nouns in the suffix
to match the verbs & nouns used in the Linux kernels generic phy framework.
This patch purely renames things, it contains no functional changes.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
This is the only function left in sunxi/usbc.c which is not phy related,
so remove it.
This is a preparation patch for turning the usbc.c code into a proper
usb phy driver.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The sunxi "usbc" code is mostly about phy setup, but currently also sets up
the host controller clocks, which is something which really belongs in the
host controller drivers, so move it there.
This is a preparation patch for moving the sunxi ehci code to the driver
model and for adding ohci support.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
All sunxi boards now use the driver-model, so remove the non driver-model
code.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Modify the sunxi-emac eth driver to support driver model.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Reviewed-by: Stefan Roese <sr@denx.de>
Add support for the axp152 and axp209 PMICs to the pmic register access
helpers. This is a preparation patch for moving the axp gpio code to a
separate gpio driver.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Move the register helpers used to access the registers via p2wi resp.
rsb bus on the otherwise identical axp221 and axp223 pmics to a separate
file, so that they can be used by the upcoming standalone axp gpio driver
too.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
The driver-model gpio functions may return another value then -1 as error,
make the sunxi usbc properly handle this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Enable full support for the A33 SoC including display, otg-usb, etc.
Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Add support for the new second DRAM PLL found on the A33 SoC.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
This is a preparation patch for adding A33 support, which will have a
mach name of sun8i-a33.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
sun6i and newer (derived) SoCs such as the sun8i-a23, sun8i-a33 and sun9i
have a various things in common, like having separate ahb reset control
registers, the SID living inside the pmic, custom pmic busses, new style
watchdog, etc.
This commit introduces a new hidden SUNXI_GEN_SUN6I Kconfig bool which can be
used to check for these features avoiding the need for an ever growing list
of "#if defined CONFIG_MACH_SUN?I" conditionals as we add support for more
"new style" sunxi SoCs.
Note that this commit changes the behavior of the gmac and hdmi code for
sun8i and the upcoming sun9i devices. This does not matter as sun8i does
not have gmac nor hdmi, and sun9i has new hardware-blocks for these so
the old code will not work there.
Also this is intentional as if a sun8i / sun9i variant which does use the
old hwblocks shows up then the GEN_SUN6I code paths will be the right ones
to use.
For completeness this also adds a SUNXI_GEN_SUN4I bool for A10/A13/A20.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
We do not use irqs in u-boot so remove the unused irq field, and all the
#ifdef-ery around the irq initialization.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
There is no reason not to and this make the #ifdef-ery easier to read.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
This is already invoked a few cycles later in monitor mode by
_secure_monitor (_sunxi_cpu_entry calls _do_nonsec_entry which triggers
_secure_monitor via smc #0). Drop it here, it serves no purpose.
CC: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Tested-by: Ian Campbell <ijc@hellion.org.uk>
Tested-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
