Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq

arch/arm/Kconfig

@@ -710,6 +710,33 @@ config TARGET_HIKEY
 	  Support for HiKey 96boards platform. It features a HI6220
 	  SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
 
+config TARGET_LS1012AQDS
+	bool "Support ls1012aqds"
+	select ARM64
+	help
+	  Support for Freescale LS1012AQDS platform.
+	  The LS1012A Development System (QDS) is a high-performance
+	  development platform that supports the QorIQ LS1012A
+	  Layerscape Architecture processor.
+
+config TARGET_LS1012ARDB
+	bool "Support ls1012ardb"
+	select ARM64
+	help
+	  Support for Freescale LS1012ARDB platform.
+	  The LS1012A Reference design board (RDB) is a high-performance
+	  development platform that supports the QorIQ LS1012A
+	  Layerscape Architecture processor.
+
+config TARGET_LS1012AFRDM
+	bool "Support ls1012afrdm"
+	select ARM64
+	help
+	  Support for Freescale LS1012AFRDM platform.
+	  The LS1012A Freedom  board (FRDM) is a high-performance
+	  development platform that supports the QorIQ LS1012A
+	  Layerscape Architecture processor.
+
 config TARGET_LS1021AQDS
 	bool "Support ls1021aqds"
 	select CPU_V7
@@ -867,6 +894,9 @@ source "board/freescale/ls1021aqds/Kconfig"
 source "board/freescale/ls1043aqds/Kconfig"
 source "board/freescale/ls1021atwr/Kconfig"
 source "board/freescale/ls1043ardb/Kconfig"
+source "board/freescale/ls1012aqds/Kconfig"
+source "board/freescale/ls1012ardb/Kconfig"
+source "board/freescale/ls1012afrdm/Kconfig"
 source "board/freescale/mx23evk/Kconfig"
 source "board/freescale/mx25pdk/Kconfig"
 source "board/freescale/mx28evk/Kconfig"

arch/arm/cpu/armv8/fsl-layerscape/Makefile

@@ -28,3 +28,7 @@ endif
 ifneq ($(CONFIG_LS1043A),)
 obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o
 endif
+
+ifneq ($(CONFIG_LS1012A),)
+obj-$(CONFIG_SYS_HAS_SERDES) += ls1012a_serdes.o
+endif

arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc

@@ -0,0 +1,129 @@
+SoC overview
+
+	1. LS1043A
+	2. LS2080A
+	3. LS1012A
+
+LS1043A
+---------
+The LS1043A integrated multicore processor combines four ARM Cortex-A53
+processor cores with datapath acceleration optimized for L2/3 packet
+processing, single pass security offload and robust traffic management
+and quality of service.
+
+The LS1043A SoC includes the following function and features:
+ - Four 64-bit ARM Cortex-A53 CPUs
+ - 1 MB unified L2 Cache
+ - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
+   support
+ - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
+   the following functions:
+   - Packet parsing, classification, and distribution (FMan)
+   - Queue management for scheduling, packet sequencing, and congestion
+     management (QMan)
+   - Hardware buffer management for buffer allocation and de-allocation (BMan)
+   - Cryptography acceleration (SEC)
+ - Ethernet interfaces by FMan
+   - Up to 1 x XFI supporting 10G interface
+   - Up to 1 x QSGMII
+   - Up to 4 x SGMII supporting 1000Mbps
+   - Up to 2 x SGMII supporting 2500Mbps
+   - Up to 2 x RGMII supporting 1000Mbps
+ - High-speed peripheral interfaces
+   - Three PCIe 2.0 controllers, one supporting x4 operation
+   - One serial ATA (SATA 3.0) controllers
+ - Additional peripheral interfaces
+   - Three high-speed USB 3.0 controllers with integrated PHY
+   - Enhanced secure digital host controller (eSDXC/eMMC)
+   - Quad Serial Peripheral Interface (QSPI) Controller
+   - Serial peripheral interface (SPI) controller
+   - Four I2C controllers
+   - Two DUARTs
+   - Integrated flash controller supporting NAND and NOR flash
+ - QorIQ platform's trust architecture 2.1
+
+LS2080A
+--------
+The LS2080A integrated multicore processor combines eight ARM Cortex-A57
+processor cores with high-performance data path acceleration logic and network
+and peripheral bus interfaces required for networking, telecom/datacom,
+wireless infrastructure, and mil/aerospace applications.
+
+The LS2080A SoC includes the following function and features:
+
+ - Eight 64-bit ARM Cortex-A57 CPUs
+ - 1 MB platform cache with ECC
+ - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
+ - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
+  the AIOP
+ - Data path acceleration architecture (DPAA2) incorporating acceleration for
+ the following functions:
+   - Packet parsing, classification, and distribution (WRIOP)
+   - Queue and Hardware buffer management for scheduling, packet sequencing, and
+     congestion management, buffer allocation and de-allocation (QBMan)
+   - Cryptography acceleration (SEC) at up to 10 Gbps
+   - RegEx pattern matching acceleration (PME) at up to 10 Gbps
+   - Decompression/compression acceleration (DCE) at up to 20 Gbps
+   - Accelerated I/O processing (AIOP) at up to 20 Gbps
+   - QDMA engine
+ - 16 SerDes lanes at up to 10.3125 GHz
+ - Ethernet interfaces
+   - Up to eight 10 Gbps Ethernet MACs
+   - Up to eight 1 / 2.5 Gbps Ethernet MACs
+ - High-speed peripheral interfaces
+   - Four PCIe 3.0 controllers, one supporting SR-IOV
+ - Additional peripheral interfaces
+   - Two serial ATA (SATA 3.0) controllers
+   - Two high-speed USB 3.0 controllers with integrated PHY
+   - Enhanced secure digital host controller (eSDXC/eMMC)
+   - Serial peripheral interface (SPI) controller
+   - Quad Serial Peripheral Interface (QSPI) Controller
+   - Four I2C controllers
+   - Two DUARTs
+   - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash
+ - Support for hardware virtualization and partitioning enforcement
+ - QorIQ platform's trust architecture 3.0
+ - Service processor (SP) provides pre-boot initialization and secure-boot
+  capabilities
+
+LS1012A
+--------
+The LS1012A features an advanced 64-bit ARM v8 Cortex-
+A53 processor, with 32 KB of parity protected L1-I cache,
+32 KB of ECC protected L1-D cache, as well as 256 KB of
+ECC protected L2 cache.
+
+The LS1012A SoC includes the following function and features:
+ - One 64-bit ARM v8 Cortex-A53 core with the following capabilities:
+ - ARM v8 cryptography extensions
+ - One 16-bit DDR3L SDRAM memory controller, Up to 1.0 GT/s, Supports
+    16-/8-bit operation (no ECC support)
+ - ARM core-link CCI-400 cache coherent interconnect
+ - Packet Forwarding Engine (PFE)
+ - Cryptography acceleration (SEC)
+ - Ethernet interfaces supported by PFE:
+ - One Configurable x3 SerDes:
+    Two Serdes PLLs supported for usage by any SerDes data lane
+    Support for up to 6 GBaud operation
+ - High-speed peripheral interfaces:
+     - One PCI Express Gen2 controller, supporting x1 operation
+     - One serial ATA (SATA Gen 3.0) controller
+     - One USB 3.0/2.0 controller with integrated PHY
+     - One USB 2.0 controller with ULPI interface. .
+ - Additional peripheral interfaces:
+    - One quad serial peripheral interface (QuadSPI) controller
+    - One serial peripheral interface (SPI) controller
+    - Two enhanced secure digital host controllers
+    - Two I2C controllers
+    - One 16550 compliant DUART (two UART interfaces)
+    - Two general purpose IOs (GPIO)
+    - Two FlexTimers
+    - Five synchronous audio interfaces (SAI)
+    - Pre-boot loader (PBL) provides pre-boot initialization and RCW loading
+    - Single-source clocking solution enabling generation of core, platform,
+    DDR, SerDes, and USB clocks from a single external crystal and internal
+    crystaloscillator
+    - Thermal monitor unit (TMU) with +/- 3C accuracy
+    - Two WatchDog timers
+    - ARM generic timer
+ - QorIQ platform's trust architecture 2.1

arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c

@@ -25,7 +25,10 @@ void get_sys_info(struct sys_info *sys_info)
 	struct fsl_ifc ifc_regs = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
 	u32 ccr;
 #endif
-#if defined(CONFIG_FSL_ESDHC) || defined(CONFIG_SYS_DPAA_FMAN)
+#if (defined(CONFIG_FSL_ESDHC) &&\
+	defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)) ||\
+	defined(CONFIG_SYS_DPAA_FMAN)
+
 	u32 rcw_tmp;
 #endif
 	struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
@@ -56,12 +59,18 @@ void get_sys_info(struct sys_info *sys_info)
 	sys_info->freq_ddrbus = sysclk;
 #endif
 
+#ifdef CONFIG_LS1012A
+	sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
+			FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
+			FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
+#else
 	sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
 			FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
 			FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
 	sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
 			FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
 			FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
+#endif
 
 	for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
 		ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0xff;
@@ -80,6 +89,11 @@ void get_sys_info(struct sys_info *sys_info)
 			freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
 	}
 
+#ifdef CONFIG_LS1012A
+	sys_info->freq_systembus = sys_info->freq_ddrbus / 2;
+	sys_info->freq_ddrbus *= 2;
+#endif
+
 #define HWA_CGA_M1_CLK_SEL	0xe0000000
 #define HWA_CGA_M1_CLK_SHIFT	29
 #ifdef CONFIG_SYS_DPAA_FMAN

arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S

@@ -94,11 +94,13 @@ ENTRY(lowlevel_init)
 	bl	ccn504_set_qos
 #endif
 
+#ifdef SMMU_BASE
 	/* Set the SMMU page size in the sACR register */
 	ldr	x1, =SMMU_BASE
 	ldr	w0, [x1, #0x10]
 	orr	w0, w0, #1 << 16  /* set sACR.pagesize to indicate 64K page */
 	str	w0, [x1, #0x10]
+#endif
 
 	/* Initialize GIC Secure Bank Status */
 #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
@@ -181,6 +183,7 @@ ENTRY(lowlevel_init)
 	ret
 ENDPROC(lowlevel_init)
 
+#ifdef CONFIG_FSL_LSCH3
 hnf_pstate_poll:
 	/* x0 has the desired status, return 0 for success, 1 for timeout
 	 * clobber x1, x2, x3, x4, x6, x7
@@ -258,6 +261,7 @@ ENTRY(__asm_flush_l3_cache)
 	mov	lr, x29
 	ret
 ENDPROC(__asm_flush_l3_cache)
+#endif
 
 #ifdef CONFIG_MP
 	/* Keep literals not used by the secondary boot code outside it */

arch/arm/cpu/armv8/fsl-layerscape/ls1012a_serdes.c

@@ -0,0 +1,74 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/immap_lsch2.h>
+
+struct serdes_config {
+	u32 protocol;
+	u8 lanes[SRDS_MAX_LANES];
+};
+
+static struct serdes_config serdes1_cfg_tbl[] = {
+	{0x2208, {SGMII_2500_FM1_DTSEC1, SGMII_2500_FM1_DTSEC2, NONE, SATA1} },
+	{0x0008, {NONE, NONE, NONE, SATA1} },
+	{0x3508, {SGMII_FM1_DTSEC1, PCIE1, NONE, SATA1} },
+	{0x3305, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, NONE, PCIE1} },
+	{0x2205, {SGMII_2500_FM1_DTSEC1, SGMII_2500_FM1_DTSEC2, NONE, PCIE1} },
+	{0x2305, {SGMII_2500_FM1_DTSEC1, SGMII_FM1_DTSEC2, NONE, PCIE1} },
+	{0x9508, {TX_CLK, PCIE1, NONE, SATA1} },
+	{0x3905, {SGMII_FM1_DTSEC1, TX_CLK, NONE, PCIE1} },
+	{0x9305, {TX_CLK, SGMII_FM1_DTSEC2, NONE, PCIE1} },
+	{}
+};
+
+static struct serdes_config *serdes_cfg_tbl[] = {
+	serdes1_cfg_tbl,
+};
+
+enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
+{
+	struct serdes_config *ptr;
+
+	if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+		return 0;
+
+	ptr = serdes_cfg_tbl[serdes];
+	while (ptr->protocol) {
+		if (ptr->protocol == cfg)
+			return ptr->lanes[lane];
+		ptr++;
+	}
+
+	return 0;
+}
+
+int is_serdes_prtcl_valid(int serdes, u32 prtcl)
+{
+	int i;
+	struct serdes_config *ptr;
+
+	if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
+		return 0;
+
+	ptr = serdes_cfg_tbl[serdes];
+	while (ptr->protocol) {
+		if (ptr->protocol == prtcl)
+			break;
+		ptr++;
+	}
+
+	if (!ptr->protocol)
+		return 0;
+
+	for (i = 0; i < SRDS_MAX_LANES; i++) {
+		if (ptr->lanes[i] != NONE)
+			return 1;
+	}
+
+	return 0;
+}

arch/arm/cpu/armv8/fsl-layerscape/soc.c

@@ -12,8 +12,10 @@
 #include <asm/io.h>
 #include <asm/global_data.h>
 #include <asm/arch-fsl-layerscape/config.h>
+#ifdef CONFIG_SYS_FSL_DDR
 #include <fsl_ddr_sdram.h>
 #include <fsl_ddr.h>
+#endif
 #ifdef CONFIG_CHAIN_OF_TRUST
 #include <fsl_validate.h>
 #endif
@@ -224,7 +226,7 @@ int sata_init(void)
 }
 #endif
 
-#elif defined(CONFIG_LS1043A)
+#elif defined(CONFIG_FSL_LSCH2)
 #ifdef CONFIG_SCSI_AHCI_PLAT
 int sata_init(void)
 {

arch/arm/dts/Makefile

@@ -122,7 +122,10 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
 	fsl-ls2080a-rdb.dtb
 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
 	fsl-ls1043a-qds-lpuart.dtb \
-	fsl-ls1043a-rdb.dtb
+	fsl-ls1043a-rdb.dtb \
+	fsl-ls1012a-qds.dtb \
+	fsl-ls1012a-rdb.dtb \
+	fsl-ls1012a-frdm.dtb
 
 dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb
 

arch/arm/dts/fsl-ls1012a-frdm.dts

@@ -0,0 +1,16 @@
+/*
+ * Device Tree file for Freescale Layerscape-1012A family SoC.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+#include "fsl-ls1012a-frdm.dtsi"
+
+/ {
+	chosen {
+		stdout-path = &duart0;
+	};
+};

arch/arm/dts/fsl-ls1012a-frdm.dtsi

@@ -0,0 +1,37 @@
+/*
+ * Device Tree file for Freescale Layerscape-1012A family SoC.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/include/ "fsl-ls1012a.dtsi"
+
+/ {
+	model = "LS1012A FREEDOM Board";
+	aliases {
+		spi0 = &qspi;
+	};
+};
+
+&qspi {
+	bus-num = <0>;
+	status = "okay";
+
+	qflash0: s25fl128s@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+&duart0 {
+	status = "okay";
+};

arch/arm/dts/fsl-ls1012a-qds.dts

@@ -0,0 +1,14 @@
+/*
+ * Copyright 2016 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+#include "fsl-ls1012a-qds.dtsi"
+
+/ {
+       chosen {
+               stdout-path = &duart0;
+       };
+};

arch/arm/dts/fsl-ls1012a-qds.dtsi

@@ -0,0 +1,123 @@
+/*
+ * Copyright 2016 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/include/ "fsl-ls1012a.dtsi"
+
+/ {
+	model = "LS1012A QDS Board";
+	aliases {
+		spi0 = &qspi;
+		spi1 = &dspi0;
+	};
+};
+
+&dspi0 {
+	bus-num = <0>;
+	status = "okay";
+
+	dflash0: n25q128a {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		reg = <0>;
+		spi-max-frequency = <1000000>; /* input clock */
+	};
+
+	dflash1: sst25wf040b {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <3500000>;
+		reg = <1>;
+	};
+
+	dflash2: en25s64 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <3500000>;
+		reg = <2>;
+	};
+};
+
+&qspi {
+	bus-num = <0>;
+	status = "okay";
+
+	qflash0: s25fl128s@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
+};
+
+&i2c0 {
+	status = "okay";
+	pca9547@77 {
+		compatible = "philips,pca9547";
+		reg = <0x77>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		i2c@0 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0>;
+
+			rtc@68 {
+				compatible = "dallas,ds3232";
+				reg = <0x68>;
+				/* IRQ10_B */
+				interrupts = <0 150 0x4>;
+			};
+		};
+
+		i2c@2 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x2>;
+
+			ina220@40 {
+				compatible = "ti,ina220";
+				reg = <0x40>;
+				shunt-resistor = <1000>;
+			};
+
+			ina220@41 {
+				compatible = "ti,ina220";
+				reg = <0x41>;
+				shunt-resistor = <1000>;
+			};
+		};
+
+		i2c@3 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x3>;
+
+			eeprom@56 {
+				compatible = "at24,24c512";
+				reg = <0x56>;
+			};
+
+			eeprom@57 {
+				compatible = "at24,24c512";
+				reg = <0x57>;
+			};
+
+			adt7461a@4c {
+				compatible = "adt7461a";
+				reg = <0x4c>;
+			};
+		};
+	};
+};
+
+&duart0 {
+	status = "okay";
+};

arch/arm/dts/fsl-ls1012a-rdb.dts

@@ -0,0 +1,16 @@
+/*
+ * Device Tree file for Freescale Layerscape-1012A family SoC.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/dts-v1/;
+#include "fsl-ls1012a-rdb.dtsi"
+
+/ {
+       chosen {
+               stdout-path = &duart0;
+       };
+};

arch/arm/dts/fsl-ls1012a-rdb.dtsi

@@ -0,0 +1,39 @@
+/*
+ * Device Tree Include file for Freescale Layerscape-1012A family SoC.
+ *
+ * Copyright 2016, Freescale Semiconductor
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+/include/ "fsl-ls1012a.dtsi"
+
+/ {
+	model = "LS1012A RDB Board";
+	aliases {
+		spi0 = &qspi;
+	};
+};
+
+&qspi {
+	bus-num = <0>;
+	status = "okay";
+
+	qflash0: s25fl128s@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "spi-flash";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+	};
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+&duart0 {
+	status = "okay";
+};

arch/arm/dts/fsl-ls1012a.dtsi

@@ -0,0 +1,119 @@
+/*
+ * Copyright 2016 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/include/ "skeleton64.dtsi"
+
+/ {
+	compatible = "fsl,ls1012a";
+	interrupt-parent = <&gic>;
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <0x0 0x0>;
+			clocks = <&clockgen 1 0>;
+		};
+
+	};
+
+	sysclk: sysclk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+		clock-output-names = "sysclk";
+	};
+
+	gic: interrupt-controller@1400000 {
+		compatible = "arm,gic-400";
+		#interrupt-cells = <3>;
+		interrupt-controller;
+		reg = <0x0 0x1401000 0 0x1000>, /* GICD */
+		      <0x0 0x1402000 0 0x2000>, /* GICC */
+		      <0x0 0x1404000 0 0x2000>, /* GICH */
+		      <0x0 0x1406000 0 0x2000>; /* GICV */
+		interrupts = <1 9 0xf08>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		clockgen: clocking@1ee1000 {
+			compatible = "fsl,ls1012a-clockgen";
+			reg = <0x0 0x1ee1000 0x0 0x1000>;
+			#clock-cells = <2>;
+			clocks = <&sysclk>;
+		};
+
+		dspi0: dspi@2100000 {
+			compatible = "fsl,vf610-dspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x2100000 0x0 0x10000>;
+			interrupts = <0 64 0x4>;
+			clock-names = "dspi";
+			clocks = <&clockgen 4 0>;
+			num-cs = <6>;
+			big-endian;
+			status = "disabled";
+		};
+
+
+		i2c0: i2c@2180000 {
+			compatible = "fsl,vf610-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x2180000 0x0 0x10000>;
+			interrupts = <0 56 0x4>;
+			clock-names = "i2c";
+			clocks = <&clockgen 4 0>;
+			status = "disabled";
+		};
+
+		i2c1: i2c@2190000 {
+			compatible = "fsl,vf610-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x2190000 0x0 0x10000>;
+			interrupts = <0 57 0x4>;
+			clock-names = "i2c";
+			clocks = <&clockgen 4 0>;
+			status = "disabled";
+		};
+
+		duart0: serial@21c0500 {
+			compatible = "fsl,ns16550", "ns16550a";
+			reg = <0x00 0x21c0500 0x0 0x100>;
+			interrupts = <0 54 0x4>;
+			clocks = <&clockgen 4 0>;
+		};
+
+		duart1: serial@21c0600 {
+			compatible = "fsl,ns16550", "ns16550a";
+			reg = <0x00 0x21c0600 0x0 0x100>;
+			interrupts = <0 54 0x4>;
+			clocks = <&clockgen 4 0>;
+		};
+
+		qspi: quadspi@1550000 {
+			compatible = "fsl,vf610-qspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x1550000 0x0 0x10000>,
+				<0x0 0x40000000 0x0 0x4000000>;
+			reg-names = "QuadSPI", "QuadSPI-memory";
+			num-cs = <2>;
+			big-endian;
+			status = "disabled";
+		};
+
+	};
+};

arch/arm/include/asm/arch-fsl-layerscape/config.h

@@ -14,8 +14,11 @@
 #else
 #define CONFIG_SYS_FSL_DDRC_ARM_GEN3	/* Enable Freescale ARM DDR3 driver */
 #endif
+
+#ifndef CONFIG_LS1012A
 #define CONFIG_SYS_FSL_DDR		/* Freescale DDR driver */
 #define CONFIG_SYS_FSL_DDR_VER		FSL_DDR_VER_5_0
+#endif
 
 /*
  * Reserve secure memory
@@ -200,6 +203,32 @@
 #define CONFIG_SYS_FSL_ERRATUM_A009942
 #define CONFIG_SYS_FSL_ERRATUM_A009660
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
+#elif defined(CONFIG_LS1012A)
+#define CONFIG_MAX_CPUS                         1
+#define CONFIG_SYS_CACHELINE_SIZE		64
+#define CONFIG_NUM_DDR_CONTROLLERS		1
+#define CONFIG_SYS_CCSRBAR_DEFAULT		0x01000000
+#define CONFIG_SYS_FSL_SEC_COMPAT		5
+#undef	CONFIG_SYS_FSL_DDRC_ARM_GEN3
+
+#define CONFIG_SYS_FSL_OCRAM_BASE		0x10000000 /* initial RAM */
+#define CONFIG_SYS_FSL_OCRAM_SIZE		0x200000 /* 2 MiB */
+
+#define GICD_BASE		0x01401000
+#define GICC_BASE		0x01402000
+
+#define CONFIG_SYS_FSL_CCSR_GUR_BE
+#define CONFIG_SYS_FSL_CCSR_SCFG_BE
+#define CONFIG_SYS_FSL_ESDHC_BE
+#define CONFIG_SYS_FSL_WDOG_BE
+#define CONFIG_SYS_FSL_DSPI_BE
+#define CONFIG_SYS_FSL_QSPI_BE
+#define CONFIG_SYS_FSL_PEX_LUT_BE
+
+#define SRDS_MAX_LANES		4
+#define CONFIG_SYS_FSL_SRDS_1
+#define CONFIG_SYS_FSL_PCIE_COMPAT		"fsl,qoriq-pcie-v2.4"
+#define CONFIG_SYS_FSL_SEC_BE
 #else
 #error SoC not defined
 #endif

arch/arm/include/asm/arch-fsl-layerscape/cpu.h

@@ -14,6 +14,7 @@ static struct cpu_type cpu_type_list[] = {
 	CPU_TYPE_ENTRY(LS1043, LS1043, 4),
 	CPU_TYPE_ENTRY(LS1023, LS1023, 2),
 	CPU_TYPE_ENTRY(LS2040, LS2040, 4),
+	CPU_TYPE_ENTRY(LS1012, LS1012, 1),
 };
 
 #ifndef CONFIG_SYS_DCACHE_OFF

arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h

@@ -55,7 +55,7 @@ enum srds {
 	FSL_SRDS_1  = 0,
 	FSL_SRDS_2  = 1,
 };
-#elif defined(CONFIG_LS1043A)
+#elif defined(CONFIG_FSL_LSCH2)
 enum srds_prtcl {
 	NONE = 0,
 	PCIE1,
@@ -134,6 +134,7 @@ enum srds_prtcl {
 	SGMII_2500_FM2_DTSEC6,
 	SGMII_2500_FM2_DTSEC9,
 	SGMII_2500_FM2_DTSEC10,
+	TX_CLK,
 	SERDES_PRCTL_COUNT
 };
 

arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h

@@ -60,7 +60,11 @@
 #define CONFIG_SYS_PCIE2_PHYS_ADDR		0x4800000000ULL
 #define CONFIG_SYS_PCIE3_PHYS_ADDR		0x5000000000ULL
 /* LUT registers */
+#ifdef CONFIG_LS1012A
+#define PCIE_LUT_BASE				0xC0000
+#else
 #define PCIE_LUT_BASE				0x10000
+#endif
 #define PCIE_LUT_LCTRL0				0x7F8
 #define PCIE_LUT_DBG				0x7FC
 

arch/arm/include/asm/arch-fsl-layerscape/ns_access.h

@@ -69,7 +69,12 @@ enum csu_cslx_ind {
 	CSU_CSLX_IIC4 = 77,
 	CSU_CSLX_WDT4,
 	CSU_CSLX_WDT3,
+	CSU_CSLX_ESDHC2 = 80,
 	CSU_CSLX_WDT5 = 81,
+	CSU_CSLX_SAI2,
+	CSU_CSLX_SAI1,
+	CSU_CSLX_SAI4,
+	CSU_CSLX_SAI3,
 	CSU_CSLX_FTM2 = 86,
 	CSU_CSLX_FTM1,
 	CSU_CSLX_FTM4,
@@ -143,7 +148,12 @@ static struct csu_ns_dev ns_dev[] = {
 	 {CSU_CSLX_IIC4, CSU_ALL_RW},
 	 {CSU_CSLX_WDT4, CSU_ALL_RW},
 	 {CSU_CSLX_WDT3, CSU_ALL_RW},
+	 {CSU_CSLX_ESDHC2, CSU_ALL_RW},
 	 {CSU_CSLX_WDT5, CSU_ALL_RW},
+	 {CSU_CSLX_SAI2, CSU_ALL_RW},
+	 {CSU_CSLX_SAI1, CSU_ALL_RW},
+	 {CSU_CSLX_SAI4, CSU_ALL_RW},
+	 {CSU_CSLX_SAI3, CSU_ALL_RW},
 	 {CSU_CSLX_FTM2, CSU_ALL_RW},
 	 {CSU_CSLX_FTM1, CSU_ALL_RW},
 	 {CSU_CSLX_FTM4, CSU_ALL_RW},

arch/arm/include/asm/arch-fsl-layerscape/soc.h

@@ -41,6 +41,7 @@ struct cpu_type {
 	{ .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
 
 #define SVR_WO_E		0xFFFFFE
+#define SVR_LS1012		0x870400
 #define SVR_LS1043		0x879200
 #define SVR_LS1023		0x879208
 #define SVR_LS2045		0x870120

board/freescale/common/ls102xa_stream_id.c

@@ -12,9 +12,12 @@ void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num)
 {
 	void *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
 	int i;
+	u32 icid;
 
-	for (i = 0; i < num; i++)
-		out_be32((u32 *)(scfg + id[i].offset), id[i].stream_id);
+	for (i = 0; i < num; i++) {
+		icid = (id[i].stream_id & 0xff) << 24;
+		out_be32((u32 *)(scfg + id[i].offset), icid);
+	}
 }
 
 void ls1021x_config_caam_stream_id(struct liodn_id_table *tbl, int size)

board/freescale/common/qixis.c

@@ -14,6 +14,13 @@
 #include <i2c.h>
 #include "qixis.h"
 
+#ifndef QIXIS_LBMAP_BRDCFG_REG
+/*
+ * For consistency with existing platforms
+ */
+#define QIXIS_LBMAP_BRDCFG_REG 0x00
+#endif
+
 #ifdef CONFIG_SYS_I2C_FPGA_ADDR
 u8 qixis_read_i2c(unsigned int reg)
 {
@@ -27,6 +34,7 @@ void qixis_write_i2c(unsigned int reg, u8 value)
 }
 #endif
 
+#ifdef QIXIS_BASE
 u8 qixis_read(unsigned int reg)
 {
 	void *p = (void *)QIXIS_BASE;
@@ -40,6 +48,7 @@ void qixis_write(unsigned int reg, u8 value)
 
 	out_8(p + reg, value);
 }
+#endif
 
 u16 qixis_read_minor(void)
 {
@@ -142,9 +151,9 @@ static void __maybe_unused set_lbmap(int lbmap)
 {
 	u8 reg;
 
-	reg = QIXIS_READ(brdcfg[0]);
+	reg = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
 	reg = (reg & ~QIXIS_LBMAP_MASK) | lbmap;
-	QIXIS_WRITE(brdcfg[0], reg);
+	QIXIS_WRITE(brdcfg[QIXIS_LBMAP_BRDCFG_REG], reg);
 }
 
 static void __maybe_unused set_rcw_src(int rcw_src)

board/freescale/ls1012afrdm/Kconfig

@@ -0,0 +1,15 @@
+if TARGET_LS1012AFRDM
+
+config SYS_BOARD
+	default "ls1012afrdm"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+	default "ls1012afrdm"
+
+endif

board/freescale/ls1012afrdm/MAINTAINERS

@@ -0,0 +1,6 @@
+LS1012AFRDM BOARD
+M:	Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+S:	Maintained
+F:	board/freescale/ls1012afrdm/
+F:	include/configs/ls1012afrdm.h
+F:	configs/ls1012afrdm_qspi_defconfig

board/freescale/ls1012afrdm/Makefile

@@ -0,0 +1,7 @@
+#
+# Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += ls1012afrdm.o

board/freescale/ls1012afrdm/README

@@ -0,0 +1,58 @@
+Overview
+--------
+QorIQ LS1012A FREEDOM (LS1012AFRDM) is a high-performance development
+platform, with a complete debugging environment. The LS1012AFRDM board
+supports the QorIQ LS1012A processor and is optimized to support the
+high-bandwidth DDR3L memory and a full complement of high-speed SerDes ports.
+
+LS1012A SoC Overview
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
+SoC overview.
+
+ LS1012AFRDM board Overview
+ -----------------------
+ - SERDES Connections, 2 lanes supportingspeeds upto 1 Gbit/s
+     - 2 SGMII 1G PHYs
+ - DDR Controller
+     - 4 Gb DDR3L SDRAM memory, running at data rates up to 1 GT/s
+	operating at 1.35 V
+ - QSPI
+     - Onboard 512 Mbit QSPI flash memory running at speed up
+      to 108/54 MHz
+ - One high-speed USB 2.0/3.0 port, one USB 2.0 port
+     - USB 2.0/3.0 port is configured as On-The-Go (OTG) with a
+       Micro-AB connector.
+     - USB 2.0 port is a debug port (CMSIS DAP) and is configured
+       as a Micro-AB device.
+ - I2C controller
+     - One I2C bus with connectivity to Arduino headers
+ - UART
+     - UART (Console): UART1 (Without flow control) for console
+ - ARM JTAG support
+     - ARM Cortex® 10-pin JTAG connector for LS1012A
+     - CMSIS DAP through K20 microcontroller
+ - SAI Audio interface
+     - One SAI port, SAI 2 with full duplex support
+ - Clocks
+     - 25 MHz crystal for LS1012A
+     - 8 MHz Crystal for K20
+     - 24 MHz for SC16IS740IPW SPI to Dual UART bridge
+ - Power Supplies
+     - 5 V input supply from USB
+     - 0.9 V, 1.35 V, and 1.8 V for VDD/Core, DDR, I/O, and
+       other board interfaces
+
+Booting Options
+---------------
+QSPI Flash 1
+
+QSPI flash map
+--------------
+Images		| Size	|QSPI Flash Address
+------------------------------------------
+RCW + PBI	| 1MB	| 0x4000_0000
+U-boot 		| 1MB	| 0x4010_0000
+U-boot Env 	| 1MB	| 0x4020_0000
+PPA FIT image	| 2MB	| 0x4050_0000
+Linux ITB	| ~53MB | 0x40A0_0000

board/freescale/ls1012afrdm/ls1012afrdm.c

@@ -0,0 +1,192 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/soc.h>
+#include <hwconfig.h>
+#include <fsl_csu.h>
+#include <environment.h>
+#include <fsl_mmdc.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
+{
+	int timeout = 1000;
+
+	out_be32(ptr, value);
+
+	while (in_be32(ptr) & bits) {
+		udelay(100);
+		timeout--;
+	}
+	if (timeout <= 0)
+		puts("Error: wait for clear timeout.\n");
+}
+
+int checkboard(void)
+{
+	puts("Board: LS1012AFRDM ");
+
+	return 0;
+}
+
+void mmdc_init(void)
+{
+	struct mmdc_p_regs *mmdc =
+		(struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
+
+	out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
+
+	/* configure timing parms */
+	out_be32(&mmdc->mdotc,  CONFIG_SYS_MMDC_CORE_ODT_TIMING);
+	out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0);
+	out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1);
+	out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2);
+
+	/* other parms	*/
+	out_be32(&mmdc->mdmisc,    CONFIG_SYS_MMDC_CORE_MISC);
+	out_be32(&mmdc->mpmur0,    CONFIG_SYS_MMDC_PHY_MEASURE_UNIT);
+	out_be32(&mmdc->mdrwd,     CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY);
+	out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL);
+
+	/* out of reset delays */
+	out_be32(&mmdc->mdor,  CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY);
+
+	/* physical parms */
+	out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1);
+	out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION);
+
+       /* Enable MMDC */
+	out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2);
+
+	/* dram init sequence: update MRs */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2));
+	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+				CMD_BANK_ADDR_3));
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
+	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) |
+				CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0));
+
+       /* dram init sequence: ZQCL */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+				CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0));
+	set_wait_for_bits_clear(&mmdc->mpzqhwctrl,
+				CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL,
+				FORCE_ZQ_AUTO_CALIBRATION);
+
+       /* Calibrations now: wr lvl */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) |
+				CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+				CMD_BANK_ADDR_1));
+	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL));
+	set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN);
+
+	mdelay(1);
+
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
+	out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
+
+	mdelay(1);
+
+       /* Calibrations now: Read DQS gating calibration */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+				CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
+	out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
+	out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG);
+	set_wait_for_bits_clear(&mmdc->mpdgctrl0,
+				AUTO_RD_DQS_GATING_CALIBRATION_EN,
+				AUTO_RD_DQS_GATING_CALIBRATION_EN);
+
+	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+				CMD_BANK_ADDR_3));
+
+       /* Calibrations now: Read calibration */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+				CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
+	out_be32(&mmdc->mppdcmpr2,  MPR_COMPARE_EN);
+	set_wait_for_bits_clear(&mmdc->mprddlhwctl,
+				AUTO_RD_CALIBRATION_EN,
+				AUTO_RD_CALIBRATION_EN);
+
+	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+				CMD_BANK_ADDR_3));
+
+       /* PD, SR */
+	out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL);
+	out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT);
+
+       /* refresh scheme */
+	set_wait_for_bits_clear(&mmdc->mdref,
+				CONFIG_SYS_MMDC_CORE_REFRESH_CTL,
+				START_REFRESH);
+
+       /* disable CON_REQ */
+	out_be32(&mmdc->mdscr, DISABLE_CFG_REQ);
+}
+
+int dram_init(void)
+{
+	mmdc_init();
+
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
+
+int board_early_init_f(void)
+{
+	fsl_lsch2_early_init_f();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+	/*
+	 * Set CCI-400 control override register to enable barrier
+	 * transaction
+	 */
+	out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+
+#ifdef CONFIG_ENV_IS_NOWHERE
+	gd->env_addr = (ulong)&default_environment[0];
+#endif
+
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+	enable_layerscape_ns_access();
+#endif
+
+	return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	arch_fixup_fdt(blob);
+
+	ft_cpu_setup(blob, bd);
+
+	return 0;
+}

board/freescale/ls1012aqds/Kconfig

@@ -0,0 +1,15 @@
+if TARGET_LS1012AQDS
+
+config SYS_BOARD
+	default "ls1012aqds"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+	default "ls1012aqds"
+
+endif

board/freescale/ls1012aqds/MAINTAINERS

@@ -0,0 +1,6 @@
+LS1012AQDS BOARD
+M:	Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+S:	Maintained
+F:	board/freescale/ls1012aqds/
+F:	include/configs/ls1012aqds.h
+F:	configs/ls1012aqds_qspi_defconfig

board/freescale/ls1012aqds/Makefile

@@ -0,0 +1,7 @@
+#
+# Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += ls1012aqds.o

board/freescale/ls1012aqds/README

@@ -0,0 +1,59 @@
+Overview
+--------
+QorIQ LS1012A Development System (LS1012AQDS) is a high-performance
+development platform, with a complete debugging environment.
+The LS1012AQDS board supports the QorIQ LS1012A processor and is
+optimized to support the high-bandwidth DDR3L memory and
+a full complement of high-speed SerDes ports.
+
+LS1012A SoC Overview
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1012A
+SoC overview.
+
+LS1012AQDS board Overview
+-----------------------
+ - SERDES Connections, 4 lanes supporting:
+      - PCI Express - 3.0
+      - SGMII, SGMII 2.5
+      - SATA 3.0
+ - DDR Controller
+     - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
+ - QSPI Controller
+     - A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
+       signals to QSPI NOR flash memory (2 virtual banks) and the QSPI
+       emulator
+ - USB 3.0
+    - One USB 3.0 controller with integrated PHY
+    - One high-speed USB 3.0 port
+ - USB 2.0
+    - One USB 2.0 controller with ULPI interface
+ - Two enhanced secure digital host controllers:
+    - SDHC1 controller can be connected to onboard SDHC connector
+    - SDHC2 controller: 1-/4-bit SD/MMC card supporting 1.8 V devices
+ - 2 I2C controllers
+ - One SATA onboard connectors
+ - UART
+ - 5 SAI
+    - One SAI port with audio codec SGTL5000:
+	• Provides MIC bias
+	• Provides headphone and line output
+    - One SAI port terminated at 2x6 header
+    - Three SAI Tx/Rx ports terminated at 2x3 headers
+ - ARM JTAG support
+
+Booting Options
+---------------
+a) QSPI Flash Emu Boot
+b) QSPI Flash 1
+c) QSPI Flash 2
+
+QSPI flash map
+--------------
+Images		| Size	|QSPI Flash Address
+------------------------------------------
+RCW + PBI	| 1MB	| 0x4000_0000
+U-boot 		| 1MB	| 0x4010_0000
+U-boot Env 	| 1MB	| 0x4020_0000
+PPA FIT image	| 2MB	| 0x4050_0000
+Linux ITB	| ~53MB | 0x40A0_0000

board/freescale/ls1012aqds/ls1012aqds.c

@@ -0,0 +1,234 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <fdt_support.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/fdt.h>
+#include <asm/arch/soc.h>
+#include <ahci.h>
+#include <hwconfig.h>
+#include <mmc.h>
+#include <scsi.h>
+#include <fm_eth.h>
+#include <fsl_csu.h>
+#include <fsl_esdhc.h>
+#include <fsl_mmdc.h>
+#include <spl.h>
+#include <netdev.h>
+
+#include "../common/qixis.h"
+#include "ls1012aqds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
+{
+	int timeout = 1000;
+
+	out_be32(ptr, value);
+
+	while (in_be32(ptr) & bits) {
+		udelay(100);
+		timeout--;
+	}
+	if (timeout <= 0)
+		puts("Error: wait for clear timeout.\n");
+}
+
+int checkboard(void)
+{
+	char buf[64];
+	u8 sw;
+
+	sw = QIXIS_READ(arch);
+	printf("Board Arch: V%d, ", sw >> 4);
+	printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
+
+	sw = QIXIS_READ(brdcfg[QIXIS_LBMAP_BRDCFG_REG]);
+
+	if (sw & QIXIS_LBMAP_ALTBANK)
+		printf("flash: 2\n");
+	else
+		printf("flash: 1\n");
+
+	printf("FPGA: v%d (%s), build %d",
+	       (int)QIXIS_READ(scver), qixis_read_tag(buf),
+	       (int)qixis_read_minor());
+
+	/* the timestamp string contains "\n" at the end */
+	printf(" on %s", qixis_read_time(buf));
+	return 0;
+}
+
+void mmdc_init(void)
+{
+	struct mmdc_p_regs *mmdc =
+		(struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
+
+	out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
+
+	/* configure timing parms */
+	out_be32(&mmdc->mdotc,  CONFIG_SYS_MMDC_CORE_ODT_TIMING);
+	out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0);
+	out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1);
+	out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2);
+
+	/* other parms	*/
+	out_be32(&mmdc->mdmisc,    CONFIG_SYS_MMDC_CORE_MISC);
+	out_be32(&mmdc->mpmur0,    CONFIG_SYS_MMDC_PHY_MEASURE_UNIT);
+	out_be32(&mmdc->mdrwd,     CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY);
+	out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL);
+
+	/* out of reset delays */
+	out_be32(&mmdc->mdor,  CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY);
+
+	/* physical parms */
+	out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1);
+	out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION);
+
+       /* Enable MMDC */
+	out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2);
+
+	/* dram init sequence: update MRs */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2));
+	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+				CMD_BANK_ADDR_3));
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
+	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) |
+				CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0));
+
+       /* dram init sequence: ZQCL */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+				CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0));
+	set_wait_for_bits_clear(&mmdc->mpzqhwctrl,
+				CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL,
+				FORCE_ZQ_AUTO_CALIBRATION);
+
+       /* Calibrations now: wr lvl */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) |
+				CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+				CMD_BANK_ADDR_1));
+	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL));
+	set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN);
+
+	mdelay(1);
+
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
+	out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
+
+	mdelay(1);
+
+       /* Calibrations now: Read DQS gating calibration */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+				CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
+	out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
+	out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG);
+	set_wait_for_bits_clear(&mmdc->mpdgctrl0,
+				AUTO_RD_DQS_GATING_CALIBRATION_EN,
+				AUTO_RD_DQS_GATING_CALIBRATION_EN);
+
+	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+				CMD_BANK_ADDR_3));
+
+       /* Calibrations now: Read calibration */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+				CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
+	out_be32(&mmdc->mppdcmpr2,  MPR_COMPARE_EN);
+	set_wait_for_bits_clear(&mmdc->mprddlhwctl,
+				AUTO_RD_CALIBRATION_EN,
+				AUTO_RD_CALIBRATION_EN);
+
+	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+				CMD_BANK_ADDR_3));
+
+       /* PD, SR */
+	out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL);
+	out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT);
+
+       /* refresh scheme */
+	set_wait_for_bits_clear(&mmdc->mdref,
+				CONFIG_SYS_MMDC_CORE_REFRESH_CTL,
+				START_REFRESH);
+
+       /* disable CON_REQ */
+	out_be32(&mmdc->mdscr, DISABLE_CFG_REQ);
+}
+
+int dram_init(void)
+{
+	mmdc_init();
+
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+int board_early_init_f(void)
+{
+	fsl_lsch2_early_init_f();
+
+	return 0;
+}
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+	u8 mux_sdhc_cd = 0x80;
+
+	i2c_set_bus_num(0);
+
+	i2c_write(CONFIG_SYS_I2C_FPGA_ADDR, 0x5a, 1, &mux_sdhc_cd, 1);
+	return 0;
+}
+#endif
+
+int board_init(void)
+{
+	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)
+				   CONFIG_SYS_CCI400_ADDR;
+
+	/* Set CCI-400 control override register to enable barrier
+	 * transaction */
+	out_le32(&cci->ctrl_ord,
+		 CCI400_CTRLORD_EN_BARRIER);
+
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+	enable_layerscape_ns_access();
+#endif
+
+#ifdef CONFIG_ENV_IS_NOWHERE
+	gd->env_addr = (ulong)&default_environment[0];
+#endif
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	arch_fixup_fdt(blob);
+
+	ft_cpu_setup(blob, bd);
+
+	return 0;
+}
+#endif

board/freescale/ls1012aqds/ls1012aqds_qixis.h

@@ -0,0 +1,35 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __LS1043AQDS_QIXIS_H__
+#define __LS1043AQDS_QIXIS_H__
+
+/* Definitions of QIXIS Registers for LS1043AQDS */
+
+/* BRDCFG4[4:7] select EC1 and EC2 as a pair */
+#define BRDCFG4_EMISEL_MASK		0xe0
+#define BRDCFG4_EMISEL_SHIFT		5
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_66			0x0
+#define QIXIS_SYSCLK_83			0x1
+#define QIXIS_SYSCLK_100		0x2
+#define QIXIS_SYSCLK_125		0x3
+#define QIXIS_SYSCLK_133		0x4
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_66			0x0
+#define QIXIS_DDRCLK_100		0x1
+#define QIXIS_DDRCLK_125		0x2
+#define QIXIS_DDRCLK_133		0x3
+
+/* BRDCFG2 - SD clock*/
+#define QIXIS_SDCLK1_100		0x0
+#define QIXIS_SDCLK1_125		0x1
+#define QIXIS_SDCLK1_165		0x2
+#define QIXIS_SDCLK1_100_SP		0x3
+
+#endif

board/freescale/ls1012ardb/Kconfig

@@ -0,0 +1,15 @@
+if TARGET_LS1012ARDB
+
+config SYS_BOARD
+	default "ls1012ardb"
+
+config SYS_VENDOR
+	default "freescale"
+
+config SYS_SOC
+	default "fsl-layerscape"
+
+config SYS_CONFIG_NAME
+	default "ls1012ardb"
+
+endif

board/freescale/ls1012ardb/MAINTAINERS

@@ -0,0 +1,6 @@
+LS1012ARDB BOARD
+M:	Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
+S:	Maintained
+F:	board/freescale/ls1012ardb/
+F:	include/configs/ls1012ardb.h
+F:	configs/ls1012ardb_qspi_defconfig

board/freescale/ls1012ardb/Makefile

@@ -0,0 +1,7 @@
+#
+# Copyright 2016 Freescale Semiconductor, Inc.
+#
+# SPDX-License-Identifier:      GPL-2.0+
+#
+
+obj-y += ls1012ardb.o

board/freescale/ls1012ardb/README

@@ -0,0 +1,54 @@
+Overview
+--------
+QorIQ LS1012A Reference Design System (LS1012ARDB) is a high-performance
+development platform, with a complete debugging environment.
+The LS1012ARDB board supports the QorIQ LS1012A processor and is
+optimized to support the high-bandwidth DDR3L memory and
+a full complement of high-speed SerDes ports.
+
+LS1012A SoC Overview
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
+SoC overview.
+
+LS1012ARDB board Overview
+-----------------------
+ - SERDES Connections, 4 lanes supporting:
+      - PCI Express - 3.0
+      - SGMII, SGMII 2.5
+      - SATA 3.0
+ - DDR Controller
+     - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
+ -QSPI: A dual 1:3 switch, NX3L4357GM,115 (U35) drives the QSPI chip-select
+ signals to
+    - QSPI NOR flash memory (2 virtual banks)
+    - the QSPI emulator.s
+ - USB 3.0
+    - one high-speed USB 2.0/3.0 port.
+ - Two enhanced secure digital host controllers:
+    - SDHC1 controller can be connected to onboard SDHC connector
+    - SDHC2 controller: Three dual 1:4 mux/demux devices,
+    74CBTLV3253DS (U30, U31, U33) drive the SDHC2 signals to eMMC,
+    SDIO WiFi, SPI, and Ardiuno shield
+ - 2 I2C controllers
+ - One SATA onboard connectors
+ - UART
+   - The LS1012A processor consists of two UART controllers,
+   out of which only UART1 is used on RDB.
+ - ARM JTAG support
+
+Booting Options
+---------------
+a) QSPI Flash Emu Boot
+b) QSPI Flash 1
+c) QSPI Flash 2
+
+QSPI flash map
+--------------
+Images		| Size	|QSPI Flash Address
+------------------------------------------
+RCW + PBI	| 1MB	| 0x4000_0000
+U-boot 		| 1MB	| 0x4010_0000
+U-boot Env 	| 1MB	| 0x4020_0000
+PPA FIT image	| 2MB	| 0x4050_0000
+Linux ITB	| ~53MB | 0x40A0_0000

board/freescale/ls1012ardb/ls1012ardb.c

@@ -0,0 +1,224 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/fsl_serdes.h>
+#include <asm/arch/soc.h>
+#include <hwconfig.h>
+#include <ahci.h>
+#include <mmc.h>
+#include <scsi.h>
+#include <fsl_csu.h>
+#include <fsl_esdhc.h>
+#include <environment.h>
+#include <fsl_mmdc.h>
+#include <netdev.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
+{
+	int timeout = 1000;
+
+	out_be32(ptr, value);
+
+	while (in_be32(ptr) & bits) {
+		udelay(100);
+		timeout--;
+	}
+	if (timeout <= 0)
+		puts("Error: wait for clear timeout.\n");
+}
+
+int checkboard(void)
+{
+	u8 in1;
+
+	puts("Board: LS1012ARDB ");
+
+	/* Initialize i2c early for Serial flash bank information */
+	i2c_set_bus_num(0);
+
+	if (i2c_read(I2C_MUX_IO1_ADDR, 1, 1, &in1, 1) < 0) {
+		printf("Error reading i2c boot information!\n");
+		return 0; /* Don't want to hang() on this error */
+	}
+
+	puts("Version");
+	if ((in1 & (~__SW_REV_MASK)) == __SW_REV_A)
+		puts(": RevA");
+	else if ((in1 & (~__SW_REV_MASK)) == __SW_REV_B)
+		puts(": RevB");
+	else
+		puts(": unknown");
+
+	printf(", boot from QSPI");
+	if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_EMU)
+		puts(": emu\n");
+	else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK1)
+		puts(": bank1\n");
+	else if ((in1 & (~__SW_BOOT_MASK)) == __SW_BOOT_BANK2)
+		puts(": bank2\n");
+	else
+		puts("unknown\n");
+
+	return 0;
+}
+
+void mmdc_init(void)
+{
+	struct mmdc_p_regs *mmdc =
+		(struct mmdc_p_regs *)CONFIG_SYS_FSL_DDR_ADDR;
+
+	out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
+
+	/* configure timing parms */
+	out_be32(&mmdc->mdotc,  CONFIG_SYS_MMDC_CORE_ODT_TIMING);
+	out_be32(&mmdc->mdcfg0, CONFIG_SYS_MMDC_CORE_TIMING_CFG_0);
+	out_be32(&mmdc->mdcfg1, CONFIG_SYS_MMDC_CORE_TIMING_CFG_1);
+	out_be32(&mmdc->mdcfg2, CONFIG_SYS_MMDC_CORE_TIMING_CFG_2);
+
+	/* other parms	*/
+	out_be32(&mmdc->mdmisc,    CONFIG_SYS_MMDC_CORE_MISC);
+	out_be32(&mmdc->mpmur0,    CONFIG_SYS_MMDC_PHY_MEASURE_UNIT);
+	out_be32(&mmdc->mdrwd,     CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY);
+	out_be32(&mmdc->mpodtctrl, CONFIG_SYS_MMDC_PHY_ODT_CTRL);
+
+	/* out of reset delays */
+	out_be32(&mmdc->mdor,  CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY);
+
+	/* physical parms */
+	out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_1);
+	out_be32(&mmdc->mdasp, CONFIG_SYS_MMDC_CORE_ADDR_PARTITION);
+
+       /* Enable MMDC */
+	out_be32(&mmdc->mdctl, CONFIG_SYS_MMDC_CORE_CONTROL_2);
+
+	/* dram init sequence: update MRs */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x8) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_2));
+	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+				CMD_BANK_ADDR_3));
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
+	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x19) |
+				CMD_ADDR_LSB_MR_ADDR(0x30) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_0));
+
+       /* dram init sequence: ZQCL */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+				CMD_ZQ_CALIBRATION | CMD_BANK_ADDR_0));
+	set_wait_for_bits_clear(&mmdc->mpzqhwctrl,
+				CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL,
+				FORCE_ZQ_AUTO_CALIBRATION);
+
+       /* Calibrations now: wr lvl */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x84) |
+				CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+				CMD_BANK_ADDR_1));
+	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | WL_EN | CMD_NORMAL));
+	set_wait_for_bits_clear(&mmdc->mpwlgcr, WR_LVL_HW_EN, WR_LVL_HW_EN);
+
+	mdelay(1);
+
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_1));
+	out_be32(&mmdc->mdscr, CONFIGURATION_REQ);
+
+	mdelay(1);
+
+       /* Calibrations now: Read DQS gating calibration */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+				CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
+	out_be32(&mmdc->mppdcmpr2, MPR_COMPARE_EN);
+	out_be32(&mmdc->mprddlctl, CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG);
+	set_wait_for_bits_clear(&mmdc->mpdgctrl0,
+				AUTO_RD_DQS_GATING_CALIBRATION_EN,
+				AUTO_RD_DQS_GATING_CALIBRATION_EN);
+
+	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+				CMD_BANK_ADDR_3));
+
+       /* Calibrations now: Read calibration */
+	out_be32(&mmdc->mdscr, (CMD_ADDR_MSB_MR_OP(0x4) | CONFIGURATION_REQ |
+				CMD_PRECHARGE_BANK_OPEN | CMD_BANK_ADDR_0));
+	out_be32(&mmdc->mdscr, (CMD_ADDR_LSB_MR_ADDR(0x4) | CONFIGURATION_REQ |
+				CMD_LOAD_MODE_REG | CMD_BANK_ADDR_3));
+	out_be32(&mmdc->mppdcmpr2,  MPR_COMPARE_EN);
+	set_wait_for_bits_clear(&mmdc->mprddlhwctl,
+				AUTO_RD_CALIBRATION_EN,
+				AUTO_RD_CALIBRATION_EN);
+
+	out_be32(&mmdc->mdscr, (CONFIGURATION_REQ | CMD_LOAD_MODE_REG |
+				CMD_BANK_ADDR_3));
+
+       /* PD, SR */
+	out_be32(&mmdc->mdpdc, CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL);
+	out_be32(&mmdc->mapsr, CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT);
+
+       /* refresh scheme */
+	set_wait_for_bits_clear(&mmdc->mdref,
+				CONFIG_SYS_MMDC_CORE_REFRESH_CTL,
+				START_REFRESH);
+
+       /* disable CON_REQ */
+	out_be32(&mmdc->mdscr, DISABLE_CFG_REQ);
+}
+
+int dram_init(void)
+{
+	mmdc_init();
+
+	gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return pci_eth_init(bis);
+}
+
+int board_early_init_f(void)
+{
+	fsl_lsch2_early_init_f();
+
+	return 0;
+}
+
+int board_init(void)
+{
+	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+	/*
+	 * Set CCI-400 control override register to enable barrier
+	 * transaction
+	 */
+	out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
+
+#ifdef CONFIG_ENV_IS_NOWHERE
+	gd->env_addr = (ulong)&default_environment[0];
+#endif
+
+#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
+	enable_layerscape_ns_access();
+#endif
+
+	return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+	arch_fixup_fdt(blob);
+
+	ft_cpu_setup(blob, bd);
+
+	return 0;
+}

board/freescale/ls1021aqds/ddr.h

@@ -31,21 +31,21 @@ static const struct board_specific_parameters udimm0[] = {
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
 	 */
 #ifdef CONFIG_SYS_FSL_DDR4
-	{2,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A,},
-	{2,  1900, 0, 4,     6, 0x08080A0C, 0x0D0E0F0A,},
-	{1,  1666, 0, 4,     8, 0x090A0B0B, 0x0C0D0E0C,},
-	{1,  1900, 0, 4,     9, 0x0A0B0C0B, 0x0D0E0F0D,},
-	{1,  2200, 0, 4,    10, 0x0B0C0D0C, 0x0E0F110E,},
+	{2,  1666, 0, 8,     7, 0x0808090B, 0x0C0D0E0A,},
+	{2,  1900, 0, 8,     6, 0x08080A0C, 0x0D0E0F0A,},
+	{1,  1666, 0, 8,     8, 0x090A0B0B, 0x0C0D0E0C,},
+	{1,  1900, 0, 8,     9, 0x0A0B0C0B, 0x0D0E0F0D,},
+	{1,  2200, 0, 8,    10, 0x0B0C0D0C, 0x0E0F110E,},
 #elif defined(CONFIG_SYS_FSL_DDR3)
-	{1,  833,  1, 6,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
-	{1,  1350, 1, 6,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
-	{1,  833,  2, 6,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
-	{1,  1350, 2, 6,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
-	{2,  833,  4, 6,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
-	{2,  1350, 4, 6,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
-	{2,  1350, 0, 6,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
-	{2,  1666, 4, 4,   0xa, 0x0B08090C, 0x0B0E0D0A,   0x1f,    2,  0},
-	{2,  1666, 0, 4,   0xa, 0x0B08090C, 0x0B0E0D0A,   0x1f,    2,  0},
+	{1,  833,  1, 12,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
+	{1,  1350, 1, 12,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
+	{1,  833,  2, 12,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
+	{1,  1350, 2, 12,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
+	{2,  833,  4, 12,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
+	{2,  1350, 4, 12,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
+	{2,  1350, 0, 12,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
+	{2,  1666, 4, 8,    0xa, 0x0B08090C, 0x0B0E0D0A,   0x1f,    2,  0},
+	{2,  1666, 0, 8,    0xa, 0x0B08090C, 0x0B0E0D0A,   0x1f,    2,  0},
 #else
 #error DDR type not defined
 #endif

board/freescale/ls1043aqds/README

@@ -8,41 +8,8 @@ debugging environment.
 
 LS1043A SoC Overview
 --------------------
-The LS1043A integrated multicore processor combines four ARM Cortex-A53
-processor cores with datapath acceleration optimized for L2/3 packet
-processing, single pass security offload and robust traffic management
-and quality of service.
-
-The LS1043A SoC includes the following function and features:
- - Four 64-bit ARM Cortex-A53 CPUs
- - 1 MB unified L2 Cache
- - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
-   support
- - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
-   the following functions:
-   - Packet parsing, classification, and distribution (FMan)
-   - Queue management for scheduling, packet sequencing, and congestion
-     management (QMan)
-   - Hardware buffer management for buffer allocation and de-allocation (BMan)
-   - Cryptography acceleration (SEC)
- - Ethernet interfaces by FMan
-   - Up to 1 x XFI supporting 10G interface
-   - Up to 1 x QSGMII
-   - Up to 4 x SGMII supporting 1000Mbps
-   - Up to 2 x SGMII supporting 2500Mbps
-   - Up to 2 x RGMII supporting 1000Mbps
- - High-speed peripheral interfaces
-   - Three PCIe 2.0 controllers, one supporting x4 operation
-   - One serial ATA (SATA 3.0) controllers
- - Additional peripheral interfaces
-   - Three high-speed USB 3.0 controllers with integrated PHY
-   - Enhanced secure digital host controller (eSDXC/eMMC)
-   - Quad Serial Peripheral Interface (QSPI) Controller
-   - Serial peripheral interface (SPI) controller
-   - Four I2C controllers
-   - Two DUARTs
-   - Integrated flash controller supporting NAND and NOR flash
- - QorIQ platform's trust architecture 2.1
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A
+SoC overview.
 
  LS1043AQDS board Overview
  -----------------------

board/freescale/ls1043aqds/ddr.h

@@ -34,21 +34,21 @@ static const struct board_specific_parameters udimm0[] = {
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
 	 */
 #ifdef CONFIG_SYS_FSL_DDR4
-	{2,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A,},
-	{2,  1900, 0, 4,     6, 0x08080A0C, 0x0D0E0F0A,},
-	{1,  1666, 0, 4,     6, 0x0708090B, 0x0C0D0E0A,},
-	{1,  1900, 0, 4,     9, 0x0A0B0C0B, 0x0D0E0F0D,},
-	{1,  2200, 0, 4,    10, 0x0B0C0D0C, 0x0E0F110E,},
+	{2,  1666, 0,  8,     7, 0x0808090B, 0x0C0D0E0A,},
+	{2,  1900, 0,  8,     6, 0x08080A0C, 0x0D0E0F0A,},
+	{1,  1666, 0,  8,     6, 0x0708090B, 0x0C0D0E0A,},
+	{1,  1900, 0,  8,     9, 0x0A0B0C0B, 0x0D0E0F0D,},
+	{1,  2200, 0,  8,    10, 0x0B0C0D0C, 0x0E0F110E,},
 #elif defined(CONFIG_SYS_FSL_DDR3)
-	{1,  833,  1, 6,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
-	{1,  1350, 1, 6,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
-	{1,  833,  2, 6,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
-	{1,  1350, 2, 6,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
-	{2,  833,  4, 6,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
-	{2,  1350, 4, 6,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
-	{2,  1350, 0, 6,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
-	{2,  1666, 4, 4,   0xa, 0x0B08090C, 0x0B0E0D0A,   0x1f,    2,  0},
-	{2,  1666, 0, 4,   0xa, 0x0B08090C, 0x0B0E0D0A,   0x1f,    2,  0},
+	{1,  833,  1, 12,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
+	{1,  1350, 1, 12,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
+	{1,  833,  2, 12,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
+	{1,  1350, 2, 12,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
+	{2,  833,  4, 12,     8, 0x06060607, 0x08080807,   0x1f,    2,  0},
+	{2,  1350, 4, 12,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
+	{2,  1350, 0, 12,     8, 0x0708080A, 0x0A0B0C09,   0x1f,    2,  0},
+	{2,  1666, 4,  8,   0xa, 0x0B08090C, 0x0B0E0D0A,   0x1f,    2,  0},
+	{2,  1666, 0,  8,   0xa, 0x0B08090C, 0x0B0E0D0A,   0x1f,    2,  0},
 #else
 #error DDR type not defined
 #endif

board/freescale/ls1043aqds/ls1043aqds.c

@@ -238,8 +238,8 @@ int board_early_init_f(void)
 	out_be32(&scfg->rcwpmuxcr0, 0x3333);
 	out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
 	usb_pwrfault =
-		(SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB3_SHIFT) |
-		(SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB2_SHIFT) |
+		(SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB3_SHIFT) |
+		(SCFG_USBPWRFAULT_DEDICATED << SCFG_USBPWRFAULT_USB2_SHIFT) |
 		(SCFG_USBPWRFAULT_SHARED << SCFG_USBPWRFAULT_USB1_SHIFT);
 	out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
 #endif

board/freescale/ls1043ardb/README

@@ -8,41 +8,8 @@ debugging environment. The LS1043A RDB is lead-free and RoHS-compliant.
 
 LS1043A SoC Overview
 --------------------
-The LS1043A integrated multicore processor combines four ARM Cortex-A53
-processor cores with datapath acceleration optimized for L2/3 packet
-processing, single pass security offload and robust traffic management
-and quality of service.
-
-The LS1043A SoC includes the following function and features:
- - Four 64-bit ARM Cortex-A53 CPUs
- - 1 MB unified L2 Cache
- - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
-   support
- - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
-   the following functions:
-   - Packet parsing, classification, and distribution (FMan)
-   - Queue management for scheduling, packet sequencing, and congestion
-     management (QMan)
-   - Hardware buffer management for buffer allocation and de-allocation (BMan)
-   - Cryptography acceleration (SEC)
- - Ethernet interfaces by FMan
-   - Up to 1 x XFI supporting 10G interface
-   - Up to 1 x QSGMII
-   - Up to 4 x SGMII supporting 1000Mbps
-   - Up to 2 x SGMII supporting 2500Mbps
-   - Up to 2 x RGMII supporting 1000Mbps
- - High-speed peripheral interfaces
-   - Three PCIe 2.0 controllers, one supporting x4 operation
-   - One serial ATA (SATA 3.0) controllers
- - Additional peripheral interfaces
-   - Three high-speed USB 3.0 controllers with integrated PHY
-   - Enhanced secure digital host controller (eSDXC/eMMC)
-   - Quad Serial Peripheral Interface (QSPI) Controller
-   - Serial peripheral interface (SPI) controller
-   - Four I2C controllers
-   - Two DUARTs
-   - Integrated flash controller supporting NAND and NOR flash
- - QorIQ platform's trust architecture 2.1
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A
+SoC overview.
 
  LS1043ARDB board Overview
  -----------------------

board/freescale/ls1043ardb/ddr.h

@@ -34,9 +34,9 @@ static const struct board_specific_parameters udimm0[] = {
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
 	 */
 #ifdef CONFIG_SYS_FSL_DDR4
-	{1,  1666, 0, 6,     7, 0x07090800, 0x00000000,},
-	{1,  1900, 0, 6,     7, 0x07090800, 0x00000000,},
-	{1,  2200, 0, 6,     7, 0x07090800, 0x00000000,},
+	{1,  1666, 0, 12,     7, 0x07090800, 0x00000000,},
+	{1,  1900, 0, 12,     7, 0x07090800, 0x00000000,},
+	{1,  2200, 0, 12,     7, 0x07090800, 0x00000000,},
 #endif
 	{}
 };

board/freescale/ls2080aqds/README

@@ -7,48 +7,9 @@ SW development platform for the Freescale LS2080A processor series, with
 a complete debugging environment.
 
 LS2080A SoC Overview
-------------------
-The LS2080A integrated multicore processor combines eight ARM Cortex-A57
-processor cores with high-performance data path acceleration logic and network
-and peripheral bus interfaces required for networking, telecom/datacom,
-wireless infrastructure, and mil/aerospace applications.
-
-The LS2080A SoC includes the following function and features:
-
- - Eight 64-bit ARM Cortex-A57 CPUs
- - 1 MB platform cache with ECC
- - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
- - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
-  the AIOP
- - Data path acceleration architecture (DPAA2) incorporating acceleration for
- the following functions:
-   - Packet parsing, classification, and distribution (WRIOP)
-   - Queue and Hardware buffer management for scheduling, packet sequencing, and
-     congestion management, buffer allocation and de-allocation (QBMan)
-   - Cryptography acceleration (SEC) at up to 10 Gbps
-   - RegEx pattern matching acceleration (PME) at up to 10 Gbps
-   - Decompression/compression acceleration (DCE) at up to 20 Gbps
-   - Accelerated I/O processing (AIOP) at up to 20 Gbps
-   - QDMA engine
- - 16 SerDes lanes at up to 10.3125 GHz
- - Ethernet interfaces
-   - Up to eight 10 Gbps Ethernet MACs
-   - Up to eight 1 / 2.5 Gbps Ethernet MACs
- - High-speed peripheral interfaces
-   - Four PCIe 3.0 controllers, one supporting SR-IOV
- - Additional peripheral interfaces
-   - Two serial ATA (SATA 3.0) controllers
-   - Two high-speed USB 3.0 controllers with integrated PHY
-   - Enhanced secure digital host controller (eSDXC/eMMC)
-   - Serial peripheral interface (SPI) controller
-   - Quad Serial Peripheral Interface (QSPI) Controller
-   - Four I2C controllers
-   - Two DUARTs
-   - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash
- - Support for hardware virtualization and partitioning enforcement
- - QorIQ platform's trust architecture 3.0
- - Service processor (SP) provides pre-boot initialization and secure-boot
-  capabilities
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
+SoC overview.
 
  LS2080AQDS board Overview
  -----------------------

board/freescale/ls2080aqds/ddr.h

@@ -28,10 +28,10 @@ static const struct board_specific_parameters udimm0[] = {
 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
 	 */
-	{2,  1350, 0, 4,     6, 0x0708090B, 0x0C0D0E09,},
-	{2,  1666, 0, 4,     7, 0x08090A0C, 0x0D0F100B,},
-	{2,  1900, 0, 4,     7, 0x09090B0D, 0x0E10120B,},
-	{2,  2300, 0, 4,     8, 0x090A0C0F, 0x1012130C,},
+	{2,  1350, 0, 8,     6, 0x0708090B, 0x0C0D0E09,},
+	{2,  1666, 0, 8,     7, 0x08090A0C, 0x0D0F100B,},
+	{2,  1900, 0, 8,     7, 0x09090B0D, 0x0E10120B,},
+	{2,  2300, 0, 8,     8, 0x090A0C0F, 0x1012130C,},
 	{}
 };
 
@@ -42,10 +42,10 @@ static const struct board_specific_parameters udimm2[] = {
 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
 	 */
-	{2,  1350, 0, 4,   0xd, 0x0C0A0A00, 0x00000009,},
-	{2,  1666, 0, 4,   0xd, 0x0C0A0A00, 0x00000009,},
-	{2,  1900, 0, 4,   0xe, 0x0D0C0B00, 0x0000000A,},
-	{2,  2200, 0, 4,   0xe, 0x0D0C0B00, 0x0000000A,},
+	{2,  1350, 0, 8,   0xd, 0x0C0A0A00, 0x00000009,},
+	{2,  1666, 0, 8,   0xd, 0x0C0A0A00, 0x00000009,},
+	{2,  1900, 0, 8,   0xe, 0x0D0C0B00, 0x0000000A,},
+	{2,  2200, 0, 8,   0xe, 0x0D0C0B00, 0x0000000A,},
 	{}
 };
 
@@ -55,10 +55,10 @@ static const struct board_specific_parameters rdimm0[] = {
 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
 	 */
-	{2,  1350, 0, 4,     6, 0x0708090B, 0x0C0D0E09,},
-	{2,  1666, 0, 4,     7, 0x08090A0C, 0x0D0F100B,},
-	{2,  1900, 0, 4,     7, 0x09090B0D, 0x0E10120B,},
-	{2,  2200, 0, 4,     8, 0x090A0C0F, 0x1012130C,},
+	{2,  1350, 0, 8,     6, 0x0708090B, 0x0C0D0E09,},
+	{2,  1666, 0, 8,     7, 0x08090A0C, 0x0D0F100B,},
+	{2,  1900, 0, 8,     7, 0x09090B0D, 0x0E10120B,},
+	{2,  2200, 0, 8,     8, 0x090A0C0F, 0x1012130C,},
 	{}
 };
 
@@ -69,10 +69,10 @@ static const struct board_specific_parameters rdimm2[] = {
 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
 	 */
-	{2,  1350, 0, 4,     6, 0x0708090B, 0x0C0D0E09,},
-	{2,  1666, 0, 4,     7, 0x0B0A090C, 0x0D0F100B,},
-	{2,  1900, 0, 4,     7, 0x09090B0D, 0x0E10120B,},
-	{2,  2200, 0, 4,     8, 0x090A0C0F, 0x1012130C,},
+	{2,  1350, 0, 8,     6, 0x0708090B, 0x0C0D0E09,},
+	{2,  1666, 0, 8,     7, 0x0B0A090C, 0x0D0F100B,},
+	{2,  1900, 0, 8,     7, 0x09090B0D, 0x0E10120B,},
+	{2,  2200, 0, 8,     8, 0x090A0C0F, 0x1012130C,},
 	{}
 };
 

board/freescale/ls2080aqds/ls2080aqds.c

@@ -282,7 +282,9 @@ void fdt_fixup_board_enet(void *fdt)
 #ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
+#ifdef CONFIG_FSL_MC_ENET
 	int err;
+#endif
 	u64 base[CONFIG_NR_DRAM_BANKS];
 	u64 size[CONFIG_NR_DRAM_BANKS];
 

board/freescale/ls2080ardb/README

@@ -5,48 +5,9 @@ evaluation, and development platform that supports the QorIQ LS2080A
 Layerscape Architecture processor.
 
 LS2080A SoC Overview
-------------------
-The LS2080A integrated multicore processor combines eight ARM Cortex-A57
-processor cores with high-performance data path acceleration logic and network
-and peripheral bus interfaces required for networking, telecom/datacom,
-wireless infrastructure, and mil/aerospace applications.
-
-The LS2080A SoC includes the following function and features:
-
- - Eight 64-bit ARM Cortex-A57 CPUs
- - 1 MB platform cache with ECC
- - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
- - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
-  the AIOP
- - Data path acceleration architecture (DPAA2) incorporating acceleration for
- the following functions:
-   - Packet parsing, classification, and distribution (WRIOP)
-   - Queue and Hardware buffer management for scheduling, packet sequencing, and
-     congestion management, buffer allocation and de-allocation (QBMan)
-   - Cryptography acceleration (SEC) at up to 10 Gbps
-   - RegEx pattern matching acceleration (PME) at up to 10 Gbps
-   - Decompression/compression acceleration (DCE) at up to 20 Gbps
-   - Accelerated I/O processing (AIOP) at up to 20 Gbps
-   - QDMA engine
- - 16 SerDes lanes at up to 10.3125 GHz
- - Ethernet interfaces
-   - Up to eight 10 Gbps Ethernet MACs
-   - Up to eight 1 / 2.5 Gbps Ethernet MACs
- - High-speed peripheral interfaces
-   - Four PCIe 3.0 controllers, one supporting SR-IOV
- - Additional peripheral interfaces
-   - Two serial ATA (SATA 3.0) controllers
-   - Two high-speed USB 3.0 controllers with integrated PHY
-   - Enhanced secure digital host controller (eSDXC/eMMC)
-   - Serial peripheral interface (SPI) controller
-   - Quad Serial Peripheral Interface (QSPI) Controller
-   - Four I2C controllers
-   - Two DUARTs
-   - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash
- - Support for hardware virtualization and partitioning enforcement
- - QorIQ platform's trust architecture 3.0
- - Service processor (SP) provides pre-boot initialization and secure-boot
-  capabilities
+--------------------
+Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A
+SoC overview.
 
  LS2080ARDB board Overview
  -----------------------

board/freescale/ls2080ardb/ddr.h

@@ -28,10 +28,10 @@ static const struct board_specific_parameters udimm0[] = {
 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
 	 */
-	{2,  1350, 0, 4,     6, 0x0708090B, 0x0C0D0E09,},
-	{2,  1666, 0, 5,     9, 0x090A0B0E, 0x0F11110C,},
-	{2,  1900, 0, 6,   0xA, 0x0B0C0E11, 0x1214140F,},
-	{2,  2300, 0, 6,   0xB, 0x0C0D0F12, 0x14161610,},
+	{2,  1350, 0, 8,     6, 0x0708090B, 0x0C0D0E09,},
+	{2,  1666, 0, 10,    9, 0x090A0B0E, 0x0F11110C,},
+	{2,  1900, 0, 12,  0xA, 0x0B0C0E11, 0x1214140F,},
+	{2,  2300, 0, 12,  0xB, 0x0C0D0F12, 0x14161610,},
 	{}
 };
 
@@ -42,10 +42,10 @@ static const struct board_specific_parameters udimm2[] = {
 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
 	 */
-	{2,  1350, 0, 4,   0xd, 0x0C0A0A00, 0x00000009,},
-	{2,  1666, 0, 4,   0xd, 0x0C0A0A00, 0x00000009,},
-	{2,  1900, 0, 4,   0xe, 0x0D0C0B00, 0x0000000A,},
-	{2,  2200, 0, 4,   0xe, 0x0D0C0B00, 0x0000000A,},
+	{2,  1350, 0, 8,   0xd, 0x0C0A0A00, 0x00000009,},
+	{2,  1666, 0, 8,   0xd, 0x0C0A0A00, 0x00000009,},
+	{2,  1900, 0, 8,   0xe, 0x0D0C0B00, 0x0000000A,},
+	{2,  2200, 0, 8,   0xe, 0x0D0C0B00, 0x0000000A,},
 	{}
 };
 
@@ -55,10 +55,10 @@ static const struct board_specific_parameters rdimm0[] = {
 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
 	 */
-	{2,  1350, 0, 4,     6, 0x0708090B, 0x0C0D0E09,},
-	{2,  1666, 0, 4,     7, 0x08090A0C, 0x0D0F100B,},
-	{2,  1900, 0, 4,     7, 0x09090B0D, 0x0E10120B,},
-	{2,  2200, 0, 4,     8, 0x090A0C0F, 0x1012130C,},
+	{2,  1350, 0, 8,     6, 0x0708090B, 0x0C0D0E09,},
+	{2,  1666, 0, 8,     7, 0x08090A0C, 0x0D0F100B,},
+	{2,  1900, 0, 8,     7, 0x09090B0D, 0x0E10120B,},
+	{2,  2200, 0, 8,     8, 0x090A0C0F, 0x1012130C,},
 	{}
 };
 
@@ -69,10 +69,10 @@ static const struct board_specific_parameters rdimm2[] = {
 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
 	 */
-	{2,  1350, 0, 4,     6, 0x0708090B, 0x0C0D0E09,},
-	{2,  1666, 0, 4,     7, 0x0B0A090C, 0x0D0F100B,},
-	{2,  1900, 0, 4,     7, 0x09090B0D, 0x0E10120B,},
-	{2,  2200, 0, 4,     8, 0x090A0C0F, 0x1012130C,},
+	{2,  1350, 0, 8,     6, 0x0708090B, 0x0C0D0E09,},
+	{2,  1666, 0, 8,     7, 0x0B0A090C, 0x0D0F100B,},
+	{2,  1900, 0, 8,     7, 0x09090B0D, 0x0E10120B,},
+	{2,  2200, 0, 8,     8, 0x090A0C0F, 0x1012130C,},
 	{}
 };
 

board/freescale/ls2080ardb/ls2080ardb.c

@@ -156,7 +156,9 @@ int board_init(void)
 {
 	char *env_hwconfig;
 	u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
+#ifdef CONFIG_FSL_MC_ENET
 	u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
+#endif
 	u32 val;
 
 	init_final_memctl_regs();
@@ -178,8 +180,10 @@ int board_init(void)
 
 	QIXIS_WRITE(rst_ctl, QIXIS_RST_CTL_RESET_EN);
 
+#ifdef CONFIG_FSL_MC_ENET
 	/* invert AQR405 IRQ pins polarity */
 	out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR405_IRQ_MASK);
+#endif
 
 	return 0;
 }
@@ -261,7 +265,9 @@ void fdt_fixup_board_enet(void *fdt)
 #ifdef CONFIG_OF_BOARD_SETUP
 int ft_board_setup(void *blob, bd_t *bd)
 {
+#ifdef CONFIG_FSL_MC_ENET
 	int err;
+#endif
 	u64 base[CONFIG_NR_DRAM_BANKS];
 	u64 size[CONFIG_NR_DRAM_BANKS];
 

board/freescale/t102xqds/ddr.c

@@ -35,18 +35,18 @@ static const struct board_specific_parameters udimm0[] = {
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
 	 */
 #if defined(CONFIG_SYS_FSL_DDR4)
-	{2,  1666,  0,  4,  7,  0x0808090B,  0x0C0D0E0A,},
-	{2,  1900,  0,  4,  6,  0x08080A0C,  0x0D0E0F0A,},
-	{1,  1666,  0,  4,  6,  0x0708090B,  0x0C0D0E09,},
-	{1,  1900,  0,  4,  6,  0x08080A0C,  0x0D0E0F0A,},
-	{1,  2200,  0,  4,  7,  0x08090A0D,  0x0F0F100C,},
+	{2,  1666,  0,  8,  7,  0x0808090B,  0x0C0D0E0A,},
+	{2,  1900,  0,  8,  6,  0x08080A0C,  0x0D0E0F0A,},
+	{1,  1666,  0,  8,  6,  0x0708090B,  0x0C0D0E09,},
+	{1,  1900,  0,  8,  6,  0x08080A0C,  0x0D0E0F0A,},
+	{1,  2200,  0,  8,  7,  0x08090A0D,  0x0F0F100C,},
 #elif defined(CONFIG_SYS_FSL_DDR3)
-	{2,  833,   0,  4,  6,  0x06060607,  0x08080807,},
-	{2,  1350,  0,  4,  7,  0x0708080A,  0x0A0B0C09,},
-	{2,  1666,  0,  4,  7,  0x0808090B,  0x0C0D0E0A,},
-	{1,  833,   0,  4,  6,  0x06060607,  0x08080807,},
-	{1,  1350,  0,  4,  7,  0x0708080A,  0x0A0B0C09,},
-	{1,  1666,  0,  4,  7,  0x0808090B,  0x0C0D0E0A,},
+	{2,  833,   0,  8,  6,  0x06060607,  0x08080807,},
+	{2,  1350,  0,  8,  7,  0x0708080A,  0x0A0B0C09,},
+	{2,  1666,  0,  8,  7,  0x0808090B,  0x0C0D0E0A,},
+	{1,  833,   0,  8,  6,  0x06060607,  0x08080807,},
+	{1,  1350,  0,  8,  7,  0x0708080A,  0x0A0B0C09,},
+	{1,  1666,  0,  8,  7,  0x0808090B,  0x0C0D0E0A,},
 #else
 #error DDR type not defined
 #endif

board/freescale/t102xrdb/ddr.c

@@ -34,12 +34,12 @@ static const struct board_specific_parameters udimm0[] = {
 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl |
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
 	 */
-	{2,  833,   0,  4,  6,  0x06060607,  0x08080807,},
-	{2,  1350,  0,  4,  7,  0x0708080A,  0x0A0B0C09,},
-	{2,  1666,  0,  4,  7,  0x0808090B,  0x0C0D0E0A,},
-	{1,  833,   0,  4,  6,  0x06060607,  0x08080807,},
-	{1,  1350,  0,  4,  7,  0x0708080A,  0x0A0B0C09,},
-	{1,  1666,  0,  4,  7,  0x0808090B,  0x0C0D0E0A,},
+	{2,  833,   0,  8,  6,  0x06060607,  0x08080807,},
+	{2,  1350,  0,  8,  7,  0x0708080A,  0x0A0B0C09,},
+	{2,  1666,  0,  8,  7,  0x0808090B,  0x0C0D0E0A,},
+	{1,  833,   0,  8,  6,  0x06060607,  0x08080807,},
+	{1,  1350,  0,  8,  7,  0x0708080A,  0x0A0B0C09,},
+	{1,  1666,  0,  8,  7,  0x0808090B,  0x0C0D0E0A,},
 	{}
 };
 

board/freescale/t1040qds/ddr.h

@@ -29,18 +29,18 @@ static const struct board_specific_parameters udimm0[] = {
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
 	 */
 #ifdef CONFIG_SYS_FSL_DDR4
-	{2,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A,},
-	{2,  1900, 0, 4,     6, 0x08080A0C, 0x0D0E0F0A,},
-	{1,  1666, 0, 4,     6, 0x0708090B, 0x0C0D0E09,},
-	{1,  1900, 0, 4,     6, 0x08080A0C, 0x0D0E0F0A,},
-	{1,  2200, 0, 4,     7, 0x08090A0D, 0x0F0F100C,},
+	{2,  1666, 0, 8,     7, 0x0808090B, 0x0C0D0E0A,},
+	{2,  1900, 0, 8,     6, 0x08080A0C, 0x0D0E0F0A,},
+	{1,  1666, 0, 8,     6, 0x0708090B, 0x0C0D0E09,},
+	{1,  1900, 0, 8,     6, 0x08080A0C, 0x0D0E0F0A,},
+	{1,  2200, 0, 8,     7, 0x08090A0D, 0x0F0F100C,},
 #elif defined(CONFIG_SYS_FSL_DDR3)
-	{2,  833,  0, 4,     6, 0x06060607, 0x08080807,},
-	{2,  1350, 0, 4,     7, 0x0708080A, 0x0A0B0C09,},
-	{2,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A,},
-	{1,  833,  0, 4,     6, 0x06060607, 0x08080807,},
-	{1,  1350, 0, 4,     7, 0x0708080A, 0x0A0B0C09,},
-	{1,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A,},
+	{2,  833,  0, 8,     6, 0x06060607, 0x08080807,},
+	{2,  1350, 0, 8,     7, 0x0708080A, 0x0A0B0C09,},
+	{2,  1666, 0, 8,     7, 0x0808090B, 0x0C0D0E0A,},
+	{1,  833,  0, 8,     6, 0x06060607, 0x08080807,},
+	{1,  1350, 0, 8,     7, 0x0708080A, 0x0A0B0C09,},
+	{1,  1666, 0, 8,     7, 0x0808090B, 0x0C0D0E0A,},
 #else
 #error DDR type not defined
 #endif

board/freescale/t104xrdb/ddr.h

@@ -29,20 +29,20 @@ static const struct board_specific_parameters udimm0[] = {
 	 * ranks| mhz| GB  |adjst| start |   ctl2
 	 */
 #ifdef CONFIG_SYS_FSL_DDR4
-	{2,  1600, 4, 4,     6, 0x07090A0c, 0x0e0f100a},
+	{2,  1600, 4, 8,     6, 0x07090A0c, 0x0e0f100a},
 #elif defined(CONFIG_SYS_FSL_DDR3)
-	{2,  833,  4, 4,     6, 0x06060607, 0x08080807},
-	{2,  833,  0, 4,     6, 0x06060607, 0x08080807},
-	{2,  1350, 4, 4,     7, 0x0708080A, 0x0A0B0C09},
-	{2,  1350, 0, 4,     7, 0x0708080A, 0x0A0B0C09},
-	{2,  1666, 4, 4,     7, 0x0808090B, 0x0C0D0E0A},
-	{2,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A},
-	{1,  833,  4, 4,     6, 0x06060607, 0x08080807},
-	{1,  833,  0, 4,     6, 0x06060607, 0x08080807},
-	{1,  1350, 4, 4,     7, 0x0708080A, 0x0A0B0C09},
-	{1,  1350, 0, 4,     7, 0x0708080A, 0x0A0B0C09},
-	{1,  1666, 4, 4,     7, 0x0808090B, 0x0C0D0E0A},
-	{1,  1666, 0, 4,     7, 0x0808090B, 0x0C0D0E0A},
+	{2,  833,  4, 8,     6, 0x06060607, 0x08080807},
+	{2,  833,  0, 8,     6, 0x06060607, 0x08080807},
+	{2,  1350, 4, 8,     7, 0x0708080A, 0x0A0B0C09},
+	{2,  1350, 0, 8,     7, 0x0708080A, 0x0A0B0C09},
+	{2,  1666, 4, 8,     7, 0x0808090B, 0x0C0D0E0A},
+	{2,  1666, 0, 8,     7, 0x0808090B, 0x0C0D0E0A},
+	{1,  833,  4, 8,     6, 0x06060607, 0x08080807},
+	{1,  833,  0, 8,     6, 0x06060607, 0x08080807},
+	{1,  1350, 4, 8,     7, 0x0708080A, 0x0A0B0C09},
+	{1,  1350, 0, 8,     7, 0x0708080A, 0x0A0B0C09},
+	{1,  1666, 4, 8,     7, 0x0808090B, 0x0C0D0E0A},
+	{1,  1666, 0, 8,     7, 0x0808090B, 0x0C0D0E0A},
 #else
 #error DDR type not defined
 #endif

board/freescale/t208xqds/ddr.h

@@ -28,17 +28,17 @@ static const struct board_specific_parameters udimm0[] = {
 	 *   num|  hi| rank|  clk| wrlvl | wrlvl | wrlvl |
 	 * ranks| mhz| GB  |adjst| start | ctl2  | ctl3  |
 	 */
-	{2,  1200,  0,  5,  7,  0x0708090a,  0x0b0c0d09},
-	{2,  1400,  0,  5,  7,  0x08090a0c,  0x0d0e0f0a},
-	{2,  1700,  0,  5,  8,  0x090a0b0c,  0x0e10110c},
-	{2,  1900,  0,  5,  8,  0x090b0c0f,  0x1012130d},
-	{2,  2140,  0,  5,  8,  0x090b0c0f,  0x1012130d},
-	{1,  1200,  0,  5,  7,  0x0808090a,  0x0b0c0c0a},
-	{1,  1500,  0,  5,  6,  0x07070809,  0x0a0b0b09},
-	{1,  1600,  0,  5,  8,  0x090b0b0d,  0x0d0e0f0b},
-	{1,  1700,  0,  4,  8,  0x080a0a0c,  0x0c0d0e0a},
-	{1,  1900,  0,  5,  8,  0x090a0c0d,  0x0e0f110c},
-	{1,  2140,  0,  4,  8,  0x090a0b0d,  0x0e0f110b},
+	{2,  1200,  0, 10,  7,  0x0708090a,  0x0b0c0d09},
+	{2,  1400,  0, 10,  7,  0x08090a0c,  0x0d0e0f0a},
+	{2,  1700,  0, 10,  8,  0x090a0b0c,  0x0e10110c},
+	{2,  1900,  0, 10,  8,  0x090b0c0f,  0x1012130d},
+	{2,  2140,  0, 10,  8,  0x090b0c0f,  0x1012130d},
+	{1,  1200,  0, 10,  7,  0x0808090a,  0x0b0c0c0a},
+	{1,  1500,  0, 10,  6,  0x07070809,  0x0a0b0b09},
+	{1,  1600,  0, 10,  8,  0x090b0b0d,  0x0d0e0f0b},
+	{1,  1700,  0,  8,  8,  0x080a0a0c,  0x0c0d0e0a},
+	{1,  1900,  0, 10,  8,  0x090a0c0d,  0x0e0f110c},
+	{1,  2140,  0,  8,  8,  0x090a0b0d,  0x0e0f110b},
 	{}
 };
 
@@ -49,15 +49,15 @@ static const struct board_specific_parameters rdimm0[] = {
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
 	 */
 	/* TODO: need tuning these parameters if RDIMM is used */
-	{4,  1350, 0, 5,     9, 0x08070605, 0x06070806},
-	{4,  1666, 0, 5,    11, 0x0a080706, 0x07090906},
-	{4,  2140, 0, 5,    12, 0x0b090807, 0x080a0b07},
-	{2,  1350, 0, 5,     9, 0x08070605, 0x06070806},
-	{2,  1666, 0, 5,    11, 0x0a090806, 0x08090a06},
-	{2,  2140, 0, 5,    12, 0x0b090807, 0x080a0b07},
-	{1,  1350, 0, 5,     9, 0x08070605, 0x06070806},
-	{1,  1666, 0, 5,    11, 0x0a090806, 0x08090a06},
-	{1,  2140, 0, 4,    12, 0x0b090807, 0x080a0b07},
+	{4,  1350, 0, 10,     9, 0x08070605, 0x06070806},
+	{4,  1666, 0, 10,    11, 0x0a080706, 0x07090906},
+	{4,  2140, 0, 10,    12, 0x0b090807, 0x080a0b07},
+	{2,  1350, 0, 10,     9, 0x08070605, 0x06070806},
+	{2,  1666, 0, 10,    11, 0x0a090806, 0x08090a06},
+	{2,  2140, 0, 10,    12, 0x0b090807, 0x080a0b07},
+	{1,  1350, 0, 10,     9, 0x08070605, 0x06070806},
+	{1,  1666, 0, 10,    11, 0x0a090806, 0x08090a06},
+	{1,  2140, 0,  8,    12, 0x0b090807, 0x080a0b07},
 	{}
 };
 

board/freescale/t208xrdb/ddr.h

@@ -28,16 +28,16 @@ static const struct board_specific_parameters udimm0[] = {
 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl |
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |
 	 */
-	{2,  1200, 2, 5,     7, 0x0808090a, 0x0b0c0c0a},
-	{2,  1500, 2, 5,     6, 0x07070809, 0x0a0b0b09},
-	{2,  1600, 2, 5,     8, 0x0808070b, 0x0c0d0e0a},
-	{2,  1700, 2, 4,     7, 0x080a0a0c, 0x0c0d0e0a},
-	{2,  1900, 0, 5,     7, 0x0808080c, 0x0b0c0c09},
-	{1,  1200, 2, 5,     7, 0x0808090a, 0x0b0c0c0a},
-	{1,  1500, 2, 5,     6, 0x07070809, 0x0a0b0b09},
-	{1,  1600, 2, 5,     8, 0x0808070b, 0x0c0d0e0a},
-	{1,  1700, 2, 4,     7, 0x080a0a0c, 0x0c0d0e0a},
-	{1,  1900, 0, 5,     7, 0x0808080c, 0x0b0c0c09},
+	{2,  1200, 2, 10,     7, 0x0808090a, 0x0b0c0c0a},
+	{2,  1500, 2, 10,     6, 0x07070809, 0x0a0b0b09},
+	{2,  1600, 2, 10,     8, 0x0808070b, 0x0c0d0e0a},
+	{2,  1700, 2,  8,     7, 0x080a0a0c, 0x0c0d0e0a},
+	{2,  1900, 0, 10,     7, 0x0808080c, 0x0b0c0c09},
+	{1,  1200, 2, 10,     7, 0x0808090a, 0x0b0c0c0a},
+	{1,  1500, 2, 10,     6, 0x07070809, 0x0a0b0b09},
+	{1,  1600, 2, 10,     8, 0x0808070b, 0x0c0d0e0a},
+	{1,  1700, 2,  8,     7, 0x080a0a0c, 0x0c0d0e0a},
+	{1,  1900, 0, 10,     7, 0x0808080c, 0x0b0c0c09},
 	{}
 };
 

board/freescale/t4qds/ddr.h

@@ -31,16 +31,16 @@ static const struct board_specific_parameters udimm0[] = {
 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
 	 */
-	{2,  1350, 4, 4,     8, 0x0809090b, 0x0c0c0d0a,   0xff,    2,  0},
-	{2,  1350, 0, 5,     7, 0x0709090b, 0x0c0c0d09,   0xff,    2,  0},
-	{2,  1666, 4, 4,     8, 0x080a0a0d, 0x0d10100b,   0xff,    2,  0},
-	{2,  1666, 0, 5,     7, 0x080a0a0c, 0x0d0d0e0a,   0xff,    2,  0},
-	{2,  1900, 0, 4,     8, 0x090a0b0e, 0x0f11120c,   0xff,    2,  0},
-	{2,  2140, 0, 4,     8, 0x090a0b0e, 0x0f11120c,   0xff,    2,  0},
-	{1,  1350, 0, 5,     8, 0x0809090b, 0x0c0c0d0a,   0xff,    2,  0},
-	{1,  1700, 0, 5,     8, 0x080a0a0c, 0x0c0d0e0a,   0xff,    2,  0},
-	{1,  1900, 0, 4,     8, 0x080a0a0c, 0x0e0e0f0a,   0xff,    2,  0},
-	{1,  2140, 0, 4,     8, 0x090a0b0c, 0x0e0f100b,   0xff,    2,  0},
+	{2,  1350, 4,  8,     8, 0x0809090b, 0x0c0c0d0a,   0xff,    2,  0},
+	{2,  1350, 0, 10,     7, 0x0709090b, 0x0c0c0d09,   0xff,    2,  0},
+	{2,  1666, 4,  8,     8, 0x080a0a0d, 0x0d10100b,   0xff,    2,  0},
+	{2,  1666, 0, 10,     7, 0x080a0a0c, 0x0d0d0e0a,   0xff,    2,  0},
+	{2,  1900, 0,  8,     8, 0x090a0b0e, 0x0f11120c,   0xff,    2,  0},
+	{2,  2140, 0,  8,     8, 0x090a0b0e, 0x0f11120c,   0xff,    2,  0},
+	{1,  1350, 0, 10,     8, 0x0809090b, 0x0c0c0d0a,   0xff,    2,  0},
+	{1,  1700, 0, 10,     8, 0x080a0a0c, 0x0c0d0e0a,   0xff,    2,  0},
+	{1,  1900, 0,  8,     8, 0x080a0a0c, 0x0e0e0f0a,   0xff,    2,  0},
+	{1,  2140, 0,  8,     8, 0x090a0b0c, 0x0e0f100b,   0xff,    2,  0},
 	{}
 };
 
@@ -50,15 +50,15 @@ static const struct board_specific_parameters rdimm0[] = {
 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3  |      |delay |
 	 */
-	{4,  1350, 0, 5,     9, 0x08070605, 0x06070806,   0xff,    2,  0},
-	{4,  1666, 0, 5,    11, 0x0a080706, 0x07090906,   0xff,    2,  0},
-	{4,  2140, 0, 5,    12, 0x0b090807, 0x080a0b07,   0xff,    2,  0},
-	{2,  1350, 0, 5,     9, 0x08070605, 0x06070806,   0xff,    2,  0},
-	{2,  1666, 0, 5,    11, 0x0a090806, 0x08090a06,   0xff,    2,  0},
-	{2,  2140, 0, 5,    12, 0x0b090807, 0x080a0b07,   0xff,    2,  0},
-	{1,  1350, 0, 5,     9, 0x08070605, 0x06070806,   0xff,    2,  0},
-	{1,  1666, 0, 5,    11, 0x0a090806, 0x08090a06,   0xff,    2,  0},
-	{1,  2140, 0, 4,    12, 0x0b090807, 0x080a0b07,   0xff,    2,  0},
+	{4,  1350, 0, 10,     9, 0x08070605, 0x06070806,   0xff,    2,  0},
+	{4,  1666, 0, 10,    11, 0x0a080706, 0x07090906,   0xff,    2,  0},
+	{4,  2140, 0, 10,    12, 0x0b090807, 0x080a0b07,   0xff,    2,  0},
+	{2,  1350, 0, 10,     9, 0x08070605, 0x06070806,   0xff,    2,  0},
+	{2,  1666, 0, 10,    11, 0x0a090806, 0x08090a06,   0xff,    2,  0},
+	{2,  2140, 0, 10,    12, 0x0b090807, 0x080a0b07,   0xff,    2,  0},
+	{1,  1350, 0, 10,     9, 0x08070605, 0x06070806,   0xff,    2,  0},
+	{1,  1666, 0, 10,    11, 0x0a090806, 0x08090a06,   0xff,    2,  0},
+	{1,  2140, 0,  8,    12, 0x0b090807, 0x080a0b07,   0xff,    2,  0},
 	{}
 };
 

board/freescale/t4rdb/ddr.h

@@ -27,16 +27,16 @@ static const struct board_specific_parameters udimm0[] = {
 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
 	 */
-	{2,  1350, 4, 4,     8, 0x0809090b, 0x0c0c0d0a},
-	{2,  1350, 0, 5,     7, 0x0709090b, 0x0c0c0d09},
-	{2,  1666, 4, 4,     8, 0x080a0a0d, 0x0d10100b},
-	{2,  1666, 0, 5,     7, 0x080a0a0c, 0x0d0d0e0a},
-	{2,  1900, 0, 4,     8, 0x090a0b0e, 0x0f11120c},
-	{2,  2140, 0, 4,     8, 0x090a0b0e, 0x0f11120c},
-	{1,  1350, 0, 5,     8, 0x0809090b, 0x0c0c0d0a},
-	{1,  1700, 0, 5,     8, 0x080a0a0c, 0x0c0d0e0a},
-	{1,  1900, 0, 4,     8, 0x080a0a0c, 0x0e0e0f0a},
-	{1,  2140, 0, 4,     8, 0x090a0b0c, 0x0e0f100b},
+	{2,  1350, 4,  8,     8, 0x0809090b, 0x0c0c0d0a},
+	{2,  1350, 0, 10,     7, 0x0709090b, 0x0c0c0d09},
+	{2,  1666, 4,  8,     8, 0x080a0a0d, 0x0d10100b},
+	{2,  1666, 0, 10,     7, 0x080a0a0c, 0x0d0d0e0a},
+	{2,  1900, 0,  8,     8, 0x090a0b0e, 0x0f11120c},
+	{2,  2140, 0,  8,     8, 0x090a0b0e, 0x0f11120c},
+	{1,  1350, 0, 10,     8, 0x0809090b, 0x0c0c0d0a},
+	{1,  1700, 0, 10,     8, 0x080a0a0c, 0x0c0d0e0a},
+	{1,  1900, 0,  8,     8, 0x080a0a0c, 0x0e0e0f0a},
+	{1,  2140, 0,  8,     8, 0x090a0b0c, 0x0e0f100b},
 	{}
 };
 
@@ -46,15 +46,15 @@ static const struct board_specific_parameters rdimm0[] = {
 	 *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
 	 * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
 	 */
-	{4,  1350, 0, 5,     9, 0x08070605, 0x06070806},
-	{4,  1666, 0, 5,    11, 0x0a080706, 0x07090906},
-	{4,  2140, 0, 5,    12, 0x0b090807, 0x080a0b07},
-	{2,  1350, 0, 5,     9, 0x08070605, 0x06070806},
-	{2,  1666, 0, 5,    11, 0x0a090806, 0x08090a06},
-	{2,  2140, 0, 5,    12, 0x0b090807, 0x080a0b07},
-	{1,  1350, 0, 5,     9, 0x08070605, 0x06070806},
-	{1,  1666, 0, 5,    11, 0x0a090806, 0x08090a06},
-	{1,  2140, 0, 4,    12, 0x0b090807, 0x080a0b07},
+	{4,  1350, 0, 10,     9, 0x08070605, 0x06070806},
+	{4,  1666, 0, 10,    11, 0x0a080706, 0x07090906},
+	{4,  2140, 0, 10,    12, 0x0b090807, 0x080a0b07},
+	{2,  1350, 0, 10,     9, 0x08070605, 0x06070806},
+	{2,  1666, 0, 10,    11, 0x0a090806, 0x08090a06},
+	{2,  2140, 0, 10,    12, 0x0b090807, 0x080a0b07},
+	{1,  1350, 0, 10,     9, 0x08070605, 0x06070806},
+	{1,  1666, 0, 10,    11, 0x0a090806, 0x08090a06},
+	{1,  2140, 0,  8,    12, 0x0b090807, 0x080a0b07},
 	{}
 };
 

configs/ls1012afrdm_qspi_defconfig

@@ -0,0 +1,29 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1012AFRDM=y
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-frdm"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_NETDEVICES=y
+CONFIG_SYS_NS16550=y

configs/ls1012aqds_qspi_defconfig

@@ -0,0 +1,32 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1012AQDS=y
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-qds"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_DSPI=y

configs/ls1012ardb_qspi_defconfig

@@ -0,0 +1,32 @@
+CONFIG_ARM=y
+CONFIG_TARGET_LS1012ARDB=y
+# CONFIG_SYS_MALLOC_F is not set
+CONFIG_SPI_FLASH=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1012a-rdb"
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_GREPENV=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_FAT=y
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_DM=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_SYS_NS16550=y
+CONFIG_FSL_DSPI=y

drivers/ddr/fsl/ctrl_regs.c

@@ -709,7 +709,7 @@ static void set_timing_cfg_2(const unsigned int ctrl_num,
 		| ((add_lat_mclk & 0xf) << 28)
 		| ((cpo & 0x1f) << 23)
 		| ((wr_lat & 0xf) << 19)
-		| ((wr_lat & 0x10) << 14)
+		| ((wr_lat & 0x10) << 18)
 		| ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
 		| ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
 		| ((cke_pls & 0x7) << 6)
@@ -1835,10 +1835,17 @@ static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
 	/* Per FSL Application Note: AN2805 */
 	ss_en = 1;
 #endif
-	clk_adjust = popts->clk_adjust;
+	if (fsl_ddr_get_version(0) >= 0x40701) {
+		/* clk_adjust in 5-bits on T-series and LS-series */
+		clk_adjust = (popts->clk_adjust & 0x1F) << 22;
+	} else {
+		/* clk_adjust in 4-bits on earlier MPC85xx and P-series */
+		clk_adjust = (popts->clk_adjust & 0xF) << 23;
+	}
+
 	ddr->ddr_sdram_clk_cntl = (0
 				   | ((ss_en & 0x1) << 31)
-				   | ((clk_adjust & 0xF) << 23)
+				   | clk_adjust
 				   );
 	debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
 }

drivers/ddr/fsl/fsl_ddr_gen4.c

@@ -206,12 +206,14 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009803
 	/* part 1 of 2 */
-	if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) { /* for RDIMM */
-		ddr_out32(&ddr->ddr_sdram_rcw_2,
-			  regs->ddr_sdram_rcw_2 & ~0x0f000000);
+	if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
+		if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) { /* for RDIMM */
+			ddr_out32(&ddr->ddr_sdram_rcw_2,
+				  regs->ddr_sdram_rcw_2 & ~0x0f000000);
+		}
+		ddr_out32(&ddr->err_disable, regs->err_disable |
+			  DDR_ERR_DISABLE_APED);
 	}
-
-	ddr_out32(&ddr->err_disable, regs->err_disable | DDR_ERR_DISABLE_APED);
 #else
 	ddr_out32(&ddr->err_disable, regs->err_disable);
 #endif
@@ -395,22 +397,24 @@ step2:
 #endif /* CONFIG_SYS_FSL_ERRATUM_A008511 */
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009803
-		/* if it's RDIMM */
-		if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) {
-			for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
-				if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
-					continue;
-				set_wait_for_bits_clear(&ddr->sdram_md_cntl,
-							MD_CNTL_MD_EN |
-							MD_CNTL_CS_SEL(i) |
-							0x070000ed,
-							MD_CNTL_MD_EN);
-				udelay(1);
+		if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
+			/* if it's RDIMM */
+			if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) {
+				for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+					if (!(regs->cs[i].config & SDRAM_CS_CONFIG_EN))
+						continue;
+					set_wait_for_bits_clear(&ddr->sdram_md_cntl,
+								MD_CNTL_MD_EN |
+								MD_CNTL_CS_SEL(i) |
+								0x070000ed,
+								MD_CNTL_MD_EN);
+					udelay(1);
+				}
 			}
-		}
 
-		ddr_out32(&ddr->err_disable,
-			  regs->err_disable & ~DDR_ERR_DISABLE_APED);
+			ddr_out32(&ddr->err_disable,
+				  regs->err_disable & ~DDR_ERR_DISABLE_APED);
+		}
 #endif
 	}
 #endif

drivers/ddr/fsl/options.c

@@ -886,7 +886,8 @@ unsigned int populate_memctl_options(const common_timing_params_t *common_dimm,
 	} else
 		popts->ecc_mode = 1;
 #endif
-	popts->ecc_init_using_memctl = 1; /* 0 = use DMA, 1 = use memctl */
+	/* 1 = use memory controler to init data */
+	popts->ecc_init_using_memctl = popts->ecc_mode ? 1 : 0;
 
 	/*
 	 * Choose DQS config

drivers/mmc/fsl_esdhc.c

@@ -308,14 +308,10 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
 static void check_and_invalidate_dcache_range
 	(struct mmc_cmd *cmd,
 	 struct mmc_data *data) {
-#ifdef CONFIG_FSL_LAYERSCAPE
 	unsigned start = 0;
-#else
-	unsigned start = (unsigned)data->dest ;
-#endif
+	unsigned end = 0;
 	unsigned size = roundup(ARCH_DMA_MINALIGN,
 				data->blocks*data->blocksize);
-	unsigned end = start+size ;
 #ifdef CONFIG_FSL_LAYERSCAPE
 	dma_addr_t addr;
 
@@ -324,7 +320,10 @@ static void check_and_invalidate_dcache_range
 		printf("Error found for upper 32 bits\n");
 	else
 		start = lower_32_bits(addr);
+#else
+	start = (unsigned)data->dest;
 #endif
+	end = start + size;
 	invalidate_dcache_range(start, end);
 }
 

drivers/mtd/spi/sf_params.c

@@ -67,6 +67,7 @@ const struct spi_flash_params spi_flash_params_table[] = {
 	{"S25FL128S_64K",  0x012018, 0x4d01,    64 * 1024,   256, RD_FULL,		     WR_QPP},
 	{"S25FL256S_256K", 0x010219, 0x4d00,   256 * 1024,   128, RD_FULL,		     WR_QPP},
 	{"S25FL256S_64K",  0x010219, 0x4d01,	64 * 1024,   512, RD_FULL,		     WR_QPP},
+	{"S25FS512S",      0x010220, 0x4D00,   128 * 1024,   512, RD_FULL,                   WR_QPP},
 	{"S25FL512S_256K", 0x010220, 0x4d00,   256 * 1024,   256, RD_FULL,		     WR_QPP},
 	{"S25FL512S_64K",  0x010220, 0x4d01,    64 * 1024,  1024, RD_FULL,		     WR_QPP},
 	{"S25FL512S_512K", 0x010220, 0x4f00,   256 * 1024,   256, RD_FULL,		     WR_QPP},

drivers/mtd/spi/spi_flash.c

@@ -1072,7 +1072,8 @@ int spi_flash_scan(struct spi_flash *flash)
 	 * sector that is not overlaid by the parameter sectors.
 	 * The uniform sector erase command has no effect on parameter sectors.
 	 */
-	if (jedec == 0x0219 && (ext_jedec & 0xff00) == 0x4d00) {
+	if ((jedec == 0x0219 || (jedec == 0x0220)) &&
+	    (ext_jedec & 0xff00) == 0x4d00) {
 		int ret;
 		u8 id[6];
 
@@ -1146,7 +1147,7 @@ int spi_flash_scan(struct spi_flash *flash)
 	 * have 256b pages.
 	 */
 	if (ext_jedec == 0x4d00) {
-		if ((jedec == 0x0215) || (jedec == 0x216))
+		if ((jedec == 0x0215) || (jedec == 0x216) || (jedec == 0x220))
 			flash->page_size = 256;
 		else
 			flash->page_size = 512;

drivers/pci/pcie_layerscape.c

@@ -569,7 +569,7 @@ static void fdt_fixup_pcie(void *blob)
 	unsigned char header_type;
 	int index;
 	u32 streamid;
-	pci_dev_t dev;
+	pci_dev_t dev, bdf;
 	int bus;
 	unsigned short id;
 	struct pci_controller *hose;
@@ -611,12 +611,15 @@ static void fdt_fixup_pcie(void *blob)
 					continue;
 				}
 
+				/* the DT fixup must be relative to the hose first_busno */
+				bdf = dev - PCI_BDF(hose->first_busno, 0, 0);
+
 				/* map PCI b.d.f to streamID in LUT */
-				ls_pcie_lut_set_mapping(pcie, index, dev >> 8,
+				ls_pcie_lut_set_mapping(pcie, index, bdf >> 8,
 							streamid);
 
 				/* update msi-map in device tree */
-				fdt_pcie_set_msi_map_entry(blob, pcie, dev >> 8,
+				fdt_pcie_set_msi_map_entry(blob, pcie, bdf >> 8,
 							   streamid);
 			}
 		}

include/configs/ls1012a_common.h

@@ -0,0 +1,145 @@
+/*
+ * Copyright 2016 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __LS1012A_COMMON_H
+#define __LS1012A_COMMON_H
+
+#define CONFIG_FSL_LAYERSCAPE
+#define CONFIG_FSL_LSCH2
+#define CONFIG_LS1012A
+#define CONFIG_GICV2
+
+#define	CONFIG_SYS_HAS_SERDES
+
+#include <asm/arch/config.h>
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_SUPPORT_RAW_INITRD
+
+#define CONFIG_DISPLAY_BOARDINFO_LATE
+
+#define CONFIG_SYS_TEXT_BASE		0x40100000
+
+#define CONFIG_SYS_FSL_CLK
+#define CONFIG_SYS_CLK_FREQ		100000000
+#define CONFIG_DDR_CLK_FREQ		125000000
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_BOARD_EARLY_INIT_F	1
+
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
+#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
+
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000
+#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY		CONFIG_SYS_CLK_FREQ/4	/* 25MHz */
+
+/* CSU */
+#define CONFIG_LAYERSCAPE_NS_ACCESS
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)
+
+/*SPI device */
+#ifdef CONFIG_QSPI_BOOT
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_FMAN_FW_ADDR		0x400d0000
+#define CONFIG_ENV_SPI_BUS		0
+#define CONFIG_ENV_SPI_CS		0
+#define CONFIG_ENV_SPI_MAX_HZ		1000000
+#define CONFIG_ENV_SPI_MODE		0x03
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_FSL_SPI_INTERFACE
+#define CONFIG_SF_DATAFLASH
+
+#define CONFIG_FSL_QSPI
+#define QSPI0_AMBA_BASE		0x40000000
+#define CONFIG_SPI_FLASH_SPANSION
+#define CONFIG_SPI_FLASH_BAR
+
+#define FSL_QSPI_FLASH_SIZE		(1 << 24)
+#define FSL_QSPI_FLASH_NUM		2
+
+/*
+ * Environment
+ */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SIZE			0x40000          /* 256KB */
+#define CONFIG_ENV_OFFSET		0x200000        /* 2MB */
+#define CONFIG_ENV_SECT_SIZE		0x40000
+#endif
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
+#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
+
+#define CONFIG_CONS_INDEX       1
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE     1
+#define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
+
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/* Command line configuration */
+#define CONFIG_CMD_ENV
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_ARCH_EARLY_INIT_R
+
+#define CONFIG_SYS_HZ			1000
+
+#define CONFIG_HWCONFIG
+#define HWCONFIG_BUFFER_SIZE		128
+
+#define CONFIG_DISPLAY_CPUINFO
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS		\
+	"initrd_high=0xffffffff\0"		\
+	"verify=no\0"				\
+	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
+	"loadaddr=0x80100000\0"			\
+	"kernel_addr=0x100000\0"		\
+	"ramdisk_addr=0x800000\0"		\
+	"ramdisk_size=0x2000000\0"		\
+	"fdt_high=0xffffffffffffffff\0"		\
+	"initrd_high=0xffffffffffffffff\0"	\
+	"kernel_start=0xa00000\0"		\
+	"kernel_load=0xa0000000\0"		\
+	"kernel_size=0x2800000\0"		\
+	"console=ttyAMA0,38400n8\0"
+
+#define CONFIG_BOOTARGS		"console=ttyS0,115200 root=/dev/ram0 " \
+				"earlycon=uart8250,mmio,0x21c0500"
+#define CONFIG_BOOTCOMMAND		"sf probe 0:0; sf read $kernel_load "\
+					"$kernel_start $kernel_size && "\
+					"bootm $kernel_load"
+#define CONFIG_BOOTDELAY		10
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE /* Boot args buffer */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_CMDLINE_EDITING		1
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_MAXARGS		64	/* max command args */
+
+#define CONFIG_PANIC_HANG
+#define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
+
+#include <asm/fsl_secure_boot.h>
+
+#endif /* __LS1012A_COMMON_H */

include/configs/ls1012afrdm.h

@@ -0,0 +1,44 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __LS1012ARDB_H__
+#define __LS1012ARDB_H__
+
+#include "ls1012a_common.h"
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	1
+#define CONFIG_NR_DRAM_BANKS		2
+#define CONFIG_SYS_SDRAM_SIZE		0x20000000
+
+#define CONFIG_SYS_MMDC_CORE_CONTROL_1		0x04180000
+#define CONFIG_SYS_MMDC_CORE_CONTROL_2		0x84180000
+
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		0x9fffffff
+
+/*
+* USB
+*/
+#define CONFIG_HAS_FSL_XHCI_USB
+
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_FSL
+#define CONFIG_USB_XHCI_DWC3
+#define CONFIG_USB_MAX_CONTROLLER_COUNT         1
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
+#define CONFIG_USB_STORAGE
+#endif
+
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		0x9fffffff
+
+#endif /* __LS1012ARDB_H__ */

include/configs/ls1012aqds.h

@@ -0,0 +1,191 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __LS1012AQDS_H__
+#define __LS1012AQDS_H__
+
+#include "ls1012a_common.h"
+
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	1
+#define CONFIG_NR_DRAM_BANKS		2
+#define CONFIG_SYS_SDRAM_SIZE		0x40000000
+
+#define CONFIG_SYS_MMDC_CORE_CONTROL_1		0x05180000
+#define CONFIG_SYS_MMDC_CORE_CONTROL_2		0x85180000
+
+/*
+ * QIXIS Definitions
+ */
+#define CONFIG_FSL_QIXIS
+
+#ifdef CONFIG_FSL_QIXIS
+#define CONFIG_QIXIS_I2C_ACCESS
+#define CONFIG_SYS_I2C_FPGA_ADDR	0x66
+#define QIXIS_LBMAP_BRDCFG_REG		0x04
+#define QIXIS_LBMAP_SWITCH		6
+#define QIXIS_LBMAP_MASK		0xf7
+#define QIXIS_LBMAP_SHIFT		0
+#define QIXIS_LBMAP_DFLTBANK		0x00
+#define QIXIS_LBMAP_ALTBANK		0x08
+#define QIXIS_RST_CTL_RESET		0x41
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE	0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START	0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+#endif
+
+/*
+ * I2C bus multiplexer
+ */
+#define I2C_MUX_PCA_ADDR_PRI		0x77
+#define I2C_MUX_PCA_ADDR_SEC		0x76 /* Secondary multiplexer */
+#define I2C_RETIMER_ADDR		0x18
+#define I2C_MUX_CH_DEFAULT		0x8
+#define I2C_MUX_CH_CH7301		0xC
+#define I2C_MUX_CH5			0xD
+#define I2C_MUX_CH7			0xF
+
+#define I2C_MUX_CH_VOL_MONITOR 0xa
+
+/*
+* RTC configuration
+*/
+#define RTC
+#define CONFIG_RTC_PCF8563 1
+#define CONFIG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
+#define CONFIG_CMD_DATE
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM    0
+#define CONFIG_SYS_I2C_EEPROM_ADDR   0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN     1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+
+/* Voltage monitor on channel 2*/
+#define I2C_VOL_MONITOR_ADDR           0x40
+#define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
+#define I2C_VOL_MONITOR_BUS_V_OVF      0x1
+#define I2C_VOL_MONITOR_BUS_V_SHIFT    3
+
+/* DSPI */
+#define CONFIG_FSL_DSPI1
+#define CONFIG_DEFAULT_SPI_BUS 1
+
+#define CONFIG_CMD_SPI
+#define MMAP_DSPI          DSPI1_BASE_ADDR
+
+#define CONFIG_SYS_DSPI_CTAR0   1
+
+#define CONFIG_SYS_DSPI_CTAR1	(DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
+				DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
+				DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
+				DSPI_CTAR_DT(0))
+#define CONFIG_SPI_FLASH_SST /* cs1 */
+
+#define CONFIG_SYS_DSPI_CTAR2	(DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
+				DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
+				DSPI_CTAR_CSSCK(0) | DSPI_CTAR_ASC(0) | \
+				DSPI_CTAR_DT(0))
+#define CONFIG_SPI_FLASH_STMICRO /* cs2 */
+
+#define CONFIG_SYS_DSPI_CTAR3	(DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
+				DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
+				DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
+				DSPI_CTAR_DT(0))
+#define CONFIG_SPI_FLASH_EON /* cs3 */
+
+#define CONFIG_SF_DEFAULT_SPEED      10000000
+#define CONFIG_SF_DEFAULT_MODE       SPI_MODE_0
+#define CONFIG_SF_DEFAULT_BUS        1
+#define CONFIG_SF_DEFAULT_CS         0
+
+/*
+* USB
+*/
+/* EHCI Support - disbaled by default */
+/*#define CONFIG_HAS_FSL_DR_USB*/
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#endif
+
+/*XHCI Support - enabled by default*/
+#define CONFIG_HAS_FSL_XHCI_USB
+
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_FSL
+#define CONFIG_USB_XHCI_DWC3
+#define CONFIG_USB_MAX_CONTROLLER_COUNT         1
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
+#define CONFIG_USB_STORAGE
+#endif
+
+/*  MMC  */
+#define CONFIG_MMC
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* SATA */
+#define CONFIG_LIBATA
+#define	CONFIG_SCSI
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_CMD_SCSI
+#define CONFIG_DOS_PARTITION
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_SYS_SATA				AHCI_BASE_ADDR
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID		1
+#define CONFIG_SYS_SCSI_MAX_LUN			1
+#define CONFIG_SYS_SCSI_MAX_DEVICE		(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+						CONFIG_SYS_SCSI_MAX_LUN)
+#define CONFIG_PCI		/* Enable PCI/PCIE */
+#define CONFIG_PCIE1		/* PCIE controller 1 */
+#define CONFIG_PCIE_LAYERSCAPE	/* Use common FSL Layerscape PCIe code */
+#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
+
+#define CONFIG_SYS_PCI_64BIT
+
+#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF	0x00000000
+#define CONFIG_SYS_PCIE_CFG0_SIZE	0x00001000	/* 4k */
+#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF	0x00001000
+#define CONFIG_SYS_PCIE_CFG1_SIZE	0x00001000	/* 4k */
+
+#define CONFIG_SYS_PCIE_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE_IO_PHYS_OFF	0x00010000
+#define CONFIG_SYS_PCIE_IO_SIZE		0x00010000	/* 64k */
+
+#define CONFIG_SYS_PCIE_MEM_BUS         0x08000000
+#define CONFIG_SYS_PCIE_MEM_PHYS_OFF    0x04000000
+#define CONFIG_SYS_PCIE_MEM_SIZE        0x80000000      /* 128M */
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_CMD_PCI
+
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		0x9fffffff
+
+#define CONFIG_MISC_INIT_R
+
+#endif /* __LS1012AQDS_H__ */

include/configs/ls1012ardb.h

@@ -0,0 +1,107 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __LS1012ARDB_H__
+#define __LS1012ARDB_H__
+
+#include "ls1012a_common.h"
+
+
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	1
+#define CONFIG_NR_DRAM_BANKS		2
+#define CONFIG_SYS_SDRAM_SIZE		0x40000000
+
+#define CONFIG_SYS_MMDC_CORE_CONTROL_1		0x05180000
+#define CONFIG_SYS_MMDC_CORE_CONTROL_2		0x85180000
+
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		0x9fffffff
+
+/*
+* USB
+*/
+#define CONFIG_HAS_FSL_XHCI_USB
+
+#ifdef CONFIG_HAS_FSL_XHCI_USB
+#define CONFIG_USB_XHCI
+#define CONFIG_USB_XHCI_FSL
+#define CONFIG_USB_XHCI_DWC3
+#define CONFIG_USB_MAX_CONTROLLER_COUNT         1
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
+#define CONFIG_USB_STORAGE
+#endif
+
+/*
+ * I2C IO expander
+ */
+
+#define I2C_MUX_IO1_ADDR	0x24
+#define __SW_BOOT_MASK		0xFC
+#define __SW_BOOT_EMU		0x10
+#define __SW_BOOT_BANK1		0x00
+#define __SW_BOOT_BANK2		0x01
+#define __SW_REV_MASK		0x07
+#define __SW_REV_A		0xF8
+#define __SW_REV_B		0xF0
+
+/*  MMC  */
+#define CONFIG_MMC
+#ifdef CONFIG_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DOS_PARTITION
+#endif
+
+/* SATA */
+#define CONFIG_LIBATA
+#define	CONFIG_SCSI
+#define CONFIG_SCSI_AHCI
+#define CONFIG_SCSI_AHCI_PLAT
+#define CONFIG_CMD_SCSI
+#define CONFIG_DOS_PARTITION
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_SYS_SATA				AHCI_BASE_ADDR
+
+#define CONFIG_SYS_SCSI_MAX_SCSI_ID		1
+#define CONFIG_SYS_SCSI_MAX_LUN			1
+#define CONFIG_SYS_SCSI_MAX_DEVICE		(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
+						CONFIG_SYS_SCSI_MAX_LUN)
+#define CONFIG_PCI		/* Enable PCI/PCIE */
+#define CONFIG_PCIE1		/* PCIE controller 1 */
+#define CONFIG_PCIE_LAYERSCAPE	/* Use common FSL Layerscape PCIe code */
+#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
+
+#define CONFIG_SYS_PCI_64BIT
+
+#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF	0x00000000
+#define CONFIG_SYS_PCIE_CFG0_SIZE	0x00001000	/* 4k */
+#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF	0x00001000
+#define CONFIG_SYS_PCIE_CFG1_SIZE	0x00001000	/* 4k */
+
+#define CONFIG_SYS_PCIE_IO_BUS		0x00000000
+#define CONFIG_SYS_PCIE_IO_PHYS_OFF	0x00010000
+#define CONFIG_SYS_PCIE_IO_SIZE		0x00010000	/* 64k */
+
+#define CONFIG_SYS_PCIE_MEM_BUS         0x08000000
+#define CONFIG_SYS_PCIE_MEM_PHYS_OFF    0x04000000
+#define CONFIG_SYS_PCIE_MEM_SIZE        0x80000000      /* 128M */
+
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_CMD_PCI
+
+#define CONFIG_CMD_MEMINFO
+#define CONFIG_CMD_MEMTEST
+#define CONFIG_SYS_MEMTEST_START	0x80000000
+#define CONFIG_SYS_MEMTEST_END		0x9fffffff
+
+#endif /* __LS1012ARDB_H__ */

include/fsl_mmdc.h

@@ -0,0 +1,160 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef FSL_MMDC_H
+#define FSL_MMDC_H
+
+#define CONFIG_SYS_MMDC_CORE_ODT_TIMING		0x12554000
+#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_0	0xbabf7954
+#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_1	0xff328f64
+#define CONFIG_SYS_MMDC_CORE_TIMING_CFG_2	0x01ff00db
+
+#define CONFIG_SYS_MMDC_CORE_MISC		0x00000680
+#define CONFIG_SYS_MMDC_PHY_MEASURE_UNIT	0x00000800
+#define CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY	0x00002000
+#define CONFIG_SYS_MMDC_PHY_ODT_CTRL		0x0000022a
+
+#define CONFIG_SYS_MMDC_CORE_OUT_OF_RESET_DELAY	0x00bf1023
+
+#define CONFIG_SYS_MMDC_CORE_ADDR_PARTITION	0x0000007f
+
+#define CONFIG_SYS_MMDC_PHY_ZQ_HW_CTRL		0xa1390003
+
+#define	FORCE_ZQ_AUTO_CALIBRATION		(0x1 << 16)
+
+/* PHY Write Leveling Configuration and Error Status (MPWLGCR) */
+#define WR_LVL_HW_EN				0x00000001
+
+/* PHY Pre-defined Compare and CA delay-line Configuration (MPPDCMPR2) */
+#define MPR_COMPARE_EN				0x00000001
+
+#define CONFIG_SYS_MMDC_PHY_RD_DLY_LINES_CFG	0x40404040
+
+/* MMDC PHY Read DQS gating control register 0 (MPDGCTRL0) */
+#define AUTO_RD_DQS_GATING_CALIBRATION_EN	0x10000000
+
+/* MMDC PHY Read Delay HW Calibration Control Register (MPRDDLHWCTL) */
+#define AUTO_RD_CALIBRATION_EN			0x00000010
+
+#define CONFIG_SYS_MMDC_CORE_PWR_DOWN_CTRL	0x00030035
+
+#define CONFIG_SYS_MMDC_CORE_PWR_SAV_CTRL_STAT	0x00001067
+
+#define CONFIG_SYS_MMDC_CORE_REFRESH_CTL	0x103e8000
+
+#define START_REFRESH				0x00000001
+
+/* MMDC Core Special Command Register (MDSCR) */
+#define CMD_ADDR_MSB_MR_OP(x)   (x << 24)
+
+#define  CMD_ADDR_LSB_MR_ADDR(x)    (x << 16)
+
+#define DISABLE_CFG_REQ		0x0
+#define CONFIGURATION_REQ	(0x1  << 15)
+#define WL_EN			(0x1  << 9)
+
+#define	CMD_NORMAL		(0x0 << 4)
+#define	CMD_PRECHARGE		(0x1 << 4)
+#define	CMD_AUTO_REFRESH	(0x2 << 4)
+#define	CMD_LOAD_MODE_REG	(0x3 << 4)
+#define	CMD_ZQ_CALIBRATION	(0x4 << 4)
+#define	CMD_PRECHARGE_BANK_OPEN	(0x5 << 4)
+#define	CMD_MRR			(0x6 << 4)
+
+#define CMD_BANK_ADDR_0		0x0
+#define CMD_BANK_ADDR_1		0x1
+#define CMD_BANK_ADDR_2		0x2
+#define CMD_BANK_ADDR_3		0x3
+#define CMD_BANK_ADDR_4		0x4
+#define CMD_BANK_ADDR_5		0x5
+#define CMD_BANK_ADDR_6		0x6
+#define CMD_BANK_ADDR_7		0x7
+
+/* MMDC Registers */
+struct mmdc_p_regs {
+	u32 mdctl;
+	u32 mdpdc;
+	u32 mdotc;
+	u32 mdcfg0;
+	u32 mdcfg1;
+	u32 mdcfg2;
+	u32 mdmisc;
+	u32 mdscr;
+	u32 mdref;
+	u32 res1[2];
+	u32 mdrwd;
+	u32 mdor;
+	u32 mdmrr;
+	u32 mdcfg3lp;
+	u32 mdmr4;
+	u32 mdasp;
+	u32 res2[239];
+	u32 maarcr;
+	u32 mapsr;
+	u32 maexidr0;
+	u32 maexidr1;
+	u32 madpcr0;
+	u32 madpcr1;
+	u32 madpsr0;
+	u32 madpsr1;
+	u32 madpsr2;
+	u32 madpsr3;
+	u32 madpsr4;
+	u32 madpsr5;
+	u32 masbs0;
+	u32 masbs1;
+	u32 res3[2];
+	u32 magenp;
+	u32 res4[239];
+	u32 mpzqhwctrl;
+	u32 mpzqswctrl;
+	u32 mpwlgcr;
+	u32 mpwldectrl0;
+	u32 mpwldectrl1;
+	u32 mpwldlst;
+	u32 mpodtctrl;
+	u32 mprddqby0dl;
+	u32 mprddqby1dl;
+	u32 mprddqby2dl;
+	u32 mprddqby3dl;
+	u32 res5[4];
+	u32 mpdgctrl0;
+	u32 mpdgctrl1;
+	u32 mpdgdlst0;
+	u32 mprddlctl;
+	u32 mprddlst;
+	u32 mpwrdlctl;
+	u32 mpwrdlst;
+	u32 mpsdctrl;
+	u32 mpzqlp2ctl;
+	u32 mprddlhwctl;
+	u32 mpwrdlhwctl;
+	u32 mprddlhwst0;
+	u32 mprddlhwst1;
+	u32 mpwrdlhwst0;
+	u32 mpwrdlhwst1;
+	u32 mpwlhwerr;
+	u32 mpdghwst0;
+	u32 mpdghwst1;
+	u32 mpdghwst2;
+	u32 mpdghwst3;
+	u32 mppdcmpr1;
+	u32 mppdcmpr2;
+	u32 mpswdar0;
+	u32 mpswdrdr0;
+	u32 mpswdrdr1;
+	u32 mpswdrdr2;
+	u32 mpswdrdr3;
+	u32 mpswdrdr4;
+	u32 mpswdrdr5;
+	u32 mpswdrdr6;
+	u32 mpswdrdr7;
+	u32 mpmur0;
+	u32 mpwrcadl;
+	u32 mpdccr;
+};
+
+#endif /* FSL_MMDC_H */

include/linux/usb/xhci-fsl.h

@@ -59,10 +59,14 @@ struct fsl_xhci {
 #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2080A_XHCI_USB1_ADDR
 #define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2080A_XHCI_USB2_ADDR
 #define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
-#elif defined(CONFIG_LS1043A)
+#elif defined(CONFIG_LS1043A) || defined(CONFIG_LS1012A)
 #define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR
 #define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS1043A_XHCI_USB2_ADDR
 #define CONFIG_SYS_FSL_XHCI_USB3_ADDR CONFIG_SYS_LS1043A_XHCI_USB3_ADDR
+#elif defined(CONFIG_LS1012A)
+#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS1043A_XHCI_USB1_ADDR
+#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
+#define CONFIG_SYS_FSL_XHCI_USB3_ADDR 0
 #endif
 
 #define FSL_USB_XHCI_ADDR	{CONFIG_SYS_FSL_XHCI_USB1_ADDR, \