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fsl-layerscape: Add workaround for PCIe erratum A010315

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As the access to serders protocol unselected PCIe controller will
hang. So disable the R/W permission to unselected PCIe controller
including its CCSR, IO space and memory space according to the
serders protocol field of RCW.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This commit is contained in:
Hou Zhiqiang 2016-08-02 19:03:27 +08:00 • committed by York Sun
parent 664b652058
commit b392a6d4b0
12 changed files with 65 additions and 0 deletions
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14
arch/arm/cpu/armv7/ls102xa/soc.c
View file

@ -7,6 +7,7 @@
#include <common.h>
#include <asm/arch/clock.h>
#include <asm/io.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/immap_ls102xa.h>
#include <asm/arch/ls102xa_soc.h>
#include <asm/arch/ls102xa_stream_id.h>
@ -59,6 +60,19 @@ unsigned int get_soc_major_rev(void)
return major;
}
#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
void erratum_a010315(void)
{
int i;
for (i = PCIE1; i <= PCIE2; i++)
if (!is_serdes_configured(i)) {
debug("PCIe%d: disabled all R/W permission!\n", i);
set_pcie_ns_access(i, 0);
}
}
#endif
int arch_soc_init(void)
{
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;

16
arch/arm/cpu/armv8/fsl-layerscape/soc.c
View file

@ -8,11 +8,14 @@
#include <fsl_ifc.h>
#include <ahci.h>
#include <scsi.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/soc.h>
#include <asm/io.h>
#include <asm/global_data.h>
#include <asm/arch-fsl-layerscape/config.h>
#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
#include <fsl_csu.h>
#endif
#ifdef CONFIG_SYS_FSL_DDR
#include <fsl_ddr_sdram.h>
#include <fsl_ddr.h>
@ -301,6 +304,19 @@ void erratum_a008850_post(void)
#endif
}
#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
void erratum_a010315(void)
{
int i;
for (i = PCIE1; i <= PCIE4; i++)
if (!is_serdes_configured(i)) {
debug("PCIe%d: disabled all R/W permission!\n", i);
set_pcie_ns_access(i, 0);
}
}
#endif
void fsl_lsch2_early_init_f(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;

2
arch/arm/include/asm/arch-fsl-layerscape/config.h
View file

@ -165,6 +165,8 @@
#define CONFIG_SYS_FSL_SEC_BE
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_ERRATUM_A010315
/* SoC related */
#ifdef CONFIG_LS1043A
#define CONFIG_MAX_CPUS 4

4
arch/arm/include/asm/arch-fsl-layerscape/soc.h
View file

@ -100,6 +100,10 @@ void cpu_name(char *name);
void erratum_a009635(void);
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
void erratum_a010315(void);
#endif
bool soc_has_dp_ddr(void);
bool soc_has_aiop(void);
#endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */

1
arch/arm/include/asm/arch-ls102xa/config.h
View file

@ -129,6 +129,7 @@
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FSL_ERRATUM_A008378
#define CONFIG_SYS_FSL_ERRATUM_A009663
#define CONFIG_SYS_FSL_ERRATUM_A010315
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#else
#error SoC not defined

4
arch/arm/include/asm/arch-ls102xa/ls102xa_soc.h
View file

@ -11,4 +11,8 @@ unsigned int get_soc_major_rev(void);
int arch_soc_init(void);
int ls102xa_smmu_stream_id_init(void);
#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
void erratum_a010315(void);
#endif
#endif /* __FSL_LS102XA_SOC_H */

4
board/freescale/ls1012aqds/ls1012aqds.c
View file

@ -206,6 +206,10 @@ int board_init(void)
out_le32(&cci->ctrl_ord,
CCI400_CTRLORD_EN_BARRIER);
#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
erratum_a010315();
#endif
#ifdef CONFIG_ENV_IS_NOWHERE
gd->env_addr = (ulong)&default_environment[0];
#endif

4
board/freescale/ls1012ardb/ls1012ardb.c
View file

@ -202,6 +202,10 @@ int board_init(void)
*/
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
erratum_a010315();
#endif
#ifdef CONFIG_ENV_IS_NOWHERE
gd->env_addr = (ulong)&default_environment[0];
#endif

4
board/freescale/ls1021aqds/ls1021aqds.c
View file

@ -430,6 +430,10 @@ int board_init(void)
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
unsigned int major;
#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
erratum_a010315();
#endif
major = get_soc_major_rev();
if (major == SOC_MAJOR_VER_1_0) {
/* Set CCI-400 control override register to

4
board/freescale/ls1021atwr/ls1021atwr.c
View file

@ -480,6 +480,10 @@ void ls1twr_program_regulator(void)
int board_init(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
erratum_a010315();
#endif
#ifndef CONFIG_SYS_FSL_NO_SERDES
fsl_serdes_init();
#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)

4
board/freescale/ls1043aqds/ls1043aqds.c
View file

@ -308,6 +308,10 @@ int misc_init_r(void)
int board_init(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
erratum_a010315();
#endif
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
board_retimer_init();

4
board/freescale/ls1043ardb/ls1043ardb.c
View file

@ -85,6 +85,10 @@ int board_init(void)
{
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
erratum_a010315();
#endif
#ifdef CONFIG_FSL_IFC
init_final_memctl_regs();
#endif