mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 23:24:38 +00:00
Merge branch 'master' of git://git.denx.de/u-boot-arm
This commit is contained in:
commit
3f2f1a0039
8 changed files with 113 additions and 13 deletions
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@ -68,7 +68,7 @@ static void v7_inval_dcache_level_setway(u32 level, u32 num_sets,
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}
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}
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/* DSB to make sure the operation is complete */
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CP15DSB;
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DSB;
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}
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static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets,
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@ -96,7 +96,7 @@ static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets,
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}
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}
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/* DSB to make sure the operation is complete */
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CP15DSB;
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DSB;
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}
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static void v7_maint_dcache_level_setway(u32 level, u32 operation)
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@ -215,7 +215,7 @@ static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op)
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}
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/* DSB to make sure the operation is complete */
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CP15DSB;
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DSB;
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}
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/* Invalidate TLB */
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@ -228,9 +228,9 @@ static void v7_inval_tlb(void)
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/* Invalidate entire instruction TLB */
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asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0));
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/* Full system DSB - make sure that the invalidation is complete */
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CP15DSB;
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DSB;
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/* Full system ISB - make sure the instruction stream sees it */
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CP15ISB;
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ISB;
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}
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void invalidate_dcache_all(void)
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@ -343,10 +343,10 @@ void invalidate_icache_all(void)
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asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
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/* Full system DSB - make sure that the invalidation is complete */
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CP15DSB;
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DSB;
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/* ISB - make sure the instruction stream sees it */
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CP15ISB;
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ISB;
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}
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#else
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void invalidate_icache_all(void)
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@ -70,6 +70,16 @@
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#define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0))
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#define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0))
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#ifdef __ARM_ARCH_7A__
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#define ISB asm volatile ("isb" : : : "memory")
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#define DSB asm volatile ("dsb" : : : "memory")
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#define DMB asm volatile ("dmb" : : : "memory")
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#else
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#define ISB CP15ISB
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#define DSB CP15DSB
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#define DMB CP15DMB
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#endif
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/*
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* Workaround for ARM errata # 798870
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* Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been
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@ -95,9 +95,6 @@ static inline int __test_and_change_bit(int nr, volatile void *addr)
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return (old & mask) != 0;
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}
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extern int find_first_zero_bit(void * addr, unsigned size);
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extern int find_next_zero_bit(void * addr, int size, int offset);
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/*
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* This routine doesn't need to be atomic.
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*/
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@ -129,6 +126,43 @@ static inline unsigned long ffz(unsigned long word)
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return k;
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}
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static inline int find_next_zero_bit(void *addr, int size, int offset)
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{
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unsigned long *p = ((unsigned long *)addr) + (offset >> 5);
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unsigned long result = offset & ~31UL;
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unsigned long tmp;
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if (offset >= size)
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return size;
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size -= result;
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offset &= 31UL;
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if (offset) {
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tmp = *(p++);
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tmp |= ~0UL >> (32-offset);
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if (size < 32)
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goto found_first;
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if (~tmp)
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goto found_middle;
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size -= 32;
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result += 32;
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}
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while (size & ~31UL) {
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tmp = *(p++);
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if (~tmp)
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goto found_middle;
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result += 32;
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size -= 32;
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}
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if (!size)
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return result;
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tmp = *p;
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found_first:
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tmp |= ~0UL >> size;
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found_middle:
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return result + ffz(tmp);
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}
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/*
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* hweightN: returns the hamming weight (i.e. the number
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* of bits set) of a N-bit word
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@ -138,6 +172,9 @@ static inline unsigned long ffz(unsigned long word)
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#define hweight16(x) generic_hweight16(x)
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#define hweight8(x) generic_hweight8(x)
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#define find_first_zero_bit(addr, size) \
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find_next_zero_bit((addr), (size), 0)
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#define ext2_set_bit test_and_set_bit
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#define ext2_clear_bit test_and_clear_bit
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#define ext2_test_bit test_bit
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@ -143,6 +143,9 @@ lr .req x30
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mov \xreg1, #0x33ff
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msr cptr_el2, \xreg1 /* Disable coprocessor traps to EL2 */
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/* Initialize Generic Timers */
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msr cntvoff_el2, xzr
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/* Initialize SCTLR_EL2
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*
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* setting RES1 bits (29,28,23,22,18,16,11,5,4) to 1
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@ -196,6 +196,28 @@ static inline void set_dacr(unsigned int val)
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isb();
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}
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#ifdef CONFIG_ARMV7
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/* Short-Descriptor Translation Table Level 1 Bits */
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#define TTB_SECT_NS_MASK (1 << 19)
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#define TTB_SECT_NG_MASK (1 << 17)
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#define TTB_SECT_S_MASK (1 << 16)
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/* Note: TTB AP bits are set elsewhere */
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#define TTB_SECT_TEX(x) ((x & 0x7) << 12)
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#define TTB_SECT_DOMAIN(x) ((x & 0xf) << 5)
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#define TTB_SECT_XN_MASK (1 << 4)
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#define TTB_SECT_C_MASK (1 << 3)
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#define TTB_SECT_B_MASK (1 << 2)
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#define TTB_SECT (2 << 0)
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/* options available for data cache on each page */
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enum dcache_option {
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DCACHE_OFF = TTB_SECT_S_MASK | TTB_SECT_DOMAIN(0) |
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TTB_SECT_XN_MASK | TTB_SECT,
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DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK,
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DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK,
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DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1),
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};
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#else
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/* options available for data cache on each page */
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enum dcache_option {
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DCACHE_OFF = 0x12,
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@ -203,6 +225,7 @@ enum dcache_option {
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DCACHE_WRITEBACK = 0x1e,
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DCACHE_WRITEALLOC = 0x16,
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};
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#endif
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/* Size of an MMU section */
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enum {
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@ -210,6 +233,20 @@ enum {
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MMU_SECTION_SIZE = 1 << MMU_SECTION_SHIFT,
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};
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#ifdef CONFIG_ARMV7
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/* TTBR0 bits */
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#define TTBR0_BASE_ADDR_MASK 0xFFFFC000
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#define TTBR0_RGN_NC (0 << 3)
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#define TTBR0_RGN_WBWA (1 << 3)
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#define TTBR0_RGN_WT (2 << 3)
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#define TTBR0_RGN_WB (3 << 3)
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/* TTBR0[6] is IRGN[0] and TTBR[0] is IRGN[1] */
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#define TTBR0_IRGN_NC (0 << 0 | 0 << 6)
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#define TTBR0_IRGN_WBWA (0 << 0 | 1 << 6)
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#define TTBR0_IRGN_WT (1 << 0 | 0 << 6)
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#define TTBR0_IRGN_WB (1 << 0 | 1 << 6)
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#endif
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/**
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* Change the cache settings for a region.
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*
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@ -96,9 +96,23 @@ static inline void mmu_setup(void)
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dram_bank_mmu_setup(i);
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}
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#ifdef CONFIG_ARMV7
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/* Set TTBR0 */
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reg = gd->arch.tlb_addr & TTBR0_BASE_ADDR_MASK;
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#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
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reg |= TTBR0_RGN_WT | TTBR0_IRGN_WT;
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#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
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reg |= TTBR0_RGN_WBWA | TTBR0_IRGN_WBWA;
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#else
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reg |= TTBR0_RGN_WB | TTBR0_IRGN_WB;
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#endif
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asm volatile("mcr p15, 0, %0, c2, c0, 0"
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: : "r" (reg) : "memory");
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#else
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/* Copy the page table address to cp15 */
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asm volatile("mcr p15, 0, %0, c2, c0, 0"
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: : "r" (gd->arch.tlb_addr) : "memory");
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#endif
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/* Set the access control to all-supervisor */
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asm volatile("mcr p15, 0, %0, c3, c0, 0"
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: : "r" (~0));
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@ -29,9 +29,9 @@
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#include <common.h>
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#include <serial.h>
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#if defined(CONFIG_CPU_V6)
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#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V7)
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/*
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* ARMV6
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* ARMV6 & ARMV7
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*/
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#define DCC_RBIT (1 << 30)
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#define DCC_WBIT (1 << 29)
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@ -34,7 +34,6 @@
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/* DCC driver */
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#if defined(CONFIG_ZYNQ_DCC)
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# define CONFIG_ARM_DCC
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# define CONFIG_CPU_V6 /* Required by CONFIG_ARM_DCC */
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#else
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# define CONFIG_ZYNQ_SERIAL
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#endif
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