mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-10 23:24:38 +00:00
Merge git://git.denx.de/u-boot-usb
This commit is contained in:
Tom Rini
commit
a5d338b2f2
9 changed files with 230 additions and 68 deletions
|
|
@ -47,8 +47,12 @@ int arch_cpu_init(void)
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#if defined(CONFIG_NAND_FSMC)
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periph1_clken |= MISC_FSMCENB;
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#endif
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#if defined(CONFIG_USB_EHCI_SPEAR)
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periph1_clken |= PERIPH_USBH1 | PERIPH_USBH2;
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#endif
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writel(periph1_clken, &misc_p->periph1_clken);
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return 0;
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}
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@ -11,6 +11,8 @@
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#define CONFIG_SYS_USBD_BASE 0xE1100000
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#define CONFIG_SYS_PLUG_BASE 0xE1200000
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#define CONFIG_SYS_FIFO_BASE 0xE1000800
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#define CONFIG_SYS_UHC0_EHCI_BASE 0xE1800000
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#define CONFIG_SYS_UHC1_EHCI_BASE 0xE2000000
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#define CONFIG_SYS_SMI_BASE 0xFC000000
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#define CONFIG_SPEAR_SYSCNTLBASE 0xFCA00000
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#define CONFIG_SPEAR_TIMERBASE 0xFC800000
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@ -15,6 +15,7 @@
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#include <linux/usb/cdc.h>
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#include <linux/usb/gadget.h>
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#include <net.h>
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#include <usb.h>
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#include <malloc.h>
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#include <linux/ctype.h>
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@ -2312,6 +2313,8 @@ static int usb_eth_init(struct eth_device *netdev, bd_t *bd)
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goto fail;
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}
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board_usb_init(0, USB_INIT_DEVICE);
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/* Configure default mac-addresses for the USB ethernet device */
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#ifdef CONFIG_USBNET_DEV_ADDR
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strlcpy(dev_addr, CONFIG_USBNET_DEV_ADDR, sizeof(dev_addr));
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@ -2492,6 +2495,7 @@ void usb_eth_halt(struct eth_device *netdev)
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}
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usb_gadget_unregister_driver(ð_driver);
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board_usb_cleanup(0, USB_INIT_DEVICE);
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}
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static struct usb_gadget_driver eth_driver = {
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@ -2501,6 +2505,7 @@ static struct usb_gadget_driver eth_driver = {
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.unbind = eth_unbind,
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.setup = eth_setup,
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.reset = eth_disconnect,
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.disconnect = eth_disconnect,
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.suspend = eth_suspend,
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@ -37,6 +37,7 @@ obj-$(CONFIG_USB_EHCI_MXC) += ehci-mxc.o
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obj-$(CONFIG_USB_EHCI_MXS) += ehci-mxs.o
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obj-$(CONFIG_USB_EHCI_MX5) += ehci-mx5.o
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obj-$(CONFIG_USB_EHCI_MX6) += ehci-mx6.o
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obj-$(CONFIG_USB_EHCI_MX7) += ehci-mx6.o
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obj-$(CONFIG_USB_EHCI_OMAP) += ehci-omap.o
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obj-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o
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obj-$(CONFIG_USB_EHCI_MARVELL) += ehci-marvell.o
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@ -1113,11 +1113,12 @@ struct dm_usb_ops dwc2_usb_ops = {
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static const struct udevice_id dwc2_usb_ids[] = {
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{ .compatible = "brcm,bcm2835-usb" },
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{ .compatible = "snps,dwc2" },
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{ }
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};
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U_BOOT_DRIVER(usb_dwc2) = {
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.name = "dwc2_exynos",
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.name = "dwc2_usb",
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.id = UCLASS_USB,
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.of_match = dwc2_usb_ids,
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.ofdata_to_platdata = dwc2_usb_ofdata_to_platdata,
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@ -45,7 +45,10 @@
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#define ANADIG_USB2_PLL_480_CTRL_POWER 0x00001000
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#define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS 0x00000040
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#define USBNC_OFFSET 0x200
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#define USBNC_PHYSTATUS_ID_DIG (1 << 4) /* otg_id status */
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#define USBNC_PHYCFG2_ACAENB (1 << 4) /* otg_id detection enable */
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#define UCTRL_PM (1 << 9) /* OTG Power Mask */
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#define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */
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#define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */
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@ -53,6 +56,7 @@
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#define UCMD_RUN_STOP (1 << 0) /* controller run/stop */
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#define UCMD_RESET (1 << 1) /* controller reset */
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#if defined(CONFIG_MX6)
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static const unsigned phy_bases[] = {
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USB_PHY0_BASE_ADDR,
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USB_PHY1_BASE_ADDR,
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@ -67,7 +71,7 @@ static void usb_internal_phy_clock_gate(int index, int on)
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phy_reg = (void __iomem *)phy_bases[index];
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phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET;
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__raw_writel(USBPHY_CTRL_CLKGATE, phy_reg);
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writel(USBPHY_CTRL_CLKGATE, phy_reg);
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}
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static void usb_power_config(int index)
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@ -100,26 +104,52 @@ static void usb_power_config(int index)
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* is totally controlled by IC, so the Software only needs
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* to enable them at initializtion.
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*/
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__raw_writel(ANADIG_USB2_CHRG_DETECT_EN_B |
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writel(ANADIG_USB2_CHRG_DETECT_EN_B |
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ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
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chrg_detect);
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__raw_writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
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writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
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pll_480_ctrl_clr);
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__raw_writel(ANADIG_USB2_PLL_480_CTRL_ENABLE |
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writel(ANADIG_USB2_PLL_480_CTRL_ENABLE |
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ANADIG_USB2_PLL_480_CTRL_POWER |
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ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
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pll_480_ctrl_set);
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}
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static int wait_for_bit(u32 *reg, const u32 mask, bool set)
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{
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u32 val;
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const unsigned int timeout = 10000;
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unsigned long start = get_timer(0);
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while(1) {
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val = readl(reg);
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if (!set)
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val = ~val;
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if ((val & mask) == mask)
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return 0;
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if (get_timer(start) > timeout)
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break;
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udelay(1);
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}
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debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n",
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__func__, reg, mask, set);
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return -ETIMEDOUT;
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}
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/* Return 0 : host node, <>0 : device mode */
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static int usb_phy_enable(int index, struct usb_ehci *ehci)
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{
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void __iomem *phy_reg;
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void __iomem *phy_ctrl;
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void __iomem *usb_cmd;
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u32 val;
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int ret;
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if (index >= ARRAY_SIZE(phy_bases))
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return 0;
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@ -129,70 +159,33 @@ static int usb_phy_enable(int index, struct usb_ehci *ehci)
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usb_cmd = (void __iomem *)&ehci->usbcmd;
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/* Stop then Reset */
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val = __raw_readl(usb_cmd);
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val &= ~UCMD_RUN_STOP;
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__raw_writel(val, usb_cmd);
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while (__raw_readl(usb_cmd) & UCMD_RUN_STOP)
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;
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clrbits_le32(usb_cmd, UCMD_RUN_STOP);
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ret = wait_for_bit(usb_cmd, UCMD_RUN_STOP, 0);
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if (ret)
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return ret;
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val = __raw_readl(usb_cmd);
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val |= UCMD_RESET;
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__raw_writel(val, usb_cmd);
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while (__raw_readl(usb_cmd) & UCMD_RESET)
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;
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setbits_le32(usb_cmd, UCMD_RESET);
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ret = wait_for_bit(usb_cmd, UCMD_RESET, 0);
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if (ret)
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return ret;
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/* Reset USBPHY module */
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val = __raw_readl(phy_ctrl);
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val |= USBPHY_CTRL_SFTRST;
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__raw_writel(val, phy_ctrl);
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setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST);
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udelay(10);
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/* Remove CLKGATE and SFTRST */
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val = __raw_readl(phy_ctrl);
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val &= ~(USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST);
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__raw_writel(val, phy_ctrl);
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clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST);
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udelay(10);
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/* Power up the PHY */
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__raw_writel(0, phy_reg + USBPHY_PWD);
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writel(0, phy_reg + USBPHY_PWD);
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/* enable FS/LS device */
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val = __raw_readl(phy_ctrl);
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val |= (USBPHY_CTRL_ENUTMILEVEL2 | USBPHY_CTRL_ENUTMILEVEL3);
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__raw_writel(val, phy_ctrl);
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setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 |
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USBPHY_CTRL_ENUTMILEVEL3);
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return 0;
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}
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/* Base address for this IP block is 0x02184800 */
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struct usbnc_regs {
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u32 ctrl[4]; /* otg/host1-3 */
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u32 uh2_hsic_ctrl;
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u32 uh3_hsic_ctrl;
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u32 otg_phy_ctrl_0;
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u32 uh1_phy_ctrl_0;
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};
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static void usb_oc_config(int index)
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{
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struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
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USB_OTHERREGS_OFFSET);
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void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]);
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u32 val;
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val = __raw_readl(ctrl);
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#if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2
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/* mx6qarm2 seems to required a different setting*/
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val &= ~UCTRL_OVER_CUR_POL;
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#else
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val |= UCTRL_OVER_CUR_POL;
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#endif
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__raw_writel(val, ctrl);
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val = __raw_readl(ctrl);
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val |= UCTRL_OVER_CUR_DIS;
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__raw_writel(val, ctrl);
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}
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int usb_phy_mode(int port)
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{
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void __iomem *phy_reg;
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@ -202,7 +195,7 @@ int usb_phy_mode(int port)
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phy_reg = (void __iomem *)phy_bases[port];
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phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
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val = __raw_readl(phy_ctrl);
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val = readl(phy_ctrl);
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if (val & USBPHY_CTRL_OTG_ID)
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return USB_INIT_DEVICE;
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@ -210,16 +203,121 @@ int usb_phy_mode(int port)
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return USB_INIT_HOST;
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}
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/* Base address for this IP block is 0x02184800 */
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struct usbnc_regs {
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u32 ctrl[4]; /* otg/host1-3 */
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u32 uh2_hsic_ctrl;
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u32 uh3_hsic_ctrl;
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u32 otg_phy_ctrl_0;
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u32 uh1_phy_ctrl_0;
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};
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#elif defined(CONFIG_MX7)
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struct usbnc_regs {
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u32 ctrl1;
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u32 ctrl2;
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u32 reserve1[10];
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u32 phy_cfg1;
|
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u32 phy_cfg2;
|
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u32 phy_status;
|
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u32 reserve2[4];
|
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u32 adp_cfg1;
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u32 adp_cfg2;
|
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u32 adp_status;
|
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};
|
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static void usb_power_config(int index)
|
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{
|
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struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
|
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(0x10000 * index) + USBNC_OFFSET);
|
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void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2);
|
||||
|
||||
/* Enable usb_otg_id detection */
|
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setbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB);
|
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}
|
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|
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int usb_phy_mode(int port)
|
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{
|
||||
struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
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(0x10000 * port) + USBNC_OFFSET);
|
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void __iomem *status = (void __iomem *)(&usbnc->phy_status);
|
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u32 val;
|
||||
|
||||
val = readl(status);
|
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|
||||
if (val & USBNC_PHYSTATUS_ID_DIG)
|
||||
return USB_INIT_DEVICE;
|
||||
else
|
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return USB_INIT_HOST;
|
||||
}
|
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#endif
|
||||
|
||||
static void usb_oc_config(int index)
|
||||
{
|
||||
#if defined(CONFIG_MX6)
|
||||
struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
|
||||
USB_OTHERREGS_OFFSET);
|
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void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]);
|
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#elif defined(CONFIG_MX7)
|
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struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
|
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(0x10000 * index) + USBNC_OFFSET);
|
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void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1);
|
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#endif
|
||||
|
||||
#if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2
|
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/* mx6qarm2 seems to required a different setting*/
|
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clrbits_le32(ctrl, UCTRL_OVER_CUR_POL);
|
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#else
|
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setbits_le32(ctrl, UCTRL_OVER_CUR_POL);
|
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#endif
|
||||
|
||||
#if defined(CONFIG_MX6)
|
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setbits_le32(ctrl, UCTRL_OVER_CUR_DIS);
|
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#elif defined(CONFIG_MX7)
|
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setbits_le32(ctrl, UCTRL_OVER_CUR_DIS | UCTRL_PM);
|
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#endif
|
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}
|
||||
|
||||
/**
|
||||
* board_ehci_hcd_init - override usb phy mode
|
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* @port: usb host/otg port
|
||||
*
|
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* Target board specific, override usb_phy_mode.
|
||||
* When usb-otg is used as usb host port, iomux pad usb_otg_id can be
|
||||
* left disconnected in this case usb_phy_mode will not be able to identify
|
||||
* the phy mode that usb port is used.
|
||||
* Machine file overrides board_usb_phy_mode.
|
||||
*
|
||||
* Return: USB_INIT_DEVICE or USB_INIT_HOST
|
||||
*/
|
||||
int __weak board_usb_phy_mode(int port)
|
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{
|
||||
return usb_phy_mode(port);
|
||||
}
|
||||
|
||||
/**
|
||||
* board_ehci_hcd_init - set usb vbus voltage
|
||||
* @port: usb otg port
|
||||
*
|
||||
* Target board specific, setup iomux pad to setup supply vbus voltage
|
||||
* for usb otg port. Machine board file overrides board_ehci_hcd_init
|
||||
*
|
||||
* Return: 0 Success
|
||||
*/
|
||||
int __weak board_ehci_hcd_init(int port)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* board_ehci_power - enables/disables usb vbus voltage
|
||||
* @port: usb otg port
|
||||
* @on: on/off vbus voltage
|
||||
*
|
||||
* Enables/disables supply vbus voltage for usb otg port.
|
||||
* Machine board file overrides board_ehci_power
|
||||
*
|
||||
* Return: 0 Success
|
||||
*/
|
||||
int __weak board_ehci_power(int port, int on)
|
||||
{
|
||||
return 0;
|
||||
|
|
@ -229,8 +327,13 @@ int ehci_hcd_init(int index, enum usb_init_type init,
|
|||
struct ehci_hccr **hccr, struct ehci_hcor **hcor)
|
||||
{
|
||||
enum usb_init_type type;
|
||||
#if defined(CONFIG_MX6)
|
||||
u32 controller_spacing = 0x200;
|
||||
#elif defined(CONFIG_MX7)
|
||||
u32 controller_spacing = 0x10000;
|
||||
#endif
|
||||
struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +
|
||||
(0x200 * index));
|
||||
(controller_spacing * index));
|
||||
|
||||
if (index > 3)
|
||||
return -EINVAL;
|
||||
|
|
@ -242,8 +345,11 @@ int ehci_hcd_init(int index, enum usb_init_type init,
|
|||
|
||||
usb_power_config(index);
|
||||
usb_oc_config(index);
|
||||
|
||||
#if defined(CONFIG_MX6)
|
||||
usb_internal_phy_clock_gate(index, 1);
|
||||
usb_phy_enable(index, ehci);
|
||||
#endif
|
||||
type = board_usb_phy_mode(index);
|
||||
|
||||
*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
|
||||
|
|
@ -256,8 +362,9 @@ int ehci_hcd_init(int index, enum usb_init_type init,
|
|||
return -ENODEV;
|
||||
if (type == USB_INIT_DEVICE)
|
||||
return 0;
|
||||
|
||||
setbits_le32(&ehci->usbmode, CM_HOST);
|
||||
__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
|
||||
writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
|
||||
setbits_le32(&ehci->portsc, USB_EN);
|
||||
|
||||
mdelay(10);
|
||||
|
|
|
|||
|
|
@ -14,7 +14,21 @@
|
|||
#include <usb.h>
|
||||
#include "ehci.h"
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/spr_misc.h>
|
||||
|
||||
static void spear6xx_usbh_stop(void)
|
||||
{
|
||||
struct misc_regs *const misc_p =
|
||||
(struct misc_regs *)CONFIG_SPEAR_MISCBASE;
|
||||
u32 periph1_rst = readl(misc_p->periph1_rst);
|
||||
|
||||
periph1_rst |= PERIPH_USBH1 | PERIPH_USBH2;
|
||||
writel(periph1_rst, misc_p->periph1_rst);
|
||||
|
||||
udelay(1000);
|
||||
periph1_rst &= ~(PERIPH_USBH1 | PERIPH_USBH2);
|
||||
writel(periph1_rst, misc_p->periph1_rst);
|
||||
}
|
||||
|
||||
/*
|
||||
* Create the appropriate control structures to manage
|
||||
|
|
@ -23,9 +37,23 @@
|
|||
int ehci_hcd_init(int index, enum usb_init_type init,
|
||||
struct ehci_hccr **hccr, struct ehci_hcor **hcor)
|
||||
{
|
||||
*hccr = (struct ehci_hccr *)(CONFIG_SYS_UHC0_EHCI_BASE + 0x100);
|
||||
*hcor = (struct ehci_hcor *)((uint32_t)*hccr
|
||||
+ HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
|
||||
u32 ehci = 0;
|
||||
|
||||
switch (index) {
|
||||
case 0:
|
||||
ehci = CONFIG_SYS_UHC0_EHCI_BASE;
|
||||
break;
|
||||
case 1:
|
||||
ehci = CONFIG_SYS_UHC1_EHCI_BASE;
|
||||
break;
|
||||
default:
|
||||
printf("ERROR: wrong controller index!\n");
|
||||
break;
|
||||
};
|
||||
|
||||
*hccr = (struct ehci_hccr *)(ehci + 0x100);
|
||||
*hcor = (struct ehci_hcor *)((uint32_t) *hccr +
|
||||
HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
|
||||
|
||||
debug("SPEAr-ehci: init hccr %x and hcor %x hc_length %d\n",
|
||||
(uint32_t)*hccr, (uint32_t)*hcor,
|
||||
|
|
@ -40,5 +68,9 @@ int ehci_hcd_init(int index, enum usb_init_type init,
|
|||
*/
|
||||
int ehci_hcd_stop(int index)
|
||||
{
|
||||
#if defined(CONFIG_SPEAR600)
|
||||
spear6xx_usbh_stop();
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -96,4 +96,5 @@ void xhci_hcd_stop(int index)
|
|||
struct omap_xhci *ctx = &omap;
|
||||
|
||||
omap_xhci_core_exit(ctx);
|
||||
board_usb_cleanup(index, USB_INIT_HOST);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -199,7 +199,7 @@ int xhci_reset(struct xhci_hcor *hcor)
|
|||
int ret;
|
||||
|
||||
/* Halting the Host first */
|
||||
debug("// Halt the HC\n");
|
||||
debug("// Halt the HC: %p\n", hcor);
|
||||
state = xhci_readl(&hcor->or_usbsts) & STS_HALT;
|
||||
if (!state) {
|
||||
cmd = xhci_readl(&hcor->or_usbcmd);
|
||||
|
|
@ -1064,6 +1064,8 @@ int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
|
|||
struct xhci_ctrl *ctrl;
|
||||
int ret;
|
||||
|
||||
*controller = NULL;
|
||||
|
||||
if (xhci_hcd_init(index, &hccr, (struct xhci_hcor **)&hcor) != 0)
|
||||
return -ENODEV;
|
||||
|
||||
|
|
@ -1077,7 +1079,12 @@ int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
|
|||
|
||||
ret = xhci_lowlevel_init(ctrl);
|
||||
|
||||
*controller = &xhcic[index];
|
||||
if (ret) {
|
||||
ctrl->hccr = NULL;
|
||||
ctrl->hcor = NULL;
|
||||
} else {
|
||||
*controller = &xhcic[index];
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
@ -1093,9 +1100,11 @@ int usb_lowlevel_stop(int index)
|
|||
{
|
||||
struct xhci_ctrl *ctrl = (xhcic + index);
|
||||
|
||||
xhci_lowlevel_stop(ctrl);
|
||||
xhci_hcd_stop(index);
|
||||
xhci_cleanup(ctrl);
|
||||
if (ctrl->hcor) {
|
||||
xhci_lowlevel_stop(ctrl);
|
||||
xhci_hcd_stop(index);
|
||||
xhci_cleanup(ctrl);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue