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sunxi: Enable non-secure access to RTC on sun6i (A31s)
On the A31s the RTC is by default secured. Thus when u-boot loads the kernel in non-secure world, the RTC is unavailable. The SoC has a TrustZone Protection Controller, which can be used to enable non-secure access to the RTC. On the A31 the TZPC doesn't seem to do anything, i.e. changes to its register contents do not affect access to the RTC. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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4 changed files with 47 additions and 0 deletions
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@ -28,6 +28,7 @@ obj-$(CONFIG_MACH_SUN6I) += clock_sun6i.o
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obj-$(CONFIG_MACH_SUN7I) += clock_sun4i.o
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obj-$(CONFIG_MACH_SUN8I) += clock_sun6i.o
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obj-$(CONFIG_MACH_SUN9I) += clock_sun9i.o
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obj-$(CONFIG_MACH_SUN6I) += tzpc.o
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obj-$(CONFIG_AXP152_POWER) += pmic_bus.o
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obj-$(CONFIG_AXP209_POWER) += pmic_bus.o
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@ -23,6 +23,7 @@
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#include <asm/arch/gpio.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/timer.h>
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#include <asm/arch/tzpc.h>
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#include <asm/arch/mmc.h>
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#include <linux/compiler.h>
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@ -115,6 +116,10 @@ void s_init(void)
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"orr r0, r0, #1 << 6\n"
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"mcr p15, 0, r0, c1, c0, 1\n");
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#endif
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#if defined CONFIG_MACH_SUN6I
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/* Enable non-secure access to the RTC */
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tzpc_init();
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#endif
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clock_init();
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timer_init();
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18
arch/arm/cpu/armv7/sunxi/tzpc.c
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arch/arm/cpu/armv7/sunxi/tzpc.c
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@ -0,0 +1,18 @@
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/*
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* (C) Copyright 2015 Chen-Yu Tsai <wens@csie.org>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/tzpc.h>
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/* Configure Trust Zone Protection Controller */
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void tzpc_init(void)
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{
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struct sunxi_tzpc *tzpc = (struct sunxi_tzpc *)SUNXI_TZPC_BASE;
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/* Enable non-secure access to the RTC */
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writel(SUNXI_TZPC_DECPORT0_RTC, &tzpc->decport0_set);
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}
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arch/arm/include/asm/arch-sunxi/tzpc.h
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arch/arm/include/asm/arch-sunxi/tzpc.h
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@ -0,0 +1,23 @@
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/*
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* (C) Copyright 2015 Chen-Yu Tsai <wens@csie.org>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _SUNXI_TZPC_H
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#define _SUNXI_TZPC_H
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#ifndef __ASSEMBLY__
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struct sunxi_tzpc {
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u32 r0size; /* 0x00 Size of secure RAM region */
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u32 decport0_status; /* 0x04 Status of decode protection port 0 */
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u32 decport0_set; /* 0x08 Set decode protection port 0 */
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u32 decport0_clear; /* 0x0c Clear decode protection port 0 */
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};
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#endif
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#define SUNXI_TZPC_DECPORT0_RTC (1 << 1)
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void tzpc_init(void);
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#endif /* _SUNXI_TZPC_H */
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